STK850_07 [STMICROELECTRONICS]
N-channel 30V - 0.0024Ω - 30A - PolarPAK® STripFET™ Power MOSFET; N沟道30V - 0.0024Ω - 30A - PolarPAK®的STripFET ™功率MOSFET
| 型号： | STK850_07 |
| 厂家： | 
ST |
| 描述： | N-channel 30V - 0.0024Ω - 30A - PolarPAK® STripFET™ Power MOSFET |
| 文件： | 总16页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK850
N-channel 30V - 0.0024Ω - 30A - PolarPAK®
STripFET™ Power MOSFET
Features
VDSS
RDS(on)
RDS(on)*Qg
71nC*mΩ
PTOT
Type
STK850 30V <0.0029Ω
5.2W
■ Ultra low top and bottom junction to case
thermal resistance
■ Very low capacitances
■ 100% Rg tested
PolarPAK®
■ Fully encapsulated die
■ 100% Matte tin finish (in compliance with the
2002/95/EC european directive)
■ PolarPAK® is a trademark of VISHAY
Figure 1.
Internal schematic diagram
Application
■ Switching applications
Description
This Power MOSFET is the latest development of
STMicroelectronics unique “single feature size”
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, moreover the double sides cooling
package with ultra low junction to case thermal
resistance allows to handle higher levels of
current.
Bottom View
Top View
Table 1.
Device summary
Order code
Marking
Package
PolarPAK®
Packaging
STK850
K850
Tape & reel
October 2007
Rev 9
1/16
www.st.com
16
Contents
STK850
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
STK850
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
30
Unit
V
VDS
Drain-source voltage (VGS = 0)
(1)
Gate-source voltage
16
V
VGS
(2)
Gate-source voltage
18
V
VGS
(4)
Drain current (continuous) at TC = 25°C
Drain current (continuous) at TC = 100°C
30
A
ID
ID
18.75
120
A
(3)
Drain current (pulsed)
A
IDM
(4)
Total dissipation at TC = 25°C
Derating factor
5.2
0.0416
1.4
W
W/°C
J
PTOT
(5)
Single pulse avalanche energy
EAS
TJ
Operating junction temperature
Storage temperature
-55 to 150
°C
Tstg
1. Continuous mode
2. Guaranteed for test time < 15ms
3. Pulse width limited by package
4. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and ≤10sec
5. Starting TJ = 25°C, ID = 15A, VDD = 25V
Table 3.
Symbol
Thermal data
Parameter
Typ.
Max.
24
Unit
°C/W
°C/W
°C/W
Rthj-amb(1)
Rthj-c(2)
Thermal resistance junction-amb
20
0.8
2.2
Thermal resistance junction-case (top drain)
Thermal resistance junction-case (source)
1
Rthj-c(3)
2.7
1. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and ≤10sec
2. Steady State
3. Measured at Source pin when the device is mounted on FR-4 board in steady state
3/16
Electrical characteristics
STK850
2
Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 4.
Symbol
On/off
Parameter
Test conditions
Min. Typ.
Max. Unit
Drain-source breakdown
voltage
V(BR)DSS
ID = 250µA, VGS= 0
30
V
V
DS = Max rating,
1
µA
µA
Zero gate voltage drain
current (VGS = 0)
IDSS
VDS = Max rating,Tc=125°C
10
Gate body leakage current
(VDS = 0)
IGSS
VGS = 16V
±100
nA
V
VGS(th)
RDS(on)
VDS= VGS, ID = 250µA
Gate threshold voltage
1
2.5
VGS= 10V, ID= 15A
VGS= 4.5V, ID= 15A
0.0024 0.0029
0.0029 0.0035
Ω
Ω
Static drain-source on
resistance
Table 5.
Symbol
Dynamic
Parameter
Test conditions
Min.
Typ.
Max. Unit
Input capacitance
Ciss
Coss
Crss
3150
940
90
pF
pF
pF
Output capacitance
VDS =25V, f=1 MHz, VGS=0
Reverse transfer
capacitance
Qg
Qgs
Qgd
VDD=15V, ID = 30A
VGS =4.5V
Total gate charge
Gate-source charge
Gate-drain charge
24.5
8
32.5 nC
nC
nC
8.2
(see Figure 16)
Pre Vth gate-to-source
charge
Qgs1
Qgs2
V
DD=15V, ID = 12A
0.6
7.2
nC
nC
VGS =4.5V
Post Vth gate-to-source
charge
(see Figure 21)
f=1 MHz Gate DC Bias = 0
Test signal level = 20mV
open drain
RG
Gate input resistance
1.1
Ω
4/16
STK850
Electrical characteristics
Min. Typ. Max. Unit
Table 6.
Symbol
Switching times
Parameter
Test conditions
VDD= 15V, ID= 15A,
RG=4.7Ω, VGS=4.5V
(see Figure 15)
td(on)
tr
Turn-on delay time
Rise time
20
57
ns
ns
V
DD=15V, ID= 15A,
td(off)
tf
Turn-off delay time
Fall time
31
13
ns
ns
RG=4.7Ω, VGS=4.5V
(see Figure 15)
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
Min. Typ. Max. Unit
Source-drain current
ISD
30
A
A
Source-drain current
(pulsed)
(1)
120
ISDM
(2)
ISD= 15A, VGS=0
Forward on voltage
1.2
V
VSD
trr
ISD= 30A, di/dt = 100A/µs,
VDD=20V, TJ=150°C
Reverse recovery time
Reverse recovery charge
Reverse recovery current
39
39.8
2
ns
nC
A
Qrr
(see Figure 20)
IRRM
1. Pulse width limited by package
2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
5/16
Electrical characteristics
STK850
2.1
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
Figure 4. Output characteristics
Figure 5. Transfer characteristics
Figure 6. Transconductance
Figure 7. Static drain-source on resistance
6/16
STK850
Electrical characteristics
Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature
temperature
Figure 12. Source-drain diode forward
characteristics
Figure 13. Normalized B
vs temperature
VDSS
7/16
Electrical characteristics
STK850
Figure 14. Allowable I vs time in avalanche
AV
The previous curve gives the single pulse safe operating area for unclamped inductive
loads, under the following conditions:
P
E
=0.5*(1.3*B
*I
)
D(AVE)
AS(AR)
VDSS AV
=P
*t
D(AVE) AV
Where:
is the allowable current in avalanche
I
AV
P
is the average power dissipation in avalanche (single pulse)
D(AVE)
t
is the time in avalanche
AV
8/16
STK850
Test circuits
3
Test circuits
Figure 15. Switching times test circuit for
resistive load
Figure 16. Gate charge test circuit
Figure 17. Test circuit for inductive load
switching and diode recovery times
Figure 18. Unclamped inductive load test
circuit
Figure 19. Unclamped inductive waveform
Figure 20. Switching time waveform
9/16
Test circuits
STK850
Figure 21. Gate charge waveform
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
10/16
STK850
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/16
Package mechanical data
STK850
®
Table 8.
Ref.
PolarPAK (option “L”) mechanical data
mm
inch
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.75
0.80
0.85
0.05
0.68
0.61
2.39
1.19
0.43
0.30
6.30
6.04
5.31
5.05
0.030
0.031
0.033
0.002
0.027
0.024
0.094
0.047
0.017
0.012
0.248
0.238
0.209
0.199
A1
b1
b2
b3
b4
b5
c
0.48
0.41
2.19
0.89
0.23
0.20
6
0.58
0.51
2.29
1.04
0.33
0.25
6.15
5.89
5.16
4.90
0.019
0.016
0.086
0.035
0.009
0.008
0.236
0.226
0.197
0.187
0.009
0.018
0.012
0.018
0.166
0.043
0.054
0.009
0.169
0.135
0.009
0.002
0.006
0.137
0.022
0.047
0.154
0.023
0.020
0.090
0.041
0.013
0.010
0.242
0.232
0.203
0.193
D
D1
E
5.74
5.01
4.75
0.23
0.45
0.31
0.45
4.22
1.08
1.37
0.24
4.30
3.43
0.22
0.05
0.15
3.48
0.56
1.20
3.90
E1
H1
H2
H3
H4
K1
K2
K3
K4
M1
M2
M3
M4
P1
T1
T2
T3
T4
T5
<
0.56
0.51
0.56
4.52
1.18
0.022
0.020
0.022
0.178
0.046
0.41
0.016
4.37
1.13
0.172
0.044
4.50
3.58
4.70
3.73
0.177
0.141
0.185
0.147
0.20
3.64
0.76
0.25
4.10
0.95
0.008
0.143
0.030
0.010
0.161
0.037
0.18
10°
0.36
12°
0.007
10°
0.014
12°
0°
0°
12/16
STK850
Package mechanical data
®
Figure 22. PolarPAK (option “L”) drawings
13/16
Package mechanical data
Figure 23. Recommended PAD layout
STK850
14/16
STK850
Revision history
5
Revision history
Document
Table 9.
Date
Document revision history
Revision
Changes
10-Nov-2005
19-Dec-2005
30-Jan-2006
21-Mar-2006
25-May-2006
10-Oct-2006
08-May-2007
03-Sep-2007
01-Oct-2007
1
2
3
4
5
6
7
8
9
First version
Complete version
Modified description on first page
The document has been reformatted
New note on Table 2
Modified general features
New data on Table 5 and new Figure 21
Updated mechanical data
Inserted new Figure 23: Recommended PAD layout
15/16
STK850
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