STL150N3LLH5 [STMICROELECTRONICS]
N-channel 30 V - 0.0014 ヘ - 35 A - PowerFLAT⑩ (6x5) STripFET⑩ V Power MOSFET; N沟道30 V - 0.0014ヘ - 35 A - PowerFLAT⑩ （引脚6x5 ） STripFET⑩ V功率MOSFET
| 型号： | STL150N3LLH5 |
| 厂家： | 
ST |
| 描述： | N-channel 30 V - 0.0014 ヘ - 35 A - PowerFLAT⑩ (6x5) STripFET⑩ V Power MOSFET |
| 文件： | 总12页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STL150N3LLH5
N-channel 30 V - 0.0014 Ω - 35 A - PowerFLAT™ (6x5)
STripFET™ V Power MOSFET
Features
RDS(on)
max
Type
VDSS
ID
STL150N3LLH5
30 V
<0.00175 Ω 35 A (1)
1. The value is rated according Rthj-pcb
■ R
* Q industry benchmark
DS(on)
g
■ Extremely low on-resistance R
■ High avalanche ruggedness
■ Low gate drive power losses
DS(on)
PowerFLAT™ ( 6x5 )
Application
■ Switching applications
Figure 1.
Internal schematic diagram
Description
th
This product utilizes the 5 generation of design
rules of ST’s proprietary STripFET™ technology.
The lowest available R
*Q , in this chip scale
DS(on)
g
package, makes this device suitable for the most
demanding DC-DC converter applications, where
high power density is to be achieved.
Table 1.
Order code
STL150N3LLH5
Device summary
Marking
Package
Packaging
150N3LLH5
PowerFLAT™ (6x5)
Tape and reel
April 2008
Rev 2
1/12
www.st.com
12
Contents
STL150N3LLH5
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
STL150N3LLH5
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
30
20
Unit
VDS
VGS
Drain-source voltage (VGS = 0)
Gate-source voltage
V
V
(1)
ID
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100 °C
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC=100 °C
Drain current (pulsed)
150
94
A
(1)
ID
A
(2)
ID
35
A
(3)
ID
21.8
140
80
A
(3)
IDM
A
(1)
PTOT
Total dissipation at TC = 25 °C
Total dissipation at TC = 25 °C
Derating factor
W
W
W/°C
(3)
PTOT
4
0.03
TJ
Operating junction temperature
Storage temperature
-55 to 150
°C
Tstg
1. The value is rated according Rthj-c
2. The value is rated according Rthj-pcb
3. Pulse width limited by safe operating area
Table 3.
Symbol
Thermal resistance
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case (drain) (steady state)
Thermal resistance junction-ambient
1.56
31.3
°C/W
°C/W
(1)
Rthj-pcb
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Table 4.
Symbol
Avalanche data
Parameter
Value
Unit
Not-repetitive avalanche current,
(pulse width limited by Tj Max)
IAV
17
A
Single pulse avalanche energy
EAS
300
mJ
(starting TJ = 25 °C, ID = IAV , VDD = 24 V)
3/12
Electrical characteristics
STL150N3LLH5
2
Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Table 5.
Symbol
On/off states
Parameter
Test conditions
Min. Typ.
Max.
Unit
Drain-source breakdown
voltage
V(BR)DSS
ID = 250 µA, VGS= 0
30
V
V
DS = Max rating,
1
µA
µA
Zero gate voltage drain
current (VGS = 0)
IDSS
VDS = Max rating @125 °C
10
Gate body leakage current
(VDS = 0)
IGSS
VGS = 20 V
±100
nA
V
VGS(th)
RDS(on)
VDS= VGS, ID = 250 µA
Gate threshold voltage
1
VGS= 10 V, ID= 17.5 A
VGS= 4.5 V, ID= 17.5 A
0.0014 0.00175
0.0019 0.0024
Ω
Ω
Static drain-source on
resistance
Table 6.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
Ciss
Coss
Crss
Input capacitance
5800
1147
127
pF
pF
pF
VDS = 25 V, f=1 MHz,
VGS=0
Output capacitance
Reverse transfer
capacitance
Qg
Qgs
Qgd
VDD=15 V, ID = 35 A
VGS =4.5 V
Total gate charge
Gate-source charge
Gate-drain charge
40
nC
nC
nC
13.4
14.9
(see Figure 14)
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
RG
Gate input resistance
1.1
Ω
4/12
STL150N3LLH5
Electrical characteristics
Min. Typ. Max. Unit
Table 7.
Switching times
Parameter
Symbol
Test conditions
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
17.2
30.8
65.8
47.8
ns
ns
ns
ns
VDD=15 V, ID= 17.5 A,
RG=4.7 Ω, VGS=10 V
(see Figure 13)
Turn-off delay time
Fall time
Table 8.
Symbol
Source drain diode
Parameter
Test conditions
Min Typ. Max Unit
ISD
Source-drain current
35
140
1.1
A
A
V
(1)
Source-drain current (pulsed)
Forward on voltage
ISDM
(2)
ISD = 35 A, VGS=0
ISD = 35 A,
VSD
trr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
43.8
46
ns
nC
A
Qrr
di/dt = 100 A/µs,
VDD=25 V
2.1
IRRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
5/12
Electrical characteristics
STL150N3LLH5
2.1
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
HV42710
TJ = 150 °C
ID(A)
TC = 25°C
Single pulse
100
10 ms
10
1
100 ms
1 s
0.1
0.01
VDS(V)
0.1
1
10
Figure 4. Output characteristics
Figure 5. Transfer characteristics
Figure 6. Normalized B
vs temperature
Figure 7. Static drain-source on resistance
VDSS
HV42790
HV42770
BVDSS
(norm)
RDS(on)
(mΩ)
1.1
1.05
1
2.5
2.0
1.5
1.0
0.5
0.95
0.9
0.85
-55 -30
-5
0
20
45
ID(A)
70
95
10
20
30
120
145
TJ(°C)
6/12
STL150N3LLH5
Electrical characteristics
Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
HV42760
HV42730
C(pF)
VGS(V)
f=1MHz
V
V
DD=15 V
GS=5 V
=34 A
12
10000
8000
6000
4000
2000
10
8
I
D
Ciss
6
4
Coss
2
Crss
0
0
20
0
40
60
0
10
20
VDS(V)
Qg(nC)
Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature temperature
HV42750
HV42740
R
DS(on)
V
GS(th)
(norm)
(norm)
ID=250µA
I
D
=17 A
1.2
1.6
1.4
1.2
1
V
GS=10 V
1
0.8
0.6
0.4
0.2
0.8
0.6
-30
-5
-55
20
145
95 120
T
45
70
-55 -30
-5
20
45
70
95 120 145
TJ (°C)
J(°C)
Figure 12. Source-drain diode forward
characteristics
HV42780
V
SD(V)
0.8
0.7
0.6
0.5
0.4
0.3
TJ=-55°C
TJ=25°C
TJ
=175°C
0
10
20
30
ID(A)
7/12
Test circuits
STL150N3LLH5
3
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
switching and diode recovery times
Figure 16. Unclamped inductive load test
circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
8/12
STL150N3LLH5
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STL150N3LLH5
PowerFLAT™(6x5) mechanical data
mm.
Typ.
0.83
0.02
0.20
0.40
5.00
4.75
4.20
6.00
5.75
3.48
2.63
1.27
0.80
inch
DIM.
Min.
Max.
0.93
0.05
Min.
Typ.
0.32
Max.
0.036
A
A1
A3
b
0.80
0.031
0.0007
0.007
0.015
0.196
0.187
0.165
0.236
0.226
0.137
0.103
0.050
0.031
0.0019
0.35
4.15
0.47
4.25
0.013
0.163
0.135
0.027
0.018
0.167
D
D1
D2
E
E1
E2
E4
e
3.43
2.58
3.53
2.68
0.139
0.105
L
0.70
0.90
0.035
10/12
STL150N3LLH5
Revision history
5
Revision history
Table 9.
Date
Document revision history
Revision
Changes
22-Oct-2007
01-Apr-2008
1
2
First release
Document status promoted from preliminary data to datasheet
11/12
STL150N3LLH5
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