STLC60133 [STMICROELECTRONICS]
XDSL LINE DRIVER; xDSL线路驱动
| 型号： | STLC60133 |
| 厂家： | 
ST |
| 描述： | XDSL LINE DRIVER |
| 文件： | 总9页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLC60133
XDSL LINE DRIVER
PRELIMINARY DATA
■
■
■
Hz
LOW NOISE : 4nV/
HIGH PEAK OUTPUT CURRENT: 500 mA
HIGH SPEED
– 140MHz Gain Bandwidth
– 30MHz Gain Flatness
– 400 V/us Slew Rate
HTSSOP28
■
LOW POWER OPERATION
– ±5V to ±15V Voltage Supply
– 12.5 mA/Amp (typ) Supply current
– Power reduced Current
ORDERING NUMBER: STLC60133
Temperature Range: -40°C to +85°C
■
■
■
■
LOW SINGLE TONE DISTORTION
THERMAL AND OVERLOAD PROTECTION
HTSSOP28 PACKAGE
Two digital pins (PWDN0 and PWDN1) allow the driv-
er to work in full performance mode, in low-power
mode or two intermediate bias states.
-40 TO +85°C OPERATING RANGE
The low-power mode biases the output stage in order
to provide a low impedance at the amplifier outputs
for back termination.
DESCRIPTION
The STLC60133 is designed optimizing bandwidth
and distortion performances. For proper device oper-
ating it is necessary to work with a gain level greater
than 15.6dB.
The STLC60133 is a dual amplifier featuring a high
slew rate and a large bandwidth optimized for XDSL
applications. The device is available in a HTSSOP 28
pin package (4x9 mm) with an exposed leadframe.
Typical differential gain is normally +27dB, while typ-
ical common mode gain is 15.6dB
Thanks to its small package this line driver is suitable
for high density ADSL line card.
Figure 1. BLOCK DIAGRAM
-VS +VS
Op1
-
IN1N
IN1P
OUT1
+
PWDN0
PWDN1
LOGIC
TH DETCT.
BIAS
DGND
-
IN2N
IN2P
OUT2
+
Op2
D00TL462A
October 2001
1/9
This is preliminary information on a new product now in development. Details are subject to change without notice.
STLC60133
PIN CONNECTION
RES
N.C.
N.C.
IN2P
IN2N
OUT2
+VS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RES
N.C.
2
3
N.C.
4
N.C.
5
PWDN1
BIAS
-VS
6
7
+VS
8
-VS
OUT1
IN1N
IN1P
N.C
9
DGND
N.C.
10
11
12
13
14
PWDN0
N.C.
N.C.
N.C.
N.C.
N.C.
D00TL463A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
+16.5
Unit
V
V
CC
Positive Supply voltage (note1)
V
Negative Supply voltage (note1)
Differential Input Voltage (note2)
Common mode Input Voltage
Operating Free Air Temperature Range
Storage temperature
-16.5
V
SS
V
±5
V
id
V
±1
V
i
T
op
-40 to +85
-65 to +150
150
°C
°C
°C
T
stg
T
Junction temperature
j
THERMAL DATA
Symbol
Parameter
Value
Unit
R
thj-amb
Thermal resistance junction to ambient (note 3)
29
°C/W
2/9
STLC60133
OPERATING RANGE
Symbol
Parameter
Value
Unit
°C
V
T
op
Operating Temperature Range
-40 to 85
+5 to +15
-5 to -15
V
V
Positive Supply voltage (note1)
Negative Supply voltage (note1)
Digital Ground level
CC
SS
V
V
V
SS
+5<V
<V -5
V
V
DGND
DGND
CC
V
icm
Common Mode Input Voltage Range
±1
Notes
1) All voltages values , except differential voltage , are with respect to network ground terminal .
2) Differential voltages are non-inverting input terminal with respect to the inverting input terminal
3) Specification is for device on a 4 layer board within 10 square inches of oz. copper at +85°C and 200m/s air velocity. With 0m/s air velocity
the parameter increases up to 33°C/W
.
PIN DESCRIPTION
N°
Pin
Description
2, 3, 12, 13, 14,
15, 16, 17, 19,
25, 26, 27
NC
Not Connected
4
5
IN2P
IN2N
Non Inverting Input of Op. Amplifier 2
Inverting Input of Op. Amplifier 2
6
OUT2 Ouput of Op. Amplifier 2
+Vs Positive Supply Voltage
OUT1 Ouput of Op. Amplifier 1
7, 8
9
10
IN1N
IN1P
Inverting Input of Op. Amplifier 1
Non Inverting Input of Op. Amplifier 1
11
14
PWDN1 Power Down 1 logic input
PWDN0 Power Down 0 logic input
18
21, 22
23
-Vs
BIAS
RES
Negative Supply Voltage
Bias Control pin
1, 28
To be left not connected
Power Down Management
The STLC60133 provides several quiescent bias levels from full performance, to reduced bias (in three steps
through PWDN0/1 pins) or to full OFF operation (through BIAS pin). According to the different XDSL application
(both site CO and CPE), different bias levels can be chosen maintaining good MTPR performances. In the fol-
lowing table are shown the bias levels versus the PWDN values.
PWDN1
PWDN0
Bias Level
1
1
0
0
X
1
0
1
0
X
100%
60%
40%
25% (low Zout but not OFF)
Full OFF (High Zout via 250uA pulled out of BIAS pin)
3/9
STLC60133
The bias level is programmed by the TTL logic level applied to the PWDN pins. The DGND pin is the logic
ground reference for the PWDN pins. For normal operation the BIAS pin shall be left open.
The BIAS control pin can be used to adjust the internal biasing and thus the quiescent current. By pulling out a
µ
µ
current of 0 A to 200 A, the quiescent current can be adjusted from 100% (full ON) to a full OFF condition.
However, considering the internal parameter spread to full shutdown the STLC60133 is recommended to pull
µ
down a 250 A current from the BIAS pin. In the following figure is shown an implementation of a complete am-
plifier shutdown. To partially reduce the internal biasing also the PWDN pins can be used.
Figure 2. Logic drive of bias pin for complete Amplifier Shutdown.
3.3V
R1
BIAS
R2
50KΩ
STLC60133
R1 = 47KΩ for ± 12V
D01TL492
R1 = 22KΩ for ± 6V
THERMAL SHUTDOWN
A thermal protection is embedded in the STLC60133. In case of thermal overload the device is shut down at
160°C and returns to normal operation when the temperature becomes lower than 145°C.
During the thermal shutdown the voltage at the BIAS pin goes to the DGND rail; when the device returns to the
normal operation the voltage at the BIAS pin goes to the positive rail. In this condition the BIAS pin can be used
as thermal overload indicator.
MAXIMUM POWER DISSIPATION
Maximum Junction Temperature allowed for proper device operation is T = 140°C. A Typical Thermal Resis-
j
tance Junction to ambient of 29°C/W can be obtained mounting the device on a 4 layer board whithin 10 square
inches of copper and having the exposed pad contacting a proper copper area . It shall be noted that the ex-
posed pad of the device is electrically connected to the V negative supply.
SS
Figure 3. Shutdown and alarm circuit
VCC
STLC60133
200µA
10KΩ
V
BIAS=VCC -1.5V
BIAS
SHUT
DOWN
OR
0-200µA
BIAS
VEE
PWDN0
PWDN1
+5V
10KΩ
ALARM
VCC
+5V
OR
BIAS
10KΩ
1MΩ
BIAS
ALARM
100KΩ
MIN β 350
1/4 HCF40109B
ST
D01TL491
4/9
STLC60133
ELECTRICAL CHARACTERISTCS
Test Conditions: (V = ±12V , Tamb = 0 to 70°C , Single amplifier in normal condition (PWDN0 = 1, PWDN1 = 1),
CC
unless otherwise specified). The limits listed below are guaranted in the above temperature range (0-70°C) by
specific testing at different temperature or by product characterisation.
TRANSMISSION PATH
Symbol
Parameter
Test Condition
G = 6, Vout = 2Vpp
Min.
Typ.
400
140
Max.
Unit
V/us
MHz
SR
Slew Rate
GBW Gain Bandwidth
G = 6, Vout = 2Vpp, f = 5MHz
90
THD Single ended Distortion
G = 6, f = 1MHz, Vout = 12Vpp,
Rl = 16.5Ω
-40
-45
-47
-52
dBc
dBc
Rl = 100Ω
(2)
DTHD
IMD
G = 6, f = 1MHz, Vout = 24Vpp,
Rl = 33Ω
Rl = 100Ω
Differential THD
-50
-55
Single ended IMD
G = 6, Vout = 3Vp each tone,
f = 500KHz, ∆f = 10KHz
Rl = 16.5Ω
-54
-60
-70
-75
dBc
dBc
Rl = 100Ω
(2)
DIMD
G = 6, Vout = 6Vp each tone,
f = 500KHz, ∆f = 10KHz
Rl = 33Ω
Differential IMD
-66
-72
Rl = 100Ω
IB
Input Biasing
5
4
µA
OZ
VN
Output Impedance
Voltage Noise (RTI)
PWDN0 = PWDN1 = 0; f = 1MHz
f = 30KHz
2
Ω
10
nV/
Hz
IOV
Input Offset Voltage
6
mV
V
ICMR Input Common Mode Voltage
Range
f = 1 MHz
-1
+1
CMRR Common Mode Rejection Ratio f = 1 MHz, Vin = 100mV
40
dB
V
OVS Output Voltage Swing
LOC Linear Output Current
Single ended, Rl = 100Ω, G = 6
Single ended, Rl = 10Ω, G = 6
Single ended
-10.8
400
+10.8
1400
600
mA
mA
(1)
SCC
QC
1000
Short Circuit Current
Quiescent Current
PWDN1, PWDN0 = 1,1
PWDN1, PWDN0 = 1,0
PWDN1, PWDN0 = 0,1
PWDN1, PWDN0 = 0,0
12
8
5
16.2
10.7
7.5
mA/Amp
4
5.3
SC
Shutdown Current
250µA out of Bias pin
1.5
2.0
mA/Amp
PSRR Power Supply Rejection ratio
BIASV Bias Pin Voltage
DCG DC Gain
f = 500kHz, V = 100mV
30
10
dB
V
10.5
80
dB
Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common
can cause the STLC60133 to source or sink 1.4A.
2. Guaranteed by product characterization.
5/9
STLC60133
ELECTRICAL CHARACTERISTICS
Test conditions (V = ±6V, T
= 0 to 70°C ,Single amplifier in normal condition (PWDN0 = 1, PWDN1 = 1),
CC
amb
unless otherwise specified.) The limits listed below are guaranted in the above temperature range by (0-70°C)
specific testing at different temperature or by product characterisation.
TRANSMISSION PATH
Symbol
SR
Parameter
Test Condition
G = 6, Vout = 2Vpp
Min.
Typ.
400
140
Max.
Unit
V/us
MHz
Slew Rate
GBW
THD
Gain Bandwidth
G = 6, Vout = 2Vpp, f = 5MHz
90
Single Ended Distortion
G = 6, f = 1MHz, Vout = 6Vpp,
Rl = 25Ω
Rl = 100Ω
-40
-45
-46
-51
dBc
dBc
(2)
DTHD
IMD
G = 6, f = 1MHz, Vout = 12Vpp,
Rl = 25Ω
Rl = 100Ω
Differential THD
-50
-55
Single Ended IMD
G = 6, Vout = 1.5Vp each tone,
f = 500KHz, ∆f = 10KHz
Rl = 25Ω
-65
-70
-76
-81
dBc
Rl = 100Ω
(2)
DIMD
G = 6, Vout = 3Vp each tone,
f = 500KHz, ∆f = 10KHz
Rl = 25Ω
Differential IMD
-77
-82
dBc
Rl = 100Ω
IB
Input Biasing
5
4
µA
VN
Voltage Noise (RTI)
f = 30KHz
10
nV/
Hz
IOV
Input Offset Voltage
6
mV
ICMR Input Common Mode Voltage
Range
f = 1 MHz
-1
+1
V
CMRR Common Mode Rejection Ratio
f = 1 MHz, Vin = 100mV
40
dB
V
OVS
Output Voltage Swing
Single ended, Rl = 100Ω,
-5
+5
G = 6
LOC
Linear Output Current
Single ended, Rl = 10Ω,
300
420
mA
G = 6
(1)
SCC
QC
Single ended,
1000
1400
mA
Short Circuit Current
Quiescent Current
PWDN1, PWDN0 = 1,1
PWDN1, PWDN0 = 1,0
PWDN1, PWDN0 = 0,1
PWDN1, PWDN0 = 0,0
10
7
5
13.7
9
6.5
mA/Amp
3.5
4.5
SC
Shutdown Current
250µA out of Bias pin
1.5
40
2.0
mA/Amp
PSRR Power Supply Rejection ratio
BIASV Bias Pin Voltage
f = 500kHz, V = 100mV
30
4
dB
V
4.5
80
DCG
DC Gain
dB
Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common
can cause the STLC60133 to source or sink 1.4A.
2. Guaranteed by product characterization.
6/9
STLC60133
DIGITAL INTERFACE (PWDN0, PWDN1, Vcc = ±12 V or ±6 V)
Symbol
Parameter
Input low voltage
Input high voltage
Test Condition
Min.
0
Typ.
Max.
0.8
Unit
V
V
il
V
2.2
5.5
V
ih
THERMAL PROTECTION
Symbol Parameter
Test Condition
Min.
Typ.
160
15
Max.
Unit
°C
T
Thermal shut down threshold
Thermal detector histeresys
hsd
hist
T
°C
Figure 4. Single ended Test Circuit G = 6
200Ω
1200Ω
VIN
VOUT
RL
-
+
+VS
10µF
0.1µF
0.1µF
10µF
-VS
D00TL464
Figure 5. Differential Test Circuit G = 6
10µF
+VS
0.1µF
+
-
200Ω
200Ω
+VOUT
1200Ω
1200Ω
VIN
RL
-
-VOUT
+
0.1µF
10µF
-VS
D00TL465A
7/9
STLC60133
mm
inch
DIM.
MIN.
OUTLINE AND
MECHANICAL DATA
TYP. MAX. MIN.
TYP. MAX.
0.0
A
1.2
A1
0.15
0.006
A2
b
0.8
0.19
0.09
9.6
1.0
1.05 0.031 0.039 0.041
0.3
0.2
9.8
0.007
0.003
0.012
0.008
c
D (*)
D1
E
9.7
5.5
6.4
4.4
3.0
0.65
0.6
1.0
0.377 0.382 0.385
0.216
6.2
4.3
6.6
4.5
0.244 0.252 0.260
0.169 0.173 0.177
0.118
E1 (*)
E2
e
0.026
L
0.45
0.75 0.018 0.024 0.029
L1
k
0.039
0˚ (min), 8˚ (max)
0.004
aaa
0.1
HTSSOP28
(Exposed Pad)
(*) Dimensions D and E1 does not include mold flash
or protusions. Mold flash or protusions shall not
exceed 0.15mm per side.
A2
A1
A
c
b
e
aaa C
E1
D
0.25mm
0.10inch
D1
GAUGE PLANE
SEATING
PLANE
1
1
4
C
E2
E
k
L
L1
28
15
HTSSO28M
8/9
STLC60133
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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