STM32F101RB_技术文档

STM32F101x6

STM32F101x8 STM32F101xB

Access line, advanced ARM-based 32-bit MCU with Flash memory,

six 16-bit timers, ADC and seven communication interfaces

Preliminary Data

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 36 MHz, 45 DMIPS with 1.25 DMIPS/MHz

LQFP100

LQFP48

LQFP64

– Single-cycle multiplication and hardware

division

14 x 14 mm

7 x 7 mm

10 x 10 mm

– Temperature sensor

– Nested interrupt controller with 43

maskable interrupt channels

■ Up to 80 fast I/O ports

– 32/49/80 5 V-tolerant I/Os

– Interrupt processing (down to 6 CPU

cycles) with tail chaining

– All mappable on 16 external interrupt

vectors

■ Memories

– Atomic read/modify/write operations

– 32-to-128 Kbytes of Flash memory

– 6-to-16 Kbytes of SRAM

■ Up to 6 timers

– Up to three 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage

detector (PVD)

– 4-to-16 MHz high-speed quartz oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 32 kHz RC

– 2 x 16-bit watchdog timers (Independent

and Window)

– SysTick timer: 24-bit downcounter

■ Up to 7 communication interfaces

2

– Up to 2 x I C interfaces (SMBus/PMBus)

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– PLL for CPU clock

– Dedicated 32 kHz oscillator for RTC with

calibration

– Up to 2 SPIs (18 Mbit/s)

■ Low power

Table 1.

Device summary

– Sleep, Stop and Standby modes

Reference

Root part number

– V

supply for RTC and backup registers

BAT

STM32F101x6

STM32F101x8

STM32F101xB

STM32F101C6, STM32F101R6

■ Debug mode

STM32F101C8, STM32F101R8

STM32F101V8

– Serial wire debug (SWD) and JTAG

interfaces

STM32F101RB, STM32F101VB

■ DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

2

I Cs and USARTs

■ 12-bit, 1 µs A/D converter (16-channel)

– Conversion range: 0 to 3.6 V

July 2007

Rev 2

1/64

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

STM32F101xx

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

2.2

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3

4

5

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1

Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2

5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 26

Embedded reset and power control block characteristics . . . . . . . . . . . 27

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Internal Clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 40

5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2/64

STM32F101xx

Contents

5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6

7

8

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.1

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.1

Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3/64

List of tables

STM32F101xx

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Device features and peripheral counts (STM32F101xx access line) . . . . . . . . . . . . . . . . . . 7

Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 27

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Maximum current consumption in Run and Sleep modes (T = 85 °C) . . . . . . . . . . . . . . . 28

A

Maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . 29

Typical current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Typical current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 31

High-speed user external (HSE) clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

LSE oscillator characteristics (

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

fLSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Flash endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SCL frequency (f

= 36 MHz, V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PCLK1

DD

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

ADC accuracy (f

= 10 MHz, f

= 10 MHz, R

< 10 kΩ, V

= 3.3 V) . . . . . . . . 55

PCLK2

ADC

AIN

DDA

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 58

LQFP64 – 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 59

LQFP48 – 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 60

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4/64

STM32F101xx

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

STM32F101xx access line block diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

STM32F101xx access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

STM32F101xx access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

STM32F101xx access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 11. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 15. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2

Figure 17. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 18. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 19. SPI timing diagram - slave mode and CPHA=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 20. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 21. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 22. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 23. Power supply and reference decoupling (V

not connected to V

). . . . . . . . . . . . . . 56

REF+

DDA

Figure 24. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . 56

Figure 25. LQPF100 – 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 26. LQFP64 – 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 27. LQFP48 – 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5/64

Introduction

STM32F101xx

1

Introduction

This datasheet contains the description of the STM32F101xx access line family features,

pinout, Electrical Characteristics, Mechanical Data and Ordering information.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10x Flash Programming Reference Manual

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual.

2

Description

The STM32F101xx access line family incorporates the high-performance ARM Cortex™-M3

32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash

memory up to 128Kbytes and SRAM up to 16 Kbytes), and an extensive range of enhanced

peripherals and I/Os connected to two APB buses. All devices offer standard communication

2

interfaces (two I Cs, two SPIs, and up to three USARTs), one 12-bit ADC and three general

purpose 16-bit timers.

The STM32F101 family operates in the −40 to +85°C temperature range, from a 2.0 to 3.6 V

power supply. A comprehensive set of power-saving mode allows to design low-power

applications.

The complete STM32F101xx access line family includes devices in 3 different package

types: from 48 pins to 100 pins. Depending on the device chosen, different sets of

peripherals are included, the description below gives an overview of the complete range of

peripherals proposed in this family.

These features make the STM32F101xx access line microcontroller family suitable for a

wide range of applications:

■

Application control and user interface

■

Medical and handheld equipment

PC peripherals, gaming and GPS platforms

Industrial applications: PLC, inverters, printers, and scanners

Alarm systems, Video intercom, and HVAC

Figure 1 shows the general block diagram of the device family.

6/64

STM32F101xx

Description

2.1

Device overview

Table 2.

Device features and peripheral counts (STM32F101xx access line)

Peripheral

STM32F101Cx

STM32F101Rx

STM32F101Vx

Flash - Kbytes

SRAM - Kbytes

32

6

64

10

32

6

64

10

128

16

64

10

128

16

General purpose

2

3

SPI

I²C

1

2

1

2

USART

2

3

2

3

12-bit synchronized ADC

number of channels

1

10 channels

16 channels

GPIOs

32

49

80

CPU frequency

Operating voltage

Operating temperature

Packages

36 MHz

2.0 to 3.6 V

-40 to +85 °C

LQFP64

LQFP48

LQFP100

7/64

Description

STM32F101xx

2.2

Overview

ARM^®Cortex^TM-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The STM32F101xx access line family having an embedded ARM core, is therefore

compatible with all ARM tools and software.

Embedded Flash memory

Up to 128 Kbytes of embedded Flash is available for storing programs and data.

Embedded SRAM

Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

Nested vectored interrupt controller (NVIC)

The STM32F101xx access line embeds a nested vectored interrupt controller able to handle

up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)

and 16 priority levels.

■

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

8/64

STM32F101xx

Description

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detectors lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect external line with pulse

width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16

external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is

monitored for failure. During such a scenario, it is disabled and software interrupt

management follows. Similarly, full interrupt management of the PLL clock entry is available

when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the High Speed APB

(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 36 MHz.

Boot modes

At startup, boot pins are used to select one of five boot options:

■

Boot from User Flash

Boot from System Memory

Boot from SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using the USART.

Power supply schemes

■

V

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

DD

Provided externally through V pins.

DD

V

, V

= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs

DDA

SSA

and PLL. In V range (ADC is limited at 2.4 V).

DD

V

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup

BAT

registers (through power switch) when V is not present.

DD

Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V is below a specified threshold, V

, without the need for an

DD

POR/PDR

external reset circuit.

The device features an embedded Programmable voltage detector (PVD) that monitors the

power supply and compares it to the V threshold. An interrupt can be generated

V

DD

PVD

when V drops below the V

and/or when V is higher than the V

threshold. The

DD

PVD

DD

PVD

interrupt service routine can then generate a warning message and/or put the MCU into a

safe state. The PVD is enabled by software.

Refer to Table 9: Embedded reset and power control block characteristics for the values of

V

and V

.

POR/PDR

PVD

9/64

Description

STM32F101xx

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

■

MR is used in the nominal regulation mode (Run)

LPR is used in the Stop modes

Power down is used in Standby Mode: the regulator output is in high impedance: the

kernel circuitry is powered-down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after RESET. It is disabled in Standby Mode, providing high

impedance output.

Low-power modes

The STM32F101xx access line supports three low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

■

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

■

Stop mode

Stop mode allows to achieve the lowest power consumption while retaining the content

of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI

and the HSE RC oscillators are disabled. The voltage regulator can also be put either in

normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output or the RTC alarm.

■

Standby mode

The Standby mode allows to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby

mode, SRAM and registers content are lost except for registers in the Backup domain

and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

2

The DMA can be used with the main peripherals: SPI, I C, USART, general purpose timers

TIMx and ADC.

10/64

STM32F101xx

Description

RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V_BATpin. The backup registers (ten 16-bit registers)

V

DD

can be used to store data when V power is not present.

DD

The Real-Time Clock provides a set of continuously running counters which can be used

with suitable software to provide a clock calendar function, and provides an alarm interrupt

and a periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low

power RC oscillator or the high-speed external clock divided by 128. The internal low power

RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512Hz

output to compensate for any natural quartz deviation. The RTC features a 32-bit

programmable counter for long term measurement using the Compare register to generate

an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to

generate a time base of 1 second from a clock at 32.768 kHz.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to

reset the device when a problem occurs, or as a free running timer for application time out

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It

features:

■

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0.

Programmable clock source

General purpose timers (TIMx)

There are up to 3 synchronizable standard timers embedded in the STM32F101xx access

line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit

prescaler and feature 4 independent channels each for input capture, output compare, PWM

or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on

the largest packages. They can work together via the Timer Link feature for synchronization

or event chaining.

The counter can be frozen in debug mode.

Any of the standard timers can be used to generate PWM outputs. Each of the timers has

independent DMA request generations.

11/64

Description

STM32F101xx

I²C bus

Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support

standard and fast modes.

They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master

mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

Universal synchronous/asynchronous receiver transmitter (USART)

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware

management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816

compliant and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-

duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

GPIOs (general purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as Peripheral Alternate Function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

ADC (analog to digital converter)

The 12-bit Analog to Digital Converter has up to 16 external channels and performs

conversions in single-shot or scan modes. In scan mode, automatic conversion is performed

on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

Temperature sensor

The temperature sensor has to generate a linear voltage with any variation in temperature.

The conversion range is between 2V < V

< 3.6V. The temperature sensor is internally

DDA

connected to the ADC_IN16 input channel which is used to convert the sensor output

voltage into a digital value.

12/64

STM32F101xx

Description

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a

specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

Figure 1.

STM32F101xx access line block diagram

Trace

Controller

JTAG & SWD

pbus

POWER

V

= 2 to 3.6V

DD

V_SS

VOLT. REG.

3.3V TO 1.8V

JNTRST

Ibus

JTDI

JTCK/SWCLK

JTMS/SWDIO

JTDO

Cortex M3 CPU

FLASH 128 KB

64 bit

@VDD

F_max: 36 MHz

NVIC

Dbus

as AF

SRAM

16 KB

NVIC

System

@VDD

OSC_IN

OSC_OUT

PCLK1

PCLK2

HCLK

FCLK

PLL &

XTAL OSC

4-16 MHz

GP DMA

CLOCK

MANAGT

7 channels

RC 8 MHz

RC 32 kHz

@VDDA

IWDG

@VDDA

Standby

interface

SUPPLY

SUPERVISION

V_BAT

NRST

VDDA

VSSA

@VBAT

Rst

Int

POR / PDR

PVD

OSC32_IN

OSC32_OUT

XTAL 32 kHz

Backup

RTC

AWU

AHB2

APB2

AHB2

APB1

ANTI_TAMP

reg

Backup interface

EXTI

80AF

WAKEUP

4 Channels

TIM2

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

TIM3

4 Channels

TIM4

RX,TX, CTS, RTS,

SmartCard as AF

USART2

USART3

RX,TX, CTS, RTS,

SmartCard as AF

MOSI,MISO,SCK,NSS

as AF

SPI2

2x(8x16bit)

I2C1

I2C2

SCL,SDA,SMBAL

as AF

MOSI,MISO,

SCK,NSS as AF

SPI1

SCL,SDA

as AF

RX,TX, CTS, RTS,

SmartCard as AF

USART1

@VDDA

16AF

V_REF+

12bit ADC1

IF

W W D G

V_REF-

Temp sensor

ai14385

1. AF = alternate function on I/O port pin.

2. TA = –40 °C to +85 °C (junction temperature up to 125 °C).

13/64

Pin descriptions

STM32F101xx

3

Pin descriptions

Figure 2.

STM32F101xx access line LQFP100 pinout

PE2

PE3

PE4

PE5

PE6

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD_2

VSS_2

NC

PA 13

PA 12

PA 11

PA 10

PA 9

PA 8

PC9

PC8

PC7

VBAT

PC13-ANTI_TAMP

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VDD_5

LQFP100

OSC_IN

OSC_OUT

NRST

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PD8

PB15

PB14

PB13

PB12

PA0-WKUP

PA1

PA2

ai14386

14/64

STM32F101xx

Pin descriptions

Figure 3.

STM32F101xx access line LQFP64 pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDD_2

VBAT

PC13-ANTI_TAMP

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

2

3

4

5

6

7

PC0

PC1

PC2

PC3

8

LQFP64

9

10

11

12

13

14

15

16

PC6

VSSA

VDDA

PA0-WKUP

PA1

PB15

PB14

PB13

PB12

PA2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

ai14387

Figure 4.

STM32F101xx access line LQFP48 pinout

48 47 46 45 44 43 42 41 40 39 38 37

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

36

1

2

3

4

5

6

7

8

9

VBAT

PC13-ANTI_TAMP

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

35

34

33

32

31

30

29

28

27

26

25

LQFP48

PA8

VSSA

VDDA

PB15

PB14

PB13

PB12

PA0-WKUP 10

PA1 11

12

PA2

24

13 14 15 16 17 18 19 20 21 22 23

ai14378

15/64

Pin descriptions

STM32F101xx

Table 3.

Pins

Pin definitions

Main

Pin name

function⁽³⁾

(after reset)

Default alternate functions⁽³⁾

FT

-

1

2

3

4

5

6

7

PE2/TRACECK

PE3/TRACED0

PE4/TRACED1

PE5/TRACED2

PE6/TRACED3

V_BAT

I/O

S

PE2

PE3

PE4

PE5

PE6

V_BAT

PC13

TRACECK

TRACED0

TRACED1

TRACED2

TRACED3

-

1

2

1

2

PC13-ANTI_TAMP⁽⁴⁾

I/O

ANTI_TAMP

PC14-

OSC32_IN

3

4

3

4

8

9

PC14-OSC32_IN⁽⁴⁾

I/O

PC15-

OSC32_OUT

PC15-OSC32_OUT⁽⁴⁾

-

10

11

12

13

14

15

16

17

18

19

20

21

22

V_{SS_5}

V_{DD_5}

S

V_{SS_5}

V_{DD_5}

OSC_IN

OSC_OUT

NRST

PC0

5

6

7

-

5

OSC_IN

I

6

OSC_OUT

NRST

O

7

I/O

S

8

PC0/ADC_IN10

PC1/ADC_IN11

PC2/ADC_IN12

PC3/ADC_IN13

V_SSA

ADC_IN10

ADC_IN11

ADC_IN12

ADC_IN13

-

9

PC1

-

10

11

12

-

PC2

-

PC3

8

-

V_SSA

VREF-

S

VREF-

VREF+

V_DDA

-

VREF+

S

9

13

V_DDA

S

PA0-WKUP/USART2_CTS/

ADC_IN0/TIM2_CH1_ETR

WKUP/USART2_CTS⁽⁷⁾/ ADC_IN0/

TIM2_CH1_ETR⁽⁷⁾

10 14

11 15

12 16

13 17

23

24

25

26

I/O

PA0

PA1

PA2

PA3

PA1/USART2_RTS/ADC_

IN1/TIM2_CH2

USART2_RTS⁽⁷⁾/ADC_IN1/

TIM2_CH2⁽⁷⁾

PA2/USART2_TX/ADC_IN2/

TIM2_CH3

USART2_TX⁽⁷⁾/ADC_IN2/

TIM2_CH3⁽⁷⁾

PA3/USART2_RX/ADC_IN3/

TIM2_CH4

USART2_RX⁽⁷⁾/ADC_IN3/

TIM2_CH4⁽⁷⁾

-

18

19

27

28

V_{SS_4}

V_{DD_4}

S

V_{SS_4}

V_{DD_4}

16/64

STM32F101xx

Pin descriptions

Table 3.

Pins

Pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Default alternate functions⁽³⁾

PA4/SPI1_NSS/

USART2_CK/ADC_IN4

SPI1_NSS/USART2_CK⁽⁷⁾

ADC_IN4

/

14 20

15 21

16 22

29

30

31

I/O

PA4

PA5

PA6

PA5/SPI1_SCK/ADC_IN5

SPI1_SCK/ADC_IN5

PA6/SPI1_MISO/ADC_IN6/

TIM3_CH1

SPI1_MISO/ADC_IN6/

TIM3_CH1⁽⁷⁾

PA7/SPI1_MOSI/ADC_IN7/

TIM3_CH2

SPI1_MOSI/ADC_IN7/

TIM3_CH2⁽⁷⁾

17 23

32

I/O

PA7

-

24

25

33

34

35

36

37

38

39

40

41

42

43

44

45

46

PC4/ADC_IN14

I/O

PC4

PC5

ADC_IN14

ADC_IN15

PC5/ADC_IN15

18 26

19 27

20 28

PB0/ADC_IN8/TIM3_CH3

PB0

ADC_IN8/TIM3_CH3⁽⁷⁾

ADC_IN9/TIM3_CH4⁽⁷⁾

PB1/ADC_IN9/TIM3_CH4

PB1

PB2/BOOT1

PE7

FT

PB2/BOOT1

PE7

-

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PE10

PE11

PE12

PE13

PE14

PE15

PB10/I2C2_SCL

USART3_TX

21 29

22 30

47

48

I/O

FT

PB10

PB11

I2C2_SCL⁽⁵⁾/USART3_TX^{(5) (7)}

I2C2_SDA⁽⁵⁾/USART3_RX^{(5) (7)}

PB11/I2C2_SDA

USART3_RX

23 31

24 32

49

50

V_{SS_1}

V_{DD_1}

S

V_{SS_1}

V_{DD_1}

PB12/SPI2_NSS/

I2C2_SMBAl/USART3_CK

SPI2_NSS^{(5) (7)}/I2C2_SMBAl⁽⁵⁾

USART3_CK^{(5) (7)}

/

25 33

26 34

51

52

53

I/O

FT

PB12

PB13

PB14

PB13/SPI2_SCK/

USART3_CTS

SPI2_SCK⁽⁵⁾⁽⁷⁾/USART3_CTS⁽⁵⁾⁽⁷⁾

PB14/SPI2_MISO/

USART3_RTS

27 35

28 36

SPI2_MISO⁽⁵⁾⁽⁷⁾/USART3_RTS⁽⁵⁾⁽⁷⁾

SPI2_MOSI^{(5) (7)}

54

55

PB15/SPI2_MOSI

PD8

I/O

FT

PB15

PD8

-

17/64

Pin descriptions

STM32F101xx

Table 3.

Pins

Pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Default alternate functions⁽³⁾

-

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

PD9

I/O

FT

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PC6

-

PD10

PD11

-

PD12

-

PD13

-

PD14

-

PD15

37

38

39

40

PC6

PC7

PC8

-

PC9

29 41

30 42

31 43

32 44

33 45

34 46

PA8/USART1_CK/MCO

PA9/USART1_TX

PA10/USART1_RX

PA11/USART1_CTS

PA12/USART1_RTS

PA13/JTMS/SWDIO

PA8

USART1_CK/MCO

USART1_TX⁽⁷⁾

USART1_RX⁽⁷⁾

USART1_CTS

USART1_RTS

PA13

PA9

PA10

PA11

PA12

FT JTMS-SWDIO

Not connected

V_{SS_2}

-

35 47

36 48

37 49

38 50

V_{SS_2}

V_{DD_2}

S

V_{DD_2}

PA14/JTCK/SWCLK

PA15/JTDI

PC10

I/O

FT JTCK/SWCLK

PA14

PA15

FT

JTDI

PC10

-

51

52

53

5

PC11

-

PC12

5

6

PD0

OSC_IN⁽⁶⁾

OSC_OUT⁽⁶⁾

PD2

6

PD1

54

-

PD2/TIM3_ETR

PD3

TIM3_ETR

-

PD3

-

PD4

-

PD5

-

PD6

18/64

STM32F101xx

Pin descriptions

Table 3.

Pins

Pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Default alternate functions⁽³⁾

-

88

89

90

91

92

93

94

95

96

97

98

99

PD7

PB3/JTDO/TRACESWO

PB4/JNTRST

I/O

I

FT

PD7

JTDO

JNTRST

PB5

39 55

40 56

41 57

42 58

43 59

44 60

45 61

46 62

PB3/TRACESWO

PB4

PB5/I2C1_SMBAl

PB6/I2C1_SCL/TIM4_CH1

PB7/I2C1_SDA/TIM4_CH2

BOOT0

I2C1_SMBAl

FT

PB6

I2C1_SCL⁽⁷⁾/TIM4_CH1^{(5) (7)}

I2C1_SDA⁽⁷⁾/TIM4_CH2^{(5) (7)}

PB7

BOOT0

PB8

PB8/TIM4_CH3

PB9/TIM4_CH4

PE0/TIM4_ETR

PE1

I/O

S

FT

TIM4_CH3^{(5) (7)}

TIM4_CH4^{(5) (7)}

TIM4_ETR⁽⁵⁾

PB9

-

PE0

PE1

47 63

V_{SS_3}

V_{DD_3}

48 64 100

V_{DD_3}

S

1. I = input, O = output, S = supply, HiZ= high impedance.

2. FT= 5 V tolerant.

3. Function availability depends on the chosen device. Refer to Table 2 on page 7.

4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used

only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.

5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.

6. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,

however the functionality of PD0 and PD1 can be remapped by software on these pins.

7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more

details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,

UM0306, available from the STMicroelectronics website: www.st.com.

19/64

Memory mapping

STM32F101xx

4

Memory mapping

The memory map is shown in Figure 5.

Figure 5.

Memory map

APB memory space

0xFFFF FFFF

reserved

0xE010 0000

0x6000 0000

0x4002 3400

0x4002 3000

0x4002 2400

0x4002 2000

0x4002 1400

0x4002 1000

0x4002 0400

0x4002 0000

4K

1K

3K

0xFFFF FFFF

0xFFFF F000

1K

3K

1K

3K

1K

Flash interface

reserved

RCC

7

0xE010 0000

Cortex-M3 internal

peripherals

reserved

DMA

0xE000 0000

reserved

1K

6

0x4001 3C00

0x4001 3800

0x4001 3400

0x4001 3000

0x4001 2C00

0x4001 2800

0x4001 2400

1K

USART1

reserved

SPI1

0xC000 0000

1K

reserved

ADC1

5

0xA000 0000

reserved

2K

0x4001 1C00

0x4001 1800

0x4001 1400

0x4001 1000

0x4001 0C00

0x4001 0800

0x4001 0400

0x4001 0000

1K

Port E

Port D

Port C

Port B

Port A

EXTI

4

0x1FFF FFFF

0x1FFF F9FF

reserved

0x8000 0000

Option bytes

0x1FFF F800

1K

System memory

1K

3

AFIO

0x1FFF F000

0x6000 0000

reserved

35K

0x4000 7400

0x4000 7000

0x4000 6C00

0x4000 6800

0x4000 6400

0x4000 6000

0x4000 5C00

0x4000 5800

0x4000 5400

PWR

1K

2

BKP

reserved

1K

reserved

Peripherals

0x4000 0000

1

I2C2

I2C1

1K

2K

SRAM

0x2000 0000

0x0801 FFFF

0x0800 0000

reserved

0x4000 4C00

0x4000 4800

0x4000 4400

USART3

USART2

1K

Flash memory

0

Code

reserved

SPI2

2K

0x0000 0000

0x4000 3C00

0x4000 3800

0x4000 3400

0x4000 3000

0x4000 2C00

0x4000 2800

1K

reserved

IWDG

Reserved

WWDG

RTC

reserved

7K

0x4000 0C00

0x4000 0800

0x4000 0400

0x4000 0000

TIM4

TIM3

TIM2

1K

ai14379

20/64

STM32F101xx

Electrical characteristics

5

Electrical characteristics

5.1

Test conditions

Unless otherwise specified, all voltages are referred to V

.

SS

5.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean±3Σ).

5.1.2

5.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the

A

DD

2 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean±2Σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

5.1.4

5.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 6.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 7.

21/64

Electrical characteristics

Figure 6.

STM32F101xx

Pin loading conditions

Figure 7.

Pin input voltage

STM32F101 PIN

C=50pF

V

IN

ai14123

ai14124

5.1.6

Power supply scheme

Figure 8.

Power supply scheme

V

3.3 V

BAT

Backup circuitry

(OSC32K,RTC,

Wake-up logic

Power switch

1.8-3.6V

Backup registers)

OUT

IN

IO

Logic

GP I/Os

Kernel logic

(CPU,

Digital

& Memories)

V

DD

V

DD

1/2/3/4/5

Regulator

5 × 100 nF

+ 1 × 10 µF

V

SS

1/2/3/4/5

3.3V

V

DD

V

DDA

V

REF

V

REF+

Analog:

RCs, PLL,

...

10 nF

+ 1 µF

10 nF

+ 1 µF

V

ADC

REF-

V

SSA

ai14125

22/64

STM32F101xx

Electrical characteristics

5.1.7

Current consumption measurement

Figure 9.

Current consumption measurement scheme

I

_V

DD BAT

V

BAT

I

DD

V

DD

V

DDA

ai14126

23/64

Electrical characteristics

STM32F101xx

5.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics,

Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device

at these conditions is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Table 4.

Symbol

Voltage characteristics

Ratings

Min

Max

Unit

External 3.3 V supply voltage (including

V_DD−V_SS

−0.3

4.0

(1)

V_DDAand V_DD

)

V

Input voltage on five volt tolerant pin⁽²⁾

Input voltage on any other pin⁽²⁾

V

_SS−0.3

+5.5

V_DD+0.3

50

V_IN

V_SS−0.3

|∆V_DDx

|

Variations between different power pins

50

mV

Variations between all the different ground

pins

|V_SSX−V_SS

|

50

see Section 5.3.11:Absolute

maximum ratings (electrical

sensitivity)

Electrostatic discharge voltage (human

body model)

V_ESD(HBM)

1. All 3.3 V power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external 3.3 V

supply.

2. I_INJ(PIN)must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if V_IN

maximum is respected. If V_INmaximum cannot be respected, the injection current must be limited

externally to the I_INJ(PIN)value. A positive injection is induced by V_IN>V_DDwhile a negative injection is

induced by V_IN<V_SS

.

Table 5.

Symbol

I_VDD

I_VSS

Current characteristics

Ratings

Max.

Unit

Total current into V_DDpower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on NRST pin

150

25

I_IO

−25

± 5

mA

Injected current on High-speed external OSC_IN and Low-

speed external OSC_IN pins

(2)(3)

I_INJ(PIN)

± 5

Injected current on any other pin⁽⁴⁾

± 5

(2)

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁴⁾

± 25

1. All 3.3 V power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external 3.3 V

supply.

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS

.

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC

characteristics.

4. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterization with ΣI_INJ(PIN)maximum current injection on four I/O port pins of the device.

24/64

STM32F101xx

Electrical characteristics

Table 6.

Symbol

T_STG

T_J

Thermal characteristics

Ratings

Storage temperature range

Value

Unit

–65 to +150

°C

Maximum junction temperature (see Thermal characteristics)

25/64

Electrical characteristics

STM32F101xx

5.3

Operating conditions

5.3.1

General operating conditions

Table 7.

Symbol

General operating conditions

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK1

f_PCLK2

V_DD

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Backup operating voltage

0

36

MHz

0

36

2

3.6

85

V

V_BAT

T_A

1.8

−40

Ambient temperature range

°C

5.3.2

Operating conditions at power-up / power-down

The parameters given in Table 8 are derived from tests performed under the ambient

temperature condition summarized in Table 7.

Table 8.

Symbol

Operating conditions at power-up / power-down

Parameter

Conditions

Min Typ Max Unit

20

µs/V

t_VDD

V_DDrise/fall time

20 ms/V

26/64

STM32F101xx

Electrical characteristics

5.3.3

Embedded reset and power control block characteristics

The parameters given in Table 9 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 7.

DD

.

Table 9.

Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

2.1 2.18 2.26

2.08 2.16

V

2

2.19 2.28 2.37

2.09 2.18 2.27

2.28 2.38 2.48

2.18 2.28 2.38

2.38 2.48 2.58

2.28 2.38 2.48

2.47 2.58 2.69

2.37 2.48 2.59

2.57 2.68 2.79

2.47 2.58 2.69

2.66 2.78 2.9

2.56 2.68 2.8

V

Programmable voltage

detector level selection

V_PVD

V

2.76 2.88

3

V

2.66 2.78 2.9

100

V

V_PVDhyst

V_POR/PDR

V_PDRhyst

PVD hysteresis

mV

V

Falling edge

Rising edge

1.8 1.88 1.96

1.84 1.92 2.0

40

Power on/power down reset

threshold

V

PDR hysteresis

mV

ms

t_RSTTEMPOReset temporization

1.5 2.5 3.5

5.3.4

Embedded reference voltage

The parameters given in Table 10 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 7.

DD

Table 10. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Typ Max Unit

V_REFINTInternal reference voltage

-45 °C < T_A< +85 °C

1.16 1.20 1.24

V

27/64

Electrical characteristics

STM32F101xx

5.3.5

Supply current characteristics

The current consumption is measured as described in Figure 9: Current consumption

measurement scheme.

Maximum current consumption

The MCU is placed under the following conditions:

■

All I/O pins are in input mode with a static value at V or V (no load)

DD SS

All peripherals are disabled except if it is explicitly mentioned

The Flash access time is adjusted to f

wait state from 24 to 36 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

The parameters given in Table 11 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 7.

DD

(1)

Table 11. Maximum current consumption in Run and Sleep modes (T = 85 °C)

A

Symbol

Parameter

Conditions

F_HCLKTyp ⁽²⁾Max⁽³⁾Unit

External clock with PLL, code running from

Flash, all peripherals enabled (see RCC register

description): f_PCLK1= f_HCLK/2, f_PCLK2=f_HCLK

36 MHz

24 MHz

22

21

TBD

External clock, PLL stopped, code running from

Flash, all peripherals enabled (see RCC register

description): f_PCLK1= f_HCLK/2, f_PCLK2=f_HCLK

8 MHz

10

TBD

Supply current in

Run mode

External clock with PLL, code running from RAM, 36 MHz

all peripherals enabled (see RCC register

description): f_PCLK1= f_HCLK/2, f_PCLK2=f_HCLK

13

11

18

15

24 MHz

I_DD

External clock, PLL stopped, code running from

mA

RAM, all peripherals enabled (see RCC register

description): f_PCLK1= f_HCLK/2, f_PCLK2=f_HCLK

8 MHz

4.5

TBD

External clock with PLL, code running from RAM 36 MHz

or Flash, all peripherals enabled (see RCC

13

10

22

17

register description): f_PCLK1= f_HCLK/2,

24 MHz

f_PCLK2=f_HCLK

Supply current in

Sleep mode

External clock, PLL stopped, code running from

RAM or Flash, all peripherals enabled (see RCC

register description): f_PCLK1= f_HCLK/2,

8 MHz

3.5

TBD

f_PCLK2=f_HCLK

1. TBD stands for to be determined.

2. Typical values are measured at T_A= 25 °C, and V_DD= 3.3 V.

3. Data based on characterization results, tested in production at V_Dmax, f_HCLKmax. T_Amax,and code executed from RAM.

28/64

STM32F101xx

Electrical characteristics

(1)

Table 12. Maximum current consumption in Stop and Standby modes

Typ⁽²⁾

_DD/ V_BATV_{DD VBAT}

Max⁽³⁾

Symbol

Parameter

Conditions

Unit

V

/

T_A= 85 °C

= 2.4 V

= 3.3 V

Regulator in Run mode,

Low-speed and high-speed internal

RC oscillators and high-speed

oscillator OFF (no independent

watchdog)

TBD

24

TBD

Supply current in

Stop mode

Regulator in Low Power mode,

Low-speed and high-speed internal

RC oscillators and high-speed

oscillator OFF (no independent

watchdog)

I_DD

TBD⁽⁴⁾

14⁽⁴⁾

TBD⁽⁴⁾

µA

Low-speed internal RC oscillator and

independent watchdog OFF, low-

speed oscillator and RTC OFF

Supply current in

Standby mode⁽⁵⁾

TBD⁽⁴⁾

2⁽⁴⁾

TBD⁽⁴⁾

I_{DD_VBA}

Backup domain

supply current

Low-speed oscillator and RTC ON

1⁽⁴⁾

1.4⁽⁴⁾

T

1. TBD stands for to be determined.

2. Typical values are measured at T_A= 25 °C, V_DD= 3.3 V, unless otherwise specified.

3. Data based on characterization results, tested in production at V_{DD max}, f_HCLKmax. and T_Amax.

4. Values expected for next silicon revision.

5. To have the Standby consumption with RTC ON, add I_{DD_VBAT}(Low-speed oscillator and RTC ON) to I_DDStandby (when

_DDis present the Backup Domain is powered by V_DDsupply).

V

29/64

Electrical characteristics

STM32F101xx

Typical current consumption

The MCU is placed under the following conditions:

■

All I/O pins are in input mode with a static value at V or V (no load)

DD SS

All peripherals are disabled except if it is explicitly mentioned

The Flash access time is adjusted to f

wait state from 24 to 36 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

The parameters given in Table 13 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 7.

DD

(1)

Table 13. Typical current consumption in Run and Sleep modes

Symbol

Parameter

Conditions

f_HCLK

Typ⁽²⁾

Unit

36 MHz

24 MHz

16 MHz

8 MHz

TBD

13

Oscillator running at 8 MHz with PLL, code running

from Flash, all peripheral disabled (see RCC register

description): f_PCLK1= f_HCLK/2, f_PCLK2= f_HCLK

mA

TBD

7.8

4 MHz

7

Running on HSI clock, code running from Flash, all

peripheral disabled (see RCC register description):

f_PCLK1= f_HCLK/2, f_PCLK2= f_HCLK.AHB pre-scaler used

2 MHz

6.3

mA

1 MHz

6.2

to reduce the frequency

Supply current in

Run mode

500 kHz

125 kHz

8 MHz

6.1

5.95

2.3

4 MHz

1.6

Running on HSI clock, code running from RAM, all

peripheral disabled (see RCC register description):

f_PCLK1= f_HCLK/2, f_PCLK2= f_HCLK.AHB pre-scaler used

I_DD

2 MHz

1.2

mA

1 MHz

1

to reduce the frequency

500 kHz

125 kHz

36 MHz

24 MHz

16 MHz

8 MHz

0.88

0.82

TBD

1

Oscillator running at 8 MHz with PLL, code running

from Flash, all peripheral disabled (see RCC register

description): f_PCLK1= f_HCLK/2, f_PCLK2= f_HCLK

mA

TBD

Supply current in

Sleep mode

Running on HSI clock, code running from Flash, all

peripheral disabled (see RCC register description):

f_PCLK1= f_HCLK/2, f_PCLK2= f_HCLK.AHB pre-scaler used

4 MHz

2 MHz

1 MHz

to reduce the frequency

500 kHz

1. TBD stands for to be determined.

2. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

30/64

STM32F101xx

Electrical characteristics

(1)

Table 14. Typical current consumption in Stop and Standby modes

Typ⁽²⁾

V_DD

Symbol

Parameter

Conditions

Unit

Regulator in Run mode,

3.3 V

24

Low-speed and high-speed internal RC

oscillators OFF

High-speed oscillator OFF (no

independent watchdog)

2.4 V

3.3 V

2.4 V

TBD

14⁽³⁾

Supply current in Stop

mode

µA

Regulator in Low Power mode,

Low-speed and high-speed internal RC

oscillators OFF,

High-speed oscillator OFF (no

independent watchdog)

TBD⁽³⁾

I_DD

3.3 V

2.4 V

3.3 V

2.4 V

3.3 V

2.4 V

3.3 V

2.4 V

3.3 V

2.4 V

2⁽³⁾

Low-speed internal RC oscillator and

independent watchdog OFF

TBD⁽³⁾

3.1⁽³⁾

TBD⁽³⁾

2.9⁽³⁾

TBD⁽³⁾

1.4⁽³⁾

1⁽³⁾

Supply current in

Standby mode⁽⁴⁾

Low-speed internal RC oscillator and

independent watchdog ON

µA

Low-speed internal RC oscillator ON,

independent watchdog OFF

Low-speed oscillator and RTC ON

Low-speed oscillator OFF, RTC ON

Backup domain

supply current

I_{DD_VBAT}

0.5⁽³⁾

TBD⁽³⁾

1. TBD stands for to be determined.

2. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

3. Values expected for next silicon revision.

4. To obtain Standby consumption with RTC ON, add I_DD_V_BAT(Low-speed oscillator, RTC ON) to I_DDStandby.

31/64

Electrical characteristics

STM32F101xx

5.3.6

External clock source characteristics

High-speed user external clock

The characteristics given in Table 15 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 7.

Table 15. High-speed user external (HSE) clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency⁽¹⁾

f_{HSE_ext}

8

25

MHz

OSC_IN input pin high level

voltage

V_HSEH

V_HSEL

0.7V_DD

V_SS

V_DD

V

OSC_IN input pin low level

voltage

0.3V_DD

t_w(HSE)

OSC_IN high or low time⁽¹⁾

OSC_IN rise or fall time⁽¹⁾

16

ns

t_r(HSE)

t_f(HSE)

5

OSC_IN Input leakage

current

I_L

V_SS≤ V_IN≤ V_DD

±1

µA

1. Value based on design simulation and/or technology characteristics. It is not tested in production.

Low-speed user external clock

The characteristics given in Table 16 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 7.

Table 16. Low-speed user external clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency⁽¹⁾

f_{LSE_ext}

32.768

1000

kHz

OSC32_IN input pin high level

voltage

V_LSEH

V_LSEL

t_w(LSE)

0.7V_DD

V_SS

V_DD

V

OSC32_IN input pin low level

voltage

0.3V_DD

OSC32_IN high or low time⁽¹⁾

OSC32_IN rise or fall time⁽¹⁾

450

t_w(LSE)

ns

t_r(LSE)

t_f(LSE)

5

OSC32_IN Input leakage

current

I_L

V_SS≤ V_IN≤ V_DD

±1

µA

1. Value based on design simulation and/or technology characteristics. It is not tested in production.

32/64

STM32F101xx

Electrical characteristics

Figure 10. High-speed external clock source AC timing diagram

V

HSEH

90%

10%

V

HSEL

t

W(HSE)

t

W(HSE)

r(HSE)

f(HSE)

T

HSE

f

HSE_ext

EXTERNAL

CLOCK SOURCE

I

L

OSC _IN

STM32F101

ai14127

Figure 11. Low-speed external clock source AC timing diagram

V

LSEH

90%

10%

V

LSEL

t

W(LSE)

t

W(LSE)

r(LSE)

f(LSE)

T

LSE

f

LSE_ext

EXTERNAL

CLOCK SOURCE

I

L

OSC32_IN

STM32F101

ai14140b

33/64

Electrical characteristics

STM32F101xx

High-speed external clock

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 17. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

(1)

Table 17. HSE 4-16 MHz oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_{OSC_IN}Oscillator frequency

4

8

16

MHz

R_F

Feedback resistor

200

kΩ

Recommended load capacitance

versus equivalent serial

C_L1

R_S= 30 Ω

30

pF

(2)

C_L2

resistance of the crystal (R_S)⁽³⁾

V_DD= 3.3 V

V_IN= V_SSwith 30 pF

load

i₂

HSE driving current

1

mA

g_m

Oscillator transconductance

Startup time

Startup

25

mA/V

ms

t_SU(HSE)

V_SSis stabilized

2

(4)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. For C_L1and C_L2it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.),

designed for high-frequency applications, and selected to match the requirements of the crystal or

resonator. C_L1and C_L2,are usually the same size. The crystal manufacturer typically specifies a load

capacitance which is the series combination of C_L1and C_L2. PCB and MCU pin capacitance must be

included when sizing C_L1and C_L2(10 pF can be used as a rough estimate of the combined pin and board

capacitance).

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a

humid environment, due to the induced leakage and the bias condition change. However, it is

recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

Figure 12. Typical application with an 8 MHz crystal

RESONATOR WITH

INTEGRATED CAPACITORS

C

L1

f

OSC_IN

HSE

Bias

controlled

gain

8 MHz

resonator

R

F

STM32F101xx

OSC_OUT

(1)

R

EXT

C

L2

ai14128

1. R_EXTvalue depends on the crystal characteristics. Typical value is in the range of 5 to 6R_S.

34/64

STM32F101xx

Electrical characteristics

Low-speed external clock

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 18. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

Table 18. LSE oscillator characteristics ( _LSE= 32.768 kHz)

f

Symbol

Parameter

Feedback resistor

Conditions

Min

Typ

Max

Unit

R_F

5

MΩ

Recommended load capacitance

versus equivalent serial

C_L1

C_L2

R_S= 30 KΩ

15

pF

µA

resistance of the crystal (R_S)⁽¹⁾

V_DD= 3.3 V

V_IN= V_SS

I₂

LSE driving current

1.4

g_m

Oscillator transconductance

Startup time

5

µA/V

s

(2)

t_SU(LSE)

V_SSis stabilized

3

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with

small R_Svalue for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details

2. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary

significantly with the crystal manufacturer

Figure 13. Typical application with a 32.768 kHz crystal

RESONATOR WITH

INTEGRATED CAPACITORS

C

L1

f

OSC32_IN

LSE

Bias

controlled

gain

32.768 KHz

resonator

R

F

STM32F101xx

OSC32_OUT

C

L2

ai14129

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Electrical characteristics

STM32F101xx

5.3.7

Internal Clock source characteristics

The parameters given in Table 19 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 7.

DD

High-speed internal (HSI) RC oscillator

(1)(2)

Table 19. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ

Max⁽³⁾

Unit

f_HSI

8

MHz

%

T_A= –40 to 85 °C

at T_A= 25 °C

TBD

1

±3

±1

TBD

2

ACC_HSIAccuracy of HSI oscillator

t_su(HSI)HSI oscillator startup time

%

µs

HSI oscillator power

I_DD(HSI)

80

100

µA

consumption

1.

V_DD= 3.3 V, T_A= −40 to 85 °C unless otherwise specified.

2. TBD stands for to be determined.

3. Values based on device characterization, not tested in production.

LSI Low Speed Internal RC Oscillator

(1)

Table 20. LSI oscillator characteristics

Max⁽²⁾

Symbol

Parameter

Frequency

Conditions

Min

Typ

Unit

f_LSI

30

60

85

kHz

µs

t_su(LSI)LSI oscillator start up time

LSI oscillator power

I_DD(LSI)

0.65

1.2

µA

consumption

1.

V_DD= 3 V, T_A= −40 to 85 °C unless otherwise specified.

2. Value based on device characterization, not tested in production.

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STM32F101xx

Electrical characteristics

Wakeup time from low power mode

The wakeup times given in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC

oscillator. The clock source used to wake up the device depends from the current operating

mode:

■

Stop or Standby mode: the clock source is the RC oscillator

Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V supply

DD

voltage conditions summarized in Table 7.

(1)

Table 21. Low-power mode wakeup timings

Symbol

Parameter

Conditions

Typ

Max Unit

(2)

Wakeup from Sleep mode

Wakeup on HSI RC clock

0.75 TBD

µs

t_WUSLEEP

Wakeup from Stop mode

(regulator in run mode)

HSI RC wakeup time = 2 µs

4

7

TBD

(2)

µs

t_WUSTOP

HSI RC wakeup time = 2 µs,

Regulator wakeup from LP

mode time = 5 µs

Wakeup from Stop mode

(regulator in low power mode)

HSI RC wakeup time = 2 µs,

Regulator wakeup from power

down time = 38 µs

(3)

t_WUSTDBY

Wakeup from Standby mode

40

TBD

µs

1. TBD stands for to be determined.

2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which

the user application code reads the first instruction.

3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device

exits from reset.

5.3.8

PLL characteristics

The parameters given in Table 22 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 7.

DD

(1)

Table 22. PLL characteristics

Value

Test

Symbol

Parameter

Unit

conditions

Min

Typ Max⁽²⁾

PLL input clock

8.0

MHz

%

f_{PLL_IN}

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

40

16

60

f_{PLL_OUT}

t_LOCK

36

MHz

µs

200

Cycle to cycle jitter (+/-3Σ peak to

peak)

t_JITTER

V_DDis stable

TBD

%

1. TBD stands for to be determined.

2. Data based on device characterization, not tested in production.

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Electrical characteristics

STM32F101xx

5.3.9

Memory characteristics

Flash memory

The characteristics are given at T = −40 to 85 °C unless otherwise specified.

A

(1)

Table 23. Flash memory characteristics

Symbol

Parameter

Conditions

Min

Typ

Max⁽²⁾Unit

t_prog

t_ERASE

t_ME

Word programming time

Page (1kB) erase time

Mass erase time

T_A= −40 to +85 °C

20

40

µs

ms

Read mode

f

_HCLK= 36MHz with

20

mA

2 wait states, V_DD

3.3 V

=

Write / Erase modes

f_HCLK= 36 MHz,

I_DD

Supply current

5

mA

µA

V_DD= 3.3 V

Power-down mode /

HALT,

50

V_DD=3.0 to 3.6 V

1. TBD stands for to be determined.

2. Values based on characterization and not tested in production.

Table 24. Flash endurance and data retention

Value

Symbol

Parameter

Conditions

Unit

Min⁽¹⁾

Typ

Max

N_ENDEndurance

t_RETData retention

10

kcycles

Years

1

T_A= 85° C

30

1. Values based on characterization not tested in production.

38/64

STM32F101xx

Electrical characteristics

5.3.10

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the

device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

■

Electrostatic Discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.

■

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 25. They are based on the EMS levels and classes

defined in application note AN1709.

(1)

Table 25. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD= 3.3 V, T_A=+25 °C,

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

V_FESD

f

_HCLK= 36 MHz

TBD

4A

conforms to IEC 1000-4-2

Fast transient voltage burst limits to be

applied through 100pF on V_DDand V_SSpins f_HCLK= 36 MHz

to induce a functional disturbance conforms to IEC 1000-4-4

V_DD= 3.3 V, T_A=+25 °C,

V_EFTB

1. TBD stands for to be determined.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre

qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

■

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

39/64

Electrical characteristics

STM32F101xx

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second. To complete these trials, ESD stress can be applied directly on the device, over the

range of specification values. When unexpected behavior is detected, the software can be

hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J

1752/3 standard which specifies the test board and the pin loading.

(1)

Table 26. EMI characteristics

Max vs.

[f_HSE/f_HCLK

]

Monitored

frequency band

Symbol Parameter

Conditions

Unit

8/36 MHz

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1GHz

SAE EMI Level

TBD

V

_DD= 3.3 V, T_A= 2 5°C,

dBµV

-

S_EMI

Peak level LQFP100 package compliant

with SAE J 1752/3

1. TBD stands for to be determined.

5.3.11

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size is

either 3 parts (cumulative mode) or 3 parts × (n + 1) supply pins (non-cumulative mode).

The human body model (HBM) can be simulated. The tests are compliant with JESD22-

A114A standard.

For more details, refer to the application note AN1181.

(1)

Table 27. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Maximum value⁽²⁾

Unit

Electrostatic discharge voltage (human

body model)

V_ESD(HBM)

2000

T_A= +25 °C

V

Electrostatic discharge voltage (charge

device model)

V_ESD(CDM)

TBD

1. TBD stands for to be determined.

2. Values based on characterization results, not tested in production.

40/64

STM32F101xx

Electrical characteristics

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up

performance:

■

A supply overvoltage is applied to each power supply pin

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78 IC latch-up standard.

Table 28. Electrical sensitivities

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T_A= +105 °C

II level A

41/64

Electrical characteristics

STM32F101xx

5.3.12

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 29 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 7.

All unused pins must be held at a fixed voltage, by using the I/O output mode, an external

pull-up or pull-down resistor (see Figure 14).

(1)

Table 29. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL

Input low level voltage⁽²⁾

–0.5

0.8

V

IO TC input high level

voltage⁽²⁾

TTL ports

2

V_DD+0.5

V_IH

IO FT high level voltage⁽²⁾

Input low level voltage⁽²⁾

Input high level voltage⁽²⁾

2

5.5V

V_IL

V_IH

–0.5

0.35 V_DD

V_DD+0.5

CMOS ports

V

0.65 V_DD

IO TC Schmitt trigger voltage

hysteresis⁽³⁾

200

mV

V_hys

IO TC Schmitt trigger voltage

hysteresis⁽³⁾

(4)

5% V_DD

V_SS≤V_IN≤V_DD

Standard I/Os

±1

3

I_lkg

Input leakage current ⁽⁴⁾

µA

V_IN= 5 V

5 V tolerant I/Os

Weak pull-up equivalent

resistor⁽⁵⁾

R_PU

V_IN= V_SS

V_IN= V_DD

30

40

50

kΩ

Weak pull-down equivalent

resistor⁽⁶⁾

R_PD

C_IO

40

5

kΩ

I/O pin capacitance

pF

1. V_DD= 3.3 V, T_A= −40 to 85 °C unless otherwise specified.

2. Values based on characterization results, and not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. With a minimum of 100 mV.

5. Leakage could be higher than max. if negative current is injected on adjacent pins.

6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable

PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).

42/64

STM32F101xx

Electrical characteristics

Figure 14. Unused I/O pin connection

V

DD

STM32F101

10 kΩ

UNUSED I/O PORT

STM32F101

UNUSED I/O PORT

10 kΩ

ai14130

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink

+20 mA (with a relaxed V ).

OL

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 5.2:

■

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

I

(see Table 5).

VDD

■

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

I

(see Table 5).

VSS

43/64

Electrical characteristics

STM32F101xx

Output voltage levels

Unless otherwise specified, the parameters given in Table 30 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 7.

Table 30. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Output Low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)

0.4

V_OL

TTL port, I_IO

+8 mA,

2.7 V < V_DD< 3.6 V

=

V

Output High level voltage for an I/O pin

when 4 pins are sourced at same time

(2)

V_DD–0.4

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)

0.4

1.3

0.4

V_OL

CMOS port

I_IO= +8 mA

V

Output high level voltage for an I/O pin

when 4 pins are sourced at same time

(2)

2.7 V < V_DD< 3.6 V

2.4

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)

V_OL

I_IO= +20 mA

2.7 V < V_DD< 3.6 V

Output high level voltage for an I/O pin

when 4 pins are sourced at same time

(2)

V

_DD–1.3

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)

V_OL

I_IO= +6 mA

2 V < V_DD< 2.7 V

Output high level voltage for an I/O pin

when 4 pins are sourced at same time

(2)

V_DD–0.4

V_OH

1. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 5

and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in

Table 5 and the sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

44/64

STM32F101xx

Electrical characteristics

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 15 and

Table 31, respectively.

Unless otherwise specified, the parameters given in Table 31 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 7.

(1)

Table 31. I/O AC characteristics

I/O

Symbol

Parameter

Conditions

Max Unit

mode⁽¹⁾

f_max(IO)outMaximum frequency⁽²⁾

C_L= 50 pF, V_DD= 2 V to 3.6 V

2

MHz

ns

Output high to low level fall

t_f(IO)out

125

10

time⁽³⁾

C_L= 50 pF, V_DD= 2 V to 3.6 V

Output low to high level rise

t_r(IO)out

125

time⁽³⁾

f_max(IO)outMaximum frequency⁽²⁾

10 MHz

Output high to low level fall

t_f(IO)out

t_r(IO)out

25

ns

25

01

time⁽³⁾

Output low to high level rise

time⁽³⁾

C_L= 30 pF, V_DD= 2.7 V to 3.6 V 50 MHz

C_L= 50 pF, V_DD= 2.7 V to 3.6 V 30 MHz

F_max(IO)outMaximum Frequency⁽²⁾

C_L= 50 pF, V_DD= 2 V to 2.7 V

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

20 MHz

5

8

Output high to low level fall

11

t_f(IO)out

time⁽³⁾

12

ns

5

Output low to high level rise

t_r(IO)out

8

time⁽³⁾

12

Pulse width of external signals

t_EXTIpw

-

10

ns

detected by the EXTI controller

1. Refer to the Reference user manual UM0306 for a description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 15.

3. Values based on design simulation and validated on silicon, not tested in production.

45/64

Electrical characteristics

STM32F101xx

Figure 15. I/O AC characteristics definition

90%

10 %

50%

90%

10%

t

EXTERNAL

OUTPUT

ON 50pF

t

r(IO)out

T

Maximum frequency is achieved if (t + t ) £ 2/3)T and if the duty cycle is (45-55%)

r

f

when loaded by 50pF

ai14131

46/64

STM32F101xx

Electrical characteristics

5.3.13

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, R (see Table 29).

PU

Unless otherwise specified, the parameters given in Table 32 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 7.

(1)

Table 32. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL(NRST)NRST Input low level voltage

V_IH(NRST)NRST Input high level voltage

–0.5

2

0.8

V

V_DD+0.5

NRST Schmitt trigger voltage

V_hys(NRST)

hysteresis

200

40

R_PU

Weak pull-up equivalent resistor⁽²⁾

V_IN= V_SS

30

50

kΩ

ns

µs

V_F(NRST)NRST Input filtered pulse⁽³⁾

V_NF(NRST)NRST Input not filtered pulse⁽³⁾

1. TBD stands for to be determined.

100

300

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance must be minimum (~10% order).

3. Values guaranteed by design, not tested in production.

Figure 16. Recommended NRST pin protection

V

DD

External

reset circuit

R

PU

Internal Reset

NRST

FILTER

0.1 µF

STM32F101xx

ai14132b

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 32. Otherwise the reset will not be taken into account by the device.

47/64

Electrical characteristics

STM32F101xx

5.3.14

TIM timer characteristics

Unless otherwise specified, the parameters given in Table 33 are derived from tests

performed under ambient temperature, f

frequency and V supply voltage conditions

PCLKx

DD

summarized in Table 7.

Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 33. TIMx characteristics

TIMx⁽¹⁾

Symbol

Parameter

Conditions

Min

Max

Unit

t_TIMxCLK

ns

1

27.8

0

Timer resolution

time

t_res(TIM)

x = 2, 3, 4

f_TIMxCLK= 36 MHz

Timer external clock

frequency on CH1 to x = 2, 3, 4

CH4

f

_TIMxCLK/2

MHz

f_EXT

f

_TIMxCLK= 36 MHz

0

18

16

Res_TIM

Timer resolution

bit

16-bit counter clock

period when internal x = 2, 3, 4

clock is selected

t_TIMxCLK

1

65536

1820

t_COUNTER

f_TIMxCLK= 36 MHz

0.0278

µs

t_TIMxCLK

s

65536 ×

65536

Maximum possible

x = 2, 3, 4

t_{MAX_COUNT}

count

f_TIMxCLK= 36 MHz

119.2

1. x gives the TIM concerned; where x = 2, TIM2 is concerned, etc.

48/64

STM32F101xx

Electrical characteristics

5.3.15

Communications interfaces

I²C interface characteristics

Unless otherwise specified, the parameters given in Table 34 are derived from tests

performed under ambient temperature, f

frequency and V supply voltage conditions

PCLK1

DD

summarized in Table 7.

2

The STM32F101xx access line I C interface meets the requirements of the standard I C

communication protocol with the following restrictions: t

he I/O pins SDA and SCL are

mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected

between the I/O pin and V is disabled, but is still present. In addition, there is a protection

DD

diode between the I/O pin and V . As a consequence, when multiple master devices are

DD

2

I C

connected to the

bus, it is not possible to power off the STM32F101xx while another

master node remains powered on. Otherwise, the ST device would be powered by the

protection diode.

2

The I C characteristics are described in Table 34. Refer also to

Section 5.3.12: I/O port

for more details on the input/output alternate function characteristics (SDA

characteristics

and SCL)

.

2

Table 34. I C characteristics

Symbol Parameter

Standard mode I²C⁽¹⁾Fast mode I²C⁽¹⁾⁽²⁾

Unit

Min

Max

Min

Max

t_w(SCLL)SCL clock low time

t_w(SCLH)SCL clock high time

t_su(SDA)SDA setup time

4.7

4.0

1.3

0.6

µs

250

0⁽³⁾

100

0⁽⁴⁾

t_h(SDA)

SDA data hold time

900⁽³⁾

300

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

1000

300

20+0.1C_b

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

Start condition hold time

20+0.1C_b

0.6

300

t_h(STA)

4.0

4.7

4.0

4.7

µs

Repeated Start condition setup

time

t_su(STA)

0.6

t_su(STO)Stop condition setup time

0.6

µs

pF

Stop to Start condition time (bus

t_w(STO:STA)

free)

1.3

C_b

Capacitive load for each bus line

400

Values based on standard I²C protocol requirement, not tested in production.

1.

2. f_PCLK1must be higher than 2 MHz to achieve the maximum standard mode I²C frequency. It must be

higher than 4 MHz to achieve the maximum fast mode I²C frequency.

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

period of SCL signal.

3.

4.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

49/64

Electrical characteristics

STM32F101xx

2

Figure 17. I C bus AC waveforms and measurement circuit

V

DD

STM32F101

SDA

4.7kΩ

100 Ω

I²C bus

SCL

START REPEATED

START

t

su(STA)

SDA

t

r(SDA)

f(SDA)

su(SDA)

t

su(STA:STO)

STOP

t

w(SCKL)

h(SDA)

h(STA)

SCL

t

su(STO)

r(SCK)

t

f(SCK)

w(SCKH)

ai14127b

Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

1.

(1)(2)(3)

Table 35. SCL frequency (f

= 36 MHz, V_DD= 3.3 V)

PCLK1

I2C_CCR value

f_SCL

(kHz)

R_P= 4.7 kΩ

400

TBD

300

200

100

50

20

1. TBD = to be determined.

2. R_P= External pull-up resistance, f_SCL= I²C speed,

3. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the

tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external

components used to design the application.

50/64

STM32F101xx

Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 36 are derived from tests

performed under ambient temperature, f

frequency and V supply voltage conditions

PCLKx

DD

summarized in Table 7.

Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO).

(1)

Table 36. SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Master mode

Slave mode

TBD

0

TBD

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

t_r(SCK)

t_f(SCK)

SPI clock rise and fall time

Capacitive load: C = 50 pF

TBD

(2)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

0

(2)

t_h(NSS)

(2)

t_w(SCKH)

t_w(SCKL)

Master mode, f_PCLK= TBD,

presc = TBD

SCK high and low time

Data input setup time

TBD

(2)

Master mode

Slave mode

TBD

t_su(MI)

t_su(SI)

(2)

Master mode

TBD

(2)

Slave mode

TBD

t_h(MI)

t_h(SI)

Data input hold time

(2)

Master mode, f_PCLK= TBD

Slave mode, f_PCLK= TBD

Slave mode

TBD⁽³⁾

TBD

ns

TBD

(2)(4)

(2)(5)

t_a(SO)

Data output access time

Data output disable time

Data output valid time

Slave mode, f_PCLK= TBD

Slave mode

TBD

t_dis(SO)

TBD

Slave mode (after enable edge)

f_PCLK= TBD

(2)(1)

t_v(SO)

Master mode (after enable edge)

(2)(1)

(2)

t_v(MO)

Data output valid time

Data output hold time

f

_PCLK= TBD

TBD

t_h(SO)

Slave mode (after enable edge)

(2)

t_h(MO)

Master mode (after enable edge) TBD

1. TBD = to be determined.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Depends on f_PCLK. For example, if f_PCLK= 8 MHz, then t_PCLK= 1/f_PLCLK=125 ns and t_v(MO)= 255 ns.

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

51/64

Electrical characteristics

STM32F101xx

Figure 18. SPI timing diagram - slave mode and CPHA=0

NSS input

t

h(NSS)

SU(NSS)

c(SCK)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

v(SO)

r(SCK)

f(SCK)

h(SO)

t

a(SO)

MISO

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

OUT PUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

Figure 19. SPI timing diagram - slave mode and CPHA=1¹⁾

NSS input

t

SU(NSS)

t

c(SCK)

h(NSS)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

MSB O UT

BI T6 OUT

LSB OUT

OUT PUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

52/64

STM32F101xx

Electrical characteristics

Figure 20. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

MSBIN

BIT6 IN

LSB IN

INPUT

t

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTUT

t

v(MO)

h(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

53/64

Electrical characteristics

STM32F101xx

5.3.16

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 37 are derived from tests

performed under ambient temperature, f

frequency and V

supply voltage

PCLK2

DDA

conditions summarized in Table 7.

Note:

It is recommended to perform a calibration after each power-up.

(1)

Table 37. ADC characteristics

Symbol

Parameter

Conditions

Min

2.4

2.0

Typ

Max

3.6

Unit

V

V_DDAADC power supply

V_DDA

V_REF+Positive reference voltage

V

f_ADC

f_S

ADC clock frequency

Sampling rate

0.6

14

MHz

TBD

0.05

1

MHz

kHz

1/f_ADC

V

823

f_TRIG

External trigger frequency

f_ADC= 14 MHz

17

Conversion voltage range ²⁾

External input impedance

V_AIN

R_AIN

V_SSA

V_DDA

kΩ

TBD⁽²⁾⁽³⁾

External capacitor on analog

input

C_AIN

pF

µA

V_IN< V_SS,| I_IN|<

400 µA on adjacent

analog pin

Negative input leakage current on

analog pins

I_lkg

5

6

R_ADC

C_ADC

Sampling switch resistance

1

5

kΩ

Internal sample and hold

capacitor

pF

5.9

83

µs

1/f_ADC

µs

t_CAL

Calibration time

f_ADC= 14 MHz

0.214

3

t_lat

Injection conversion latency

f_ADC= 14 MHz

1/f_ADC

µs

t_S

Sampling time

Power-up time

0.107

17.1

1

t_STAB

0

1

0

µs

18

Total conversion time (including

sampling time)

14 (1.5 for sampling

+12.5 for successive

approximation)

t_CONV

f_ADC= 14 MHz

1/f_ADC

1. TBD = to be determined.

2. Depending on the input signal variation (f_AIN), C_AINcan be increased for stabilization time and reduced to

allow the use of a larger serial resistor (R_AIN). It is valid for all f_ADCfrequencies ≤14 MHz.

3. During the sample time the input capacitance C_AIN(5 max) can be charged/discharged by the external

source. The internal resistance of the analog source must allow the capacitance to reach its final voltage

level within t_S.After the end of the sample time t_S, changes of the analog input voltage have no effect on

the conversion result. Values for the sample clock t_Sdepend on programming.

54/64

STM32F101xx

Electrical characteristics

Table 38. ADC accuracy (f

= 10 MHz, f

= 10 MHz, R

< 10 kΩ, V

=

DDA

PCLK2

ADC

AIN

(1)

3.3 V)

Symbol

Parameter

Conditions

Typ

Max

Unit

|E_T|

|E_O|

|E_G|

|E_D|

|E_L|

Total unadjusted error⁽²⁾

Offset error⁽²⁾

3

1

2

3

2

TBD

Gain Error⁽²⁾

LSB

Differential linearity error⁽²⁾

Integral linearity error⁽²⁾

1. TBD = to be determined.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to

standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 5.3.12 does not

affect the ADC accuracy.

Figure 21. ADC accuracy characteristics

E_G

(1) Example of an actual transfer curve

1023

(2) The ideal transfer curve

(3) End point correlation line

V

– V

1022

1021

DDA

SSA

1LSB

= ----------------------------------------

IDEAL

1024

(2)

E_T=Total Unadjusted Error: maximum deviation

E_T

between the actual and the ideal transfer curves.

(3)

7

6

5

4

3

2

1

E_O=Offset Error: deviation between the first actual

transition and the first ideal one.

(1)

E_G=Gain Error: deviation between the last ideal

transition and the last actual one.

E_O

E_L

E_D=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

E_L=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

E_D

1 LSB_IDEAL

0

1

2

3

4

5

6

7

1021 1022 1023 1024

V_DDA

V_SSA

ai14395

Figure 22. Typical connection diagram using the ADC

V

DD

STM32F101

V

T

0.6V

R

AIN

ADC

AINx

(1)

12-bit A/D

conversion

V

T

I ±1mA

V

C

L

AIN

ADC

0.6V

ai14139

1. Refer to Table 37 for the values of R_ADCand C_ADC

.

2. C_PARASITICmust be added to C_AIN. It represents the capacitance of the PCB (dependent on soldering and

PCB layout quality) plus the pad capacitance (3 pF). A high C_PARASITICvalue will downgrade conversion

accuracy. To remedy this, f_ADCshould be reduced.

55/64

Electrical characteristics

STM32F101xx

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 23 or Figure 24,

depending on whether V is connected to V or not. The 10 nF capacitors should be

REF+

DDA

ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 23. Power supply and reference decoupling (V

not connected to V

)

DDA

REF+

STM32F101xx

V

REF+

DDA

1 µF // 10 nF

V

1 µF // 10 nF

/V

SSA REF-

ai14380

1. V_REF+and V_REF-inputs are available only on 100-pin packages.

Figure 24. Power supply and reference decoupling (V

connected to V

)

REF+

DDA

STM32F101xx

V_REF+/V_DDA

1 µF // 10 nF

V_REF–/V_SSA

ai14380

1. V_REF+and V_REF-inputs are available only on 100-pin packages.

56/64

STM32F101xx

Electrical characteristics

5.3.17

Temperature sensor characteristics

Table 39. TS characteristics

Symbol

Parameter

V_SENSElinearity with temperature

Conditions Min

Typ

Max

Unit

T

°C

mV/°C

V

±1.5

4.478

1.4

L

Avg_Slope Average slope

V₂₅

Voltage at 25°C

Startup time

t_START

4

10

µs

57/64

Package characteristics

STM32F101xx

6

Package characteristics

Figure 25. LQPF100 – 100-pin low-profile quad flat package outline

A

D

D1

A2

A1

b

e

E1

E

c

L1

L

h

ai14382

Table 40. LQPF100 – 100-pin low-profile quad flat package mechanical data

mm

Typ

inches

Typ

Dim.

Min

Max

Min

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.063

0.006

0.057

0.011

0.008

0.05

1.35

0.17

0.09

0.002

0.053

0.007

0.004

1.40

0.22

0.055

0.009

C

D

16.00

14.00

16.00

14.00

0.50

0.630

0.551

0.630

0.551

0.020

3.5°

D1

E

E1

e

θ

0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.018

0.024

0.039

0.030

L1

1.00

Number of pins

100

N

58/64

STM32F101xx

Package characteristics

Figure 26. LQFP64 – 64-pin low-profile quad flat package outline

D

A

D1

A2

A1

b

e

E1

E

c

L1

L

ai14383

Table 41. LQFP64 – 64-pin low-profile quad flat package mechanical data

mm

Typ

inches

Typ

Dim.

Min

Max

Min

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.063

0.006

0.057

0.011

0.008

0.05

1.35

0.17

0.09

0.002

0.053

0.007

0.004

1.40

0.22

0.055

0.009

c

D

12.00

10.00

12.00

10.00

0.50

0.472

0.394

0.472

0.394

0.020

3.5°

D1

E

E1

e

θ

0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.018

0.024

0.039

0.030

L1

1.00

Number of pins

64

N

59/64

Package characteristics

STM32F101xx

Figure 27. LQFP48 – 48-pin low-profile quad flat package outline

D

A

D1

A2

A1

b

e

E1

E

c

L1

L

ai14384

Table 42. LQFP48 – 48-pin low-profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.063

0.006

0.057

0.011

0.008

0.05

1.35

0.17

0.09

0.002

0.053

0.007

0.004

1.40

0.22

0.055

0.009

C

D

9.00

7.00

9.00

7.00

0.50

3.5°

0.60

1.00

0.354

0.276

0.354

0.276

0.020

3.5°

D1

E

E1

e

θ

0°

7°

0°

7°

L

0.45

0.75

0.018

0.024

0.039

0.030

L1

Number of pins

48

N

1. Values in inches are converted from mm and rounded to 3 decimal digits.

60/64

STM32F101xx

Package characteristics

6.1

Thermal characteristics

The average chip-junction temperature, T , in degrees Celsius, may be calculated using the

J

following equation:

T = T + (P x Θ )

(1)

J

A

D

JA

Where:

■

T is the ambient temperature in °C,

A

Θ

is the package junction-to-ambient thermal resistance, in °C/W,

JA

P is the sum of P

and P (P = P

+ P ),

INT I/O

D

INT

I/O

D

P

is the product of I and V , expressed in Watts. This is the chip internal power.

DD DD

INT

P

represents the power dissipation on input and output pins;

I/O

Most of the time for the application P < P and can be neglected. On the other hand, P

I/O

INT

may be significant if the device is configured to drive continuously external modules and/or

memories.

An approximate relationship between P and T (if P is neglected) is given by:

D

J

I/O

P = K / (T + 273 °C)

(2)

D

J

Therefore (solving equations 1 and 2):

2

K = P x (T + 273 °C) + Θ x P

D

(3)

D

A

JA

where:

K is a constant for the particular part, which may be determined from equation (3) by

measuring P (at equilibrium) for a known T Using this value of K, the values of P and T

J

D

A.

D

may be obtained by solving equations (1) and (2) iteratively for any value of T .

A

Table 43. Thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

LQFP 100 - 14 x 14 mm / 0.5 mm pitch

46

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm / 0.5 mm pitch

Θ

45

55

°C/W

JA

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm / 0.5 mm pitch

61/64

Order codes

STM32F101xx

7

Order codes

Table 44. Order codes

Partnumber

Flash program

memory

SRAM

memory

Package

Kbytes

STM32F101C6T6

STM32F101C8T6

STM32F101R6T6

STM32F101R8T6

STM32F101RBT6

STM32F101V8T6

STM32F101VBT6

32

64

6

LQFP48

LQFP64

LQFP100

10

6

32

64

10

16

10

16

128

64

128

7.1

Future family enhancements

Further developments of the STM32F101xx access line will see an expansion of the current

options. Larger packages will soon be available with up to 512KB Flash, 48KB SRAM and

with extended features such as EMI support, DAC and additional timers and USARTS.

62/64

STM32F101xx

Revision history

8

Revision history

Table 45. Document revision history

Date

Revision

Changes

06-Jun-2007

1

First draft.

I_DDvalues modified in Table 11: Maximum current consumption in Run

and Sleep modes (T_A= 85 °C).

V_BATrange modified in Power supply schemes.

V_REF+min value, t_STAB, t_latand f_TRIGadded to Table 37: ADC

characteristics. Table 33: TIMx characteristics modified.

Note 5 modified and Note 7, Note 4 and Note 6 added below Table 3:

Pin definitions.

Figure 11: Low-speed external clock source AC timing diagram,

Figure 8: Power supply scheme, Figure 16: Recommended NRST pin

protection and Figure 17: I²C bus AC waveforms and measurement

circuit modified.

Sample size modified and machine model removed in Electrostatic

discharge (ESD).

Number of parts modified and standard reference updated in Static

latch-up. 25 °C and 85 °C conditions removed and class name modified

in Table 28: Electrical sensitivities.

20-Jul-07

2

t_SU(LSE)changed to t_SU(LSE)in Table 17: HSE 4-16 MHz oscillator

characteristics.

In Table 24: Flash endurance and data retention, typical endurance

added, data retention for T_A= 25 °C removed and data retention for T_A=

85 °C added. Note removed below Table 7: General operating

conditions.

V_BGchanged to V_REFINTin Table 10: Embedded internal reference

voltage. I_DDmax values added to Table 11: Maximum current

consumption in Run and Sleep modes (T_A= 85 °C).

I_DD(HSI)max value added to Table 19: HSI oscillator characteristics.

R_PUand R_PDmin and max values added to Table 29: I/O static

characteristics. R_PUmin and max values added to Table 32: NRST pin

characteristics (two notes removed).

Datasheet title corrected. USB characteristics section removed.

Features on page 1 list optimized. Small text changes.

63/64

STM32F101xx

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64/64


型号：	STM32F101RB
厂家：	ST
描述：	Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces 接入线路，先进的基于ARM的32位微控制器与闪存， 6个16位定时器， ADC和七个通信接口闪存微控制器通信
文件：	总64页 (文件大小：969K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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