STM32L151RBT6TR_技术文档

STM32L15xx6/8/B

Ultra-low-power 32-bit MCU ARM-based Cortex-M3,

128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC

Datasheet − production data

Features

■ Ultra-low-power platform

LQFP100 14 × 14 mm

LQFP64 10 × 10 mm

LQFP48 7 × 7 mm

BGA100 7 × 7 mm

BGA64 5 × 5 mm

UFQFPN48

7 × 7 mm

– 1.65 V to 3.6 V power supply

– -40°C to 85°C/105°C temperature range

– 0.3 µA Standby mode (3 wakeup pins)

– 0.9 µA Standby mode + RTC

– 0.57 µA Stop mode (16 wakeup lines)

– 1.2 µA Stop mode + RTC

– 9 µA Low-power Run mode

– 214 µA/MHz Run mode

– 10 nA ultra-low I/O leakage

– < 8 µs wakeup time

■ Memories

– Up to 128 KB Flash with ECC

– Up to 16 KB RAM

– Up to 4 KB of true EEPROM with ECC

– 80 Byte Backup Register

■ LCD Driver for up to 8x40 segments

– Support contrast adjustment

– Support blinking mode

– Step-up converter on board

™

■ Core: ARM 32-bit Cortex -M3 CPU

■ Rich analog peripherals (down to 1.8 V)

– 12-bit ADC 1 Msps up to 24 channels

– 12-bit DAC 2 channels with output buffers

– From 32 kHz up to 32 MHz max

– 33.3 DMIPS peak (Dhrystone 2.1)

– Memory protection unit

– 2x Ultra-low-power-comparators

(window mode and wake up capability)

■ Reset and supply management

– Ultra-safe, low-power BOR (brownout

reset) with 5 selectable thresholds

– Ultra-low-power POR/PDR

■ DMA controller 7x channels

■ 8x peripherals communication interface

– 1x USB 2.0 (internal 48 MHz PLL)

– 3x USART (ISO 7816, IrDA)

– 2x SPI 16 Mbits/s

– Programmable voltage detector (PVD)

■ Clock sources

– 1 to 24 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– High Speed Internal 16 MHz factory-

trimmed RC (+/- 1%)

– 2x I2C (SMBus/PMBus)

■ 10x timers: 6x 16-bit with up to 4 IC/OC/PWM

channels, 2x 16-bit basic timer, 2x watchdog

timers (independent and window)

– Internal Low Power 37 kHz RC

– Internal multispeed low power 65 kHz to

4.2 MHz

■ Up to 20 capacitive sensing channels

supporting touchkey, linear and rotary touch

sensors

– PLL for CPU clock and USB (48 MHz)

■ CRC calculation unit, 96-bit unique ID

■ Pre-programmed bootloader

Table 1.

Device summary

Part number

– USART supported

Reference

■ Development support

STM32L151CB, STM32L151C8, STM32L151C6,

STM32L151xx STM32L151RB, STM32L151R8, STM32L151R6,

STM32L151VB, STM32L151V8

– Serial wire debug supported

– JTAG and trace supported

STM32L152CB, STM32L152C8, STM32L152C6,

STM32L152xx STM32L152RB, STM32L152R8, STM32L152R6,

STM32L152VB, STM32L152V8

■ Up to 83 fast I/Os (73 I/Os 5V tolerant), all

mappable on 16 external interrupt vectors

February 2013

Doc ID 17659 Rev 8

1/121

This is information on a product in full production.

www.st.com

1

Contents

STM32L151x6/8/B, STM32L152x6/8/B

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

2.2

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.1

2.2.2

2.2.3

2.2.4

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1

3.2

3.3

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

ARM® Cortex™-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3.1

3.3.2

3.3.3

3.3.4

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4

3.5

3.6

3.7

3.8

3.9

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22

GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.10.2 Internal voltage reference (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

REFINT

3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 25

3.13 Routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.14 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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Contents

3.15.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) 28

3.15.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.15.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.15.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.15.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 29

3.16.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.17 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30

3.18 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4

5

6

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2

6.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

6.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Embedded reset and power control block characteristics . . . . . . . . . . . 51

Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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6.3.10 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 77

6.3.11 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.3.19 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.3.20 LCD controller (STM32L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . 101

7

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

7.1

7.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.2.1

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

8

9

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ultra-low-power STM32L15xxx device features and peripheral counts . . . . . . . . . . . . . . . 10

Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14

CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15

Functionalities depending on the working mode (from Run/active down to

standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

STM32L15xxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 51

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Current consumption in Run mode, code with data processing running from Flash. . . . . . 54

Current consumption in Run mode, code with data processing running from RAM . . . . . . 55

Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 59

Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 61

Typical and maximum timings in Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

HSE 1-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

LSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Flash memory, data EEPROM endurance and data retention . . . . . . . . . . . . . . . . . . . . . . 75

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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List of tables

SCL frequency (f

STM32L151x6/8/B, STM32L152x6/8/B

= 32 MHz, V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

Table 69.

PCLK1

DD

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

R

max for f

= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

AIN

ADC

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 104

LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 106

LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 108

UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 110

UFBGA100 - 7 x 7 x 0.6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . 111

TFBGA64 - 8.0x8.0x1.2 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . 112

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Ultra-low-power STM32L15xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

STM32L15xVx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

STM32L15xVx LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

STM32L15xRx TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

STM32L15xRx LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

STM32L15xCx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

STM32L15xCx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 14. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 16. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 18. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

2

Figure 20. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 21. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

(1)

Figure 22. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

(1)

Figure 23. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 24. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 25. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 26. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 27. Maximum dynamic current consumption on V

supply pin during ADC

REF+

conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 28. Power supply and reference decoupling (V

Figure 29. Power supply and reference decoupling (V

not connected to V

). . . . . . . . . . . . . . 95

). . . . . . . . . . . . . . . . . 95

REF+

DDA

connected to V

REF+

DDA

Figure 30. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 31. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 103

Figure 32. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 33. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 105

Figure 34. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 35. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 107

Figure 36. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 37. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 38. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 39. UFBGA100 - 7 x 7 x 0.6 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . 111

Figure 40. TFBGA64 - 8.0x8.0x1.2 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . 112

Figure 41. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 113

Figure 42. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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Introduction

STM32L151x6/8/B, STM32L152x6/8/B

1

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32L151xx and STM32L152xx ultra-low-power ARM Cortex™-based

microcontrollers product line.

The ultra-low-power STM32L15xxx family includes devices in 3 different package types:

from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are

included, the description below gives an overview of the complete range of peripherals

proposed in this family.

These features make the ultra-low-power STM32L15xxx microcontroller family suitable for a

wide range of applications:

●

Medical and handheld equipment

●

Application control and user interface

PC peripherals, gaming, GPS and sport equipment

Alarm systems, Wired and wireless sensors, Video intercom

Utility metering

This STM32L151xx and STM32L152xx datasheet should be read in conjunction with the

STM32L1xxxx reference manual (RM0038).

The document "Getting started with STM32L1xxx hardware development" AN3216 gives a

hardware implementation overview. The both documents are available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g.

Figure 1 shows the general block diagram of the device family.

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Description

2

Description

The ultra-low-power STM32L15xxx incorporates the connectivity power of the universal

™

serial bus (USB) with the high-performance ARM Cortex -M3 32-bit RISC core operating at

a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories

(Flash memory up to 128 Kbytes and RAM up to 16 Kbytes) and an extensive range of

enhanced I/Os and peripherals connected to two APB buses.

All devices offer a 12-bit ADC, 2 DACs and 2 ultra-low-power comparators, six general-

purpose 16-bit timers and two basic timers, which can be used as time bases.

Moreover, the STM32L15xxx devices contain standard and advanced communication

2

interfaces: up to two I Cs and SPIs, three USARTs and a USB. The STM32L15xxx devices

offer up to 20 capacitive sensing channels to simply add touch sensing functionality to any

application.

They also include a real-time clock and a set of backup registers that remain powered in

Standby mode.

Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to

drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.

The ultra-low-power STM32L15xxx operates from a 1.8 to 3.6 V power supply (down to

1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option.

It is available in the -40 to +85 °C temperature range, extended to 105°C in low power

dissipation state. A comprehensive set of power-saving modes allows the design of low-

power applications.

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Description

STM32L151x6/8/B, STM32L152x6/8/B

2.1

Device overview

Table 2.

Ultra-low-power STM32L15xxx device features and peripheral counts

Peripheral

STM32L15xCx STM32L15xRx STM32L15xVx

Flash (Kbytes)

32

64

128

32

64

4

128

64

128

Data EEPROM (Kbytes)

RAM (Kbytes)

10

16

10

16

10

16

General-

6

purpose

Basic

SPI

Timers

2

I²C

2

Communication

interfaces

USART

USB

3

1

GPIOs

37

51

83

1

12-bit synchronized ADC

Number of channels

1

16 channels

20 channels

24 channels

12-bit DAC

Number of channels

2

LCD (STM32L152xx Only)

COM x SEG

4x32

8x28

4x44

8x40

4x16

13

Comparator

2

Capacitive sensing channels

Max. CPU frequency

20

32 MHz

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

1.65 V to 3.6 V without BOR option

Operating voltage

Ambient temperatures: –40 to +85 °C

Junction temperature: –40 to + 105 °C

Operating temperatures

Packages

LQFP48, UFQFPN48

LQFP64, BGA64

LQFP100, BGA100

.

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Description

2.2

Ultra-low-power device continuum

The ultra-low-power STM32L151xx and STM32L152xx are fully pin-to-pin and software

compatible. Besides the full compatibility within the family, the devices are part of

STMicroelectronics microcontrollers ultra-low-power strategy which also includes

STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a

continuum of performance, peripherals, system architecture and features.

They are all based on STMicroelectronics ultralow leakage process.

Note:

The ultra-low-power STM32L and general-purpose STM32Fxxxx families are pin-to-pin

compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx

devices. Please refer to the STM32F and STM8L documentation for more information on

these devices.

2.2.1

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and

pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core

for STM32L family. In addition specific care for the design architecture has been taken to

optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

2.2.2

2.2.3

Shared peripherals

STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy

migration from one family to another:

●

Analog peripherals: ADC, DAC and comparators

●

Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L15xx and STM32L15xx families use

a common architecture:

●

Same power supply range from 1.65 V to 3.6 V, (1.65 V at power down only for

STM8L15xx devices)

●

Architecture optimized to reach ultralow consumption both in low power modes and

Run mode

●

Fast startup strategy from low power modes

Flexible system clock

Ultrasafe reset: same reset strategy including power-on reset, power-down reset,

brownout reset and programmable voltage detector.

2.2.4

Features

ST ultra-low-power continuum also lies in feature compatibility:

●

More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm

Memory density ranging from 4 to 384 Kbytes

●

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Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

3

Functional overview

Figure 1 shows the block diagrams.

Figure 1. Ultra-low-power STM32L15xxx block diagram

TRACECK, TRACED0, TRACED1, TRACED2, TRACED3

@V DD

PO WE R

J T AG & SW

Trace controller

ETM

V

CO R E

pbus

V

=1. 65 V to 3.6 V

DD

SS

VOLT. R E G.

NJT R ST

Cortex-M3 CPU

JT DI

JT CK/ S WCLK

JTMS /SWDAT

Ibus

128 KB Flash

4 KB data EEPROM

F

: 32 MHz

ma x

Db us

JTDO

as A F

MP U

S yst em

RAM

16 KB

NV IC

@V DD A

GP DMA

7 c hannels

@V DD A

Supply

OSC_IN

OSC_OUT

A HBP CL K

AP BP CL K

HC L K

PLL

clock

management

&

X T AL O S C

1-24 MHz

FC LK

RC HS

RC MS

RC LS

NRST

VR EF O UTPU T

monitoring

Power reset

Int

IWDG

BOR/V REFINT

Standby interface

X T A L 32 kHz

@VD DA

VDDA /

VSS

PV D

A

OS C32 _IN

OS C32 _OUT

Co mp 1

Co mp 2

COMP2 _IN- /IN+

RTC_AFIN

RT C

Power-up/

Power-down

AW U

RTC_OUT, RTC_TS,RTC_TAMP

Backup

register

P A [15:0 ]

P B [15:0 ]

P C [15:0 ]

PD[ 15:0]

PE[1 5:0]

PH[2 :0]

GPIOA

Backup interface

GPIOB

GPIOC

GPIOD

GPIOE

GPIOH

LCD step-up

converter

V

=2.5 V to 3.6 V

LCD

4 Ch an nels

TIM2

TIM3

TIM4

4 Ch an nels

RX ,TX, C T S, R T S,

S martCa rd as A F

AH B2

AHB/APB2

AHB 2

US ART

2

3

AHB/APB1

EXT. IT

WKU P

RX ,T X , CT S , RT S ,

S martC ard a s AF

83A F

MO S I,MIS O, S CK, NS S

as AF

MOSI ,MIS O,

SC K, NS S as AF

SP I2

SPI 1

RX ,T X , C T S, R T S,

S mar tC ar d as AF

SC L, S DA

as AF

I2C 1

I2C 2

US ART

1

@V DD A

12-bit ADC

S C L, SD A, SMB us ,P MB us

as AF

24A F

*

V

DDREF _ADC

SS REF_ ADC

IF

*

US B_DP

US B_DM

USB 2.0 FS device

US B RAM 512 B

WWDG

Te mp s ens or

SEG

x

LCD 8x4 0 (4x44 )

@V DD A

COM x

General purpose

timers

BA SI C T IME RS

TIM6

2 Channe ls

1 C hannel

1 Channel

TI M9

TI M10

TI M11

DAC_OUT1 as AF

DAC_OUT2 as AF

12-bit DAC1

IIFF

TIMM7

12-bit DAC2

Ai15687h

1. AF = alternate function on I/O port pin.

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STM32L151x6/8/B, STM32L152x6/8/B

Functional overview

3.1

Low power modes

The ultra-low-power STM32L15xxx supports dynamic voltage scaling to optimize its power

consumption in run mode. The voltage from the internal low-drop regulator that supplies the

logic can be adjusted according to the system’s maximum operating frequency and the

external voltage supply:

●

In range 1 (V range limited to 2.0-3.6 V), the CPU runs at up to 32 MHz (refer to

Table 17 for consumption).

DD

In range 2 (full V range), the CPU runs at up to 16 MHz (refer to Table 17 for

DD

consumption)

In range 3 (full V range), the CPU runs at up to 4 MHz (generated only with the

DD

multispeed internal RC oscillator clock source). Refer to Table 17 for consumption.

Seven low power modes are provided to achieve the best compromise between low power

consumption, short startup time and available wakeup sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

Sleep mode power consumption: refer to Table 19.

Low power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the

minimum clock (65 kHz), execution from SRAM or Flash memory, and internal regulator

in low power mode to minimize the regulator's operating current. In the Low power run

mode, the clock frequency and the number of enabled peripherals are both limited.

Low power run mode consumption: refer to Table 20.

Low power sleep mode

●

This mode is achieved by entering the Sleep mode with the internal voltage regulator in

Low power mode to minimize the regulator’s operating current. In the Low power sleep

mode, both the clock frequency and the number of enabled peripherals are limited; a

typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the run

mode with the regulator on.

Low power sleep mode consumption: refer to Table 21.

Stop mode with RTC

●

Stop mode achieves the lowest power consumption while retaining the RAM and

register contents and real time clock. All clocks in the V

domain are stopped, the

CORE

PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still

running. The voltage regulator is in the low power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI

line source can be one of the 16 external lines. It can be the PVD output, the

Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be

the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event

or the RTC wakeup.

●

Stop mode without RTC

Stop mode achieves the lowest power consumption while retaining the RAM and

register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and

HSE crystal oscillators are disabled. The voltage regulator is in the low power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI

line source can be one of the 16 external lines. It can be the PVD output, the

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Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can

also be wakened by the USB wakeup.

Stop mode consumption: refer to Table 22.

●

Standby mode with RTC

Standby mode is used to achieve the lowest power consumption and real time clock.

The internal voltage regulator is switched off so that the entire V

domain is

CORE

powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched

off. The LSE or LSI is still running. After entering Standby mode, the RAM and register

contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,

RTC, LSI, LSE Crystal 32K osc, RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG

reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),

RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.

●

Standby mode without RTC

Standby mode is used to achieve the lowest power consumption. The internal voltage

regulator is switched off so that the entire V

domain is powered off. The PLL, MSI,

CORE

RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After

entering Standby mode, the RAM and register contents are lost except for registers in

the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,

RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising

edge on one of the three WKUP pin occurs.

Standby mode consumption: refer to Table 23.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the

Stop or Standby mode.

Table 3.

Functionalities depending on the operating power supply range

Operating power

supply range

DAC and ADC

operation

Dynamicvoltage

scaling range

USB

I/O operation

Range 2 or

range 3

Degraded speed

performance

V_DD= 1.65 to 1.8 V

Not functional

Conversion time

up to 500 Ksps

Range 2 or

range 3

Degraded speed

performance

V_DD= 1.8 to 2.0 V

V_DD= 2.0 to 2.4 V

Conversion time

up to 500 Ksps

Range 1, range 2

or range 3

Functional⁽¹⁾

Full speed operation

Conversion time

up to 1 Msps

Range 1, range 2

or range 3

V_DD= 2.4 to 3.6 V

1. Should be USB compliant from I/O voltage standpoint, the minimum V_DDis 3.0 V.

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Functional overview

Table 4.

CPU frequency range depending on dynamic voltage scaling

CPU frequency range

Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

Range 1

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

Range 2

Range 3

2.1 MHz to 4.2 MHz (1ws)

32 kHz to 2.1 MHz (0ws)

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Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

Table 5.

Functionalities depending on the working mode (from Run/active down to

standby)

Stop

Standby

Low-

power

Run

Low-

power

Sleep

Ips

Run/Active

Sleep

Wakeup

capability

Wakeup

capability

CPU

Flash

RAM

Y

--

Y

--

Y

--

N

Y

--

Y

--

Y

--

Backup Registers

EEPROM

Brown-out rest

(BOR)

Y

--

Y

--

DMA

Programable

Voltage Detector

(PVD)

Y

Power On Reset

(POR)

Y

--

Y

--

Y

--

Y

--

Y

--

Power Down Rest

(PDR)

High Speed

Internal (HSI)

High Speed

External (HSE)

Low Speed Internal

(LSI)

Low Speed

External (LSE)

Multi-Speed

Internal (MSI)

Inter-Connect

Controler

RTC

Y

RTC Tamper

Y

Auto WakeUp

(AWU)

Y

LCD

USB

USART

SPI

Y

--

Y

--

Y

--

Y

--

Y

(1)

I2C

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Table 5.

Functional overview

Standby

Functionalities depending on the working mode (from Run/active down to

standby) (continued)

Stop

Low-

power

Run

Low-

power

Sleep

Ips

Run/Active

Sleep

Wakeup

capability

ADC

Y

--

Y

--

Y

--

Y

--

DAC

Tempsensor

Comparators

Y

16-bit and 32-bit

Timers

Y

--

IWDG

Y

--

Y

--

Y

--

Y

--

Y

--

Y

WWDG

Touch sensing

Systic Timer

GPIOs

Y

3Pins

50 µs

Wakeup time to

Run mode

0 µs

0.36 µs

3 µs

32 µs

< 8 µs

0.65 µA (No

RTC) V_DD=1.8V

0.3 µA (No RTC)

V_DD=1.8V

1.4 µA (with

RTC) V_DD=1.8V

1 µA (with RTC)

V_DD=1.8V

Consumption

V_DD=1.8V to 3.6V

(Typ)

Down to

214 µA/MHz

(from Flash)

Down to

50 µA/MHz

(from Flash)

Down to Down to

9 µA 4.4 µA

0.65 µA (No

RTC) V_DD=3.0V

0.3 µA (No RTC)

V_DD=3.0V

1.6 µA (with

1.3 µA (with

RTC) V_DD=3.0V RTC) V_DD=3.0V

1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before

entering run mode.

3.2

ARM^®Cortex™-M3 core with MPU

The ARM Cortex™-M3 processor is the industry leading processor for embedded systems.

It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The memory protection unit (MPU) improves system reliability by defining the memory

attributes (such as read/write access permissions) for different memory regions. It provides

up to eight different regions and an optional predefined background region.

Owing to its embedded ARM core, the STM32L15xxx is compatible with all ARM tools and

software.

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Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L15xxx embeds a nested vectored interrupt controller able to

handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of

Cortex™-M3) and 16 priority levels.

●

Closely coupled NVIC gives low-latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving, higher-priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.3

Reset and supply management

3.3.1

Power supply schemes

●

V

= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.

DD

Provided externally through V pins.

DD

●

V

, V

= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

DDA

SSA

and PLL (minimum voltage to be applied to V

is 1.8 V when the ADC is used).

DDA

V

and V

must be connected to V and V , respectively.

DDA

SSA DD SS

3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

The device exists in two versions:

●

The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

The other version without BOR operates between 1.65 V and 3.6 V.

●

After the V threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or

DD

not at power-on), the option byte loading process starts, either to confirm or modify default

thresholds, or to disable the BOR permanently: in this case, the V min value becomes

DD

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever

the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the

power ramp-up should guarantee that 1.65 V is reached on V at least 1 ms after it exits

DD

the POR area.

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Functional overview

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Stop mode, it is possible to automatically switch off the

internal reference voltage (V ) in Stop mode. The device remains in reset mode when

REFINT

V

is below a specified threshold, V

or V

, without the need for any external

DD

POR/PDR

BOR

reset circuit.

Note:

3.3.3

3.3.4

The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-

up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive

at power-up.

The device features an embedded programmable voltage detector (PVD) that monitors the

V

/V

power supply and compares it to the V

threshold. This PVD offers 7 different

DD DDA

PVD

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when V /V drops below the V threshold and/or when

DD DDA

PVD

V

/V

is higher than the V

threshold. The interrupt service routine can then generate

DD DDA

PVD

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●

MR is used in Run mode (nominal regulation)

LPR is used in the Low-power run, Low-power sleep and Stop modes

Power down is used in Standby mode. The regulator output is high impedance, the

kernel circuitry is powered down, inducing zero consumption but the contents of the

registers and RAM are lost are lost except for the standby circuitry (wakeup logic,

IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR).

Boot modes

At startup, boot pins are used to select one of three boot options:

●

Boot from Flash memory

Boot from System Memory

Boot from embedded RAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1 or USART2. See STM32™ microcontroller system memory boot mode

AN2606 for details.

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Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

3.4

Clock management

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low power modes and ensures clock

robustness. It features:

●

Clock prescaler: to get the best tradeoff between speed and current consumption, the

clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

●

Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

Master clock source: three different clock sources can be used to drive the master

clock:

–

1-24 MHz high-speed external crystal (HSE), that can supply a PLL

16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can

supply a PLL

–

Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7

frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz)

with a consumption proportional to speed, down to 750 nA typical. When a

32.768 kHz clock source is available in the system (LSE), the MSI frequency can

be trimmed by software down to a 0.5% accuracy.

●

Auxiliary clock source: two ultra-low-power clock sources that can be used to drive

the LCD controller and the real-time clock:

–

32.768 kHz low-speed external crystal (LSE)

37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for

greater precision.

●

RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock

the RTC and the LCD, whatever the system clock.

USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply

the USB interface.

Startup clock: after reset, the microcontroller restarts by default with an internal

2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the

application program as soon as the code execution starts.

●

Clock security system (CSS): this feature can be enabled by software. If a HSE clock

failure occurs, the master clock is automatically switched to HSI and a software

interrupt is generated if enabled.

Clock-out capability (MCO: microcontroller clock output): it outputs one of the

internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 32 MHz. See Figure 2 for details on the clock tree.

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Functional overview

Figure 2.

Clock tree

MSI RC

MSI

ADCCLK

to ADC

Peripheral clock

enable

16 MHz

HSI RC

HSI

48 MHz

USBCLK

to USB interface

PLLVCO/2

SW

PLLSRC

PLLMUL

PLLDIV

/2,/3,/4

x3,x4,x6,x8

HSI

PLLCLK

32

MHz

max

SYSCLK

x12,x16,x24

OSC_OUT

OSC_IN

x32,x48

1-24 MHz

HSE OSC

HSE

CSS

HCLK

32 MHz max

to AHB bus, core,

memory and DMA

Clock

Enable

to Cortex System timer

/8

FCLK Cortex

free running clock

AHB

Prescaler

/1, 2..512

APB1

32 MHz max

PCLK1

Prescaler

to APB1

/1, 2, 4, 8, 16

peripherals

Peripheral Clock

Enable

If (APB1 prescaler =1) x1

else x2

to TIM2,3,4,6 and 7

TIMxCLK

Peripheral Clock

Enable

APB2

32 MHz max

PCLK2

peripherals to APB2

Prescaler

/1, 2, 4, 8, 16

Peripheral Clock

Enable

to TIM9, 10, and 11

TIMxCLK

Peripheral Clock

Enable

If (APB2 prescaler =1) x1

else x2

to

Timer 9, 10, 11 ETR

/2,4,

8,16

OSC32_IN

to RTC

to LCD

LSE

LSE OSC

32.768 kHz

RTCCLK

OSC32_OUT

RTCSEL[1:0]

to Independent Watchdog (IWDG)

IWDGCLK

LSI

LSI RC

37 kHz

Legend:

HSE = High-speed external clock signal

HSI = High-speed internal clock signal

LSI = Low-speed internal clock signal

LSE = Low-speed external clock signal

MSI = Multispeed internal clock signal

SYSCLK

HSI

/1,2,4,

8,16

MSI

MCO

HSE

PLLCLK

LSI

LSE

MCOSEL

ai17212c

2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either

24 MHz or 32 MHz.

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Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

3.5

Low power real-time clock and backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain

the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded

decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made

automatically. The RTC provides a programmable alarm and programmable periodic

interrupts with wakeup from Stop and Standby modes.

●

The programmable wakeup time ranges from 120 µs to 36 hours

●

Stop mode consumption with LSI and Auto-wakeup: 1.2 µA (at 1.8 V) and 1.4 µA (at

3.0 V)

●

Stop mode consumption with LSE, calendar and Auto-wakeup: 1.3 µA (at 1.8V), 1.6 µA

(at 3.0 V)

The RTC can be calibrated with an external 512 Hz output, and a digital compensation

circuit helps reduce drift due to crystal deviation.

There are twenty 32-bit backup registers provided to store 80 bytes of user application data.

They are cleared in case of tamper detection.

3.6

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions, and can be individually

remapped using dedicated AFIO registers. All GPIOs are high current capable. The

alternate function configuration of I/Os can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/O registers. The I/O controller is

connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge detector lines used to generate

interrupt/event requests. Each line can be individually configured to select the trigger event

(rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected

to the 16 external interrupt lines. The 7 other lines are connected to RTC, PVD, USB or

Comparator events.

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Functional overview

3.7

Memories

The STM32L15xxx devices have the following features:

●

Up to 16 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0

wait states. With the enhanced bus matrix, operating the RAM does not lead to any

performance penalty during accesses to the system bus (AHB and APB buses).

●

The non-volatile memory is divided into three arrays:

–

32, 64 or 128 Kbyte of embedded Flash program memory

4 Kbyte of data EEPROM

Options bytes

The options bytes are used to write-protect the memory (with 4 KB granularity) and/or

readout-protect the whole memory with the following options:

–

Level 0: no readout protection

Level 1: memory readout protection, the Flash memory cannot be read from or

written to if either debug features are connected or boot in RAM is selected

–

Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire)

and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.8

DMA (direct memory access)

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management, avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger

support for each channel. Configuration is done by software and transfer sizes between

source and destination are independent.

2

The DMA can be used with the main peripherals: SPI, I C, USART, general-purpose timers

and ADC.

3.9

LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320

pixels.

●

Internal step-up converter to guarantee functionality and contrast control irrespective of

. This converter can be deactivated, in which case the V pin is used to provide

V

DD

LCD

the voltage to the LCD

●

Supports static, 1/2, 1/3, 1/4 and 1/8 duty

Supports static, 1/2, 1/3 and 1/4 bias

Phase inversion to reduce power consumption and EMI

Up to 8 pixels can be programmed to blink

Unneeded segments and common pins can be used as general I/O pins

LCD RAM can be updated at any time owing to a double-buffer

The LCD controller can operate in Stop mode

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Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

3.10

ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L15xxx devices with up to 24

external channels, performing conversions in single-shot or scan mode. In scan mode,

automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to

the ADC start trigger and injection trigger, to allow the application to synchronize A/D

conversions and timers. An injection mode allows high priority conversions to be done by

interrupting a scan mode which runs in as a background task.

The ADC includes a specific low power mode. The converter is able to operate at maximum

speed even if the CPU is operating at a very low frequency and has an auto-shutdown

function. The ADC’s runtime and analog front-end current consumption are thus minimized

whatever the MCU operating mode.

3.10.1

Temperature sensor

The temperature sensor (T

temperature.

) generates a voltage V

that varies linearly with

SENSE

The temperature sensor is internally connected to the ADC_IN16 input channel which is

used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy

of the temperature measurement. As the offset of the temperature sensor varies from chip

to chip due to process variation, the uncalibrated internal temperature sensor is suitable for

applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode.

Table 6.

Temperature sensor calibration values

Calibration value name

Description

Memory address

TS ADC raw data acquired at

temperature of 30 °C,

TSENSE_CAL1

TSENSE_CAL2

0x1FF8 007A-0x1FF8 007B

V_DDA= 3 V

TS ADC raw data acquired at

temperature of 110 °C

0x1FF8 007E-0x1FF8 007F

V_DDA= 3 V

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Functional overview

3.10.2

Internal voltage reference (V

)

REFINT

The internal voltage reference (V

) provides a stable (bandgap) voltage output for the

REFINT

ADC and Comparators. V

is internally connected to the ADC_IN17 input channel. It

REFINT

enables accurate monitoring of the V

value (when no external voltage, VREF+, is

DD

available for ADC). The precise voltage of V

is individually measured for each part by

REFINT

ST during production test and stored in the system memory area. It is accessible in read-

only mode.

Table 7.

Internal voltage reference measured values

Calibration value name

Description

Memory address

Raw data acquired at

temperature of 30 °C

VREFINT_CAL

0x1FF8 0078-0x1FF8 0079

V_DDA= 3 V

3.11

DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two

analog voltage signal outputs. The chosen design structure is composed of integrated

resistor strings and an amplifier in non-inverting configuration.

This dual digital Interface supports the following features:

●

two DAC converters: one for each output channel

left or right data alignment in 12-bit mode

synchronized update capability

noise-wave generation

triangular-wave generation

dual DAC channels’ independent or simultaneous conversions

DMA capability for each channel (including the underrun interrupt)

external triggers for conversion

input reference voltage V

REF+

Eight DAC trigger inputs are used in the STM32L15xxx. The DAC channels are triggered

through the timer update outputs that are also connected to different DMA channels.

3.12

Ultra-low-power comparators and reference voltage

The STM32L15xxx embeds two comparators sharing the same current bias and reference

voltage. The reference voltage can be internal or external (coming from an I/O).

●

one comparator with fixed threshold

●

one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of

the following:

–

DAC output

External I/O

Internal reference voltage (V

) or V

submultiple (1/4, 1/2, 3/4)

REFINT

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Functional overview

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Both comparators can wake up from Stop mode, and be combined into a window

comparator.

The internal reference voltage is available externally via a low power / low current output

buffer (driving current capability of 1 µA typical).

3.13

3.14

Routing interface

This interface controls the internal routing of I/Os to TIM2, TIM3, TIM4 and to the

comparator and reference voltage output.

Touch sensing

The STM32L15xxx devices provide a simple solution for adding capacitive sensing

functionality to any application. These devices offer up to 20 capacitive sensing channels

distributed over 10 analog I/O groups. Only software capacitive sensing acquisition mode is

supported.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which

is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation

introduced by the finger (or any conductive object) is measured using a proven

implementation based on a surface charge transfer acquisition principle. It consists of

charging the sensor capacitance and then transferring a part of the accumulated charges

into a sampling capacitor until the voltage across this capacitor has reached a specific

threshold. The capacitive sensing acquisition only requires few external components to

operate.

Reliable touch sensing functionality can be quickly and easily implemented using the free

STM32L1xx STMTouch touch sensing firmware library.

3.15

Timers and watchdogs

The ultra-low-power STM32L15xxx devices include six general-purpose timers, two basic

timers and two watchdog timers.

Table 8 compares the features of the general-purpose and basic timers.

Table 8.

Timer

Timer feature comparison

Counter Counter Prescaler DMA request Capture/compare Complementary

resolution

type

factor

generation

channels

outputs

TIM2,

TIM3,

TIM4

Up,

down,

up/down and 65536

Any integer

between 1

16-bit

Yes

4

No

Any integer

TIM9

16-bit

Up

between 1

and 65536

No

2

No

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Functional overview

Table 8.

Timer

Timer feature comparison

Counter

Counter Prescaler DMA request Capture/compare Complementary

resolution

type

factor

generation

channels

outputs

Any integer

between 1

and 65536

TIM10,

TIM11

16-bit

Up

No

1

No

Any integer

between 1

and 65536

TIM6,

TIM7

Up

Yes

0

No

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Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

3.15.1

General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11)

There are six synchronizable general-purpose timers embedded in the STM32L15xxx

devices (see Table 8 for differences).

TIM2, TIM3, TIM4

These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.

They feature 4 independent channels each for input capture/output compare, PWM or one-

pulse mode output. This gives up to 12 input captures/output compares/PWMs on the

largest packages.

The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11

and TIM9 general-purpose timers via the Timer Link feature for synchronization or event

chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers

can be used to generate PWM outputs.

TIM2, TIM3, TIM4 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and

TIM11 feature one independent channel, whereas TIM9 has two independent channels for

input capture/output compare, PWM or one-pulse mode output. They can be synchronized

with the TIM2, TIM3, TIM4 full-featured general-purpose timers.

They can also be used as simple time bases and be clocked by the LSE clock source

(32.768 kHz) to provide time bases independent from the main CPU clock.

3.15.2

3.15.3

Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic

16-bit time bases.

SysTick timer

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is

based on a 24-bit downcounter with autoreload capability and a programmable clock

source. It features a maskable system interrupt generation when the counter reaches 0.

3.15.4

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 37 kHz internal RC and, as it operates independently of the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free-running timer for application timeout

management. It is hardware- or software-configurable through the option bytes. The counter

can be frozen in debug mode.

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Functional overview

3.15.5

Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

3.16

Communication interfaces

3.16.1

I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support

standard and fast modes.

They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master

mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

3.16.2

3.16.3

Universal synchronous/asynchronous receiver transmitter (USART)

All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide

hardware management of the CTS and RTS signals. They support IrDA SIR ENDEC, are

ISO 7816 compliant and have LIN Master/Slave capability.

All USART interfaces can be served by the DMA controller.

Serial peripheral interface (SPI)

Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in

full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

3.16.4

Universal serial bus (USB)

The STM32L15xxx embeds a USB device peripheral compatible with the USB full speed

12 Mbit/s. The USB interface implements a full speed (12 Mbit/s) function interface. It has

software-configurable endpoint setting and supports suspend/resume. The dedicated

48 MHz clock is generated from the internal main PLL (the clock source must use a HSE

crystal oscillator).

Doc ID 17659 Rev 8

29/121

Functional overview

STM32L151x6/8/B, STM32L152x6/8/B

3.17

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.18

Development support

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a

specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.

The JTAG port can be permanently disabled with a JTAG fuse.

Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and

data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L15xxx through a small number of ETM pins to an external hardware trace port

analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or

any other high-speed channel. Real-time instruction and data flow activity can be recorded

and then formatted for display on the host computer running debugger software. TPA

hardware is commercially available from common development tool vendors. It operates

with third party debugger software tools.

30/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Pin descriptions

4

Pin descriptions

Figure 3.

STM32L15xVx UFBGA100 ballout

2

3

4

5

6

7

8

9

10

11

12

1

PD5

PD6

PA12

PA11

PA10

PC9

BOOT0

PB7

PD7

PB3

PD3

PD2

PA13

PC10

PH2

PB8

PA15

PD1

PE1

PB4

PD4

PA14

PC12

PE3

A

B

C

PB9

PB6

PB5

PE4

PE2

PE5

PC13

WKUP2

VDD_3

PE0

PD0

PC11

PA9

PE6

WUKP3

PC14

OSC32_IN

D

E

PA8

VSS_3

VSS_4

PC7

PC6

PC8

PC15

VLCD

OSC32_OUT

PH0

OSC_IN

VSS_2

VSS_1

F

VSS_5

PH1

OSC_OUT

G

VDD_2 VDD_1

VDD_5

PD14

PD11

PB14

PD13

PD10

PB13

PB12

PE15

H

J

PD15

PD12

PB15

PB10

PE13

PC0

NRST

PC1

VDD_4

PC2

VSSA

VREF-

VREF+

VDDA

PD9

PD8

PA5

PA6

PC4

PC5

PB0

PA2

K

L

PC3

PB2

PB1

PA3

PE10 PE12

PB11

PE14

PE8

PA0

WKUP1

PA7

PA4

PE9

PE11

PE7

PA1

M

ai17096e

1. This figure shows the package top view.

Doc ID 17659 Rev 8

31/121

Pin descriptions

Figure 4.

STM32L151x6/8/B, STM32L152x6/8/B

STM32L15xVx LQFP100 pinout

PE2

PE3

PE4

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD_2

VSS_2

PH2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PE5

PE6-WKUP3

V_LCD

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VDD_5

PH0-OSC_IN

PH1-OSC_OUT

NRST

LQFP100

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PD8

PB15

PB14

PB13

PB12

PA0-WKUP1

PA1

PA2

ai15692c

1. This figure shows the package top view.

32/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Pin descriptions

Figure 5.

STM32L15xRx TFBGA64 ballout

1

2

3

4

5

6

7

8

PC14-

OSC32_IN WKUP2

PC13-

A

B

PB9

PB8

PB7

PB6

PB4

BOOT0

PB5

PB3

PD2

PA15

PC11

PA10

PA14

PC10

PA9

PA13

PA12

PA11

PC9

PC15-

VLCD

OSC32_OUT

PH0-

OSC_IN

C

D

E

F

V

PC12

SS_4

PH1-

OSC_OUT

V

PA8

DD_4

SS_3

SS_2

SS_1

NRST

PC1

PC2

PC0

PA2

V

PC7

PC8

DD_3

DD_2

DD_1

V

PA5

PB0

PC6

PB15

PB14

SSA

V

REF+

G

H

PA0-WKUP1

PA1

PA3

PA6

PA7

PB1

PC4

PB2

PC5

PB10

PB11

PB13

PB12

V

PA4

DDA

AI16090c

1. This figure shows the package top view.

Doc ID 17659 Rev 8

33/121

Pin descriptions

Figure 6.

STM32L151x6/8/B, STM32L152x6/8/B

STM32L15xRx LQFP64 pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

V

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

LCD

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

PH0 -OSC_IN

PH1-OSC_OUT

NRST

2

3

4

5

6

7

PC0

PC1

PC2

PC3

8

LQFP64

9

10

11

12

13

14

15

16

PC6

VSSA

VDDA

PA0-WKUP1

PB15

PB14

PB13

PB12

PA1

PA2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

ai15693c

1. This figure shows the package top view.

Figure 7.

STM32L15xCx LQFP48 pinout

48 47 46 45 44 43 42 41 40 39 38 37

36

VDD_2

V

1

2

3

4

5

6

7

8

9

LCD

VSS_2

PA13

PA12

PA11

PA10

PA9

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

35

34

33

32

31

30

29

28

27

26

25

LQFP48

PA8

VSSA

VDDA

PB15

PB14

PB13

PB12

PA0 -WKUP1 10

PA1 11

12

PA2

24

13 14 15 16 17 18 19 20 21 22 23

ai15694c

1. This figure shows the package top view.

34/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Figure 8. STM32L15xCx UFQFPN48 pinout

Pin descriptions

48 47 46

45 44 43 42 41 40

39 38 37

36

V

1

LCD

DD_2

V

2

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

35

SS_2

PA13

PA12

PA11

PA10

PA9

3

34

33

4

PH0-OSC_IN

32

31

5

PH1-OSC_OUT

6

UFQFPN48

7

30

29

NRST

V

8

PA8

SSA

V

9

28

27

PB15

PB14

DDA

PA0-WKUP1

PA1

10

11

12

26

PB13

PB12

25

24

PA2

13 14 15 16

17 18 19 20

21 22 23

ai15695d

1. This figure shows the package top view.

Doc ID 17659 Rev 8

35/121

Pin descriptions

STM32L151x6/8/B, STM32L152x6/8/B

Table 9.

Pins

STM32L15xxx pin definitions

Main

Pin name

function⁽³⁾

(after reset)

Alternate functions

1

2

3

4

5

6

7

-

B2

A1

B1

-

PE2

PE3

PE4

PE5

I/O FT

PE2

PE3

PE4

PE5

PE6

V_LCD

PC13

TRACECLK/LCD_SEG38/TIM3_ETR

TRACED0/LCD_SEG39/TIM3_CH1

TRACED1/TIM3_CH2

-

C2

D2

-

TRACED2/TIM9_CH1

-

PE6-WKUP3 I/O FT

TRACED3/WKUP3/TIM9_CH2

(4)

1 B2 E2

2 A2 C1

1

2

V_LCD

S

PC13-WKUP2 I/O FT

RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2

OSC32_IN

PC14-

I/O

8

9

3 A1 D1

4 B1 E1

3

4

PC14

PC15

OSC32_IN⁽⁵⁾

PC15-

OSC32_OUT I/O

OSC32_OUT

(5)

10

11

-

F2

-

V_{SS_5}

V_{DD_5}

S

V_{SS_5}

V_{DD_5}

G2

PH0-

12 5 C1 F1

13 6 D1 G1

5

6

I

PH0

PH1

OSC_IN

OSC_IN⁽⁶⁾

PH1-

OSC_OUT

O

OSC_OUT

14 7 E1 H2

15 8 E3 H1

16 9 E2 J2

17 10 F2 J3

18 11 -⁽⁷⁾K2

19 12 F1 J1

7

-

NRST

PC0

I/O

NRST

PC0

I/O FT

I/O

ADC_IN10/LCD_SEG18/COMP1_INP

ADC_IN11/LCD_SEG19/COMP1_INP

ADC_IN12/LCD_SEG20/COMP1_INP

ADC_IN13/LCD_SEG21/COMP1_INP

-

PC1

-

PC2

-

PC3

8

-

V_SSA

V_REF-

S

V_SSA

V_REF-

20

21

-

K1

L1

S

G1

-

V_REF+

V_DDA

S

V_REF+

V_DDA

PA0

(7)

22 13 H1 M1

9

WKUP1/USART2_CTS/ADC_IN0/TIM2_CH1_ETR/

COMP1_INP

23 14 G2 L2 10 PA0-WKUP1 I/O FT

24 15 H2 M2 11 PA1 I/O FT

USART2_RTS/ADC_IN1/TIM2_CH2/LCD_SEG0/

COMP1_INP

PA1

36/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Pin descriptions

Table 9.

Pins

STM32L15xxx pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Alternate functions

USART2_TX/ADC_IN2/TIM2_CH3/TIM9_CH1/

LCD_SEG1/COMP1_INP

25 16 F3 K3 12

26 17 G3 L3 13

PA2

PA3

I/O FT

I/O

PA2

PA3

USART2_RX/ADC_IN3/TIM2_CH4/TIM9_CH2/

LCD_SEG2/COMP1_INP

27 18 C2 E3

28 19 D2 H3

-

V_{SS_4}

V_{DD_4}

S

V_{SS_4}

V_{DD_4}

SPI1_NSS/USART2_CK/

ADC_IN4/DAC_OUT1/COMP1_INP

29 20 H3 M3 14

30 21 F4 K4 15

31 22 G4 L4 16

32 23 H4 M4 17

PA4

PA5

PA6

PA7

I/O

PA4

PA5

PA6

PA7

SPI1_SCK/ADC_IN5/

DAC_OUT2/TIM2_CH1_ETR/COMP1_INP

I/O

SPI1_MISO/ADC_IN6/TIM3_CH1/

LCD_SEG3/TIM10_CH1/COMP1_INP

I/O FT

SPI1_MOSI/ADC_IN7/TIM3_CH2/

LCD_SEG4/TIM11_CH1/COMP1_INP

33 24 H5 K5

34 25 H6 L5

-

PC4

PC5

I/O FT

PC4

PC5

ADC_IN14/LCD_SEG22/COMP1_INP

ADC_IN15/LCD_SEG23/COMP1_INP

ADC_IN8/TIM3_CH3/LCD_SEG5/

COMP1_INP/VREF_OUT

35 26 F5 M5 18

PB0

PB1

I/O

PB0

PB1

ADC_IN9/TIM3_CH4/LCD_SEG6/

COMP1_INP/VREF_OUT

36 27 G5 M6 19

37 28 G6 L6 20

I/O FT

PB2

PE7

I/O FT PB2/BOOT1

38

39

40

41

42

43

44

45

46

-

M7

L7

-

I/O

PE7

PE8

ADC_IN22/COMP1_INP

ADC_IN23/COMP1_INP

PE8

I/O

M8

L8

PE9

I/O

PE9

ADC_IN24/TIM2_CH1_ETR/COMP1_INP

ADC_IN25/TIM2_CH2/COMP1_INP

TIM2_CH3

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

I/O

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

M9

L9

I/O FT

TIM2_CH4/SPI1_NSS

- M10

- M11

- M12

SPI1_SCK

SPI1_MISO

SPI1_MOSI

47 29 G7 L10 21

48 30 H7 L11 22

I2C2_SCL/USART3_TX/TIM2_CH3/LCD_SEG10

I2C2_SDA/USART3_RX/TIM2_CH4/LCD_SEG11

Doc ID 17659 Rev 8

37/121

Pin descriptions

STM32L151x6/8/B, STM32L152x6/8/B

Table 9.

Pins

STM32L15xxx pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Alternate functions

49 31 D6 F12 23

50 32 E6 G12 24

V_{SS_1}

V_{DD_1}

S

V_{SS_1}

V_{DD_1}

SPI2_NSS/I2C2_SMBA/USART3_CK/LCD_SEG12/

ADC_IN18/COMP1_INP/TIM10_CH1

51 33 H8 L12 25

52 34 G8 K12 26

53 35 F8 K11 27

54 36 F7 K10 28

PB12

PB13

PB14

PB15

I/O FT

PB12

PB13

PB14

PB15

SPI2_SCK/USART3_CTS/LCD_SEG13/ADC_IN19/

COMP1_INP/TIM9_CH1

SPI2_MISO/USART3_RTS/LCD_SEG14/ADC_IN20/

COMP1_INP/TIM9_CH2

SPI2_MOSI/LCD_SEG15/ADC_IN21/

COMP1_INP/TIM11_CH1/RTC_REFIN

55

56

57

58

59

60

61

62

-

K9

K8

-

PD8

PD9

I/O FT

PD8

PD9

USART3_TX/LCD_SEG28

USART3_RX/LCD_SEG29

USART3_CK/LCD_SEG30

USART3_CTS/LCD_SEG31

TIM4_CH1/USART3_RTS/LCD_SEG32

TIM4_CH2/LCD_SEG33

J12

J11

J10

H12

H11

H10

PD10

PD11

PD12

PD13

PD14

PD15

PC6

PD10

PD11

PD12

PD13

PD14

PD15

PC6

TIM4_CH3/LCD_SEG34

TIM4_CH4/LCD_SEG35

63 37 F6 E12

64 38 E7 E11

65 39 E8 E10

66 40 D8 D12

TIM3_CH1/LCD_SEG24

PC7

TIM3_CH2/LCD_SEG25

PC8

TIM3_CH3/LCD_SEG26

-

PC9

TIM3_CH4/LCD_SEG27

67 41 D7 D11 29

68 42 C7 D10 30

69 43 C6 C12 31

70 44 C8 B12 32

71 45 B8 A12 33

PA8

USART1_CK/MCO/LCD_COM0

USART1_TX/LCD_COM1

PA9

PA10

PA11

PA12

PA10

PA11

PA12

USART1_RX/LCD_COM2

USART1_CTS/USB_DM/SPI1_MISO

USART1_RTS/USB_DP/SPI1_MOSI

JTMS/

SWDAT

72 46 A8 A11 34

PA13

I/O FT

73

-

C11

-

PH2

I/O FT

S

PH2

74 47 D5 F11 35

V_{SS_2}

38/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Pin descriptions

Table 9.

Pins

STM32L15xxx pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Alternate functions

75 48 E5 G11 36

76 49 A7 A10 37

77 50 A6 A9 38

V_{DD_2}

PA14

PA15

PC10

S

V_{DD_2}

JTCK

/SWCLK

I/O FT

JTDI

TIM2_CH1_ETR/PA15/SPI1_NSS/LCD_SEG17

USART3_TX/LCD_SEG28/LCD_SEG40/

LCD_COM4

78 51 B7 B11

79 52 B6 C10

80 53 C5 B10

-

PC10

USART3_RX/LCD_SEG29/LCD_SEG41/

LCD_COM5

PC11

PC12

I/O FT

PC11

PC12

USART3_CK/LCD_SEG30/LCD_SEG42/

LCD_COM6

81

82

-

C9

B9

-

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

I/O FT

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

SPI2_NSS/TIM9_CH1

SPI2_SCK

83 54 B5 C8

TIM3_ETR/LCD_SEG31/LCD_SEG43/LCD_COM7

USART2_CTS/SPI2_MISO

USART2_RTS/SPI2_MOSI

USART2_TX

84

85

86

87

88

-

B8

B7

A6

B6

A5

-

USART2_RX

USART2_CK/TIM9_CH2

TIM2_CH2/PB3/SPI1_SCK/COMP2_INM/

LCD_SEG7

89 55 A5 A8 39

90 56 A4 A7 40

PB3

PB4

I/O FT

JTDO

TIM3_CH1/PB4/

SPI1_MISO/COMP2_INP/LCD_SEG8

NJTRST

I2C1_SMBA/TIM3_CH2/SPI1_MOSI/COMP2_INP/

LCD_SEG9

91 57 C4 C5 41

92 58 D3 B5 42

93 59 C3 B4 43

PB5

PB6

PB7

I/O FT

PB5

PB6

PB7

I2C1_SCL/TIM4_CH1/USART1_TX

I2C1_SDA/TIM4_CH2/

USART1_RX/PVD_IN

94 60 B4 A4 44

95 61 B3 A3 45

96 62 A3 B3 46

BOOT0

PB8

I

BOOT0

PB8

I/O FT

TIM4_CH3/I2C1_SCL/LCD_SEG16/TIM10_CH1

TIM4_CH4/I2C1_SDA/LCD_COM3/TIM11_CH1

TIM4_ETR/LCD_SEG36/TIM10_CH1

LCD_SEG37/TIM11_CH1

PB9

97

98

-

C3

A2

-

PE0

PE1

Doc ID 17659 Rev 8

39/121

Pin descriptions

STM32L151x6/8/B, STM32L152x6/8/B

Table 9.

Pins

STM32L15xxx pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Alternate functions

99 63 D4 D3 47

100 64 E4 C4 48

V_{SS_3}

V_{DD_3}

S

V_{SS_3}

V_{DD_3}

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower

number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1

and USART1 & USART2, respectively. Refer to Table 2 on page 10.

4. Applicable to STM32L152xx devices only. In STM32L151xx devices, this pin should be connected to V_DD

.

5. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the

LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose

PC14/PC15 I/Os, respectively, when the LSE oscillator is off ( after reset, the LSE oscillator is off ). The LSE has priority

over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins

section in the STM32L15xxx reference manual (RM0038).

6. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on ( by setting the HSEON

bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,

respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off ). The HSE has priority over the GPIO

function.

7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V_REF+functionality is provided instead.

40/121

Doc ID 17659 Rev 8

Memory mapping

STM32L151x6/8/B, STM32L152x6/8/B

5

Memory mapping

The memory map is shown in the following figure.

Figure 9. Memory map

APB memory space

0xFFFF FFFF

reserved

0xE010 0000

reserved

0x6000 0000

reserved

0x4002 6400

DMA

0x4002 6000

0xFFFF FFFF

reserved

0x4002 4000

Flash Interface

0x4002 3C00

RCC

0x4002 3800

7

reserved

0x4002 3400

0xE010 0000

Cortex-M3 Internal

Peripherals

CRC

0x4002 3000

0xE000 0000

reserved

0x4002 1800

Port H

0x4002 1400

Port E

0x4002 1000

6

Port D

0x4002 0C00

Port C

0x4002 0800

Port B

0xC000 0000

0x4002 0400

Port A

0x4002 0000

reserved

0x4001 3C00

USART1

5

0x4001 3800

reserved

0x4001 3400

SPI1

0xA000 0000

0x4001 3000

reserved

0x4001 2800

ADC

0x4001 2400

4

reserved

0x4001 1400

TIM11

0x4001 1000

0x8000 0000

TIM10

0x4001 0C00

TIM9

0x4001 0800

EXTI

3

0x4001 0400

0x1FF8 001F

0x1FF8 0000

SYSCFG

Option Bytes

reserved

0x4001 0000

reserved

0x6000 0000

COMP + RI

0x1FF0 0FFF

0x4000 7C00

reserved

0x4000 7800

DAC1 & 2

2

System memory

0x4000 7400

PWR

0x4000 7000

reserved

Peripherals

0x4000 0000

0x1FF0 0000

0x4000 6200

512 byte

USB

USB Registers

0x4000 6000

0x4000 5C00

0x4000 5800

1

I2C2

I2C1

reserved

0x4000 5400

0x4000 4C00

SRAM

0x2000 0000

reserved

USART3

0x4000 4800

0x4000 4400

0x4000 3C00

USART2

reserved

0

0x0808 0FFF

0x0808 0000

Data EEPROM

reserved

SPI2

0x4000 3800

0x0000 0000

reserved

0x4000 3400

0x4000 3000

IWDG

WWDG

RTC

0x0801 FFFF

0x4000 2C00

0x4000 2800

Flash memory

LCD

0x4000 2400

0x4000 1C00

0x4000 1400

0x4000 1000

Reserved

0x0800 0000

0x0000 0000

reserved

TIM7

Aliased to Flash or system

memory depending on

BOOT pins

TIM6

reserved

0x4000 0C00

0x4000 0800

TIM4

TIM3

TIM2

0x4000 0400

0x4000 0000

ai18200b

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Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

6

Electrical characteristics

6.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

6.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3Σ).

6.1.2

6.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.6 V (for the

A

DD

1.65 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean 2Σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

6.1.4

6.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

Figure 10. Pin loading conditions

Figure 11. Pin input voltage

STM32L15xxx pin

C = 50 pF

V

IN

ai17852

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

6.1.6

Power supply scheme

Figure 12. Power supply scheme

Standby-power circuitry

(OSC32K,RTC,

Wake-up logic

RTC backup registers)

OUT

IN

IO

Logic

GP I/Os

Kernel logic

(CPU,

Digital

& Memories)

V

DD

V

DD1/2/.../5

Regulator

11 × 100 nF

+ 1 × 4.7 µF

V

SS1/2/.../5

V

DD

V

DDA

V

REF

V

REF+

Analog:

RCs, PLL,

...

10 nF

+ 1 µF

10 nF

+ 1 µF

V

ADC

REF-

V

SSA

ai15401c

6.1.7

Current consumption measurement

Figure 13. Current consumption measurement scheme

I

DD

V

DD

V

DDA

ai14126b

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STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

6.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,

Table 12: Current characteristics, and Table 13: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Table 11. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

External main supply voltage

V_DD–V_SS

–0.3

4.0

(1)

(including V_DDAand V_DD

)

V

Input voltage on five-volt tolerant pin

Input voltage on any other pin

V_SS− 0.3

V_DD+4.0

4.0

(2)

V_IN

|ΔV_DDx

|

Variations between different V_DDpower pins

Variations between all different ground pins

50

mV

|V_SSX− V_SS

|

50

Electrostatic discharge voltage

(human body model)

V_ESD(HBM)

see Section 6.3.10

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. V_INmaximum must always be respected. Refer to Table 12 for maximum allowed injected current values.

Table 12. Current characteristics

Symbol

Ratings

Max.

Unit

I_VDD

I_VSS

Total current into V_DD/V_DDApower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current sourced by any I/O and control pin

Injected current on five-volt tolerant I/O⁽³⁾

80

25

I_IO

- 25

+0 /-5

5

mA

(2)

I_INJ(PIN)

Injected current on any other pin ⁽⁴⁾

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁵⁾

25

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.16.

3. Positive current injection is not possible on these I/Os. A negative injection is induced by V_IN<V_SS. I_INJ(PIN)

must never be exceeded. Refer to Table 11 for maximum allowed input voltage values.

4. A positive injection is induced by V_IN> V_DDwhile a negative injection is induced by V_IN< V_SS. I_INJ(PIN)

must never be exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage

values.

5. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values).

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Electrical characteristics

Table 13. Thermal characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Symbol

Ratings

Value

Unit

T_STG

T_J

Storage temperature range

–65 to +150

150

°C

Maximum junction temperature

6.3

Operating conditions

6.3.1

General operating conditions

Table 14. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK1

f_PCLK2

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

0

32

3.6

MHz

0

BOR detector disabled

1.65

BOR detector enabled,

at power on

1.8

1.65

1.8

3.6

339

V_DD

Standard operating voltage

V

BOR detector disabled,

after power on

Analog operating voltage

(ADC and DAC not used)

Must be the same voltage

(1)

V_DDA

V

(2)

as V_DD

Analog operating voltage

(ADC or DAC used)

Power dissipation at

T_A= 85 °C⁽³⁾

P_D

BGA100 package

mW

Maximum power dissipation –40

85

TA

TJ

Temperature range

°C

Low power dissipation⁽⁴⁾

–40

105

Junction temperature range

-40 °C ≤ T_A≤ 105 °C

1. When the ADC is used, refer to Table 54: ADC characteristics.

2. It is recommended to power V_DDand V_DDAfrom the same source. A maximum difference of 300 mV

between V_DDand V_DDAcan be tolerated during power-up and operation.

3. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax (see Table 68: Thermal

characteristics on page 114).

4. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax

(see Table 68: Thermal characteristics on page 114).

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Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

6.3.2

Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the

ambient temperature condition summarized in Table 14.

Table 15. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

BOR detector enabled

BOR detector disabled

BOR detector enabled

BOR detector disabled

Min

0

Typ

Max Unit

∞

V_DDrise time rate

0

1000

µs/V

∞

(1)

t_VDD

20

0

V

_DDfall time rate

1000

V

_DDrising, BOR enabled

2

3.3

ms

1.6

(1)

T_RSTTEMPO

Reset temporization

V_DDrising, BOR disabled⁽²⁾

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

0.4

1

0.7

1.5

1.7

1.65

1.74

1.8

Power on/power down reset

threshold

V_POR/PDR

V_BOR0

V_BOR1

V_BOR2

V_BOR3

V_BOR4

V_PVD0

V_PVD1

V_PVD2

V_PVD3

V_PVD4

V_PVD5

1.3

1.67

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

1.69 1.76

1.87 1.93 1.97

1.96 2.03 2.07

2.22 2.30 2.35

2.31 2.41 2.44

2.45 2.55 2.60

2.54 2.66

2.7

2.68

2.78

1.8

2.8

2.9

2.85

2.95

V

1.85 1.88

Programmable voltage detector

threshold 0

1.88 1.94 1.99

1.98 2.04 2.09

2.08 2.14 2.18

2.20 2.24 2.28

2.28 2.34 2.38

2.39 2.44 2.48

2.47 2.54 2.58

2.57 2.64 2.69

2.68 2.74 2.79

2.77 2.83 2.88

2.87 2.94 2.99

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Table 15. Embedded reset and power control block characteristics (continued)

Symbol

Parameter

PVD threshold 6

Conditions

Falling edge

Min

Typ

Max Unit

2.97 3.05 3.09

3.08 3.15 3.20

40

V_PVD6

V

Rising edge

BOR0 threshold

V_hyst

Hysteresis voltage

mV

All BOR and PVD thresholds

excepting BOR0

100

1. Guaranteed by characterisation, not tested in production.

2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.

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Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

6.3.3

Embedded internal reference voltage

The parameters given in Table 16 are based on characterization results, unless otherwise

specified.

Table 16. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Max

Unit

Typ

(1)

V_{REFINT out}

Internal reference voltage

– 40 °C < T_J< +105 °C 1.202 1.224 1.242

V

Internal reference current

consumption

I_REFINT

1.4

2

2.3

3

µA

ms

V

T_VREFINT

Internal reference startup time

V_DDAand V_REF+voltage during

V_{VREF_MEAS}

2.99

3

3.01

V_REFINTfactory measure

Including uncertainties

due to ADC and

V_DDA/V_REF+values

Accuracy of factory-measured

V_REFvalue⁽²⁾

A_{VREF_MEAS}

5

mV

–40 °C < T_J< +105 °C

0 °C < T_J< +50 °C

20

50

20

(3)

T_Coeff

Temperature coefficient

ppm/°C

(3)

A_Coeff

Long-term stability

Voltage coefficient

1000 hours, T= 25 °C

3.0 V < V_DDA< 3.6 V

1000

2000

ppm

VDDCoeff⁽³⁾

ppm/V

ADC sampling time when

reading the internal reference

voltage

(3)(4)

T_{S_vrefint}

5

10

µs

Startup time of reference voltage

buffer for ADC

(3)

T_{ADC_BUF}

10

25

µs

Consumption of reference

voltage buffer for ADC

(3)

I_{BUF_ADC}

13.5

µA

(3)

VREF_OUT output current⁽⁵⁾

VREF_OUT output load

I_{VREF_OUT}

1

µA

pF

(3)

C_{VREF_OUT}

50

Consumption of reference

voltage buffer for VREF_OUT

and COMP

(3)

I_LPBUF

730

1200

nA

(3)

V_{REFINT_DIV1}

V_{REFINT_DIV2}

V_{REFINT_DIV3}

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

24

49

74

25

50

75

26

51

76

%

V_REFINT

(3)

1. Tested in production;

2. The internal V_REFvalue is individually measured in production and stored in dedicated EEPROM bytes.

3. Guaranteed by design, not tested in production.

4. Shortest sampling time can be determined in the application by multiple iterations.

5. To guarantee less than 1% VREF_OUT deviation.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

6.3.4

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code. The current consumption is measured as described in Figure 13: Current

consumption measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a

reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

●

V

= 3.6 V

DD

All I/O pins are in input mode with a static value at V or V (no load)

DD

SS

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted depending on f

range

frequency and voltage

HCLK

●

Prefetch and 64-bit access are enabled in configurations with 1 wait state

The parameters given in Table 17, Table 14 and Table 15 are derived from tests performed

under ambient temperature and V supply voltage conditions summarized in Table 14.

DD

Table 17. Current consumption in Run mode, code with data processing running from Flash

Max⁽¹⁾

Conditions

Symbol Parameter

f_HCLK

Typ

Unit

55 °C 85 °C 105 °C

1 MHz

2 MHz

4 MHz

8 MHz

270

470

400

600

400

600

400

600

Range 3,

V_CORE=1.2 V

VOS[1:0] = 11

µA

890 1025 1025 1025

f_HSE= f_HCLK

up to 8 MHz,

included

f_HSE= f_HCLK/2

above 8 MHz

(PLL ON)⁽²⁾

1

2

1.3

2.5

5

1.3

2.5

5

1.3

2.5

5

Range 2,

V_CORE=1.5 V

VOS[1:0] = 10

16 MHz 3.9

8 MHz 2.16

16 MHz 4.8

32 MHz 9.6

3

Supply

Range 1,

current in

Run mode,

code

executed

V_CORE=1.8 V

5.5

11

5.5

11

5.5

11

I_{DD (Run}

VOS[1:0] = 01

from

Flash)

Range 2,

mA

from Flash

V_CORE=1.5 V

16 MHz

4

5

VOS[1:0] = 10

HSI clock source

(16 MHz)

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01

32 MHz 9.4

11

MSI clock, 65 kHz

65 kHz 0.05 0.085 0.09

524 kHz 0.15 0.185 0.19

0.1

0.2

1

Range 3,

MSI clock, 524 kHz V_CORE=1.2 V

VOS[1:0] = 11

MSI clock, 4.2 MHz

4.2 MHz 0.9

1

1. Based on characterization, not tested in production, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

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Electrical characteristics

Table 18. Current consumption in Run mode, code with data processing running from RAM

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Typ

Unit

55 °C 85 °C 105 °C

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

200

380

720

0.9

1.65

3.2

2

300

500

860

1

300

500

860 860⁽³⁾

300

500

Range 3,

V_CORE=1.2 V

VOS[1:0] = 11

µA

f_HSE= f_HCLK

up to 8 MHz,

included

f_HSE= f_HCLK/2

above 8 MHz

(PLL ON)⁽²⁾

1

Range 2,

V_CORE=1.5 V

VOS[1:0] = 10

2

3.7

2.5

4.5

8.5

3.7

2.5

4.5

8.5

3.7

2.5

4.5

8.5

Supply current

in Run mode,

code executed

from RAM,

Flash switched

off

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01

4

I_{DD (Run}

mA

7.7

from

RAM)

Range 2,

V_CORE=1.5 V

VOS[1:0] = 10

16 MHz

3.3

3.8

9.2

3.8

9.2

3.8

9.2

HSI clock source

(16 MHz)

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01

32 MHz

65 kHz

7.8

40

MSI clock, 65 kHz

60

80

Range 3,

MSI clock, 524 kHz V_CORE=1.2 V

524 kHz 110

4.2 MHz 700

140

800

140

800

160

820

µA

VOS[1:0] = 11

MSI clock, 4.2 MHz

1. Based on characterization, not tested in production, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

3. Tested in production.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Max⁽¹⁾

Table 19. Current consumption in Sleep mode

Symbol Parameter

Conditions

f_HCLK

Typ

Unit

55 °C 85 °C 105 °C

1 MHz

2 MHz

4 MHz

8 MHz

80

140

210

330

400

550

140

210

330

400

550

140

210

330⁽³⁾

Range 3,

V_CORE=1.2 V

VOS[1:0] = 11

150

280

450

f_HSE= f_HCLKup to

16 MHz included,

f_HSE= f_HCLK/2

400

Range 2,

V_CORE=1.5 V

550

above 16 MHz (PLL VOS[1:0] = 10

Supply

current in

Sleep

mode,

code

executed

from RAM,

Flash

switched

OFF

16 MHz 900 1050 1050 1050

8 MHz 550 650 650 650

ON)⁽²⁾

Range 1,

V_CORE=1.8 V

16 MHz 1050 1200 1200 1200

32 MHz 2300 2500 2500 2500

VOS[1:0] = 01

µA

Range 2,

V_CORE=1.5 V

VOS[1:0] = 10

16 MHz 1000 1100 1100 1100

32 MHz 2300 2500 2500 2500

HSI clock source

(16 MHz)

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01

MSI clock, 65 kHz

MSI clock, 524 kHz

MSI clock, 4.2 MHz

65 kHz

30

50

60

Range 3,

I_DD

V_CORE=1.2 V

524 kHz 50

4.2 MHz 200

70

80

(Sleep)

VOS[1:0] = 11

240

140

210

350

400

600

240

140

210

350

400

600

250

140

210

350

400

600

1 MHz

2 MHz

4 MHz

8 MHz

80

Range 3,

V_CORE=1.2 V

VOS[1:0] = 11

150

290

300

500

f_HSE= f_HCLKup to

16 MHz included,

f_HSE= f_HCLK/2

Range 2,

V_CORE=1.5 V

Supply

current in

Sleep

above 16 MHz (PLL VOS[1:0] = 10

16 MHz 1000 1100 1100 1100

8 MHz 550 650 650 650

ON)⁽²⁾

Range 1,

mode,

µA

V

_CORE=1.8 V

16 MHz 1050 1200 1200 1200

32 MHz 2300 2500 2500 2500

code

VOS[1:0] = 01

executed

from Flash

Range 2,

V

_CORE=1.5 V

16 MHz 1000 1100 1100 1100

32 MHz 2300 2500 2500 2500

VOS[1:0] = 10

HSI clock source

(16 MHz)

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01

Supply

current in

Sleep

MSI clock, 65 kHz

MSI clock, 524 kHz

65 kHz

40

70

90

70

90

80

524 kHz 60

100

Range 3,

I_DD

mode,

code

executed

V_CORE=1.2V

VOS[1:0] = 11

µA

(Sleep)

MSI clock, 4.2 MHz

4.2 MHz 210

250

260

from Flash

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STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

1. Based on characterization, not tested in production, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)

3. Tested in production

Table 20. Current consumption in Low power run mode

Max

Symbol

Parameter

Conditions

Typ

Unit

(1)

T_A= -40 °C to 25 °C

T_A= 85 °C

9

17.5

31

14

22

35

37

48

24

33

48

31

40

54

48

54

56

70

12

24

46

17

29

51

42

65

32

42

64

40

48

70

58

63

65

90

MSI clock, 65 kHz

All

f_HCLK= 32 kHz

T_A= 105 °C

peripherals

OFF, code

executed

from RAM,

Flash

switched

OFF, V_DD

from 1.65 V

to 3.6 V

T_A= -40 °C to 25 °C

T_A= 85 °C

MSI clock, 65 kHz

f_HCLK= 65 kHz

T_A= 105 °C

T_A= -40 °C to 25 °C

T_A= 55 °C

MSI clock, 131 kHz

f_HCLK= 131 kHz

T_A= 85 °C

Supply

T_A= 105 °C

I_{DD (LP}

current in

Low power

run mode

Run)

T_A= -40 °C to 25 °C

T_A= 85 °C

MSI clock, 65 kHz

f_HCLK= 32 kHz

µA

T_A= 105 °C

All

peripherals

OFF, code

executed

from Flash,

V_DDfrom

1.65 V to

3.6 V

T_A= -40 °C to 25 °C

T_A= 85 °C

MSI clock, 65 kHz

f_HCLK= 65 kHz

T_A= 105 °C

T_A= -40 °C to 25 °C

T_A= 55 °C

MSI clock, 131 kHz

f_HCLK= 131 kHz

T_A= 85 °C

T_A= 105 °C

Max allowed

current in

Low power

run mode

I

_DDMax

V_DDfrom

1.65 V to

3.6 V

(LP

200

Run)⁽²⁾

1. Based on characterization, not tested in production, unless otherwise specified.

2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator.

Consumption of the I/Os is not included in this limitation.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Table 21. Current consumption in Low power sleep mode

Max

Symbol Parameter

Conditions

Typ

Unit

(1)

MSI clock, 65 kHz

f_HCLK= 32 kHz

Flash OFF

T_A= -40 °C to 25 °C 4.4

T_A= -40 °C to 25 °C 17.5 25

MSI clock, 65 kHz

f_HCLK= 32 kHz

Flash ON

T_A= 85 °C

22

31

27

39

26

28

40

30

32

34

45

All

T_A= 105 °C

peripherals

OFF, V_DD

from1.65 V

to 3.6 V

T_A= -40 °C to 25 °C 18

MSI clock, 65 kHz

T_A= 85 °C

23

31

f_HCLK= 65 kHz,

Flash ON

T_A= 105 °C

T_A= -40 °C to 25 °C 22

MSI clock, 131 kHz

Supply

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

24

26

34

current in

Low power

sleep

f_HCLK= 131 kHz,

Flash ON

I_DD(LP

Sleep)

mode

T_A= -40 °C to 25 °C 17.5 25

µA

MSI clock, 65 kHz

f_HCLK= 32 kHz

T_A= 85 °C

22

31

27

39

26

28

40

30

32

34

45

T_A= 105 °C

TIM9 and

USART1

enabled,

Flash ON,

V_DDfrom

1.65 V to

3.6 V

T_A= -40 °C to 25 °C 18

MSI clock, 65 kHz

T_A= 85 °C

23

31

f

_HCLK= 65 kHz

T_A= 105 °C

T_A= -40 °C to 25 °C 22

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

24

26

34

MSI clock, 131 kHz

f_HCLK= 131 kHz

Max

allowed

current in

(LP Sleep) Low power

V_DDfrom

1.65 V to

3.6 V

I

_DDMax

200

Sleep

mode

1. Based on characterization, not tested in production, unless otherwise specified.

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Electrical characteristics

Table 22. Typical and maximum current consumptions in Stop mode

Max

(1)(2)

Symbol

Parameter

Conditions

Typ⁽¹⁾

Unit

T_A= -40°C to 25°C

V_DD= 1.8 V

1.2 2.75

T_A= -40°C to 25°C 1.4

4

LCD OFF

T_A= 55°C

T_A= 85°C

T_A= 105°C

2.6

4.8

6

10

23

6

10.2

RTC clocked by LSI,

regulator in LP mode,

HSI and HSE OFF

(no independent

watchdog)

T_A= -40°C to 25°C 3.3

LCD ON

(static

T_A= 55°C

T_A= 85°C

T_A= 105°C

4.5

6.6

8

duty)⁽³⁾

12

27

10

12

16

40

4

13.6

T_A= -40°C to 25°C 7.7

LCD ON

(1/8

T_A= 55°C

T_A= 85°C

T_A= 105°C

8.6

duty)⁽⁴⁾

10.7

19.8

T_A= -40°C to 25°C 1.6

Supply current in

Stop mode with

RTC enabled

I_{DD (Stop}

T_A= 55°C

T_A= 85°C

T_A= 105°C

2.7

4.8

6

µA

LCD OFF

with RTC)

10

23

6

10.3

RTC clocked by LSE

T_A= -40°C to 25°C 3.6

external clock (32.768

kHz), regulator in LP

mode, HSI and HSE

OFF (no independent

watchdog)

LCD ON

(static

T_A= 55°C

T_A= 85°C

T_A= 105°C

4.6

6.7

8

duty)⁽³⁾

12

23

10

12

16

40

10.9

T_A= -40°C to 25°C 7.6

LCD ON

(1/8

T_A= 55°C

T_A= 85°C

T_A= 105°C

8.6

duty)⁽⁴⁾

10.7

19.8

T_A= -40°C to 25°C

V_DD= 1.8 V

1.45

1.9

RTC clocked by LSE

(no independent

watchdog)⁽⁵⁾

T_A= -40°C to 25°C

V_DD= 3.0 V

LCD OFF

T_A= -40°C to 25°C

V_DD= 3.6 V

2.2

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Table 22. Typical and maximum current consumptions in Stop mode

Max

(1)(2)

Symbol

Parameter

Conditions

Typ⁽¹⁾

Unit

Regulator in LP mode, HSI and

HSE OFF, independent watchdog T_A= -40°C to 25°C 1.1

and LSI enabled

2.2

Supply current in

I_{DD (Stop)}Stop mode (

RTC disabled)

T_A= -40°C to 25°C 0.5

0.9

5

µA

Regulator in LP mode, LSI, HSI

and HSE OFF (no independent

watchdog)

T_A= 55°C

T_A= 85°C

T_A= 105°C

1.9

3.7

8

8.9 20⁽⁶⁾

RMS (root mean MSI = 4.2 MHz

2

square) supply

I_{DD (WU}current during

_{from Stop)}wakeup time

when exiting

MSI = 1.05 MHz

1.45

V_DD= 3.0 V

T_A= -40°C to 25°C

mA

MSI = 65 kHz⁽⁷⁾

1.45

from Stop mode

1. The typical values are given for V_DD= 3.0 V and max values are given for V_DD= 3.6 V, unless otherwise

specified.

2. Based on characterization, not tested in production, unless otherwise specified

3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected

4. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

5. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY)

with two 6.8pF loading capacitors.

6. Tested in production

7. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the

remaining time of the wakeup period, the current is similar to the Run mode current.

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Electrical characteristics

Table 23. Typical and maximum current consumptions in Standby mode

Max

(1)(2)

Symbol

Parameter

Conditions

Typ⁽¹⁾

Unit

T_A= -40 °C to 25 °C

V_DD= 1.8 V

0.9

T_A= -40 °C to 25 °C

T_A= 55 °C

1.1

1.8

2.5

3

RTC clocked by LSI (no

independent watchdog)

1.42

1.87

2.78

T_A= 85 °C

I_DD

T_A= 105 °C

5

Supply current in Standby

mode with RTC enabled

(Standby

T_A= -40 °C to 25 °C

with RTC)

1

V_DD= 1.8 V

T_A= -40 °C to 25 °C

1.33

1.59

2.01

3.27

2.9

3.4

4.3

6.3

RTC clocked by LSE (no

independent watchdog)⁽³⁾T_A= 55 °C

µA

T_A= 85 °C

T_A= 105 °C

Independent watchdog and

LSI enabled

T_A= -40 °C to 25 °C

1.1

1.6

T_A= -40 °C to 25 °C

T_A= 55 °C

0.3

0.5

1

0.55

0.8

I_DD

(Standby)

Supply current in Standby

mode with RTC disabled

Independent watchdog and

LSI OFF

T_A= 85 °C

1.7

T_A= 105 °C

2.5

4⁽⁴⁾

RMS supply current during

wakeup time when exiting

from Standby mode

I_{DD (WU}

from

Standby)

V_DD= 3.0 V

T_A= -40 °C to 25 °C

1

µA

1. The typical values are given for V_DD= 3.0 V and max values are given for V_DD= 3.6 V, unless otherwise specified.

2. Based on characterization, not tested in production, unless otherwise specified.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF

loading capacitors.

4. Tested in production.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Wakeup time from Low power mode

The wakeup times given in the following table are measured with the MSI RC oscillator. The

clock source used to wake up the device depends on the current operating mode:

●

Sleep mode: the clock source is the clock that was set before entering Sleep mode

●

Stop mode: the clock source is the MSI oscillator in the range configured before

entering Stop mode

●

Standby mode: the clock source is the MSI oscillator running at 2.1 MHz

All timings are derived from tests performed under ambient temperature and V supply

DD

voltage conditions summarized in Table 14.

Table 24. Typical and maximum timings in Low power modes

Max⁽¹⁾

Symbol

Parameter

Conditions

Typ

Unit

t_WUSLEEP

Wakeup from Sleep mode f_HCLK= 32 MHz

f_HCLK= 262 kHz

0.36

32

34

Wakeup from Low power

Flash enabled

sleep mode

t_{WUSLEEP_LP}

f_HCLK= 262 kHz

Flash switched OFF

Wakeup from Stop mode,

f_HCLK= f_MSI= 4.2 MHz

regulator in Run mode

8.2

f_HCLK= f_MSI= 4.2 MHz

Voltage range 1 and 2

9.3

f_HCLK= f_MSI= 4.2 MHz

Voltage range 3

µs

7.8

10

11.2

t_WUSTOP

f_HCLK= f_MSI= 2.1 MHz

12

20

Wakeup from Stop mode,

f_HCLK= f_MSI= 1.05 MHz 15.5

regulator in low power mode

f_HCLK= f_MSI= 524 kHz

f_HCLK= f_MSI= 262 kHz

f_HCLK= f_MSI= 131 kHz

f_HCLK= MSI = 65 kHz

29

53

35

63

105

210

118

237

Wakeup from Standby mode

FWU bit = 1

f_HCLK= MSI = 2.1 MHz

50

103

3.2

t_WUSTDBY

Wakeup from Standby mode

FWU bit = 0

2.5

ms

1. Based on characterization, not tested in production, unless otherwise specified

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STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU

is placed under the following conditions:

●

all I/O pins are in input mode with a static value at V or V (no load)

DD SS

all peripherals are disabled unless otherwise mentioned

the given value is calculated by measuring the current consumption

–

with all peripherals clocked off

with only one peripheral clocked on

(1)

Table 25. Peripheral current consumption

Typical consumption, V_DD= 3.0 V, T_A= 25 °C

Range 1,

Range 2,

Range 3,

V_CORE

1.8 V

=

V_CORE

1.5 V

=

V_CORE

1.2 V

=

Low power

sleep and

run

Peripheral

Unit

VOS[1:0] = VOS[1:0] = VOS[1:0] =

01

10

11

TIM2

TIM3

TIM4

TIM6

TIM7

LCD

13

14

10.5

12

10.5

4.5

5

8

9

10.5

12

11

4.5

5

12.5

5.5

4

8

3.5

2.5

4

5

WWDG

3.5

5

3.5

5

SPI2

5.5

9

µA/MHz

APB1

(f_HCLK

)

USART2

USART3

I2C1

8

5.5

6

8.5

8

10.5

8.5

12.5

4.5

9

7

5.5

6.5

3

7.5

6.5

10

3.5

7

I2C2

7

USB

10

4

PWR

DAC

7.5

4

6

COMP

4.5

3.5

4.5

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

(1)

Table 25. Peripheral current consumption (continued)

Typical consumption, V_DD= 3.0 V, T_A= 25 °C

Range 1,

Range 2,

V_CORE

1.5 V

Range 3,

V_CORE

1.2 V

V_CORE

=

Low power

sleep and

run

Peripheral

Unit

1.8 V

VOS[1:0] = VOS[1:0] = VOS[1:0] =

01

10

11

SYSCFG &

RI

3

2.5

2

2.5

TIM9

9

6.5

7

7.5

5.5

6

4.5

8

7

5.5

9

TIM10

TIM11

ADC⁽²⁾

SPI1

APB2

11.5

5

9.5

4.5

7.5

4.5

4

3

4

USART1

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOH

CRC

9

6

7.5

4

5

3.5

3

µA/MHz

(f_HCLK)

5

4.5

3.5

0.5

18.5

10.5

130

5

AHB

5

4

1

0.5

11.5

10

0.5

9

FLASH

DMA1

13

12

166

8

All enabled

I_{DD (RTC)}

I_{DD (LCD)}

138

106

0.47

3.1

1450

340

0.16

2

(3)

I_{DD (ADC)}

(4)

I_{DD (DAC)}

I_{DD (COMP1)}

I_{DD (COMP2)}

µA

Slow mode

Fast mode

5

(5)

I_{DD (PVD / BOR)}

I_{DD (IWDG)}

2.6

0.25

1. Data based on differential I_DDmeasurement between all peripherals OFF an one peripheral with clock

enabled, in the following conditions: f_HCLK= 32 MHz (range 1), f_HCLK= 16 MHz (range 2), f_HCLK= 4 MHz

(range 3), f_HCLK= 64kHz (Low power run/sleep), f_APB1= f_HCLK, f_APB2= f_HCLK, default prescaler value for

each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.

2. HSI oscillator is OFF for this measure.

3. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC

conversion (HSI consumption not included).

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Electrical characteristics

4. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC

conversion of VDD/2. DAC is in buffered mode, output is left floating.

5. Including supply current of internal reference voltage.

6.3.5

External clock source characteristics

High-speed external user clock generated from an external source

(1)

Table 26. High-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency

f_{HSE_ext}

1

8

32

MHz

V_HSEH

V_HSEL

t_w(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

0.7V_DD

V_SS

V_DD

V

0.3V_DD

OSC_IN high or low time

OSC_IN rise or fall time

12

45

t_w(HSE)

ns

t_r(HSE)

t_f(HSE)

20

C_in(HSE)OSC_IN input capacitance

DuCy_(HSE)Duty cycle

2.6

pF

%

55

1

V_SS≤ V_IN≤ V_D

I_L

OSC_IN Input leakage current

µA

D

1. Guaranteed by design, not tested in production.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a low-

speed external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 14.

(1)

Table 27. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency

f_{LSE_ext}

1

32.768

1000

kHz

OSC32_IN input pin high level

voltage

V_LSEH

V_LSEL

t_w(LSE)

0.7V_DD

V_SS

465

-

V_DD

0.3V_DD

-

V

OSC32_IN input pin low level

voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

-

t_w(LSE)

ns

t_r(LSE)

t_f(LSE)

10

C_IN(LSE)OSC32_IN input capacitance

DuCy_(LSE)Duty cycle

-

45

-

0.6

-

pF

%

-

55

1

I_L

OSC32_IN Input leakage current V_SS≤ V_IN≤ V_DD

µA

1. Guaranteed by design, not tested in production

Figure 14. Low-speed external clock source AC timing diagram

V

LSEH

90%

10%

V

LSEL

t

W(LSE)

t

W(LSE)

r(LSE)

f(LSE)

T

LSE

f

LSE_ext

EXTERNAL

I

L

OSC32_IN

CLOCK SOURCE

STM32Lxx

ai18233

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STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

Figure 15. High-speed external clock source AC timing diagram

V

HSEH

90%

10%

V

HSEL

t

W(HSE)

t

W(HSE)

r(HSE)

f(HSE)

T

HSE

f

HSE_ext

EXTERNAL

I

L

OSC _IN

CLOCK SOURCE

STM32Lxx

ai18232

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 28. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

(1)(2)

Table 28. HSE 1-24 MHz oscillator characteristics

Symbol

Parameter

Conditions

Min Typ

Max

Unit

f_{OSC_IN}Oscillator frequency

1

24

MHz

R_F

C

Feedback resistor

200

kΩ

Recommended load

capacitance versus

R_S= 30 Ω

20

pF

equivalent serial resistance

of the crystal (R_S)⁽³⁾

V

_DD= 3.3 V, V_IN= V_SS

with 30 pF load

I_HSE

I_DD(HSE)

g_m

HSE driving current

3

mA

C = 20 pF

2.5 (startup)

f_OSC= 16 MHz

0.7 (stabilized)

HSE oscillator power

consumption

mA

C = 10 pF

2.5 (startup)

f_OSC= 16 MHz

0.46 (stabilized)

mA

/V

Oscillator transconductance

Startup time

Startup

3.5

t_SU(HSE)

V_DDis stabilized

1

ms

(4)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization results, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a

humid environment, due to the induced leakage and the bias condition change. However, it is

recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer.

For C and C , it is recommended to use high-quality external ceramic capacitors in the

L1

L2

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 16). C and C are usually the

L1

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of C and C . PCB and MCU pin capacitance must be included (10 pF

L1

L2

can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C . Refer to the application note AN2867 “Oscillator design guide for ST

C

L1

L2

microcontrollers” available from the ST website www.st.com.

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STM32L151x6/8/B, STM32L152x6/8/B

Figure 16. HSE oscillator circuit diagram

Electrical characteristics

f

to core

HSE

R

m

R

F

C

O

L

m

C

L1

OSC_IN

C

m

g

m

Resonator

Consumption

control

Resonator

STM32

ai18235

OSC_OUT

C

L2

1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 29. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

(1)

Table 29. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Low speed external oscillator

frequency

f_LSE

R_F

C⁽²⁾

I_LSE

32.768

1.2

kHz

Feedback resistor

MΩ

Recommended load capacitance

versus equivalent serial

R_S= 30 kΩ

8

pF

resistance of the crystal (R_S)⁽³⁾

LSE driving current

V_DD= 3.3 V, V_IN= V_SS

V_DD= 1.8 V

1.1

µA

nA

450

600

750

LSE oscillator current

consumption

I_{DD (LSE)}

V_DD= 3.0 V

V_DD= 3.6V

g_m

Oscillator transconductance

Startup time

3

µA/V

s

(4)

t_SU(LSE)

V_DDis stabilized

1

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator

design guide for ST microcontrollers”.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with

small R_Svalue for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details;

4. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary

significantly with the crystal manufacturer.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Note:

For C and C , it is recommended to use high-quality ceramic capacitors in the 5 pF to

L1

L2

15 pF range selected to match the requirements of the crystal or resonator (see Figure 17).

and C are usually the same size. The crystal manufacturer typically specifies a load

C

L1

L2,

capacitance which is the series combination of C and C .

L1

L2

Load capacitance C has the following formula: C = C x C / (C + C ) + C where

L

L1

L2

L1

L2

stray

C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

between 2 pF and 7 pF.

Caution:

To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended

L1

L2

to use a resonator with a load capacitance C ≤ 7 pF. Never use a resonator with a load

L

capacitance of 12.5 pF.

Example: if you choose a resonator with a load capacitance of C = 6 pF and C

= 2 pF,

stray

L

then C = C = 8 pF.

L1

L2

Figure 17. Typical application with a 32.768 kHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC32_IN

LSE

Bias

controlled

gain

32.768 kHz

resonator

R

F

STM32L15xxx

OSC32_OUT

C

L2

ai17853

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Electrical characteristics

6.3.6

Internal clock source characteristics

The parameters given in Table 30 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 14.

DD

High-speed internal (HSI) RC oscillator

Table 30. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ Max Unit

f_HSI

V_DD= 3.0 V

16

MHz

%

Trimming code is not a multiple of 16

Trimming code is a multiple of 16

0.4 0.7

HSI user-trimmed

resolution

(1)(2)

TRIM

1.5

%

V

_DDA= 3.0 V, T_A= 25 °C

-1⁽³⁾

-1.5

-2

1⁽³⁾

1.5

2

%

V_DDA= 3.0 V, T_A= 0 to 55 °C

V_DDA= 3.0 V, T_A= -10 to 70 °C

%

Accuracy of the

factory-calibrated

HSI oscillator

(2)

ACC_HSI

V

_DDA= 3.0 V, T_A= -10 to 85 °C

V_DDA= 3.0 V, T_A= -10 to 105 °C

_DDA= 1.65 V to 3.6 V

T_A= -40 to 105 °C

-2.5

-4

2

%

2

%

V

-4

3

6

%

µs

µA

HSI oscillator

startup time

(2)

t_SU(HSI)

3.7

HSI oscillator

power consumption

(2)

I_DD(HSI)

100

140

1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are

multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).

2. Based on characterization, not tested in production.

3. Tested in production.

Low-speed internal (LSI) RC oscillator

Table 31. LSI oscillator characteristics

Symbol

Parameter

LSI frequency

Min

Typ

Max

Unit

(1)

f_LSI

26

38

56

kHz

%

LSI oscillator frequency drift

(2)

D_LSI

-10

4

0°C ≤ T_A≤ 85°C

(3)

t_su(LSI)

LSI oscillator startup time

200

510

µs

(3)

I_DD(LSI)

LSI oscillator power consumption

400

nA

1. Tested in production.

2. This is a deviation for an individual part, once the initial frequency has been measured.

3. Guaranteed by design, not tested in production.

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STM32L151x6/8/B, STM32L152x6/8/B

Multi-speed internal (MSI) RC oscillator

Table 32. MSI oscillator characteristics

Symbol

Parameter

Condition

Typ Max Unit

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

65.5

131

kHz

262

Frequency after factory calibration, done at

V_DD= 3.3 V and T_A= 25 °C

f_MSI

524

1.05

2.1

4.2

0.5

MHz

ACC_MSI

Frequency error after factory calibration

%

MSI oscillator frequency drift

0 °C ≤ T_A≤ 85 °C

(1)

D_TEMP(MSI)

3

MSI oscillator frequency drift

1.65 V ≤ V_DD≤ 3.6 V, T_A= 25 °C

(1)

D_VOLT(MSI)

2.5 %/V

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

0.75

1

1.5

2.5

4.5

8

(2)

I_DD(MSI)

MSI oscillator power consumption

µA

15

30

20

15

10

6

t_SU(MSI)

MSI oscillator startup time

µs

5

MSI range 6,

Voltage range 1

and 2

3.5

5

MSI range 6,

Voltage range 3

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Table 32. MSI oscillator characteristics (continued)

Electrical characteristics

Symbol

Parameter

Condition

Typ Max Unit

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

40

20

10

4

2.5

µs

2

(2)

t_STAB(MSI)

MSI oscillator stabilization time

MSI range 6,

Voltage range 1

and 2

2

3

MSI range 3,

Voltage range 3

Any range to

range 5

4

f_OVER(MSI)

MSI oscillator frequency overshoot

MHz

6

Any range to

range 6

1. This is a deviation for an individual part, once the initial frequency has been measured.

2. Based on characterization, not tested in production.

6.3.7

PLL characteristics

The parameters given in Table 33 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 14.

DD

Table 33. PLL characteristics

Value

Symbol

Parameter

Unit

Min

Typ

Max⁽¹⁾

PLL input clock⁽²⁾

2

45

2

24

55

32

MHz

%

f_{PLL_IN}

f_{PLL_OUT}

PLL input clock duty cycle

PLL output clock

MHz

Worst case PLL lock time

PLL input = 2 MHz

t_LOCK

100

130

µs

PLL VCO = 96 MHz

Jitter

Cycle-to-cycle jitter

600

450

150

ps

I_DDA(PLL)

I_DD(PLL)

Current consumption on V_DDA

Current consumption on V_DD

220

120

µA

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

the range defined by f_{PLL_OUT}

.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

6.3.8

Memory characteristics

The characteristics are given at T = -40 to 105 °C unless otherwise specified.

A

RAM memory

Table 34. RAM and hardware registers

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VRM Data retention mode⁽¹⁾

STOP mode (or RESET)

1.65

V

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware

registers (only in Stop mode).

Flash memory and data EEPROM

Table 35. Flash memory and data EEPROM characteristics

Symbol

Parameter

Conditions

Min

Typ

Max⁽¹⁾Unit

Operating voltage

V_DD

1.65

3.6

V

Read / Write / Erase

Erasing

3.28

3.94

Programming time for

word or half-page

t_prog

ms

Programming

Average current during

whole programme/erase

operation

300

1.5

µA

I_DD

T_A= 25 °C, V_DD= 3.6 V

Maximum current (peak)

during programme/erase

operation

2.5

mA

1. Guaranteed by design, not tested in production.

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Electrical characteristics

Table 36. Flash memory, data EEPROM endurance and data retention

Value

Symbol

Parameter

Conditions

Unit

Min⁽¹⁾Typ Max

Cycling (erase / write )

Program memory

10

300

30

T_A= -40°C to

(2)

N_CYC

kcycles

105 °C

Cycling (erase / write )

EEPROM data memory

Data retention (program memory) after

10 kcycles at T_A= 85 °C

T_RET= +85 °C

Data retention (EEPROM data memory)

after 300 kcycles at T_A= 85 °C

30

(2)

t_RET

years

Data retention (program memory) after

10 kcycles at T_A= 105 °C

10

T_RET= +105 °C

Data retention (EEPROM data memory)

after 300 kcycles at T_A= 105 °C

10

1. Based on characterization not tested in production.

2. Characterization is done according to JEDEC JESD22-A117.

6.3.9

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the

device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

●

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

●

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 37. They are based on the EMS levels and classes

defined in application note AN1709.

Table 37. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD= 3.3 V, LQFP100, T_A= +25 °C,

f_HCLK= 32 MHz

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

V_FESD

2B

4A

conforms to IEC 61000-4-2

Fast transient voltage burst limits to be

applied through 100 pF on V_DDand V_SS

pins to induce a functional disturbance

V_DD= 3.3 V, LQFP100, T_A= +25 °C,

f_HCLK= 32 MHz

conforms to IEC 61000-4-4

V_EFTB

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

●

Corrupted program counter

Unexpected reset

Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 38. EMI characteristics

Max vs. frequency range

Monitored

4 MHz 16 MHz

32MHz

voltage

range 1

Symbol Parameter

Conditions

Unit

frequency band

voltage voltage

range 3 range 2

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

3

-6

4

-5

-7

1

V_DD= 3.3 V,

T_A= 25 °C,

LQFP100 package

compliant with IEC

61967-2

18

15

2.5

dBµV

-

S_EMI

Peak level

5

2

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Electrical characteristics

6.3.10

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 39. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class Maximum value⁽¹⁾Unit

Electrostatic discharge

voltage (human body model) to JESD22-A114

T_A= +25 °C, conforming

V_ESD(HBM)

2

II

2000

500

V

Electrostatic discharge

T_A= +25 °C, conforming

V

^ESD(CDM)voltage (charge device model) to JESD22-C101

1. Based on characterization results, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

●

A supply overvoltage is applied to each power supply pin

●

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 40. Electrical sensitivities

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T_A= +105 °C conforming to JESD78A

II level A

6.3.11

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V or

SS

above V (for standard pins) should be avoided during normal product operation. However,

DD

in order to give an indication of the robustness of the microcontroller in cases when

abnormal injection accidentally happens, susceptibility tests are performed on a sample

basis during device characterization.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into the

I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error, out of spec current

injection on adjacent pins or other functional failure (for example reset, oscillator frequency

deviation, LCD levels, etc.).

The test results are given in the following table.

Table 41. I/O current injection susceptibility

Functional susceptibility

Symbol

Description

Unit

Negative

injection

Positive

injection

Injected current on true open-drain pins

Injected current on all 5 V tolerant (FT) pins

Injected current on any other pin

-5

+0

+5

I_INJ

mA

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Electrical characteristics

6.3.12

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 42 are derived from tests

performed under conditions summarized in Table 14. All I/Os are CMOS and TTL compliant.

Table 42. I/O static characteristics

Symbol

Parameter

Input low level voltage

Conditions

Min

Typ

Max

Unit

V_IL

V_SS- 0.3

0.8

V_DD+0.3

5.5V

TTL ports

2.7 V ≤ V_DD≤ 3.6 V

Standard I/O input high level voltage

FT⁽²⁾I/O input high level voltage

V_IH

V_IL

2⁽¹⁾

CMOS ports

1.65 V ≤ V_DD≤ 3.6 V

(3)

Input low level voltage

–0.3

0.3V_DD

CMOS ports

1.65 V ≤ V_DD≤ 3.6 V

Standard I/O Input high level voltage

V_DD+0.3

5.25

V

CMOS ports

1.65 V ≤ V_DD≤ 2.0 V

0.7

V_DD

V_IH

(3)(4)

FT⁽⁵⁾I/O input high level voltage

CMOS ports

2.0 V≤ V_DD≤ 3.6 V

5.5

Standard I/O Schmitt trigger voltage

hysteresis⁽⁶⁾

(7)

V_hys

10% V_DD

V_SS≤ V_IN≤ V_DD

I/Os with LCD

50

V_SS≤ V_IN≤ V_DD

I/Os with analog switches

V_SS≤ V_IN≤ V_DD

I/Os with analog switches

and LCD

I_lkg

Input leakage current ⁽⁸⁾⁽³⁾

50

nA

V_SS≤ V_IN≤ V_DD

I/Os with USB

TBD

50

V_SS≤ V_IN≤ V_DD

Standard I/Os

R_PU

R_PD

C_IO

Weak pull-up equivalent resistor⁽⁹⁾⁽³⁾

Weak pull-down equivalent resistor⁽⁹⁾⁽³⁾

I/O pin capacitance

V_IN= V_SS

V_IN= V_DD

30

45

5

60

kΩ

pF

1. Guaranteed by design.

2. FT = 5V tolerant. To sustain a voltage higher than VDD +0.5 the internal pull-up/pull-down resistors must be disabled.

3. Tested in production

4. 0.7V_DDfor 5V-tolerant receiver

5. FT = Five-volt tolerant.

6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

7. With a minimum of 200 mV. Based on characterization, not tested in production.

8. The max. value may be exceeded if negative current is injected on adjacent pins.

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or

source up to 20 mA (with the non-standard V /V specifications given in Table 43.

OL OH

in the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

●

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

I

(see Table 12).

VDD

●

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

I

(see Table 12).

VSS

Output voltage levels

Unless otherwise specified, the parameters given in Table 43 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 14. All I/Os are CMOS and TTL compliant.

Table 43. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max Unit

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)(2)

V_OL

0.4

I_IO= +8 mA

2.7 V < V_DD< 3.6 V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(3)(2)

V_OH

2.4

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)(4)

V_OL

0.45

V

I

_IO=+ 4 mA

1.65 V < V_DD

2.7 V

<

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(3)(4)

V_OH

V_DD-0.45

V_DD-1.3

Output low level voltage for an I/O pin

when 4 pins are sunk at same time

(1)(4)

V_OL

1.3

I_IO= +20 mA

2.7 V < V_DD< 3.6 V

Output high level voltage for an I/O pin

when 4 pins are sourced at same time

(3)(4)

V_OH

1. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 12

and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. Tested in production.

3. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in

Table 12 and the sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

4. Based on characterization data, not tested in production.

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Electrical characteristics

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 18 and

Table 44, respectively.

Unless otherwise specified, the parameters given in Table 44 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 14.

(1)

Table 44. I/O AC characteristics

OSPEEDRx

[1:0] bit

Symbol

Parameter

Conditions

Min Max⁽²⁾Unit

value⁽¹⁾

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

-

400

625

2

f_max(IO)outMaximum frequency⁽³⁾

kHz

ns

00

01

10

t_f(IO)out

Output rise and fall time

t_r(IO)out

f_max(IO)outMaximum frequency⁽³⁾

MHz

ns

1

125

250

10

2

t_f(IO)out

Output rise and fall time

t_r(IO)out

F_max(IO)outMaximum frequency⁽³⁾

MHz

ns

25

125

50

8

t_f(IO)out

Output rise and fall time

t_r(IO)out

F_max(IO)outMaximum frequency⁽³⁾

MHz

11

-

5

t_f(IO)out

Output rise and fall time

t_r(IO)out

30

ns

Pulse width of external

t_EXTIpw

signals detected by the

EXTI controller

8

-

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L15xxx reference manual for a description

of GPIO Port configuration register.

2. Guaranteed by design. Not tested in production.

3. The maximum frequency is defined in Figure 18.

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Electrical characteristics

Figure 18. I/O AC characteristics definition

STM32L151x6/8/B, STM32L152x6/8/B

90%

10 %

50%

90%

10%

External

Output

on 50pF

t

r(IO)out

f(IO)out

T

Maximum frequency is achieved if (t + t ) ≤ 2/3)T and if the duty cycle is (45-55%)

r

f

when loaded by 50 pF

ai14131b

6.3.13

NRST pin characteristics

The NRST pin input driver uses CMOS technology.

Unless otherwise specified, the parameters given in Table 45 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 14.

Table 45. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

(1)

V_IL(NRST)

NRST input low level voltage

NRST input high level voltage

V_SS

1.4

0.8

(1)

V_IH(NRST)

V_DD

I_OL= 2 mA

V

2.7 V < V_DD< 3.6 V

NRST output low level

voltage

(1)

V_OL(NRST)

0.4

I_OL= 1.5 mA

1.65 V < V_DD< 2.7 V

NRST Schmitt trigger voltage

hysteresis

(1)

(2)

V_hys(NRST)

10%V_DD

30

mV

Weak pull-up equivalent

resistor⁽³⁾

R_PU

V_IN= V_SS

45

60

50

kΩ

(1)

V_F(NRST)

NRST input filtered pulse

ns

V_NF(NRST)

NRST input not filtered pulse

350

1. Guaranteed by design, not tested in production.

2. 200 mV minimum value

3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance is around 10%.

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Figure 19. Recommended NRST pin protection

Electrical characteristics

V

DD

External

reset circuit⁽¹⁾

R

PU

(2)

Internal reset

NRST

Filter

0.1 μF

STM32L15xxx

ai17854

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 45. Otherwise the reset will not be taken into account by the device.

6.3.14

TIM timer characteristics

The parameters given in the following table are guaranteed by design.

Refer to Section 6.3.11: I/O current injection characteristics for details on the input/output

alternate function characteristics (output compare, input capture, external clock, PWM

output).

(1)

Table 46. TIMx characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

t_TIMxCLK

ns

1

t_res(TIM)

Timer resolution time

f_TIMxCLK= 32 MHz 31.25

0

f_TIMxCLK/2

16

MHz

Timer external clock

frequency on CH1 to CH4

f_EXT

f_TIMxCLK= 32 MHz

0

MHz

Res_TIM

Timer resolution

16

bit

16-bit counter clock period

when internal clock is

selected (timer’s prescaler

disabled)

t_TIMxCLK

1

65536

t_COUNTER

f_TIMxCLK= 32 MHz 0.0312

2048

µs

t_TIMxCLK

s

65536 × 65536

134.2

t_{MAX_COUNT}

Maximum possible count

f_TIMxCLK= 32 MHz

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

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STM32L151x6/8/B, STM32L152x6/8/B

6.3.15

Communications interfaces

I²C interface characteristics

2

I

The line C interface meets the requirements of the standard I C communication protocol

with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When

configured as open-drain, the PMOS connected between the I/O pin and V is disabled,

DD

but is still present.

2

The I C characteristics are described in Table 47. Refer also to Section 6.3.11: I/O current

for more details on the input/output alternate function characteristics

injection characteristics

(SDA and SCL)

.

2

Table 47. I C characteristics

Standard mode I²C⁽¹⁾

Fast mode I²C⁽¹⁾⁽²⁾

Symbol

Parameter

Unit

Min

Max

Min

Max

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

SCL clock high time

SDA setup time

4.7

4.0

250

0

1.3

0.6

100

0

µs

SDA data hold time

900⁽³⁾

300

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

1000

300

20 + 0.1C_b

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

Start condition hold time

300

t_h(STA)

t_su(STA)

4.0

4.7

4.0

4.7

0.6

1.3

µs

Repeated Start condition

setup time

t_su(STO)

Stop condition setup time

μs

Stop to Start condition time

(bus free)

t_w(STO:STA)

Capacitive load for each bus

line

C_b

400

pF

Guaranteed by design, not tested in production.

1.

2. f_PCLK1must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to

achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast

mode clock.

The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL

signal.

3.

84/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

2

Figure 20. I C bus AC waveforms and measurement circuit

V

DD

STM32L15xxx

SDA

4.7k

100

I²C bus

SCL

START REPEATED

START

t

su(STA)

SDA

t

r(SDA)

f(SDA)

su(SDA)

t

su(STA:STO)

STOP

t

w(SCKL)

h(SDA)

h(STA)

SCL

t

su(STO)

r(SCK)

t

f(SCK)

w(SCKH)

ai17855

Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

1.

(1)(2)

Table 48. SCL frequency (f

f_SCL(kHz)

= 32 MHz, V_DD= 3.3 V)

PCLK1

I2C_CCR value

R_P= 4.7 kΩ

400

300

200

100

50

0x801B

0x8024

0x8035

0x00A0

0x0140

0x0320

20

1. R_P= External pull-up resistance, f_SCL= I²C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the

tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external

components used to design the application.

Doc ID 17659 Rev 8

85/121

Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

SPI characteristics

Unless otherwise specified, the parameters given in the following table are derived from

tests performed under ambient temperature, f

frequency and V supply voltage

PCLKx

DD

conditions summarized in Table 14.

Refer to Section 6.3.11: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

(1)

Table 49. SPI characteristics

Symbol

Parameter

Conditions

Master mode

Min

Max⁽²⁾Unit

-

16

f_SCK

1/t_c(SCK)

SPI clock frequency

Slave mode

16

MHz

Slave transmitter

12⁽³⁾

(2)

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

Slave mode

-

6

ns

%

(2)

SPI slave input clock duty

cycle

DuCy(SCK)

30

70

t_su(NSS)

t_h(NSS)

NSS setup time

NSS hold time

Slave mode

4t_HCLK

2t_HCLK

-

(2)

t_w(SCKH)

t_w(SCKL)

t_SCK/2 t_SCK/2+

SCK high and low time

Data input setup time

Master mode

(2)

−5

3

(2)

t_su(MI)

Master mode

Slave mode

Master mode

Slave mode

5

-

(2)

t_su(SI)

6

-

(2)

t_h(MI)

5

-

ns

Data input hold time

(2)

t_h(SI)

5

-

(4)

t_a(SO)

Data output access time Slave mode

0

3t_HCLK

(2)

t_v(SO)

Data output valid time

Slave mode

Master mode

Slave mode

Master mode

-

33

6.5

-

(2)

t_v(MO)

-

(2)

t_h(SO)

17

0.5

Data output hold time

(2)

t_h(MO)

-

1. The characteristics above are given for voltage range 1.

2. Based on characterization, not tested in production.

3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty

cycle (DuCy(SCK)) ranging between 40 to 60%.

4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the

data.

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STM32L151x6/8/B, STM32L152x6/8/B

Figure 21. SPI timing diagram - slave mode and CPHA = 0

NSS input

Electrical characteristics

t

c(SCK)

t

h(NSS)

SU(NSS)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

r(SCK)

f(SCK)

v(SO)

a(SO)

h(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134c

(1)

Figure 22. SPI timing diagram - slave mode and CPHA = 1

NSS input

t

SU(NSS)

t

c(SCK)

h(NSS)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

Doc ID 17659 Rev 8

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Electrical characteristics

Figure 23. SPI timing diagram - master mode

STM32L151x6/8/B, STM32L152x6/8/B

(1)

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

INPUT

MSBIN

t

BIT6 IN

LSB IN

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTPUT

t

v(MO)

h(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

USB characteristics

The USB interface is USB-IF certified (full speed).

Table 50. USB startup time

Symbol

Parameter

Max

Unit

µs

(1)

t_STARTUP

USB transceiver startup time

1

1. Guaranteed by design, not tested in production.

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STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

Table 51. USB DC electrical characteristics

Symbol

Parameter

Conditions

Min.⁽¹⁾

Max.⁽¹⁾Unit

Input levels

V_DD

USB operating voltage⁽²⁾

Differential input sensitivity

3.0

0.2

0.8

1.3

3.6

V

(3)

V_DI

I(USB_DP, USB_DM)

(3)

V_CM

Differential common mode range Includes V_DIrange

Single ended receiver threshold

2.5

2.0

(3)

V_SE

Output levels

(4)

V_OL

V_OH

Static output level low

Static output level high

R_Lof 1.5 kΩ to 3.6 V⁽⁵⁾

0.3

3.6

V

(4)

(5)

R_Lof 15 kΩ to V_SS

2.8

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full speed electrical specification, the USB_DP (D+) pin should be pulled

up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.

3. Guaranteed by characterization, not tested in production.

4. Tested in production.

R_Lis the load connected on the USB drivers.

5.

Figure 24. USB timings: definition of data signal rise and fall time

Crossover

points

Differential

Data Lines

V

CR S

V

SS

t

r

f

ai14137

Table 52.

Symbol

USB: full speed electrical characteristics

Driver characteristics⁽¹⁾

Parameter

Conditions

Min

Max

Unit

t_r

t_f

Rise time⁽²⁾

Fall Time⁽²⁾

C_L= 50 pF

t_r/t_f

4

20

ns

%

V

t_rfm

V_CRS

Rise/ fall time matching

90

1.3

110

2.0

Output signal crossover voltage

1. Guaranteed by design, not tested in production.

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

2.

Doc ID 17659 Rev 8

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

6.3.16

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 54 are guaranteed by design.

Table 53. ADC clock frequency

Symbol Parameter

Conditions

Min

Max

Unit

V_{REF+ =}V_DDA

16

V_REF+< V_DDA

8

4

2.4 V ≤ V_DDA≤ 3.6 V V_REF+> 2.4 V

Voltage

range 1 & 2

V_REF+< V_DDA

V_REF+≤ 2.4 V

ADC clock

f_ADC

0.480

MHz

frequency

V

_{REF+ =}V_DDA

8

4

1.8 V ≤ V_DDA≤ 2.4 V

V_REF+< V_DDA

Voltage range 3

Table 54. ADC characteristics

Symbol

Parameter

Power supply

Conditions

Min

Typ

Max

Unit

V_DDA

1.8

3.6

2.4 V ≤ V_DDA≤ 3.6 V

V_REF+must be below

or equal to V_DDA

V_REF+

Positive reference voltage

1.8⁽¹⁾

V_DDA

V

V_REF-

I_VDDA

Negative reference voltage

V_SSA

1000

Current on the V_DDAinput

1450

µA

Peak

700

450

V_REF+

1

Current on the V_REFinput

(2)

I_VREF

400

Average

Conversion voltage range⁽³⁾

0⁽⁴⁾

0.03

V

V_AIN

Direct channels

Multiplexed channels

Direct channels

12-bit sampling rate

Msps

0.76

1.07

0.8

10-bit sampling rate

8-bit sampling rate

6-bit sampling rate

Msps

Multiplexed channels

Direct channels

f_S

1.23

0.89

1.45

1

Multiplexed channels

Direct channels

Multiplexed channels

90/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Table 54. ADC characteristics (continued)

Electrical characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Direct channels

0.25

2.4 V ≤ V_DDA≤ 3.6 V

Multiplexed channels

0.56

1

2.4 V ≤ V_DDA≤ 3.6 V

µs

t_S

Sampling time

Direct channels

1.8 V ≤ V_DDA≤ 2.4 V

Multiplexed channels

1.8 V ≤ V_DDA≤ 2.4 V

4

1

384

1/f_ADC

µs

f_ADC= 16 MHz

24.75

Total conversion time

(including sampling time)

4 to 384 (sampling

phase) +12 (successive

approximation)

t_CONV

1/f_ADC

Direct channels

Multiplexed channels

12-bit conversions

6/8/10-bit conversions

12-bit conversions

6/8/10-bit conversions

Internal sample and hold

capacitor

C_ADC

f_TRIG

16

pF

Tconv+1 1/f_ADC

Tconv 1/f_ADC

Tconv+2 1/f_ADC

Tconv+1 1/f_ADC

External trigger frequency

Regular sequencer

External trigger frequency

Injected sequencer

R_AIN

t_lat

External input impedance

50

281

4.5

219

3.5

kΩ

ns

f_ADC= 16 MHz

219

3.5

156

2.5

Injection trigger conversion

latency

1/f_ADC

ns

Regular trigger conversion

latency

t_latr

1/f_ADC

µs

t_STAB

Power-up time

1. The Vref+ input can be grounded iif neither the ADC nor the DAC are used (this allows to shut down an

external voltage reference).

2. The current consumption through VREF is composed of two parameters:

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.

So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x

400 = 450 µA at 1Msps

3. V_REF+can be internally connected to V_DDAand V_REF-can be internally connected to V_SSA, depending on

the package. Refer to Section 4: Pin descriptions for further details.

4. V_SSAor V_REF-must be tied to ground.

Doc ID 17659 Rev 8

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Electrical characteristics

Table 55. ADC accuracy

STM32L151x6/8/B, STM32L152x6/8/B

(1)(2)

Symbol

Parameter

Test conditions

Min⁽³⁾

Typ

Max⁽³⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

-

2

1

4

2

2.4 V ≤ V_DDA≤ 3.6 V

2.4 V ≤ V_REF+≤ 3.6 V

f_ADC= 8 MHz, R_AIN= 50 Ω

T_A= -40 to 105 °C

-

Gain error

-

1.5

1

3.5

2

LSB

Differential linearity error

Integral linearity error

-

1.7

10

3

ENOB Effective number of bits

9.2

-

bits

dB

2.4 V ≤ V_DDA≤ 3.6 V

V_DDA= V_REF+

Signal-to-noise and

SINAD

57.5

62

-

distorsion ratio

f_ADC= 16 MHz, R_AIN= 50 Ω

T_A= -40 to 105 °C

1 kHz ≤ F_input≤ 100 kHz

SNR

THD

ET

Signal-to-noise ratio

Total harmonic distorsion

Total unadjusted error

Offset error

57.5

62

-75

4

-

-74

-

6.5

4

2.4 V ≤ V_DDA≤ 3.6 V

1.8 V ≤ V_REF+≤ 2.4 V

EO

EG

ED

EL

2

Gain error

4

6

LSB

f_ADC= 4 MHz, R_AIN= 50 Ω

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

1

2

T_A= -40 to 105 °C

1.5

2

3

ET

3

1.8 V ≤ V_DDA≤ 2.4 V

1.8 V ≤ V_REF+≤ 2.4 V

f_ADC= 4 MHz, R_AIN= 50 Ω

T_A= -40 to 105 °C

EO

EG

ED

EL

1

1.5

2

Gain error

1.5

1

Differential linearity error

Integral linearity error

2

1

1.5

1. ADC DC accuracy values are measured after internal calibration.

2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this

significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 6.3.11 does not affect the ADC

accuracy.

3. Based on characterization, not tested in production.

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Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Figure 25. ADC accuracy characteristics

Electrical characteristics

V_REF+

V_DDA

4096

[1LSB_IDEAL

=

(or

depending on package)]

4096

E

G

(1) Example of an actual transfer curve

4095

4094

4093

(2) The ideal transfer curve

(3) End point correlation line

(2)

E =Total Unadjusted Error: maximum deviation

T

E

between the actual and the ideal transfer curves.

T

(3)

7

6

5

4

3

2

1

E

=Offset Error: deviation between the first actual

O

(1)

transition and the first ideal one.

=Gain Error: deviation between the last ideal

E

G

transition and the last actual one.

E

O

E

L

E =Differential Linearity Error: maximum deviation

D

between actual steps and the ideal one.

E =Integral Linearity Error: maximum deviation

L

E

between any actual transition and the end point

correlation line.

D

1 LSB

IDEAL

0

1

2

3

4

5

6

7

4093 4094 4095 4096

V

DDA

SSA

ai14395b

Figure 26. Typical connection diagram using the ADC

VDD

STM32L15xxx

Sample and hold ADC

converter

VT

0.6 V

R

_AIN(1)

AINx

12-bit

converter

IL 50 nA

C

VT

0.6 V

parasitic

VAIN

C

_ADC(1)

ai17856c

1. Refer to Table 56: R_AINmax for f_ADC= 16 MHz for the value of RAIN and Table 54: ADC characteristics for

the value of CADC

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high C_parasiticvalue will downgrade conversion accuracy. To remedy

this, f_ADCshould be reduced.

Doc ID 17659 Rev 8

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

supply pin during ADC

Figure 27. Maximum dynamic current consumption on V

REF+

conversion

Sampling (n cycles)

Conversion (12 cycles)

ADC clock

I

ref+

700µA

300µA

(1)

Table 56.

R

max for f

= 16 MHz

ADC

AIN

R_AINmax (kohm)

Ts

(cycles)

Ts

(µs)

Multiplexed channels

Direct channels

2.4 V < V_DDA< 3.6 V 1.8 V < V_DDA< 2.4 V 2.4 V < V_DDA< 3.3 V 1.8 V < V_DDA< 2.4 V

4

9

0.25

Not allowed

0.8

Not allowed

0.8

0.7

2.0

Not allowed

1.0

0.5625

16

24

48

96

192

384

1

1.5

3

2.0

4.0

3.0

1.8

6.0

4.5

6.8

4.0

15.0

30.0

50.0

10.0

6

15.0

32.0

50.0

10.0

20.0

12

24

25.0

40.0

50.0

1. Guaranteed by design, not tested in production.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 28 or Figure 29,

depending on whether V is connected to V or not. The 10 nF capacitors should be

REF+

DDA

ceramic (good quality). They should be placed as close as possible to the chip.

94/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

Figure 28. Power supply and reference decoupling (V

not connected to V

)

DDA

REF+

STM32L15xxx

V_REF+

(see note 1)

1 μF // 100 nF

V_DDA

1 μF // 100 nF

V_SSA/V_REF–

(see note 1)

ai17857b

1. V_REF+and V_REF–inputs are available only on 100-pin packages.

Figure 29. Power supply and reference decoupling (V

connected to V

)

REF+

DDA

STM32L15xxx

V

/V

REF+ DDA

(See note 1)

1 μF // 100 nF

V

/V

REF– SSA

(See note 1)

ai17858a

1. V_REF+and V_REF–inputs are available only on 100-pin packages.

Doc ID 17659 Rev 8

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Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

6.3.17

DAC electrical specifications

Data guaranteed by design, not tested in production, unless otherwise specified.

Table 57. DAC characteristics

Symbol

V_DDA

V_REF+

V_REF-

Parameter

Conditions

Min

Typ

Max

Unit

Analog supply voltage

1.8

3.6

V

V_DDA

_REF+must always be below

V

Reference supply voltage

Lower reference voltage

1.8

3.6

V_SSA

Current consumption on No load, middle code (0x800)

V_REF+supply

130

220

210

320

220

350

320

520

(1)

I_DDVREF+

No load, worst code (0x000)

V_REF+= 3.3 V

µA

Current consumption on No load, middle code (0x800)

V_DDAsupply

(1)

I_DDA

No load, worst code (0xF1C)

V_DDA= 3.3 V

(2)

R_L

Resistive load

5

kΩ

pF

kΩ

DAC output buffer ON

Capacitive load

(2)

C_L

50

10

R_O

Output impedance

DAC output buffer OFF

6

8

DAC output buffer ON

0.2

V_DDA– 0.2

V

Voltage on DAC_OUT

output

V_{DAC_OUT}

DAC output buffer OFF

0.5

V_REF+– 1LSB mV

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

1.5

3

DNL⁽¹⁾

Differential non linearity⁽³⁾

Integral non linearity⁽⁴⁾

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

1.5

2

3

4

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

INL⁽¹⁾

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

LSB

4

2

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

10

5

25

8

Offset error at code 0x800

Offset⁽¹⁾

(5)

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

Offset error at code

0x001⁽⁶⁾

Offset1⁽¹⁾

1.5

5

96/121

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STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

Table 57. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDA= 3.3V

V_REF+= 3.0V

T_A= 0 to 50 °C

-20

-10

0

DAC output buffer OFF

Offset error temperature

coefficient (code 0x800)

dOffset/dT⁽¹⁾

µV/°C

V_DDA= 3.3V

V_REF+= 3.0V

T_A= 0 to 50 °C

DAC output buffer ON

0

20

50

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

+0.1 / -0.2% +0.2 / -0.5%

Gain⁽¹⁾

Gain error⁽⁷⁾

%

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

+0 / -0.2%

-2

+0 / -0.4%

V_DDA= 3.3V

V_REF+= 3.0V

T_A= 0 to 50 °C

DAC output buffer OFF

-10

-40

0

Gain error temperature

coefficient

dGain/dT⁽¹⁾

µV/°C

V_DDA= 3.3V

V_REF+= 3.0V

T_A= 0 to 50 °C

DAC output buffer ON

-8

0

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

12

8

30

12

TUE⁽¹⁾

Total unadjusted error

LSB

µs

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

Settling time (full scale: for

a 12-bit code transition

between the lowest and

the highest input codes till

DAC_OUT reaches final

value 1LSB

t_SETTLING

C_L≤ 50 pF, R_L≥ 5 kΩ

7

12

1

Max frequency for a

correct DAC_OUT change

Update rate (95% of final value) with 1 C_L≤ 50 pF, R_L≥ 5 kΩ

Msps

LSB variation in the input

code

Wakeup time from off

state (setting the ENx bit

t_WAKEUP

PSRR+

C_L≤ 50 pF, R_L≥ 5 kΩ

9

15

µs

in the DAC Control

register)⁽⁸⁾

V_DDAsupply rejection ratio

(static DC measurement)

-60

-35

dB

1. Data based on characterization results.

2. Connected between DAC_OUT and V_SSA

.

3. Difference between two consecutive codes - 1 LSB.

Doc ID 17659 Rev 8

97/121

Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and

last Code 4095.

5. Difference between the value measured at Code (0x800) and the ideal value = V_REF+/2.

6. Difference between the value measured at Code (0x001) and the ideal value.

7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and

0xFFF when buffer is OFF, and from code giving 0.2 V and (V_DDA– 0.2) V when buffer is ON.

8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

Figure 30. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

R

LOAD

DAC_OUTx

12-bit

digital to

analog

converter

C

LOAD

ai17157V2

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

6.3.18

Temperature sensor characteristics

Table 58. Temperature sensor characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(1)

T_L

V_SENSElinearity with temperature

1

1.61

626.8

3.4

2

1.75

641.5

6

°C

mV/°C

mV

Avg_Slope⁽¹⁾Average slope

1.48

612

V₁₁₀

Voltage at 110°C 5°C⁽²⁾

(3)

I_DDA(TEMP)

Current consumption

Startup time

µA

(3)

t_START

10

µs

ADC sampling time when reading the

temperature

(4)(3)

T_{S_temp}

10

1. Guaranteed by characterization, not tested in production.

2. Measured at V_DD= 3 V 10 mV. V110 ADC conversion result is stored in the TSENSE_CAL2 byte.

3. Guaranteed by design, not tested in production.

4. Shortest sampling time can be determined in the application by multiple iterations.

98/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

6.3.19

Comparator

Table 59. Comparator 1 characteristics

Symbol

Parameter

Conditions

Min⁽¹⁾Typ

Max⁽¹⁾

Unit

V_DDA

R_400K

R_10K

Analog supply voltage

R_400Kvalue

1.65

400

10

3.6

V

kΩ

R_10Kvalue

Comparator 1 input

voltage range

V_IN

0.6

V_DDA

V

t_START

td

Comparator startup time

Propagation delay⁽²⁾

Comparator offset

7

3

10

µs

Voffset

mV

V_DDA= 3.6 V

V_IN+= 0 V

Comparator offset

d_Voffset/dt variation in worst voltage

stress conditions

0

1.5

10

mV/1000 h

nA

V_IN-= V_REFINT

T_A= 25 °C

I_COMP1

Current consumption⁽³⁾

160

260

1. Based on characterization, not tested in production.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-

inverting input set to the reference.

3. Comparator consumption only. Internal reference voltage not included.

Doc ID 17659 Rev 8

99/121

Electrical characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Table 60. Comparator 2 characteristics

Symbol

Parameter

Conditions

Min Typ Max⁽¹⁾Unit

V_DDA

V_IN

Analog supply voltage

1.65

0

3.6

V_DDA

20

V

Comparator 2 input voltage range

Fast mode

15

20

t_START

Comparator startup time

Slow mode

25

1.65 V ≤ V_DDA

≤

1.8

2.5

0.8

3.5

6

2.7 V

t_{d slow}

Propagation delay⁽²⁾in slow mode

µs

2.7 V ≤ V_DDA≤ 3.6 V

1.65 V ≤ V_DDA

2.7 V

≤

2

t_{d fast}

Propagation delay⁽²⁾in fast mode

Comparator offset error

2.7 V ≤ V_DDA≤ 3.6 V

1.2

4

V_offset

20

mV

V_DDA= 3.3V

T_A= 0 to 50 °C

V- = V_REF+, 3/4

dThreshold/ Threshold voltage temperature

ppm

/°C

15

30

dt

coefficient

V_REF+

,

1/2 V_REF+, 1/4 V_REF+

.

Fast mode

3.5

0.5

5

2

I_COMP2

Current consumption⁽³⁾

µA

Slow mode

1. Based on characterization, not tested in production.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-

inverting input set to the reference.

3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not

included.

100/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

6.3.20

LCD controller (STM32L152xx only)

The STM32L152xx embeds a built-in step-up converter to provide a constant LCD reference

voltage independently from the V voltage. An external capacitor C must be connected

DD

ext

to the V

pin to decouple this converter.

LCD

Table 61. LCD controller characteristics

Symbol

Parameter

LCD external voltage

Min

Typ

Max

Unit

V_LCD

V_LCD0

V_LCD1

V_LCD2

V_LCD3

V_LCD4

V_LCD5

V_LCD6

V_LCD7

C_ext

3.6

LCD internal reference voltage 0

LCD internal reference voltage 1

LCD internal reference voltage 2

LCD internal reference voltage 3

LCD internal reference voltage 4

LCD internal reference voltage 5

LCD internal reference voltage 6

LCD internal reference voltage 7

V_LCDexternal capacitance

2.6

2.73

2.86

2.98

3.12

3.26

3.4

V

3.55

0.1

2

µF

µA

Supply current at V_DD= 2.2 V

3.3

3.1

6.6

240

(1)

I_LCD

Supply current at V_DD= 3.0 V

(2)

R_Htot

Low drive resistive network overall value

High drive resistive network total value

Segment/Common highest level voltage

Segment/Common 3/4 level voltage

Segment/Common 2/3 level voltage

Segment/Common 1/2 level voltage

Segment/Common 1/3 level voltage

Segment/Common 1/4 level voltage

Segment/Common lowest level voltage

5.28

192

7.92

288

MΩ

kΩ

V

(2)

R_L

V₄₄

V₃₄

V₂₃

V₁₂

V₁₃

V₁₄

V₀

V_LCD

3/4 V_LCD

2/3 V_LCD

1/2 V_LCD

1/3 V_LCD

1/4 V_LCD

V

0

Segment/Common level voltage error

ΔVxx⁽³⁾

50

mV

T_A= -40 to 85 °C

1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD

connected

2. Guaranteed by design, not tested in production.

3. Based on characterization, not tested in production.

Doc ID 17659 Rev 8

101/121

Package characteristics

STM32L151x6/8/B, STM32L152x6/8/B

7

Package characteristics

7.1

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specification

ECOPACK is an ST trademark.

s, grade definitions and product status are available at: www.st.com.

®

102/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Package characteristics

Figure 31. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline

SEATING

PLANE

C

0.25 mm

GAUGE PLANE

ccc

C

L

D

L1

D1

D3

51

75

50

76

100

26

PIN 1

IDENTIFICATION

25

1

e

1L_ME_V3

1. Drawing is not to scale.

Doc ID 17659 Rev 8

103/121

Package characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Table 62. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical

data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

16.200

14.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

0.050

1.350

0.170

0.090

15.800

13.800

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

1.400

0.220

0.0551

0.0087

c

D

16.000

14.000

12.000

16.000

14.000

12.000

0.500

0.6299

0.5512

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

D1

D3

E

15.800

13.800

16.200

14.200

0.6220

0.5433

0.6378

0.5591

E1

E3

e

L

0.450

0.0°

0.600

0.750

0.0177

0.0°

0.0295

L1

k

1.000

3.5°

7.0°

ccc

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 32. Recommended footprint

75

51

76

50

0.5

0.3

16.7 14.3

100

26

1.2

1

25

12.3

16.7

ai14906

1. Dimensions are in millimeters.

104/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Package characteristics

Figure 33. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline

SEATING

PLANE

C

0.25 mm

GAUGE PLANE

ccc

C

L

D

L1

D1

D3

33

48

32

49

b

64

17

16

1

PIN 1

IDENTIFICATION

e

5W_ME_V2

1. Drawing is not to scale.

Doc ID 17659 Rev 8

105/121

Package characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Table 63. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

12.200

10.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.4803

0.4016

0.050

1.350

0.170

0.090

11.800

9.800

0.0020

0.0531

0.0067

0.0035

0.4646

0.3858

1.400

0.220

0.0551

0.0087

c

D

12.000

10.000

7.500

12.000

10.000

7.500

0.500

0.600

1.000

0.4724

0.3937

0.2953

0.4724

0.3937

0.2953

0.0197

0.0236

0.0394

D1

D3

E

11.800

9.800

12.200

10.200

0.4646

0.3858

0.4803

0.4016

E1

E3

e

L

0.450

0.750

0.0177

0.0

0.0295

L1

ccc

K

0.080

7.0

0.0031

7.0

3.5

0.0

3.5

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 34. Recommended footprint

48

33

0.3

49

32

0.5

12.7

10.3

64

17

1.2

1

16

7.8

12.7

ai14909

1. Dimensions are in millimeters.

106/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Package characteristics

Figure 35. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline

SEATING

PLANE

C

0.25 mm

GAUGE PLANE

ccc

C

D

L

D1

D3

L1

36

25

37

24

b

48

13

PIN 1

IDENTIFICATION

1

12

e

5B_ME_V2

1. Drawing is not to scale.

Doc ID 17659 Rev 8

107/121

Package characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Table 64. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

9.200

7.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

0.050

1.350

0.170

0.090

8.800

6.800

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

1.400

0.220

0.0551

0.0087

c

D

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

0.3543

0.2756

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

D1

D3

E

8.800

6.800

9.200

7.200

0.3465

0.2677

0.3622

0.2835

E1

E3

e

L

0.450

0°

0.750

0.0177

0°

0.0295

L1

k

7°

ccc

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 36. Recommended footprint

0.50

1.20

0.30

36

25

37

24

0.20

7.30

9.70 5.80

7.30

48

13

12

1

1.20

5.80

9.70

ai14911b

1. Dimensions are in millimeters.

108/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Package characteristics

Figure 37. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline

Pin 1 indentifier

laser marking area

D

A

E

Y

E

Seating

plane

T

ddd

A1

b

e

Detail Y

D

Exposed pad

area

D2

1

L

48

C 0.500x45°

pin1 corner

R 0.125 typ.

Detail Z

E2

1

48

Z

A0B9_ME_V3

1. Drawing is not to scale.

1. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

1. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and

solder this back-side pad to PCB ground.

Doc ID 17659 Rev 8

109/121

Package characteristics

Symbol

STM32L151x6/8/B, STM32L152x6/8/B

Table 65. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data

millimeters

Typ

inches⁽¹⁾

Min

Max

Min

Typ

Max

A

A1

D

E

L

0.500

0.000

6.900

0.300

0.550

0.020

7.000

0.400

0.152

0.250

0.500

0.600

0.050

7.100

0.500

0.0197

0.0000

0.2717

0.0118

0.0217

0.0008

0.2756

0.0157

0.0060

0.0098

0.0197

0.0236

0.0020

0.2795

0.0197

T

b

0.200

0.300

0.0079

0.0118

e

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 38. Recommended footprint

7.30

48

37

1

36

6.20

5.60

5.80

0.20

7.30

6.20

5.60

5.80

0.30

0.55

12

25

13

24

0.75

0.50

ai15697

1. Dimensions are in millimeters.

110/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Package characteristics

Figure 39. UFBGA100 - 7 x 7 x 0.6 mm, 0.5 mm pitch, package outline

Z Seating plane

ddd Z

A4

A2

A

A3

A1

A

E1

X

A1 ball

E

identifier index area

e

F

D1

D

e

Y

M

12

1

Øb (100 balls)

Øeee M Z Y X

Øfff M Z

BOTTOM VIEW

TOP VIEW

A0C2_ME_V2

1. Drawing is not to scale.

Table 66. UFBGA100 - 7 x 7 x 0.6 mm, 0.5 mm pitch, package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

0.530

0.460

0.050

0.400

0.080

0.270

0.200

6.950

5.450

6.950

5.450

0.600

0.0209

0.0181

0.0236

A1

A2

A3

A4

b

0.080

0.450

0.130

0.320

0.250

7.000

5.500

7.000

5.500

0.110

0.500

0.180

0.370

0.300

7.050

5.550

7.050

5.550

0.0031

0.0177

0.0051

0.0126

0.0098

0.2756

0.2165

0.2756

0.2165

0.0020

0.0157

0.0031

0.0106

0.0079

0.2736

0.2146

0.2736

0.2146

0.0043

0.0197

0.0071

0.0146

0.0118

0.2776

0.2185

0.2776

0.2185

D

D1

E

E1

e

0.500

0.750

0.0197

0.0295

F

0.700

0.800

0.100

0.0276

0.0315

0.0039

ddd

eee

fff

0.150

0.050

0.0059

0.0020

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 17659 Rev 8

111/121

Package characteristics

STM32L151x6/8/B, STM32L152x6/8/B

Figure 40. TFBGA64 - 8.0x8.0x1.2 mm, 0.5 mm pitch, package outline

Z Seating plane

ddd Z

A4

A2

A1

A

E1

X

A1 ball

E

identifier index area

e

F

A

H

F

D1

D

e

Y

8

1

Øb (64 balls)

Øeee M Z Y X

Øfff M Z

BOTTOM VIEW

TOP VIEW

R8_ME_V3

1. Drawing is not to scale.

Table 67. TFBGA64 - 8.0x8.0x1.2 mm, 0.5 mm pitch, package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

A4

b

1.200

0.0472

0.150

0.0059

0.200

0.0079

0.600

0.350

5.150

0.0236

0.0138

0.2028

0.300

5.000

3.500

5.000

3.500

0.500

0.750

0.250

4.850

0.0118

0.1969

0.1378

0.1969

0.1378

0.0197

0.0295

0.0098

0.1909

D

D1

E

4.850

5.150

0.1909

0.2028

E1

e

F

ddd

eee

fff

0.080

0.150

0.050

0.0031

0.0059

0.0020

1. Values in inches are converted from mm and rounded to 4 decimal digits.

112/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Package characteristics

Figure 41. Recommended PCB design rules for pads (0.5 mm pitch BGA)

0.5 mm

Pitch

D pad

0.27 mm

0.35 mm typ (depends on

the soldermask registration

tolerance)

Dsm

Solder paste

0.27 mm aperture diameter

Dpad

Dsm

ai15495

1. Non solder mask defined (NSMD) pads are recommended

2. 4 to 6 mils solder paste screen printing process

Doc ID 17659 Rev 8

113/121

Package characteristics

STM32L151x6/8/B, STM32L152x6/8/B

7.2

Thermal characteristics

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max × Θ )

J

A

D

JA

Where:

●

T max is the maximum ambient temperature in °C,

A

Θ

is the package junction-to-ambient thermal resistance, in °C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (V × I ) + Σ((V – V ) × I ),

OL OL DD OH OH

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 68. Thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

BGA100 - 7 x 7 mm

59

Thermal resistance junction-ambient

LQFP100 - 14 x 14 mm / 0.5 mm pitch

46

65

45

55

16

Thermal resistance junction-ambient

TFBGA64 - 5 x 5 mm

Θ_JA

°C/W

Thermal resistance junction-ambient

LQFP64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

UFQFPN48 - 7 x 7 mm / 0.5 mm pitch

114/121

Doc ID 17659 Rev 8

STM32L151x6/8/B, STM32L152x6/8/B

Figure 42. Thermal resistance

Package characteristics

3000.00

'PSCJEEFOꢅBSFB

5+ꢅꢆꢅ5+ꢅNBY

2500.00

2000.00

UQFN48 7x7mm

LQFP48 7x7mm

PD (mW)

1500.00

LQFP64 10x10mm

LQFP100 14x14mm

UFBGA100 7x7mm

1000.00

500.00

0.00

100

75

50

25

0

Temperature(°C)

.4ꢀꢁꢂꢃꢄ7ꢁ

7.2.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

Doc ID 17659 Rev 8

115/121

Ordering information scheme

STM32L151x6/8/B, STM32L152x6/8/B

8

Ordering information scheme

Table 69. Ordering information scheme

Example:

STM32 L 151 C

8

T

6

D xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

L = Low power

Device subfamily

151: Devices without LCD

152: Devices with LCD

Pin count

C = 48 pins

R = 64 pins

V = 100 pins

Flash memory size

6 = 32 Kbytes of Flash memory

8 = 64 Kbytes of Flash memory

B = 128 Kbytes of Flash memory

Package

H = BGA

T = LQFP

U = UFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C

Options

No character = V_DDrange: 1.8 to 3.6 V and BOR enabled

D = V_DDrange: 1.65 to 3.6 V and BOR disabled

Packing

TR = tape and reel

No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

116/121

Doc ID 17659 Rev 8

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Revision history

9

Revision history

on

Table 70. Document revision history

Date

Revision

Changes

02-Jul-2010

1

Initial release.

Removed 5 V tolerance (FT) from PA3, PB0 and PC3 in Table 9:

STM32L15xxx pin definitions on page 36

Updated Table 15: Embedded reset and power control block

characteristics on page 51

01-Oct-2010

16-Dec-2010

2

3

Updated Table 16: Embedded internal reference voltage on page 53

Added Table 53: ADC clock frequency on page 90

Updated Table 54: ADC characteristics on page 90

Modified consumptions on page 1 and in Section 3.1: Low power

modes on page 13

LED_SEG8 removed on PB6

Updated Section 6: Electrical characteristics on page 47

VFQFPN48 replaced by UFQFPN48

Features: updated value of Low-power sleep.

Section 3.3.2: Power supply supervisor: updated note.

Table 9: STM32L15xxx pin definitions: modified main function (after

reset) and alternate function for OSC_IN and OSC_OUT pins; modified

footnote 5; added footnote to OSC32_IN and OSC32_OUT pins; C1

and D1 removed on PD0 and PD1 pins (TFBGA64 column).

Section 3.11: DAC (digital-to-analog converter): updated bullet list.

Table 11: Voltage characteristics on page 49: updated footnote 3

regarding I_INJ(PIN)

.

Table 12: Current characteristics on page 49: updated footnote 4

regarding positive and negative injection.

Table 15: Embedded reset and power control block characteristics on

page 51: updated typ and max values for T_RSTTEMPO(V_DDrising, BOR

enabled).

Table 17: Current consumption in Run mode, code with data

processing running from Flash on page 54: removed values for HSI

clock source (16 MHz), Range 3.

25-Feb-2011

4

Table 18: Current consumption in Run mode, code with data

processing running from RAM on page 55: removed values for HSI

clock source (16 MHz), Range 3.

Table 19: Current consumption in Sleep mode on page 56: removed

values for HSI clock source (16 MHz), Range 3 for both RAM and

Flash; changed units.

Table 20: Current consumption in Low power run mode on page 57:

updated parameter and max value of I_DDMax (LP Run).

Table : on page 58: updated symbol, parameter, and max value of I_DD

Max (LP Sleep).

Table 18: Typical and maximum current consumptions in Stop mode:

updated values for I_{DD (Stop with RTC)}- RTC clocked by LSE external

clock (32.768 kHz), regulator in LP mode, HSI and HSE OFF (no

independent watchdog).

Doc ID 17659 Rev 8

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Revision history

STM32L151x6/8/B, STM32L152x6/8/B

Changes

Table 70. Document revision history (continued)

Date

Revision

Updated Table 23: Typical and maximum current consumptions in

Standby mode on page 61 (I_DD(WU from Standby) instead of (I_DD(WU

from Stop).

Table 24: Typical and maximum timings in Low power modes on

page 62: updated condition for Wakeup from Stop mode, regulator in

Run mode; updated max values for Wakeup from Stop mode, regulator

in low power mode; updated max values for t_WUSTDBY

.

Table 25: Peripheral current consumption on page 63: updated values

for column Low power sleep and run; updated Flash values; renamed

ADC1 to ADC; updated I_{DD (LCD)}value; updated units; added values for

I_{DD (RTC)}and I_{DD (IWDG)}; updated footnote 1 and 3; added foot note 2

concerning ADC.

Table 26: High-speed external user clock characteristics on page 65:

added min value for t_{w(HSE) w(HSE)}

max value for t_r(HSE)/t_f(HSE)OSC_IN rise or fall time; updated I_Lfor typ

and max values.

/t

OSC_IN high or low time; added

Table 27: Low-speed external user clock characteristics on page 66:

updated max value for I_L.

Table 28: HSE 1-24 MHz oscillator characteristics on page 68:

renamed i₂as I_HSEand updated max value; updated max values for

I_DD(HSE)

Table 29: LSE oscillator characteristics (f_LSE= 32.768 kHz) on page 69:

updated max value for I_LSE

Table 30: HSI oscillator characteristics on page 71: updated some min

and max values for ACC_HSI

Table 32: MSI oscillator characteristics on page 72: updated parameter,

typ, and max values for D_VOLT(MSI)

Table 35: Flash memory and data EEPROM characteristics on

page 74: updated typ values for t_prog

.

4

.

25-Feb-2011

cont’d

.

Table 44: I/O AC characteristics on page 81: updated some max values

for 01, 10, and 11; updated min value; updated footnotes.

Table 55: ADC accuracy on page 92: updated typ values and some of

the test conditions for ENOB, SINAD, SNR, and THD.

Table 57: DAC characteristics on page 96: updated footnote 7 and

added footnote 8.

Updated leakage value in Figure 26: Typical connection diagram using

the ADC.

Added Figure 27: Maximum dynamic current consumption on V_REF+

supply pin during ADC conversion.

Added Table 56: R_AINmax for f_ADC= 16 MHz on page 94

Figure 28: Power supply and reference decoupling (V_REF+not

connected to V_DDA): replaced all 10 nF capacitors with 100 nF

capacitors.

Figure 29: Power supply and reference decoupling (V_REF+connected to

V_DDA): replaced 10 nF capacitor with 100 nF capacitor.

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STM32L151x6/8/B, STM32L152x6/8/B

Revision history

Table 70. Document revision history (continued)

Date Revision

Changes

Modified 1st page (low power features)

Added STM32L15xC6 and STM32L15xR6 devices (32 Kbytes of Flash

memory).

Modified Section 3.6: GPIOs (general-purpose inputs/outputs) on

page 22

17-June-2011

5

Modified Section 6.3: Operating conditions on page 50

Modified Table 55: ADC accuracy on page 92, Table 57: DAC

characteristics on page 96 and Table 59: Comparator 1 characteristics

on page 99

Features: updated internal multispeed low power RC.

Table 2: Ultra-low-power STM32L15xxx device features and peripheral

counts: LCD 4x44 and 8x40 available for both 64- and 128-Kbyte

devices; two comparators available for all devices.

Figure 8: STM32L15xCx UFQFPN48 pinout: replaced VFQPN48 by

UFQFPN48 as name of package.

Table 9: STM32L15xxx pin definitions: replaced PH0/PH1 by

PC14/PC15.

Table 10: Alternate function input/output: removed EVENT OUT from

PH2 port, AFIO15 column.

Table 13: Functionalities depending on the operating power supply

range: added footnote 1.

Table 19: Current consumption in Sleep mode: updated MSI conditions

and f_HCLK

.

Table 20: Current consumption in Low power run mode: updated some

temperature conditions; added footnote 2.

Table : : updated some temperature conditions and one of the MSI

clock conditions.

Table 22: Typical and maximum current consumptions in Stop mode:

updated I_DD(WU from Stop) parameter.

25-Jan-2012

6

Table 23: Typical and maximum current consumptions in Standby

mode: updated I_DD(WU from Standby) parameter.

Table 24: Typical and maximum timings in Low power modes: updated

f_HCLKvalue for t_{WUSLEEP_LP}; updated typical value of parameter

“Wakeup from Stop mode, regulator in Run mode”.

Table 25: Peripheral current consumption: replaced GPIOF by GPIOH.

Table 33: PLL characteristics: updated “PLL output clock”

Table 35: Flash memory and data EEPROM characteristics: updated all

information for I_DD

.

Figure 18: I/O AC characteristics definition: replaced the falling edge

“t_r(IO)out” by “t_f(IO)out”.

Table 47: I²C characteristics: amended footnote 2.

Table 54: ADC characteristics: updated f_Smax value for direct

channels, 6-bit sampling rate.

Table 55: ADC accuracy: Updated the first, third and fourth f_ADCtest

condition.

Table 58: Temperature sensor characteristics: updated typ, min, and

max values of the T_{S_temp}parameter.

Doc ID 17659 Rev 8

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Revision history

STM32L151x6/8/B, STM32L152x6/8/B

Changes

Table 70. Document revision history (continued)

Date

Revision

Updated cover page

Updated Section 3.10: ADC (analog-to-digital converter)

Updated Table 3: Functionalities depending on the operating power

supply range, added Table 4: CPU frequency range depending on

dynamic voltage scaling and Table 5: Functionalities depending on the

working mode (from Run/active down to standby)

Updated Table 27: Low-speed external user clock characteristics

Added footnote 2. in Table 15: Embedded reset and power control block

characteristics

Updated Table 22: Typical and maximum current consumptions in Stop

mode and Table 23: Typical and maximum current consumptions in

Standby mode

Updated footnote 4. in Table 22: Typical and maximum current

consumptions in Stop mode

26-Oct-2012

7

Updated Table 44: I/O AC characteristics

Updated Table 47: I²C characteristics

Updated Table 49: SPI characteristics

Updated Section 6.3.8: Memory characteristics

Updated “non-robust” Table 54: ADC characteristics

Removed the note “position of 4.7 µf capacitor” in Section 6.1.6: Power

supply scheme

Updated Table 65: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package

mechanical data

Updated Table 64: LQFP48, 7 x 7 mm, 48-pin low-profile quad flat

package mechanical data

Added the resistance of TFBGA in Table 68: Thermal characteristics

Added Figure 42: Thermal resistance

Removed AHB1/AHB2 in Figure 1: Ultra-low-power STM32L15xxx

block diagram

Added IWDG and WWDG rows in Table 5: Functionalities depending

on the working mode (from Run/active down to standby)

Updated I_DD(Supply current during wakeup time from Standby mode)

in Table 23: Typical and maximum current consumptions in Standby

mode

The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz)"

replaced by "fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2

above 16 MHz (PLL ON)(2)” in Table 19: Current consumption in Sleep

mode

07-Feb-2013

8

Updated Stop mode current to 1.2 µA in Ultra-low-power platform

Updated entire Section 7: Package characteristics

Removed alternate function “I2C2_SMBA” for GPIO pin “PH2” in

Table 9: STM32L15xxx pin definitions

Updated Figure 26: Typical connection diagram using the ADC and

definition of symbol “R_AIN” in Table 54: ADC characteristics

Removed first sentence in Section : I2C interface characteristics

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STM32L151x6/8/B, STM32L152x6/8/B

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型号：	STM32L151RBT6TR
厂家：	ST
描述：	Ultra-low-power ARM Cortex-M3 MCU with 128 Kbytes Flash, 32 MHz CPU, USB 微控制器和处理器外围集成电路时钟
文件：	总121页 (文件大小：2252K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM32L151RBT6TR [STMICROELECTRONICS]

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