STM6510ZCACDG6F [STMICROELECTRONICS]
Dual push-button Smart ResetTM with capacitor-adjustable delays; 与电容可调延时双按钮式智能ResetTM
| 型号： | STM6510ZCACDG6F |
| 厂家： | 
ST |
| 描述： | Dual push-button Smart ResetTM with capacitor-adjustable delays |
| 文件： | 总26页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM6510
Dual push-button Smart ResetTM with capacitor-adjustable delays
Features
■ Dual Smart Reset™ push-button inputs with
capacitor-adjustable extended reset setup
delay (t
)
SRC
■ Capacitor-adjustable reset pulse duration
(t
)
REC
■ Power-on reset
– RST active-low, open-drain
■ Factory-programmable thresholds to monitor
TDFN8 (DG)
2 mm x 2 mm
V
in the range of 1.575 to 4.625 V typ.
CC
■ Operating voltage 1.0 V (active-low output
valid) to 5.5 V
■ Low supply current (1.4 µA)
Applications
■ Operating temperature: industrial grade –40 °C
to +85 °C
■ Mobile phones, smartphones
■ e-books
■ TDFN8 package: 2 mm x 2 mm x 0.75 mm
■ RoHS compliant
■ MP3 players
■ Games
■ Portable navigation devices
■ Any application that requires delayed reset
push-button(s) response for improved system
stability
February 2010
Doc ID 16788 Rev 2
1/26
www.st.com
1
Contents
STM6510
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
Smart Reset™ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
STM6510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
Power supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Ground (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
Smart Reset™ push-button inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . 9
Adjustable delay of Smart Reset™ input (SRC pin) . . . . . . . . . . . . . . . . 9
Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Adjustable reset timeout (TREC
pin) . . . . . . . . . . . . . . . . . . . . . . . . 10
ADJ
2
3
4
5
6
7
8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
Doc ID 16788 Rev 2
STM6510
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
tSRC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
tREC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Possible VCC voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 18
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 19
Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 16788 Rev 2
3/26
List of figures
STM6510
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Single-button Smart Reset™ typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Dual-button Smart Reset™ typical hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply current (I ) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Smart Reset™ delay (t
Reset timeout period (t
) vs. temperature, C
) vs. temperature, C
= 0.56 µF . . . . . . . . . . . . . . . . . . . . . . 11
= 0.01 µF . . . . . . . . . . . . . . . . . . . . . 12
SRC
SRC
REC
tREC
Figure 10. Reset threshold (V
) vs. temperature, “S” threshold option, V falling. . . . . . . . . . . . . 12
RST
CC
Figure 11. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline. . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. Package marking, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4/26
Doc ID 16788 Rev 2
STM6510
Description
1
Description
1.1
Smart Reset™ devices
The Smart Reset™ device family STM65xx provides a useful feature that ensures
inadvertent short reset push-button closures do not cause system resets. This is done by
implementing an extended Smart Reset™ input delay (t
). Once the valid Smart Reset™
SRC
input levels and setup delay are met, the device generates an output reset pulse with user-
programmable timeout period (t ).
REC
The typical application hookup shows that the dual Smart Reset™ inputs can be also
connected to the applications interrupt to allow the control of both the interrupt pin and the
hard reset functions. If the push-buttons are closed for a short time, the processor is only
interrupted. If the system still does not respond properly, holding the push-buttons for the
extended setup time (t
) causes a hard reset of the processor through the reset output.
SRC
The Smart Reset™ feature helps significantly increase system stability.
The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset
circuits targeted at applications such as MP3 players, portable navigation devices or mobile
phones, generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset™
inputs (SRx). The delayed Smart Reset™ setup time (t
) options are adjustable by
SRC
adding an external capacitor on the SRC pin or selectable by three-state logic. The delayed
setup period ignores switch closures shorter than t , thus preventing undesired resets.
SRC
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST)
output(s) with or without an internal pull-up resistor or push-pull as output options, with or
without the power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage V drops below the specified threshold. The
CC
reset output remains asserted for the reset timeout period (t
voltage goes above the specified threshold.
) after the monitored supply
REC
1.2
STM6510
The STM6510 has two combined Smart Reset™ inputs (SR0 and SR1) with Smart Reset™
setup delay (t ) programmed by an external capacitor on the SRC pin. An additional
SRC
STM6510 feature is adjustable output reset pulse time t
by adding an external capacitor
REC
(C
).
tREC
Additionally, the V is monitored and if it drops below the selected V
threshold, the
CC
RST
reset output goes active and remains active while V is below the V
threshold, plus the
CC
RST
defined duration of the reset pulse t
.
REC
Doc ID 16788 Rev 2
5/26
Description
STM6510
Figure 1.
Logic diagram
V
CC
SR0
SR1
SRC
RST
STM6510
TREC
ADJ
V
SS
AM00389a
Figure 2.
Pin connections
RST
1
8
7
V
CC
V
2
SR0
SS
STM
6510
SR1
NC
3
4
6
5
TREC
SRC
ADJ
AM00390
Table 1.
Symbol
Signal names
Input/output
Description
Reset output, active-low (open-drain).
Primary push-button Smart Reset™ input. Active-low, internal 65 kΩ
RST
SR0
Output
Input
pull-up resistor to VCC
.
Secondary push-button Smart Reset™ input. Active-low, internal 65 kΩ
SR1
SRC
Input
Input
Input
pull-up resistor to VCC
.
Smart Reset™ input delay setup control. Connect an external capacitor
to this pin to adjust the delay setup time (tSRC).
Input pin for tREC reset pulse duration adjustment. Connect an external
TRECADJ
capacitor (CtREC) to this pin to determine tREC
.
Supply voltage input. Power supply for the device and an input for the
monitored supply voltage. A 0.1 µF decoupling ceramic capacitor is
recommended to be connected between VCC and VSS pins.
VCC
Supply
Supply
VSS
NC
Ground
No connect (not bonded); should be connected to VSS.
6/26
Doc ID 16788 Rev 2
STM6510
Description
Figure 3.
Block diagram
V
CC
V
COMPARE
RST
65 kΩ
65 kΩ
t
REC
generator
RST
SR0
SR1
TREC
Logic
ADJ
C
tREC
SRC
AM00391a
Doc ID 16788 Rev 2
7/26
Description
STM6510
Figure 4.
Single-button Smart Reset™ typical hookup
V
CC
100 kΩ
V
V
CC
CC
RST
RESET
TREC
ADJ
SRC
C
C
tREC
SRC
STM6510
MCU
SR1
SR0
INT/
NMI
V
V
SS
SS
PUSH-BUTTON
SWITCH
AM04870v1
Note:
When only one Smart Reset™ input push-button is used, tie both the SR inputs together.
Figure 5.
Dual-button Smart Reset™ typical hookup
V
CC
100 kΩ
V
V
CC
CC
RST
SRC
RESET
TREC
ADJ
C
C
tREC
SRC
MCU
STM6510
SR1
SR0
INT/
NMI
V
V
SS
SS
PUSH-BUTTON
SWITCH
PUSH-BUTTON
SWITCH
AM004871v1
8/26
Doc ID 16788 Rev 2
STM6510
Description
1.3
Pin descriptions
1.3.1
Power supply (V )
CC
This pin is used to provide the power to the Smart Reset™ device and to monitor the power
supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between
the V and V pins.
CC
SS
1.3.2
1.3.3
Ground (V )
SS
This is the supply ground for the device.
Smart Reset™ push-button inputs (SR0, SR1)
Both SR0 and SR1 need to be held active at the same time for at least t
to activate the
SRC
reset output pulse. Include an internal 65 kΩ pull-up resistor to V for each input.
CC
Figure 6.
Timing waveforms
t
t
REC
SRC
SR0
SR1
RST
AM00393
1.3.4
Adjustable delay of Smart Reset™ input (SRC pin)
This pin controls the setup time before the push-button action is validated by the reset
output. It is connected to an external capacitor (C ), which is tied to ground to provide the
SRC
desired value of setup time (t
).
SRC
Calculated t
and C
examples are given in Table 2. Refer also to Table 6.
SRC
SRC
Table 2.
t
programmed by an ideal external capacitor
Setup delay tSRC [s](1)(2)
SRC
Calculated CSRC
value [µF]
Closest common
CSRC value [µF]
Min.
Typ.
Max.
0.2
0.3
0.6
1
2
3
3
4.5
9
4
6
0.22
0.33
0.56
1
6
12
20
10
15
1. Example calculations based on an ideal capacitor. During application design and component selection it
should be considered that the current flowing into the external tSRC programming capacitor (CSRC) is on
the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB
environment should be used to prevent tSRC accuracy from being affected. A recommended minimum
value of CSRC is 0.01 µF.
2. In case of repeated activations of the tSRC counter, an interval of 10 ms min. is needed between the
activations to fully discharge CSRC, so that the next tSRC is as specified.
Doc ID 16788 Rev 2
9/26
Description
STM6510
1.3.5
Reset output (RST)
RST is active-low, open-drain.
1.3.6
Adjustable reset timeout (TREC
pin)
ADJ
The reset timeout (t
) is adjustable by connecting an external capacitor C
to this pin.
REC
tREC
Calculated t
and C
examples are given in Table 3. Refer also to Table 6.
REC
tREC
Table 3.
t
programmed by an ideal external capacitor
tREC [ms](1)(2)
REC
Calculated CtREC
value [µF]
Closest common
tREC value [µF]
C
Min.
Typ.
Max.
0.001
0.002
0.01
10
20
15
30
20
40
0.001
0.0022
0.01
100
140
280
560
1120
150
210
420
840
1680
200
280
560
1120
2240
0.014
0.028
0.056
0.112
0.015
0.027
0.056
0.1
1. Example calculations based on an ideal capacitor. During application design and component selection it
should be considered that the current flowing into the external tREC programming capacitor (CtREC) is on
the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB
environment should be used to prevent tREC accuracy from being affected. A recommended minimum
value of CtREC is 0.001 µF.
2. In case of repeated activations of the tREC counter, an interval of 10 ms min. is needed between tREC
intervals to fully discharge CtREC, so that the next tREC is as specified.
10/26
Doc ID 16788 Rev 2
STM6510
2
Typical operating characteristics
Typical operating characteristics
Figure 7.
Supply current (I ) vs. temperature
CC
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature [°C]
AM04876v1
5.5 V
3.3 V
5 V
3 V
Figure 8.
Smart Reset™ delay (t
) vs. temperature, C
= 0.56 µF
SRC
SRC
12
11
10
9
8
7
6
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature [°C]
AM04877v1
5.75 V
5.5 V
3.3 V
Doc ID 16788 Rev 2
11/26
Typical operating characteristics
STM6510
Figure 9.
Reset timeout period (t
) vs. temperature, C
= 0.01 µF
REC
tREC
200
190
180
170
160
150
140
130
120
110
100
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature [°C]
5.75 V
5.5 V
3.3 V
AM04878v1
Figure 10. Reset threshold (V
) vs. temperature, “S” threshold option, V falling
CC
RST
2.99
2.97
2.95
2.93
2.91
2.89
2.87
2.85
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature [°C]
AM04879v1
12/26
Doc ID 16788 Rev 2
STM6510
Maximum ratings
3
Maximum ratings
Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics™ SURE
Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TSTG
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
Thermal resistance (junction to ambient)
Input or output voltage
–55 to +150
260
°C
°C
(1)
TSLD
TDFN8
149.0
°C/W
V
θJA
VIO
–0.3 to VCC +0.3
–0.3 to 7
VCC
Supply voltage
V
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Doc ID 16788 Rev 2
13/26
DC and AC parameters
STM6510
4
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the Table 6: DC and AC characteristics that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 5: Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 5.
Operating and measurement conditions
Parameter Value
CC supply voltage
Unit
V
1.0 to 5.5
–40 to +85
≤ 5
V
°C
ns
V
Ambient operating temperature (TA)
Input rise and fall times
Input pulse voltages
0.2 to 0.8 VCC
0.3 to 0.7 VCC
Input and output timing ref. voltages
V
Figure 11. AC testing input/output waveforms
0.8 V
CC
0.7 V
CC
0.2 V
0.3 V
CC
CC
AM00478
14/26
Doc ID 16788 Rev 2
STM6510
DC and AC parameters
Table 6.
Symbol
DC and AC characteristics
Parameter
Test conditions(1)
Reset output valid - active-low
CC = 5.0 V
Min.
Typ.(2)
Max.
Units
VCC
ICC
Supply voltage range
Supply current (VCC
1.0
5.5
2.4
V
µA
µA
V
V
1.5
1.4
)
VCC = 3.0 V(3)
VCC ≥ 4.5 V, sinking 3.2 mA
VCC ≥ 3.3 V, sinking 2.5 mA
VCC ≥ 1.0 V, sinking 0.1 mA
0.3
0.3
0.3
VOL
Reset output voltage low
V
V
VRST
–2.5%
VRST
+2.5%
–40 to +85 °C
25 °C
VRST
VRST
V
V
VCC undervoltage reset
threshold (refer to Table 7)
VRST
VRST
–2.0%
VRST
+2.0%
L, M
0.5%
1%
VHYST Hysteresis of VRST
CC to reset delay(4)
T, S, R, Z, Y, W, V
VCC falling from (VRST + 100 mV)
to (VRST - 100 mV) at 10 mV/µs
V
20
µs
User-adjustable reset timeout
period on RST. Refer to
Table 3.
10 000 x 15000x 20 000 x
(4)
tREC
CtREC
(µF)
CtREC
(µF)
CtREC
(µF)
ms
Smart Reset™ inputs
User-adjustable delayed Smart
10 x
CSRC
(µF)
15 x
CSRC
(µF)
20 x
CSRC
(µF)
(5)
tSRC
Reset™ setup time. Refer to
s
Table 2.
VIL
VIH
SR0, SR1 input voltage low
SR0, SR1 input voltage high
0.3 VCC
V
V
0.7 VCC
Internal pull-up resistor, SR0,
SR1 inputs
RPUI
65
kΩ
1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 to 5.5 V (except where noted).
2. Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted.
3. For devices with VRST < 3.0 V.
4. Guaranteed by design.
5. Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite).
Doc ID 16788 Rev 2
15/26
DC and AC parameters
Table 7.
STM6510
Unit
Possible V voltage thresholds
CC
2.5% (–40 °C to +85 °C)
2.0% (25 °C)
VCC voltage
threshold VRST
Typ.
Min.
Max.
Min.
Max.
L (falling)
M (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
4.625
4.375
3.075
2.925
2.625
2.313
2.188
1.665
1.575
4.509
4.266
2.998
2.852
2.559
2.255
2.133
1.623
1.536
4.741
4.484
3.152
2.998
2.691
2.371
2.243
1.707
1.614
4.533
4.288
3.014
2.867
2.573
2.267
2.144
1.632
1.544
4.718
4.463
3.137
2.984
2.678
2.359
2.232
1.698
1.607
V
V
V
V
V
V
V
V
V
16/26
Doc ID 16788 Rev 2
STM6510
Package mechanical data
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Doc ID 16788 Rev 2
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Package mechanical data
Figure 12. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline
STM6510
D
A
B
PIN 1 INDEX AREA
E
2x
C
0.10
0.10 C 2x
TOP VIEW
0.10
C
A
C
A1
SEATING
PLANE
SIDE VIEW
e
0.08
C
b
PIN 1 INDEX AREA
0.10
C A B
1
4
Pin#1 ID
L
5
8
BOTTOM VIEW
8070540_A
Table 8.
Symbol
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data
Dimension (mm)
Dimension (inches)
Min.
Nom.
Max.
Min.
Nom.
Max.
A
A1
b
0.70
0.00
0.15
0.75
0.02
0.20
0.80
0.05
0.25
0.028
0.000
0.006
0.030
0.001
0.008
0.031
0.002
0.010
D
2.00
2.00
0.079
0.079
BSC
E
BSC
e
L
0.50
0.55
0.020
0.022
0.45
0.65
0.018
0.026
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Doc ID 16788 Rev 2
STM6510
Package mechanical data
Figure 13. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad
D
P
E
E1
L
b
AM00441
Table 9.
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package
Dimension (mm)
Description
Parameter
Min.
Nom.
Max.
L
b
Contact length
1.05
0.25
—
1.15
0.30
—
—
—
Contact width
E
Max. land pattern Y-direction
Contact gap spacing
Max. land pattern X-direction
Contact pitch
2.75
0.65
1.75
0.5
E1
D
P
—
—
—
—
—
—
Doc ID 16788 Rev 2
19/26
Package mechanical data
Figure 14. Carrier tape
STM6510
P
0
D
P
2
T
E
A
0
F
Top cover
tape
W
B
0
Center lines
of cavity
K
0
P
1
User direction of feed
AM03073v2
Table 10. Carrier tape dimensions
Bulk
Unit
Package
W
D
E
P0
P2
F
A0
B0
K0
P1
T
qty.
8.00
+0.30 +0.10/
–0.10 –0.00
1.50
1.75
0.10
4.00
0.10
2.00
0.10
3.50
0.05
2.30
0.05
2.30
0.05
1.00
0.05
4.00 0.250
0.10 0.05
TDFN8
mm 3000
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Doc ID 16788 Rev 2
STM6510
Package mechanical data
Figure 15. Reel dimensions
T
40 mm min.
acces hole
at slot location
B
D
C
N
A
Full radius
Tape slot
in core for
tape start
25 mm min width
G measured
at hub
AM00443
Table 11. Reel dimensions
Tape sizes
A max.
B min.
C
D min.
N min.
G
T max.
8 mm
180 (7 inches)
1.50
13.0 +/– 0.20
20.20
60
8.4 +2/–0 14.40
Doc ID 16788 Rev 2
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Package mechanical data
Figure 16. Tape trailer/leader
STM6510
End
Start
Top
No components
Components
100 mm min. No components
cover
tape
T RA IL ER
L EA D ER
160 mm min.
400 mm min.
Sealed with cover tape
User direction of feed
AM00444
Figure 17. Pin 1 orientation
User direction of feed
AM00442
Note:
1
2
Drawings are not to scale.
All dimensions are in mm, unless otherwise noted.
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Doc ID 16788 Rev 2
STM6510
Part numbering
6
Part numbering
Table 12. Ordering information scheme
Example:
STM6510
W
C
A
C
DG
6
F
Device type
STM6510
Reset (VCC monitoring threshold) voltage VRST
L = 4.625 V (typ., falling)
M = 4.375 V
T = 3.075 V
S = 2.925 V
R = 2.625 V
Z = 2.313 V
Y = 2.188 V
W = 1.665 V
V = 1.575 V
Smart Reset™ setup delay control (tSRC); presence of internal input pull-up on all
Smart Reset™ inputs (SR0, SR1)
C = 1 to 15 s, user-programmable (external capacitor); 65 kΩ input pull-up
Output type
A = open-drain, active-low
Reset timeout period (tREC
)
C = user-programmable (external capacitor)
Package
DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch
Temperature range
6 = –40 °C to +85 °C
Shipping method
F = ECOPACK® package, tape and reel
For device options currently available refer to Table 13. For other options, voltage threshold values etc. or
for more information on any aspect of this device, please contact the ST sales office nearest you.
Doc ID 16788 Rev 2
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Package marking
STM6510
7
Package marking
Table 13. Package marking
tSRC
Smart
Reset™
inputs type
Reset
tREC
Part name
delay
VRST
Topmark
output type programming
control
STM6510WCACDG6F
STM6510SCACDG6F
STM6510RCACDG6F
CSRC
CSRC
CSRC
AL, PU
AL, PU
AL, PU
W
S
AL, OD
AL, OD
AL, OD
CtREC
CtREC
CtREC
8WK
8SK
8RK
R
Note:
AL = Active-Low, AH = Active-High; PU = with internal pull-up resistor, OD = Open-Drain.
Figure 18. Package marking, top view
A
B
E
C
D
Topmark
A = dot (pin 1 reference)
B = assembly plant (P)
C = assembly year (Y, 0-9): 9 = 2009 etc.
D = assembly work week (WW, 01 to 52): 20 = WW20 etc.
E = marking area (topmark)
AM00479
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Doc ID 16788 Rev 2
STM6510
Revision history
8
Revision history
Table 14. Document revision history
Date
Revision
Changes
12-Feb-2010
1
Initial release.
Updated title of datasheet, Features, Applications; updated footnote 1
of Table 2; updated Table 6, 12, 13; Figure 3; Section 1.3.3; minor
textual and formatting changes.
26-Feb-2010
2
Doc ID 16788 Rev 2
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STM6510
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Doc ID 16788 Rev 2
相关型号：
STM6513
Dual push-button Smart ResetTM with dual reset outputs and user-selectable setup delay
STMICROELECTR
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