STM705DS6F [STMICROELECTRONICS]
5 V supervisor; 5 V主管
| 型号： | STM705DS6F |
| 厂家： | 
ST |
| 描述： | 5 V supervisor |
| 文件： | 总32页 (文件大小：835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM705, STM706
STM707, STM708, STM813L
5 V supervisor
Features
■ 5 V operating voltage
■ Precision V monitor
CC
8
– STM705/707/813L
– 4.50 V ≤ V
≤ 4.75 V
RST
– STM706/708
1
– 4.25 ≤ V
≤ 4.50 V
RST
SO8 (M)
■ RST and RST outputs
■ 200 ms (typ) t
rec
■ Watchdog timer - 1.6 s (typ)
■ Manual reset input (MR)
■ Power-fail comparator (PFI/PFO)
■ Low supply current - 40 µA (typ)
■ Guaranteed RST (RST) assertion down to
(1)
TSSOP8 3x3 (DS)
V
= 1.0 V
CC
■ Operating temperature: –40 °C to 85 °C
(industrial grade)
■ RoHS compliance
1. Contact local ST sales office for availability.
– Lead-free components are compliant with
the RoHS directive
Table 1.
Device summary
Watchdog
input
Watchdog
output(1)
Active-low
RST(1)
Active-high Manual reset
Power-fail
comparator
RST(1)
input
STM705
STM706
STM707
STM708
STM813L
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
1. Push-pull output
August 2010
Doc ID 10520 Rev 9
1/33
www.st.com
1
Contents
STM705, STM706, STM707, STM708, STM813L
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Watchdog input (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Watchdog output (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . . 12
Interfacing to microprocessors with bidirectional reset pins . . . . . . . . . . . 13
4
5
6
7
8
9
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO8 - 8-lead plastic small outline, 150 mils body width, pack. mech. data . . . . . . . . . . . . 28
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 29
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 10520 Rev 9
3/33
List of figures
STM705, STM706, STM707, STM708, STM813L
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic diagram (STM707/708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
STM705/706/813L SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM705/706/813L TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM707/708 SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM707/708 TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block diagram (STM707/708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Reset output valid to ground circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.
V
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PFI
Figure 14. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Power-up t vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
rec
Figure 16. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Watchdog time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Output voltage vs. load current (V = 5 V; T = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CC
A
Figure 20. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 26. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 28. Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 30. Watchdog timing (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 31. SO8 – 8-lead plastic small outline, 150 mils body width, outline . . . . . . . . . . . . . . . . . . . . 28
Figure 32. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline . . . . . . . . . . . . . 29
4/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Description
1
Description
The STM705/706/707/708/813L supervisors are self-contained devices which provide
microprocessor supervisory functions. A precision voltage reference and comparator
monitors the V input for an out-of-tolerance condition. When an invalid V condition
CC
CC
occurs, the reset output (RST) is forced low (or high in the case of RST).
These devices also offer a watchdog timer (except for STM707/708) as well as a power-fail
comparator to provide the system with an early warning of impending power failure.
These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin
TSSOP package.
Figure 1.
Logic diagram (STM705/706/813L)
V
CC
WDO
WDI
(1)
RST
RST
STM705/706;
STM813L
MR
(2)
PFI
PFO
V
SS
AI08825
1. For STM705/706 only.
2. For STM813L only.
Figure 2.
Logic diagram (STM707/708)
V
CC
RST
MR
PFI
RST
PFO
STM707/708
V
SS
AI08826
Doc ID 10520 Rev 9
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Description
STM705, STM706, STM707, STM708, STM813L
Table 2.
Signal names
MR
Push-button reset input
Watchdog input
Watchdog output
Active-low reset output
Active-high reset output
Supply voltage
WDI
WDO
RST
RST(1)
VCC
PFI
Power-fail input
Power-fail output
Ground
PFO
VSS
NC
No connect
1. For STM813L only.
Figure 3.
STM705/706/813L SO8 connections
SO8
MR
1
2
3
4
8
7
6
5
WDO
(1)
V
RST (RST)
WDI
CC
V
SS
PFI
PFO
AI08827a
1. For STM813L, reset output is active-high.
Figure 4.
STM705/706/813L TSSOP8 connections
TSSOP8
(1)
WDI
PFO
PFI
1
2
3
4
8
7
6
5
(RST) RST
WDO
MR
V
V
SS
CC
AI09114
1. For STM813L, reset output is active-high.
6/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Description
Figure 5.
STM707/708 SO8 connections
SO8
MR
RST
RST
NC
1
2
3
4
8
7
6
5
V
CC
V
SS
PFI
PFO
AI08828a
Figure 6.
STM707/708 TSSOP8 connections
TSSOP8
RST
NC
1
2
3
4
8
7
6
5
RST
MR
PFO
PFI
V
V
SS
CC
AI09115
Doc ID 10520 Rev 9
7/33
Pin descriptions
STM705, STM706, STM707, STM708, STM813L
2
Pin descriptions
2.1
MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for t after MR returns high. This active-low input has an internal pull-up. It can be
rec
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
2.2
2.3
WDI
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset
(or WDO) is triggered. The internal watchdog timer clears while reset is asserted or when
WDI sees a rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
WDO
It goes low when a transition does not occur on WDI within 1.6 s, and remains low until
a transition occurs on WDI (indicating the watchdog interrupt has been serviced). WDO also
goes low when V falls below the reset threshold; however, unlike the reset output, WDO
CC
goes high as soon as V exceeds the reset threshold. Output type is push-pull.
CC
Note:
For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO
is connected to MR.
2.4
RST
Pulses low when triggered, and stays low whenever V is below the reset threshold or
CC
when MR is a logic low. It remains low for t after either V rises above the reset
rec
CC
threshold, or MR goes from low to high.
2.5
2.6
RST
Goes high with triggered, and stays high whenever V is above the reset threshold or
when MR is a logic high. It stays high for t after either V falls below the reset threshold,
or MR goes from high to low.
CC
rec
CC
PFI
When PFI is less than V , PFO goes low; otherwise, PFO remains high. Connect to
PFI
ground if unused.
8/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Pin descriptions
2.7
PFO
When PFI is less than V , PFO goes low; otherwise, PFO remains high. Leave open if
PFI
unused. Output type is push-pull.
Table 3.
Pin description
Pin
Name
Function
STM707
STM708
STM705
STM706
STM813L
1
6
1
—
—
7
1
6
MR
WDI
WDO
RST
RST
VCC
PFI
Push-button reset input
Watchdog input
8
8
Watchdog output (push-pull)
Active-low reset output
Active-high reset output
Supply voltage
—
7
7
8
—
2
2
2
4
4
4
Power-fail input
5
5
5
PFO
VSS
NC
Power-fail output (push-pull)
Ground
3
3
3
—
6
—
No connect
Figure 7.
Block diagram (STM705/706/813L)
WDI
transitional
detector
WATCHDOG
TIMER
WDI
WDO
V
CC
V
COMPARE
RST
V
CC
t
(1)
rec
RST (RST)
PFO
MR
PFI
generator
V
COMPARE
PFI
AI08829
1. For STM813L only.
Doc ID 10520 Rev 9
9/33
Pin descriptions
STM705, STM706, STM707, STM708, STM813L
Figure 8.
Block diagram (STM707/708)
V
CC
COMPARE
COMPARE
5 V
V
RST
RST
V
CC
t
rec
RST
MR
PFI
generator
V
PFO
PFI
AI08830
Figure 9.
Hardware hookup
Regulator
Unregulated
voltage
V
V
V
IN
CC
CC
STM705
STM706
STM707
STM708
STM813L
0.1 mF
(1)
(1)
WDO
WDI
To microprocessor IRQ
R1
R2
From microprocessor
PFI
MR
PFO
RST
To microprocessor NMI
To microprocessor reset
Push-button
AI08831a
1. For STM705/706/813L.
10/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Operation
3
Operation
3.1
Reset output
The STM705/706/707/708/813L supervisor asserts a reset signal to the MCU whenever
goes below the reset threshold (V ), a watchdog time-out occurs (if WDO is tied to
V
CC
RST
MR), or when the push-button reset input (MR) is taken low. RST is guaranteed to be a logic
low (logic high for STM707/708/813L) for V < V
down to V =1 V for T = 0 °C to
CC
RST
CC A
85 °C.
During power-up, once V exceeds the reset threshold an internal timer keeps RST low for
CC
the reset time-out period, t . After this interval RST returns high.
rec
If V drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
CC
low for at least the reset time-out period (t ). Any time V goes below the reset threshold
rec
CC
the internal timer clears. The reset timer starts when V returns above the reset threshold.
CC
3.2
3.3
Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t (see
rec
Figure 29) after it returns high. The MR input has an internal 40 Ω pull-up resistor, allowing it
to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to V when
not used.
CC
Watchdog input (STM705/706/813L)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within t
timer is cleared by either:
(1.6 s), the reset is asserted. The internal 1.6s
WD
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 s (t
connected to MR.
+ t ), if WDO is
WD
rec
See Figure 30 for STM705/706/813L.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
Note:
The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
Doc ID 10520 Rev 9
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Operation
STM705, STM706, STM707, STM708, STM813L
3.4
Watchdog output (STM705/706/813L)
When V drops below the reset threshold, WDO will go low even if the watchdog timer has
CC
not yet timed out. However, unlike the reset output, WDO goes high as soon as V
CC
exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it
to the MR input.
3.5
Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the V
comparator). If PFI is less than the power-fail threshold (V ), the power-fail
RST
PFI
output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of
the V regulator. The voltage divider can be set up such that the voltage at PFI falls below
CC
V
several milliseconds before the regulated V input to the STM705/706/707/708/ 813L
PFI
CC
or the microprocessor drops below the minimum operating voltage.
If the comparator is unused, PFI should be connected to V and PFO left unconnected.
SS
PFO may be connected to MR on the STM703/704/818 so that a low voltage on PFI will
generate a reset output.
3.6
Ensuring a valid reset output down to VCC = 0 V
When V falls below 1 V, the state of the RST output can no longer be guaranteed, and
CC
becomes essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output will be held low during this condition. A resistor value of approximately
100 kΩ will be large enough to not load the output under operating conditions, but still
sufficient to pull RST to ground during this low voltage condition (see Figure 10).
Figure 10. Reset output valid to ground circuit
STMXXX
RST
R1
AI08835
12/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Operation
3.7
Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STM705-708 reset
output. For example, if the reset output is driven high and the micro wants to pull it low,
signal contention will result. To prevent this from occurring, connect a 4.7 kΩ resistor
between the reset output and the micro's reset I/O as in Figure 11.
Figure 11. Interfacing to microprocessors with bidirectional reset I/O
Buffered reset to other
system components
V
V
CC
CC
STMXXX
Microprocessor
4.7 k
RST
RST
GND
GND
AI08836
Doc ID 10520 Rev 9
13/33
Typical operating characteristics
STM705, STM706, STM707, STM708, STM813L
4
Typical operating characteristics
Typical values are at T = 25 °C.
A
Figure 12. Supply current vs. temperature (no load)
30
25
20
15
10
5
V
= 2.7 V
= 3.0 V
= 3.6 V
= 4.5 V
= 5.5 V
CC
V
CC
V
CC
V
CC
V
CC
0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09141b
Figure 13. V
threshold vs. temperature
PFI
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
V
= 2.5 V
= 3.0 V
= 3.3 V
= 3.6 V
CC
V
CC
V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09142b
14/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Typical operating characteristics
Figure 14. Reset comparator propagation delay vs. temperature
30
28
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09143b
Figure 15. Power-up t vs. temperature
rec
240
235
230
225
220
215
210
V
= 3.0 V
CC
V
= 4.5 V
= 5.5 V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09144b
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Typical operating characteristics
STM705, STM706, STM707, STM708, STM813L
Figure 16. Normalized reset threshold vs. temperature
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09145b
Figure 17. Watchdog time-out period vs. temperature
1.90
1.85
1.80
1.75
1.70
1.65
1.60
V
= 3.0 V
= 4.5 V
= 5.5 V
CC
V
V
CC
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09146b
16/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Typical operating characteristics
Figure 18. PFI to PFO propagation delay vs. temperature
4.0
V
= 3.0 V
= 3.6 V
= 4.5 V
= 5.5 V
CC
V
CC
3.0
2.0
1.0
0.0
V
CC
V
CC
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09148b
Figure 19. Output voltage vs. load current (V = 5 V; T = 25 °C)
CC
A
5.00
4.98
4.96
4.94
0
10
20
30
40
50
I
(mA)
OUT
AI10496
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Typical operating characteristics
STM705, STM706, STM707, STM708, STM813L
Figure 20. RST output voltage vs. supply voltage
5
5
4
V
RST
V
CC
4
3
2
3
2
1
0
1
0
500 ms / div
AI09149b
Figure 21. RST output voltage vs. supply voltage
5
5
4
3
2
1
0
V
RST
V
CC
4
3
2
1
0
500 ms / div
AI09150b
18/33
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STM705, STM706, STM707, STM708, STM813L
Figure 22. RST response time (assertion)
Typical operating characteristics
5 V
1 V / div
4 V
V
CC
5 V
4 V
RST
1V/div
0 V
5 µs / div
AI09151b
1. VRST = 4.603 V at 25 °C.
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Typical operating characteristics
STM705, STM706, STM707, STM708, STM813L
Figure 23. RST response time (assertion)
5 V
4 V
V
CC
1 V / div
4 V
RST
1 V / div
0 V
5 µs / div
AI09152b
1. VRST = 4.603 V at 25 °C.
Figure 24. Power-fail comparator response time (assertion)
5 V
1 V / div
PFO
0 V
1.3 V
PFI
500 mV / div
0 V
500 ns / div
AI09153b
20/33
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STM705, STM706, STM707, STM708, STM813L
Typical operating characteristics
Figure 25. Power-fail comparator response time (de-assertion)
5 V
1 V / div
PFO
0 V
PFI
1.3 V
500 mV / div
0 V
AI09154b
500 ns / div
Figure 26. Maximum transient duration vs. reset threshold overdrive
6000
5000
4000
Reset occurs
above the curve
3000
2000
1000
0
0.001
0.01
0.1
1
10
Reset comparator overdrive, V
– V
(V)
CC
RST
AI09156b
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Maximum ratings
STM705, STM706, STM707, STM708, STM813L
5
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4.
Symbol
TSTG
Absolute maximum ratings
Parameter
Value
Unit
Storage temperature (V
Off)
–55 to 150
260
°C
°C
V
CC
(1)
TSLD
VIO
VCC
IO
Lead solder temperature for 10 seconds
Input or output voltage
Supply voltage
–0.3 to VCC +0.3
–0.3 to 7.0
20
V
Output current
mA
mW
PD
Power dissipation
320
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
22/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
DC and AC parameters
6
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
STM705/706/707/708; STM813L
Unit
V
CC supply voltage
1.0 to 5.5
–40 to 85
V
°C
ns
V
Ambient operating temperature (TA)
Input rise and fall times
≤
5
Input pulse voltages
0.2 to 0.8 VCC
0.3 to 0.7 VCC
Input and output timing ref. voltages
V
Figure 27. AC testing input/output waveforms
0.8 V
CC
0.7 V
CC
0.3 V
CC
0.2 V
CC
AI02568
Figure 28. Power-fail comparator waveform
V
CC
V
RST
t
rec
PFO
RST
AI08834b
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DC and AC parameters
STM705, STM706, STM707, STM708, STM813L
Figure 29. MR timing waveform
MR
t
MLRL
(1)
RST
t
t
rec
MLMH
AI07837a
1. RST for STM805.
Figure 30. Watchdog timing (STM705/706/813L)
V
CC
t
RST
WDI
rec
t
WD
WDO
AI08833
24/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
DC and AC parameters
Table 6.
Sym
DC and AC characteristics
Description
Test condition(1)
Min
Typ
Max
Unit
VCC Operating voltage
1.2(2)
5.5
60
V
µA
µA
nA
µA
µA
V
ICC
VCC supply current
25
125
2
Input leakage current (MR)
Input leakage current (PFI)
4.5 V < VCC < 5.5 V
0 V < VIN < VCC
75
300
+25
160
–25
ILI
WDI = VCC, time average
WDI = GND, time average
4.5 V < VCC < 5.5 V
120
–15
Input leakage current (WDI)
–20
2.0
VIH
VIH
VIL
VIL
Input high voltage (MR)
Input high voltage (WDI)
Input low voltage (MR)
Input low voltage (WDI)
VRST (max) < VCC < 5.5 V
4.5 V < VCC < 5.5 V
0.7 VCC
V
0.8
V
VRST (max) < VCC < 5.5 V
0.3 VCC
V
Output low voltage (PFO, RST,
RST, WDO)
VOL
VCC = VRST (max), ISINK = 3.2 mA
0.3
V
ISINK = 50 µA, VCC = 1.0 V,
TA = 0 °C to 85 °C
0.3
0.3
V
V
V
VOL Output low voltage (RST)
Output high voltage (RST, RST,
I
SINK = 100 µA, VCC = 1.2 V
ISOURCE = 1 mA,
2.4
WDO)
VCC = VRST (max)
VOH
ISOURCE = 75 µA,
VCC = VRST (max)
Output high voltage (PFO)
0.8 VCC
V
I
SOURCE = 4 µA, VCC = 1.1 V,
TA = 0 °C to 85 °C
0.8
0.9
V
V
VOH Output high voltage (RST)
I
SOURCE = 4 µA, VCC = 1.2 V
Power-fail comparator
VPFI PFI input threshold
PFI falling (VCC = 5 V)
1.20
1.25
2
1.30
V
tPFD PFI to PFO propagation delay
µs
Doc ID 10520 Rev 9
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DC and AC parameters
STM705, STM706, STM707, STM708, STM813L
Table 6.
Sym
DC and AC characteristics
Description
Test condition(1)
Min
Typ
Max
Unit
Reset thresholds
STM705/707/813L
STM706/708
4.50
4.25
4.65
4.40
25
4.75
4.50
V
V
VRST Reset threshold(3)
Reset threshold hysteresis
RST pulse width
mV
Blank (see Table 9)
A (see Table 9)
140
160
200
200
280
280
trec
ms
Push-button reset input
tMLMH
MR pulse width
150
ns
ns
(or tMR
)
tMLRL
(tMRD)
MR to RST output delay
250
Watchdog timer (STM705/706/813L)
tWD Watchdog timeout period
WDI pulse width
4.5 V < VCC < 5.5 V
4.5 V < VCC < 5.5 V
1.12
50
1.60
2.24
s
ns
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.75 V to 5.5 V for STM705/707/813L;
VCC = 4.5 V to 5.5 V for STM706/708 (except where noted).
2. VCC (min) = 1.0 V for TA = 0 °C to +85 °C.
3. For VCC falling.
26/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Doc ID 10520 Rev 9
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Package mechanical data
STM705, STM706, STM707, STM708, STM813L
Figure 31. SO8 – 8-lead plastic small outline, 150 mils body width, outline
A2
A
C
B
ddd
e
D
8
1
E
H
A1
L
SO-A
1. Drawing is not to scale.
Table 7.
Symbol
SO8 - 8-lead plastic small outline, 150 mils body width, pack. mech. data
mm
inches
Typ
Min
Max
Typ
Min
Max
A
A1
B
—
—
1.35
0.10
0.33
0.19
4.80
—
1.75
0.25
0.51
0.25
5.00
0.10
4.00
—
—
—
0.053
0.004
0.013
0.007
0.189
—
0.069
0.010
0.020
0.010
0.197
0.004
0.157
—
—
—
C
—
—
D
—
—
ddd
E
—
—
—
3.80
—
—
0.150
—
e
1.27
—
0.050
—
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
—
—
L
—
—
α
—
—
N
8
8
28/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Package mechanical data
Figure 32. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
D
8
1
5
4
c
E1
E
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
1. Drawing is not to scale.
Table 8.
TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
—
—
—
0.05
0.75
0.25
0.13
—
1.10
0.15
0.95
0.40
0.23
0.10
3.10
—
—
—
—
0.043
0.006
0.037
0.016
0.009
0.004
0.122
—
0.002
0.030
0.010
0.005
—
0.85
—
0.034
—
c
—
—
CP
D
—
—
3.00
0.65
4.90
3.00
0.55
0.95
—
2.90
—
0.118
0.026
0.193
0.118
0.022
0.037
—
0.114
—
e
E
4.65
2.90
0.40
—
5.15
3.10
0.70
—
0.183
0.114
0.016
—
0.203
0.122
0.030
—
E1
L
L1
α
0°
6°
0°
6°
N
8
8
Doc ID 10520 Rev 9
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Part numbering
STM705, STM706, STM707, STM708, STM813L
8
Part numbering
Table 9.
Example:
Ordering information scheme
STM705
M
6
E
Device type and reset threshold voltage
STM705/707/813L = VRST = 4.50 V to 4.75 V
STM706/708 = VRST = 4.25 V to 4.50 V
RST pulse width
Blank = 140 to 280 ms
A
(1) = 160 to 280 ms
Package
M = SO8
DS(2) = TSSOP8
Temperature range
6 = –40 to 85 °C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape and reel
1. Available for STM706/708 in SO8 (M) package only.
2. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Table 10. Marking description
Part number
Reset threshold
Package
Topside marking
SO8
TSSOP8
SO8
STM705
4.63 V
705
STM706
STM707
STM708
STM813L
4.38 V
4.63 V
4.38 V
4.63 V
706
707
TSSOP8
SO8
TSSOP8
SO8
708
TSSOP8
SO8
813L
TSSOP8
30/33
Doc ID 10520 Rev 9
STM705, STM706, STM707, STM708, STM813L
Revision history
9
Revision history
Table 11. Document revision history
Date
Revision
Changes
Sep-2003
1
Initial release.
31-Oct-2003
1.1
Update Table 6.
Reformatted; update characteristics (Figure 1, 2, 3, 4, 6, 8, 9, 10, 28;
29, 30, Table 7, 9, 11)
12-Dec-2003
16-Jan-2004
09-Apr-2004
2
2.1
3
Add typical characteristics (Figure 12 to 18, 20 to 26)
Reformatted; update characteristics (Figure 14, 18, 20 to 23, 26;
Table 7)
25-May-2004
02-Jul-2004
4
5
Update characteristics (Table 4, 7)
Document promoted; corrected waveform (Figure 28)
Clarify root part numbers, pin descriptions (Figure 2, 3, 10; Table 6, 7,
10)
21-Sep-2004
6
08-Mar-2005
02-Nov-2009
06-Aug-2010
7
8
9
Update typical characteristics (Figure 12 to 26)
Updated Table 1, 3, 4, 6, 9, Section 2.3, Section 2.7, text in Section 7.
Updated Features, Section 4: Typical operating characteristics,Table 9.
Doc ID 10520 Rev 9
31/33
STM705, STM706, STM707, STM708, STM813L
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