STM8S103K3P3TR [STMICROELECTRONICS]
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash;
| 型号： | STM8S103K3P3TR |
| 厂家： | 
ST |
| 描述： | Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash |
| 文件： | 总113页 (文件大小：1267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM8S103K3 STM8S103F3 STM8S103F2
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data
EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
Permanently active, low consumption power-on
and power-down reset
•
Interrupt management
Nested interrupt controller with 32 interrupts
•
UFQFPN32 5x5
LQFP32 7x7
Up to 27 external interrupts on 6 vectors
•
Timers
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
•
16-bit general purpose timer, with 3 CAPCOM
•
•
•
•
TSSOP20
SO20W 300 mils
channels (IC, OC or PWM)
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
UFQFPN20 3x3
Features
Core
Window watchdog and independent watchdog
timers
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
•
•
Communications interfaces
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
•
Extended instruction set
SPI interface up to 8 Mbit/s
I2C interface up to 400 Kbit/s
•
Memories
Program memory: 8 Kbytes Flash; data retention
20 years at 55 °C after 10 kcycles
•
•
•
•
Analog to digital converter (ADC)
Data memory: 640 bytes true data EEPROM;
endurance 300 kcycles
10-bit, ±1 LSB ADC with up to 5 multiplexed
channels, scan mode and analog watchdog
•
RAM: 1 Kbytes
I/Os
Clock, reset and supply management
Up to 28 I/Os on a 32-pin package including 21
high sink outputs
•
•
•
2.95 to 5.5 V operating voltage
•
Flexible clock control, 4 master clock sources:
•
Highly robust I/O design, immune against current
injection
Low power crystal resonator oscillator
-
External clock input
Development support
-
Embedded single wire interface module
(SWIM) for fast on-chip programming and
non intrusive debugging
Internal, user-trimmable 16 MHz RC
-
-
Internal low power 128 kHz RC
-
Clock security system with clock monitor
•
Unique ID
Power management:
•
96-bit unique key for each device
Low power modes (wait, active-halt, halt)
•
-
Switch-off peripheral clocks individually
-
September 2010
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Contents
STM8S103K3 STM8S103F3 STM8S103F2
Contents
1 Introduction ..............................................................................................................8
2 Description ...............................................................................................................9
3 Block diagram ........................................................................................................10
4 Product overview ...................................................................................................11
4.1 Central processing unit STM8 .....................................................................................11
4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11
4.3 Interrupt controller .......................................................................................................12
4.4 Flash program and data EEPROM memory ................................................................12
4.5 Clock controller ............................................................................................................13
4.6 Power management ....................................................................................................14
4.7 Watchdog timers ..........................................................................................................14
4.8 Auto wakeup counter ...................................................................................................15
4.9 Beeper ........................................................................................................................15
4.10 TIM1 - 16-bit advanced control timer .........................................................................15
4.11 TIM2 - 16-bit general purpose timer ..........................................................................16
4.12 TIM4 - 8-bit basic timer ..............................................................................................16
4.13 Analog-to-digital converter (ADC1) ............................................................................16
4.14 Communication interfaces .........................................................................................17
4.14.1 UART1 ...............................................................................................17
4.14.2 SPI .....................................................................................................18
4.14.3 I²C ......................................................................................................18
5 Pinout and pin description ...................................................................................19
5.1 STM8S103Kx UFQFPN32/LQFP32 pinout and pin description ..................................19
5.2 STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin description .....................22
5.2.1 STM8S103Fx TSSOP20/SO20 pinout .................................................22
5.2.2 STM8S103Fx UFQFPN20 pinout ........................................................23
5.2.3 STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description ................24
5.3 Alternate function remapping .......................................................................................25
6 Memory and register map .....................................................................................26
6.1 Memory map ................................................................................................................26
6.2 Register map ...............................................................................................................27
6.2.1 I/O port hardware register map ............................................................27
6.2.2 General hardware register map ..........................................................28
6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................38
7 Interrupt vector mapping ......................................................................................40
8 Option bytes ...........................................................................................................42
8.1 Alternate function remapping bits ................................................................................44
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Contents
9 Unique ID ................................................................................................................47
10 Electrical characteristics ....................................................................................48
10.1 Parameter conditions .................................................................................................48
10.1.1 Minimum and maximum values .........................................................48
10.1.2 Typical values .....................................................................................48
10.1.3 Typical curves ....................................................................................48
10.1.4 Loading capacitor ...............................................................................48
10.1.5 Pin input voltage .................................................................................49
10.2 Absolute maximum ratings ........................................................................................49
10.3 Operating conditions ..................................................................................................51
10.3.1 VCAP external capacitor ....................................................................52
10.3.2 Supply current characteristics ............................................................53
10.3.3 External clock sources and timing characteristics .............................63
10.3.4 Internal clock sources and timing characteristics ...............................65
10.3.5 Memory characteristics ......................................................................68
10.3.6 I/O port pin characteristics .................................................................69
10.3.7 Reset pin characteristics ....................................................................77
10.3.8 SPI serial peripheral interface ............................................................79
10.3.9 I2C interface characteristics ...............................................................82
10.3.10 10-bit ADC characteristics ................................................................83
10.3.11 EMC characteristics .........................................................................87
11 Package information ............................................................................................91
11.1 32-pin LQFP package mechanical data .....................................................................91
11.2 32-lead UFQFPN package mechanical data .............................................................93
11.3 20-lead UFQFPN package mechanical data .............................................................94
11.4 20-pin TSSOP package mechanical data ..................................................................96
11.5 20-pin SO package mechanical data .........................................................................97
11.6 UFQFPN recommended footprint ..............................................................................98
12 Thermal characteristics ....................................................................................100
12.1 Reference document ...............................................................................................101
12.2 Selecting the product temperature range ................................................................101
13 Ordering information .........................................................................................102
13.1 STM8S103 FASTROM microcontroller option list ...................................................103
14 STM8 development tools ..................................................................................108
14.1 Emulation and in-circuit debugging tools .................................................................108
14.2 Software tools ..........................................................................................................108
14.2.1 STM8 toolset ....................................................................................109
14.2.2 C and assembly toolchains ..............................................................109
14.3 Programming tools ..................................................................................................109
15 Revision history .................................................................................................110
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List of tables
STM8S103K3 STM8S103F3 STM8S103F2
List of tables
Table 1. STM8S103xx access line features .............................................................................................9
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14
Table 3. TIM timer features ....................................................................................................................16
Table 4. Legend/abbreviations for pinout tables ...................................................................................19
Table 5. UFQFPN32/LQFP32 pin description ........................................................................................20
Table 6. STM8S103Fx pin description ...................................................................................................24
Table 7. I/O port hardware register map ................................................................................................27
Table 8. General hardware register map ...............................................................................................28
Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................38
Table 10. Interrupt mapping ...................................................................................................................40
Table 11. Option bytes .........................................................................................................................110
Table 12. Option byte description ...........................................................................................................42
Table 13. STM8S103K alternate function remapping bits for 32-pin devices ........................................44
Table 14. STM8S103F alternate function remapping bits for 20-pin devices ........................................45
Table 15. Unique ID registers (96 bits) .................................................................................................110
Table 16. Voltage characteristics ...........................................................................................................49
Table 17. Current characteristics ...........................................................................................................50
Table 18. Thermal characteristics ..........................................................................................................50
Table 19. General operating conditions .................................................................................................51
Table 20. Operating conditions at power-up/power-down ......................................................................52
Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................53
Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................54
Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................55
Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................55
Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................56
Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................57
Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................58
Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................58
Table 29. Wakeup times .........................................................................................................................58
Table 30. Total current consumption and timing in forced reset state ....................................................59
Table 31. Peripheral current consumption .............................................................................................60
Table 32. HSE user external clock characteristics .................................................................................63
Table 33. HSE oscillator characteristics .................................................................................................64
Table 34. HSI oscillator characteristics ..................................................................................................65
Table 35. LSI oscillator characteristics ...................................................................................................67
Table 36. RAM and hardware registers ..................................................................................................68
Table 37. Flash program memory/data EEPROM memory ....................................................................68
Table 38. I/O static characteristics .........................................................................................................69
Table 39. Output driving current (standard ports) ..................................................................................71
Table 40. Output driving current (true open drain ports) ........................................................................71
Table 41. Output driving current (high sink ports) ..................................................................................72
Table 42. NRST pin characteristics ........................................................................................................77
Table 43. SPI characteristics ..................................................................................................................80
Table 44. I2C characteristics ..................................................................................................................82
Table 45. ADC characteristics ................................................................................................................84
Table 46. ADC accuracy with RAIN < 10 kΩ , VDD= 5 V .........................................................................84
Table 47. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V ..............................................................85
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List of tables
Table 48. EMS data ................................................................................................................................88
Table 49. EMI data .................................................................................................................................88
Table 50. ESD absolute maximum ratings .............................................................................................89
Table 51. Electrical sensitivities .............................................................................................................90
Table 52. 32-pin low profile quad flat package mechanical data ............................................................91
Table 53. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................93
Table 54. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data ....95
Table 55. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .........................................................97
Table 56. 20-lead, plastic small outline (300 mils) mechanical data ......................................................97
Table 57. Thermal characteristics ........................................................................................................100
Table 58. Document revision history ....................................................................................................110
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List of figures
STM8S103K3 STM8S103F3 STM8S103F2
List of figures
Figure 1. Block diagram .........................................................................................................................10
Figure 2. Flash memory organization ....................................................................................................13
Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................19
Figure 4. STM8S103Fx TSSOP20/SO20 pinout ....................................................................................22
Figure 5. STM8S103Fx UFQFPN20-pin pinout .....................................................................................23
Figure 6. Memory map ...........................................................................................................................26
Figure 7. Pin loading conditions .............................................................................................................48
Figure 8. Pin input voltage .....................................................................................................................49
Figure 9. fCPUmax versus VDD ................................................................................................................52
Figure 10. External capacitor CEXT .......................................................................................................53
Figure 11. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz .............................................61
Figure 12. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ....................................................61
Figure 13. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................62
Figure 14. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ..............................................62
Figure 15. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .....................................................63
Figure 16. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................63
Figure 17. HSE external clocksource .....................................................................................................64
Figure 18. HSE oscillator circuit diagram ...............................................................................................65
Figure 19. Typical HSI accuracy at VDD = 5 V vs 5 temperatures ..........................................................66
Figure 20. Typical HSI frequency variation vs VDD @ 4 temperatures ..................................................67
Figure 21. Typical LSI frequency variation vs VDD @ 4 temperatures ...................................................67
Figure 22. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................70
Figure 23. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................70
Figure 24. Typical pull-up current vs VDD @ 4 temperatures .................................................................71
Figure 25. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................72
Figure 26. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................73
Figure 27. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................73
Figure 28. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................74
Figure 29. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................74
Figure 30. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................75
Figure 31. Typ. VDD - VOH@ VDD = 5 V (standard ports) .......................................................................75
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ...................................................................76
Figure 33. Typ. VDD - VOH@ VDD = 5 V (high sink ports) .......................................................................76
Figure 34. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ....................................................................77
Figure 35. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................78
Figure 36. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................78
Figure 37. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................79
Figure 38. Recommended reset pin protection ......................................................................................79
Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................81
Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................81
Figure 41. SPI timing diagram - master mode(1) ...................................................................................82
Figure 42. Typical application with I2C bus and timing diagram ............................................................86
Figure 43. ADC accuracy characteristics ...............................................................................................86
Figure 44. Typical application with ADC ................................................................................................87
Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................91
Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................93
Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................94
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List of figures
Figure 48. 20-pin, 4.40 mm body, 0.65 mm pitch ...................................................................................97
Figure 49. 20-lead, plastic small outline (300 mils) package .................................................................97
Figure 50. Recommended footprint for on-board emulation ..................................................................98
Figure 51. Recommended footprint without on-board emulation ...........................................................99
Figure 52. STM8S103x access line ordering information scheme ......................................................102
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Introduction
STM8S103K3 STM8S103F3 STM8S103F2
1
Introduction
This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and peripherals,
please refer to the STM8S microcontroller family reference manual (RM0016).
•
•
•
•
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the STM8
SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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STM8S103K3 STM8S103F3 STM8S103F2
Description
2
Description
The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory,
plus integrated true data EEPROM. The STM8S microcontroller family reference manual
(RM0016) refers to devices in this family as low-density. They provide the following benefits:
Reduced system cost
•
Integrated true data EEPROM for up to 300 k write/erase cycles
-
High system integration level with internal clock oscillators, watchdog and brown-out
reset.
-
Performance and robustness
•
16 MHz CPU clock frequency
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Robust I/O, independent watchdogs with separate clock source
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Clock security system
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Full documentation and a wide choice of development tools
•
Advanced core and peripherals made in a state-of-the art technology
•
Table 1: STM8S103xx access line features
Device
STM8S103K3
STM8S103F3
STM8S103F2
Pin count
32
20
20
Maximum number of GPIOs (I/Os) 28
16
16
7
16
16
7
Ext. interrupt pins
27
7
Timer CAPCOM channels
Timer complementary outputs
A/D converter channels
High sink I/Os
3
2
2
4
5
5
21
12
12
Low density Flash program
memory (bytes)
8K
8K
4K
Data EEPROM (bytes)
RAM (bytes)
640(1)
1K
640(1)
1K
640(1)
1K
Multipurpose timer (TIM1), SPI, I2C, UART window
WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit
timer (TIM4)
Peripheral set
(1) No read-while-write (RWW) capability
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Block diagram
STM8S103K3 STM8S103F3 STM8S103F2
3
Block diagram
Figure 1: Block diagram
Reset block
Reset
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock controller
Detector
Reset
POR
BOR
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
8 Kbytes
program
Flash
Single wire
debug interf.
Debug/SWIM
640 bytes
data EEPROM
400 Kbit/s
8 Mbit/s
2
1 Kbyte
RAM
I
C
Up to
4 CAPCOM
channels +3
SPI
complementary
outputs
16-bit advanced
control timer (TIM1)
LIN master
SPI emul.
UART1
16-bit general purpose
timer (TIM2)
Up to
3 CAPCOM
channels
8-bit basic timer
(TIM4)
Up to 5
channels
ADC1
1/2/4 kHz
beep
AWU timer
Beeper
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STM8S103K3 STM8S103F3 STM8S103F2
Product overview
4
Product overview
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture
•
3-stage pipeline
•
32-bit wide program memory bus - single cycle fetching for most instructions
•
X and Y 16-bit index registers - enabling indexed addressing modes with or without offset
and read-modify-write type data manipulations
•
8-bit accumulator
•
24-bit program counter - 16-Mbyte linear memory space
•
16-bit stack pointer - access to a 64 K-level stack
•
8-bit condition code register - 7 condition flags for the result of the last instruction
•
Addressing
20 addressing modes
•
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
•
Stack pointer relative addressing mode for local variables and parameter passing
•
Instruction set
80 instructions with 2-byte average instruction size
•
Standard data movement and logic/arithmetic functions
•
8-bit by 8-bit multiplication
•
16-bit by 8-bit and 16-bit by 16-bit division
•
Bit manipulation
•
Data transfer between stack and accumulator (push/pop) with direct stack access
•
Data transfer using the X and Y registers or direct memory-to-memory transfers
•
4.2
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
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Product overview
SWIM
STM8S103K3 STM8S103F3 STM8S103F2
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
R/W to RAM and peripheral registers in real-time
•
R/W access to all resources by stalling the CPU
•
Breakpoints on all program-memory instructions (software breakpoints)
•
Two advanced breakpoints, 23 predefined configurations
•
4.3
4.4
Interrupt controller
Nested interrupts with three software priority levels
•
32 interrupt vectors with hardware priority
•
Up to 27 external interrupts on 6 vectors including TLI
•
Trap and reset interrupts
•
Flash program and data EEPROM memory
8 Kbytes of Flash program single voltage Flash memory
•
640 bytes true data EEPROM
•
User option byte area
•
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: Up to 8 Kbytes minus UBC
•
User-specific boot code (UBC): Configurable up to 8 Kbytes
•
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
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Product overview
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2: Flash memory organization
Data memory area ( 640 bytes)
Data
EEPROM
memory
Option bytes
Programmable
area from 64
UBC area
bytes(1 page)
Remains write protected during IAP
up to 8 Kbytes
(in 1 page steps)
Low density
Flash program
memory
(8 Kbytes)
Program memory area
Write access possible for IAP
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
•
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•
•
Master clock sources: Four different clock sources can be used to drive the master
clock:
1-16 MHz high-speed external crystal (HSE)
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Product overview
STM8S103K3 STM8S103F3 STM8S103F2
Up to 16 MHz high-speed user-external clock (HSE user-ext)
-
-
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16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
•
•
Clock security system (CSS): This feature can be enabled by software. If an HSE clock
failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Bit
Peripheral Bit
clock
Peripheral Bit
clock
Peripheral Bit
clock
Peripheral
clock
PCKEN17 TIM1
PCKEN13 UART1
PCKEN27 Reserved PCKEN23 ADC
PCKEN16 Reserved PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU
PCKEN15 TIM2
PCKEN14 TIM4
PCKEN11 SPI
PCKEN10 I2C
PCKEN25 Reserved PCKEN21 Reserved
PCKEN24 Reserved PCKEN20 Reserved
4.6
Power management
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
•
•
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with regulator
on, except that the main voltage regulator is powered off, so the wake up time is slower.
•
•
Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
4.7
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
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STM8S103K3 STM8S103F3 STM8S103F2
Product overview
Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8
Auto wakeup counter
Used for auto wakeup from active halt mode
•
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
•
LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
•
4.9
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
16-bit up, down and up/down autoreload counter with 16-bit prescaler
•
Four independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse mode
output
•
Synchronization module to control the timer with external signals
•
DocID15441 Rev 6
15/113
Product overview
STM8S103K3 STM8S103F3 STM8S103F2
Break input to force the timer outputs into a defined state
•
•
•
•
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11
4.12
TIM2 - 16-bit general purpose timer
16-bit autoreload (AR) up-counter
•
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
•
3 individually configurable capture/compare channels
•
PWM mode
•
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
•
TIM4 - 8-bit basic timer
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
•
Clock source: CPU clock
•
Interrupt source: 1 x overflow/update
•
Table 3: TIM timer features
Timer
synchronization/
chaining
Counter
size (bits)
Counting CAPCOM Complem. Ext.
Timer
Prescaler
mode
channels outputs
trigger
Any integer
from 1 to
65536
TIM1
16
16
8
Up/down
4
3
0
3
0
0
Yes
Any power of
2 from 1 to
32768
No
TIM2
TIM4
Up
Up
No
No
Any power of
2 from 1 to
128
4.13
Analog-to-digital converter (ADC1)
The STM8S103xx family products contain a 10-bit successive approximation A/D converter
(ADC1) with up to 5 external multiplexed input channels and the following main features:
Input voltage range: 0 to VDD
•
Conversion time: 14 clock cycles
•
Single and continuous and buffered continuous conversion modes
•
Buffer size (n x 10 bits) where n = number of input channels
•
Scan mode for single and continuous conversion of a sequence of channels
•
16/113
DocID15441 Rev 6
STM8S103K3 STM8S103F3 STM8S103F2
Product overview
Analog watchdog capability with programmable upper and lower thresholds
•
•
•
•
•
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
4.14
Communication interfaces
The following communication interfaces are implemented:
UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
mode, single wire mode, LIN2.1 master capability
•
SPI : Full and half-duplex, 8 Mbit/s
I²C: Up to 400 Kbit/s
•
•
4.14.1
UART1
Main features
One Mbit/s full duplex SCI
•
SPI emulation
•
High precision baud rate generator
•
Smartcard emulation
•
IrDA SIR encoder decoder
•
LIN master mode
•
Single wire half duplex mode
•
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
•
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
•
Separate enable bits for transmitter and receiver
•
Two receiver wakeup modes:
•
Address bit (MSB)
-
Idle line (interrupt)
-
Transmission error detection with interrupt generation
•
Parity control
•
Synchronous communication
Full duplex synchronous transfers
•
SPI master operation
•
8-bit data communication
•
Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
•
DocID15441 Rev 6
17/113
Product overview
LIN master mode
STM8S103K3 STM8S103F3 STM8S103F2
Emission: Generates 13-bit synch break frame
•
Reception: Detects 11-bit break frame
•
4.14.2
SPI
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
•
•
•
•
•
•
•
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
4.14.3
I²C
I²C master features:
•
•
Clock generation
-
Start and stop generation
-
I²C slave features:
Programmable I2C address detection
-
Stop bit detection
-
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
•
•
Standard speed (up to 100 kHz)
-
Fast speed (up to 400 kHz)
-
18/113
DocID15441 Rev 6
STM8S103K3 STM8S103F3 STM8S103F2
Pinout and pin description
5
Pinout and pin description
Table 4: Legend/abbreviations for pinout tables
Type
I= Input, O = Output, S = Power supply
CM = CMOS
Level
Input
Output
HS = High sink
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control
configuration
Input
float = floating, wpu = weak pull-up
Output
T = True open drain, OD = Open drain, PP =
Push pull
Reset state
Bold X (pin state after internal reset release).
Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
5.1
STM8S103Kx UFQFPN32/LQFP32 pinout and pin description
Figure 3: STM8S103Kx UFQFPN32/LQFP32 pinout
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
NRST
OSCIN/PA1
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
OSCOUT/PA2
PC5 (HS)/SPI_SCK
V
PC4 (HS)/TIM1_CH4/CLK_CCO
PC3 (HS)/TIM1_CH3
SS
VCAP
V
PC2 (HS)/TIM1_CH2
DD
[SPI_NSS] TIM2_CH3/(HS)PA3
PF4
PC1 (HS)/TIM1_CH1/UART1_CK
PE5 (HS)/SPI_NSS
9
10 11 12 13 14 15 16
DocID15441 Rev 6
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Pinout and pin description
STM8S103K3 STM8S103F3 STM8S103F2
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
Table 5: UFQFPN32/LQFP32 pin description
Input
Output
Alternate
function
after remap
[option bit]
Main
function
(after reset) function
Default
alternate
Pin
Pin
no.
Type
Ext.
High
name
floating wpu
Speed OD PP
(1)
interrupt sink
1
2
NRST
I/O
I/O
X
Reset
(2)
PA1/ OSCI
X
X
X
X
X
X
O1
O1
X
X
X
X
Port A1
Resonator/
crystal in
3
PA2/ OSCOUT I/O
Port A2
Resonator/
crystal out
4
5
6
7
V
S
Digital ground
SS
VCAP
S
1.8 V regulator capacitor
Digital power supply
V
S
DD
PA3/
TIM2_CH3
[SPI_NSS]
I/O
X
X
X
HS
O3
X
X
Port A3
Timer 2
channel 3
SPI master/
slave select
[AFR1]
8
PF4
PB7
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
O1
O1
O1
O1
O1
O3
X
X
X
X
X
X
Port F4
Port B7
Port B6
Port B5
Port B4
Port B3
9
X
X
X
X
X
10
11
12
13
PB6
2
(3)
2
PB5/ I C_SDA I/O
T
I C data
2
(3)
2
PB4/ I C_SCL I/O
T
I C clock
PB3/AIN3/
TIM1_ETR
I/O
X
X
HS
HS
X
X
X
X
Analog input 3/
Timer 1
external trigger
14
PB2/AIN2/
I/O
X
X
O3
Port B2
Analog input 2/
Timer 1 -
TIM1_CH3N
inverted
channel 3
20/113
DocID15441 Rev 6
STM8S103K3 STM8S103F3 STM8S103F2
Pinout and pin description
Input
Output
Alternate
Default
Main
function
Pin
Pin
function
Type
alternate
(after reset) function
no.
after remap
Ext.
High
name
floating wpu
Speed OD PP
(1)
[option bit]
interrupt sink
15
PB1/AIN1/
TIM1_CH2N
I/O
I/O
X
X
X
HS
O3
X
X
Port B1
Port B0
Analog input 1/
Timer 1 -
inverted
channel 2
16
PB0/AIN0/
TIM1_CH1N
X
X
X
HS
O3
X
X
Analog input 0/
Timer 1 -
inverted
channel 1
17
18
PE5/
I/O
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port E5
Port C1
SPI
master/slave
select
SPI_NSS
PC1/
Timer 1 -
TIM1_CH1/
UART1_CK
channel 1
UART1 clock
19
20
21
PC2/
TIM1_CH2
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS
HS
HS
O3
O3
O3
X
X
X
X
X
X
Port C2
Port C3
Port C4
Timer 1 -
channel 2
PC3/
TIM1_CH3
Timer 1 -
channel 3
PC4/
Timer 1 -
TIM1_CH4/
CLK_CCO
channel 4
/configurable
clock output
22
23
PC5/ SPI_SCK I/O
PC6/ PI_MOSI I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port C5
Port C6
SPI clock
SPI master
out/slave in
24
25
PC7/ PI_MISO I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port C7
Port D0
SPI master in/
slave out
PD0/
I/O
Timer 1 - break Configurable
TIM1_BKIN
[CLK_CCO]
input
clock output
[AFR5]
26
27
PD1/ SWIM
I/O
I/O
X
X
X
X
HS
HS
O4
O3
X
X
X
X
Port D1
Port D2
SWIM data
interface
(4)
PD2
[TIM2_CH3]
X
X
Timer 2 -
channel
3[AFR1]
DocID15441 Rev 6
21/113
Pinout and pin description
STM8S103K3 STM8S103F3 STM8S103F2
Input
Output
Alternate
function
after remap
[option bit]
Main
function
(after reset) function
Default
alternate
Pin
Pin
Type
no.
Ext.
High
name
floating wpu
Speed OD PP
(1)
interrupt sink
28
29
PD3/
TIM2_CH2/
ADC_ETR
I/O
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port D3
Port D4
Timer 2 -
channel 2/ADC
external trigger
PD4/BEEP/
TIM2_CH1
Timer 2 -
channel
1/BEEP output
30
31
32
PD5/
UART1_TX
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS
HS
HS
O3
O3
O3
X
X
X
X
X
X
Port D5
Port D6
Port D7
UART1 data
transmit
PD6/
UART1_RX
UART1 data
receive
PD7/ TLI
[TIM1_CH4]
Top level
interrupt
Timer 1 -
channel 4
[AFR6]
(1)
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total
driven current must respect the absolute maximum ratings (see Electrical characteristics).
(2)
When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull up and cannot be used for waking
up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt
is used in the application.
(3)
In the open-drain output column, "T" defines a true open-drain I/O (P-buffer and protection diode to V
are not implemented)
DD
(4)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
5.2
STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin
description
5.2.1
STM8S103Fx TSSOP20/SO20 pinout
Figure 4: STM8S103Fx TSSOP20/SO20 pinout
1
20
19
18
17
16
15
14
13
12
11
UART1_CK/TIM2_CH1/BEEP/(HS)PD4
UART1_TX/AIN5/(HS) PD5
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD2 (HS)/AIN3/[TIM2_CH3]
2
UART1_RX/AIN6/(HS) PD6
NRST
3
PD1(HS)/SWIM
4
PC7 (HS)/SPI_MISO [TIM1_CH2]
PC6 (HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
OSCIN/PA1
5
OSCOUT/PA2
6
7
V
SS
8
VCAP
2
V
9
10
DD
PB4 (T)/I C_SCL [ADC_ETR]
2
[SPI_NSS] TIM2_CH3/(HS) PA3
PB5 (T)/I C_SDA [TIM1_BKIN]
22/113
DocID15441 Rev 6
STM8S103K3 STM8S103F3 STM8S103F2
Pinout and pin description
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
5.2.2
STM8S103Fx UFQFPN20 pinout
Figure 5: STM8S103Fx UFQFPN20-pin pinout
20 19 18 17
16
15
14
13
1
2
3
4
5
NRST
PD1(HS)/SWIM
OSCIN/PA1
PC7(HS)/SPI_MISO[TIM1_CH2]
PC6(HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
OSCOUT/PA2
V
SS
12
11
VCAP
6
7
8
9
10
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
DocID15441 Rev 6
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Pinout and pin description
STM8S103K3 STM8S103F3 STM8S103F2
5.2.3
STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description
Table 6: STM8S103Fx pin description
Pin no.
Input
Output
Main
function
(after
Default
alternate
function
Alternate function
after remap [option
bit]
Pin name
Type
Ext.
interr.
High sink
TSSOP/SO20 UFQFPN20
floating wpu
Speed OD
PP
(1)
reset)
1
18
PD4/ BEEP/
TIM2_ CH1/
UART1 _CK
I/O
X
X
X
HS
O3
X
X
Port D4
Timer 2 -
channel
1/BEEP output/
UART1 clock
2
3
19
20
PD5/ AIN5/
UART1 _TX
I/O
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port D5
Port D6
Analog input 5/
UART1 data
transmit
PD6/ AIN6/
UART1 _RX
Analog input 6/
UART1 data
receive
4
5
1
2
NRST
I/O
I/O
X
Reset
(2)
PA1/ OSCIN
X
X
X
X
X
O1
O1
X
X
X
X
Port A1
Resonator/
crystal in
6
3
PA2/ OSCOUT
I/O
X
Port A2
Resonator/
crystal out
7
4
5
6
7
V
S
Digital ground
SS
8
VCAP
S
1.8 V regulator capacitor
Digital power supply
9
V
S
DD
10
PA3/ TIM2_ CH3
[SPI_ NSS]
I/O
X
X
X
X
X
X
X
X
X
HS
O3
O1
O1
O3
X
X
Port A3
Port B5
Port B4
Port C3
Timer 2
channel 3
SPI master/ slave
select [AFR1]
2
2
11
12
13
8
PB5/ I C_ SDA
[TIM1_ BKIN]
I/O
I/O
I/O
T
I
I
C data
Timer 1 - break
input [AFR4]
(3)
2
2
9
PB4/ I C_ SCL
T
C clock
ADC external
trigger [AFR4]
(3)
10
PC3/ TIM1_CH3
[TLI] [TIM1_
CH1N]
X
X
HS
HS
X
X
X
Timer 1 -
channel 3
Top level interrupt
[AFR3] Timer 1 -
inverted channel 1
[AFR7]
14
11
PC4/ CLK_CCO/
TIM1_
I/O
X
X
O3
X
Port C4
Configurable
clock
Timer 1 - inverted
channel 2 [AFR7]
CH4/AIN2/[TIM1_
CH2N]
output/Timer 1
- channel
4/Analog input
2
15
16
17
18
19
20
12
13
14
15
16
17
PC5/ SPI_SCK
[TIM2_ CH1]
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS
HS
HS
HS
HS
HS
O3
O3
O3
O4
O3
O3
X
X
X
X
X
X
X
X
X
X
X
X
Port C5
Port C6
Port C7
Port D1
Port D2
Port D3
SPI clock
Timer 2 - channel 1
[AFR0]
PC6/ SPI_MOSI
[TIM1_ CH1]
SPI master
out/slave in
Timer 1 - channel 1
[AFR0]
PC7/ SPI_MISO
[TIM1_ CH2]
SPI master in/
slave out
Timer 1 - channel 2
[AFR0]
PD1/ SWIM
SWIM data
interface
PD2/AIN3/[TIM2_
CH3]
Analog input 3
Timer 2 - channel 3
[AFR1]
PD3/ AIN4/ TIM2_ I/O
CH2/ ADC_ ETR
Analog input 4/
Timer 2 -
channel 2/ADC
external trigger
24/113
DocID15441 Rev 6
STM8S103K3 STM8S103F3 STM8S103F2
Pinout and pin description
(1)
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute
maximum ratings.
(2)
When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull up and cannot be used for waking up the device. In this mode, the output
state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application.
(3)
In the open-drain output column, "T" defines a true open-drain I/O (P-buffer and protection diode to V
are not implemented).
DD
5.3
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).
DocID15441 Rev 6
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Memory and register map
STM8S103K3 STM8S103F3 STM8S103F2
6
Memory and register map
6.1
Memory map
Figure 6: Memory map
0x00 0000
RAM
(1 Kbyte)
513 bytes stack
Reserved
0x00 03FF
0x00 0800
0x00 3FFF
0x00 4000
640 bytes data EEPROM
Reserved
0x00 427F
0x00 4280
0x00 47FF
0x00 4800
0x00 480A
0x00 480B
0x00 4864
Option bytes
Reserved
0x00 4865
0x00 4870
0x00 4871
0x00 4FFF
0x00 5000
Unique ID
Reserved
GPIO and periph. reg.
0x00 57FF
0x00 5800
Reserved
0x00 7EFF
0x00 7F00
CPU/SWIM/debug/ITC
registers
0x00 7FFF
0x00 8000
32 interrupt vectors
0x00 807F
0x00 8080
Flash program memory
(8 Kbytes)
0x00 9FFF
0x00 A000
Reserved
0x02 7FFF
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DocID15441 Rev 6
STM8S103K3 STM8S103F3 STM8S103F2
Memory and register map
6.2
Register map
6.2.1
I/O port hardware register map
Table 7: I/O port hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
0x00 5014
0x00 5015
0x00 5016
0x00 5017
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x02
0x00
0x00
0xXX
0x00
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C
Port C control register 2
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
Port D
Port D control register 2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
Port E
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Memory and register map
STM8S103K3 STM8S103F3 STM8S103F2
Reset
Address
Block
Port E
Register label
Register name
status
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
Port E control register 2
0x00
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00
0xXX
0x00
0x00
0x00
Port F
Port F control register 2
6.2.2
General hardware register map
Table 8: General hardware register map
Address
Block
Register label
Register name
Reset
status
0x00 501E to
0x00 5059
Reserved area (60 bytes)
FLASH_CR1
FLASH_CR2
FLASH_NCR2
Flash control register 1
Flash control register 2
0x00
0x00
0x00 505A
0x00 505B
0x00 505C
Flash
Flash complementary control register 0xFF
2
0x00 505D
0x00 505E
FLASH _FPR
Flash protection register
0x00
0xFF
FLASH _NFPR
Flash complementary protection
register
0x00 505F
FLASH _IAPSR Flash in-application programming
status register
0x00
0x00 5060 to
0x00 5061
Reserved area (2 bytes)
0x00 5062
Flash
FLASH _PUKR
Flash program memory unprotection 0x00
register
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STM8S103K3 STM8S103F3 STM8S103F2
Memory and register map
Address
Block
Register label
Register name
Reset
status
0x00 5063
0x00 5064
Reserved area (1 byte)
Flash
FLASH _DUKR
Data EEPROM unprotection register 0x00
0x00 5065 to
0x00 509F
Reserved area (59 bytes)
0x00 50A0
0x00 50A1
ITC
EXTI_CR1
EXTI_CR2
External interrupt control register 1 0x00
External interrupt control register 2 0x00
0x00 50A2 to
0x00 50B2
Reserved area (17 bytes)
0x00 50B3
RST
RST_SR
Reset status register
0xXX(1)
0x00 50B4 to
0x00 50BF
Reserved area (12 bytes)
0x00 50C0
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
CLK
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
0x01
0x00
Reserved area (1 byte)
CLK CLK_CMSR
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
0xE1
0xE1
0xXX
0x18
0xFF
0x00
0x00
CLK_SWR
CLK_SWCR
CLK_CKDIVR
CLK_PCKENR1 Peripheral clock gating register 1
CLK_CSSR
CLK_CCOR
Clock security system register
Configurable clock control register
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Memory and register map
STM8S103K3 STM8S103F3 STM8S103F2
Address
Block
Register label
Register name
Reset
status
0x00 50CA
0x00 50CB
0x00 50CC
CLK_PCKENR2 Peripheral clock gating register 2
0xFF
0x00
0x00
CLK_CANCCR
CAN clock control register
CLK_HSITRIMR HSI clock calibration trimming
register
0x00 50CD
CLK_SWIMCCR SWIM clock control register
0bXXXX
XXX0
0x00 50CE to
0x00 50D0
Reserved area (3 bytes)
0x00 50D1
0x00 50D2
WWDG
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
0x00 50D3 to 00 Reserved area (13 bytes)
50DF
0x00 50E0
0x00 50E1
0x00 50E2
IWDG
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
0xXX(2)
0x00
IWDG prescaler register
IWDG reload register
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
AWU
AWU_CSR1
AWU_APR
AWU control/status register 1
0x00
AWU asynchronous prescaler buffer 0x3F
register
0x00 50F2
0x00 50F3
AWU_TBR
BEEP_CSR
AWU timebase selection register
BEEP control/status register
0x00
0x1F
BEEP
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STM8S103K3 STM8S103F3 STM8S103F2
Memory and register map
Address
Block
Register label
Register name
Reset
status
0x00 50F4 to
0x00 50FF
Reserved area (12 bytes)
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
SPI
SPI_CR1
SPI control register 1
SPI control register 2
0x00
0x00
SPI_CR2
SPI_ICR
SPI interrupt control register
SPI status register
0x00
0x02
0x00
0x07
0xFF
0xFF
SPI_SR
SPI_DR
SPI data register
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
0x00 5208 to
0x00 520F
Reserved area (8 bytes)
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
I2C
I2C_CR1
I2C_CR2
I2C_FREQR
I2C_OARL
I2C_OARH
Reserved
I2C_DR
I2C control register 1
0x00
0x00
0x00
0x00
0x00
I2C control register 2
I2C frequency register
I2C Own address register low
I2C Own address register high
I2C data register
0x00
0x00
I2C_SR1
I2C status register 1
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Memory and register map
STM8S103K3 STM8S103F3 STM8S103F2
Address
Block
Register label
Register name
Reset
status
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E
I2C_SR2
I2C status register 2
0x00
0x0X
0x00
0x00
0x00
0x02
0x00
I2C_SR3
I2C status register 3
I2C_ITR
I2C interrupt control register
I2C Clock control register low
I2C Clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
I2C_PECR
I2C packet error checking register
0x00 521F to
0x00 522F
Reserved area (17 bytes)
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
UART1
UART1_SR
UART1 status register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
UART1_DR
UART1 data register
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
UART1 baud rate register 1
UART1 baud rate register 2
UART1 control register 1
UART1 control register 2
UART1 control register 3
UART1 control register 4
UART1 control register 5
UART1 guard time register
UART1 prescaler register
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STM8S103K3 STM8S103F3 STM8S103F2
Memory and register map
Address
Block
Register label
Register name
Reset
status
0x00 523B to
0x00 523F
Reserved area (21 bytes)
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
TIM1
TIM1_CR1
TIM1_CR2
TIM1_SMCR
TIM1_ETR
TIM1_IER
TIM1 control register 1
TIM1 control register 2
0x00
0x00
TIM1 slave mode control register
TIM1 external trigger register
TIM1 interrupt enable register
TIM1 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
TIM1_SR1
TIM1_SR2
TIM1_EGR
TIM1_CCMR1
TIM1 status register 2
TIM1 event generation register
TIM1 capture/compare mode register 0x00
1
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1 capture/compare mode register 0x00
2
TIM1 capture/compare mode register 0x00
3
TIM1 capture/compare mode register 0x00
4
TIM1 capture/compare enable
register 1
0x00
0x00
0x00
TIM1 capture/compare enable
register 2
TIM1 counter high
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Memory and register map
STM8S103K3 STM8S103F3 STM8S103F2
Address
Block
Register label
Register name
Reset
status
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter low
0x00
0x00
0x00
0xFF
0xFF
0x00
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1 capture/compare register 1 high 0x00
TIM1 capture/compare register 1 low 0x00
TIM1 capture/compare register 2 high 0x00
TIM1 capture/compare register 2 low 0x00
TIM1 capture/compare register 3 high 0x00
TIM1 capture/compare register 3 low 0x00
TIM1 capture/compare register 4 high 0x00
TIM1 capture/compare register 4 low 0x00
TIM1 break register
0x00
0x00
0x00
TIM1_DTR
TIM1 dead-time register
TIM1 output idle state register
TIM1_OISR
0x00 5270 to
0x00 52FF
Reserved area (147 bytes)
0x00 5300
TIM2
TIM2_CR1
TIM2 control register 1
0x00
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STM8S103K3 STM8S103F3 STM8S103F2
Memory and register map
Address
Block
Register label
Register name
Reset
status
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
Reserved
Reserved
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2_EGR
TIM2_CCMR1
TIM2 Interrupt enable register
TIM2 status register 1
0x00
0x00
0x00
0x00
TIM2 status register 2
TIM2 event generation register
TIM2 capture/compare mode register 0x00
1
0x00 5308
0x00 5309
0x00 530A
0x00 530B
TIM2_CCMR2
TIM2_CCMR3
TIM2_CCER1
TIM2_CCER2
TIM2 capture/compare mode register 0x00
2
TIM2 capture/compare mode register 0x00
3
TIM2 capture/compare enable
register 1
0x00
0x00
TIM2 capture/compare enable
register 2
0x00 530C
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5311
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2 counter high
0x00
0x00
0x00
0xFF
0xFF
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high 0x00
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Memory and register map
STM8S103K3 STM8S103F3 STM8S103F2
Address
Block
Register label
Register name
Reset
status
0x00 5312
0x00 5313
0x00 5314
0x00 5315
0x00 5316
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
TIM2 capture/compare register 1 low 0x00
TIM2 capture/compare reg. 2 high
0x00
TIM2 capture/compare register 2 low 0x00
TIM2 capture/compare register 3 high 0x00
TIM2 capture/compare register 3 low 0x00
0x00 5317 to
0x00 533F
Reserved area (43 bytes)
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347
0x00 5348
TIM4
TIM4_CR1
Reserved
TIM4 control register 1
0x00
Reserved
TIM4_IER
TIM4_SR
TIM4 interrupt enable register
TIM4 status register
0x00
0x00
0x00
0x00
0x00
0xFF
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register
0x00 5349 to
0x00 53DF
Reserved area (153 bytes)
0x00 53E0 to
0x00 53F3
ADC1
ADC _DBxR
ADC data buffer registers
0x00
0x00 53F4 to
0x00 53FF
Reserved area (12 bytes)
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STM8S103K3 STM8S103F3 STM8S103F2
Memory and register map
Address
Block
Register label
Register name
Reset
status
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
ADC1
ADC _CSR
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRH
ADC_DRL
ADC_TDRH
ADC control/status register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
ADC data register high
0x00
0x00
0x00
0x00
0xXX
0xXX
ADC data register low
ADC Schmitt trigger disable register 0x00
high
0x00 5407
ADC_TDRL
ADC Schmitt trigger disable register 0x00
low
0x00 5408
0x00 5409
0x00 540A
0x00 540B
0x00 540C
ADC_HTRH
ADC_HTRL
ADC_LTRH
ADC_LTRL
ADC_AWSRH
ADC high threshold register high
ADC high threshold register low
ADC low threshold register high
ADC low threshold register low
0x03
0xFF
0x00
0x00
ADC analog watchdog status register 0x00
high
0x00 540D
0x00 540E
0x00 540F
ADC_AWSRL
ADC _AWCRH
ADC_AWCRL
ADC analog watchdog status register 0x00
low
ADC analog watchdog control
register high
0x00
0x00
ADC analog watchdog control
register low
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Memory and register map
STM8S103K3 STM8S103F3 STM8S103F2
Address
Block
Register label
Register name
Reset
status
0x00 5410 to
0x00 57FF
Reserved area (1008 bytes)
(1)Depends on the previous reset source.
(2)Write only register.
6.2.3
CPU/SWIM/debug module/interrupt controller registers
Table 9: CPU/SWIM/debug module/interrupt controller registers
Address
Block
Register label
Register name
Reset status
0x00 7F00
A
Accumulator
0x00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
PCE
PCH
PCL
XH
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
CPU(1)
XL
YH
YL
SPH
SPL
CCR
Stack pointer low
Condition code register
0x00 7F0B to
0x00 7F5F
Reserved area (85 bytes)
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
CPU
ITC
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
Global configuration register
0x00
Interrupt software priority register 1 0xFF
Interrupt software priority register 2 0xFF
Interrupt software priority register 3 0xFF
Interrupt software priority register 4 0xFF
Interrupt software priority register 5 0xFF
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STM8S103K3 STM8S103F3 STM8S103F2
Memory and register map
Reset status
Address
Block
Register label
Register name
0x00 7F75
ITC_SPR6
Interrupt software priority register 6 0xFF
Interrupt software priority register 7 0xFF
Interrupt software priority register 8 0xFF
0x00 7F76
0x00 7F77
ITC_SPR7
ITC_SPR8
0x00 7F78 to
0x00 7F79
Reserved area (2 bytes)
0x00 7F80
SWIM
SWIM_CSR
DM_BK1RE
SWIM control status register
Reserved area (15 bytes)
0x00
0xFF
0x00 7F81 to
0x00 7F8F
0x00 7F90
DM breakpoint 1 register extended
byte
0x00 7F91
0x00 7F92
0x00 7F93
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
0xFF
0xFF
0xFF
DM breakpoint 2 register extended
byte
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
0xFF
0xFF
DM
DM debug module control register 1 0x00
DM debug module control register 2 0x00
DM_CR2
DM_CSR1
DM debug module control/status
register 1
0x10
0x00
0xFF
0x00 7F99
0x00 7F9A
DM_CSR2
DM debug module control/status
register 2
DM_ENFCTR
DM enable function register
Reserved area (5 bytes)
0x00 7F9B to
0x00 7F9F
(1) Accessible by debug module only
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Interrupt vector mapping
STM8S103K3 STM8S103F3 STM8S103F2
7
Interrupt vector mapping
Table 10: Interrupt mapping
IRQ Source
no. block
Description
Wakeup from Wakeup from
Vector address
halt mode
active-halt mode
RESET Reset
Yes
Yes
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
TRAP
TLI
Software interrupt
-
-
0
External top level interrupt
Auto wake up from halt
Clock controller
-
-
1
AWU
CLK
-
Yes
2
-
-
3
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
Reserved
Yes(1)
Yes
Yes
Yes
Yes
-
Yes(1)
Yes
Yes
Yes
Yes
-
4
5
6
7
8
9
Reserved
-
-
10
11
SPI
End of transfer
Yes
-
Yes
-
TIM1 update/ overflow/ underflow/
trigger/ break
TIM1
12
13
14
15
16
17
18
19
20
21
22
TIM1
TIM2
TIM2
TIM1 capture/ compare
TIM2 update/ overflow
TIM2 capture/ compare
Reserved
-
-
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8060
-
-
-
-
-
-
Reserved
-
-
UART1 Tx complete
-
-
UART1 Receive register DATA FULL
-
-
I2C
I2C interrupt
Reserved
Reserved
Yes
Yes
-
-
-
-
-
-
ADC1 end of conversion/ analog
watchdog interrupt
ADC1
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Interrupt vector mapping
IRQ Source
no. block
Description
Wakeup from Wakeup from
Vector address
halt mode
active-halt mode
23
24
TIM4
Flash
TIM4 update/ overflow
EOP/WR_PG_DIS
-
-
0x00 8064
0x00 8068
-
-
0x00 806C to
0x00 807C
Reserved
(1) Except PA1
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Option bytes
STM8S103K3 STM8S103F3 STM8S103F2
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 11: Option bytes
Addr.
Option
name
Option Option bits
byte no.
Factory
default
setting
7
6
5
4
3
2
1
0
0x4800 Read-out
protection
OPT0
ROP [7:0]
00h
(ROP)
0x4801 User boot
code(UBC)
0x4802
OPT1
UBC [7:0]
00h
FFh
00h
NOPT1 NUBC [7:0]
OPT2 AFR7 AFR6
NOPT2 NAFR7
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
0x4803 Alternate
function
0x4804
NAFR6 NAFR5 NAFR4
NAFR3
NAFR2 NAFR1
NAFR0 FFh
remapping
(AFR)
0x4805h Miscell.
option
OPT3
Reserved
HSI
TRIM
LSI_ EN
IWDG
_HW
WWDG WWDG 00h
_HW _HALT
0x4806
NOPT3 Reserved
NHSI
TRIM
NLSI_
EN
NIWDG NWWDG NWW
_HW _HW G_HALT
FFh
0x4807 Clock
option
OPT4
Reserved
EXT CLK CKAWU PRS C1 PRS C0 00h
SEL
0x4808
NOPT4 Reserved
NEXT
CLK
NCKA
WUSEL
NPRSC1 NPR
SC0
FFh
0x4809 HSE clock OPT5
startup
HSECNT [7:0]
00h
FFh
0x480A
NOPT5 NHSECNT [7:0]
Table 12: Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
Option byte no.
OPT0
0xAA: Enable readout protection (write access via SWIM protocol)
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Option bytes
Option byte no.
Description
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT1
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 defined as UBC, memory write-protected
0x02: Pages 0 to 1 defined as UBC, memory write-protected.
Page 0 and 1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Pages 0 to 127 defined as UBC, memory
write-protected
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
OPT2
OPT3
AFR[7:0]
Refer to following section for alternate function remapping decriptions
of bits [7:2] and [1:0] respectively.
HSITRIM:High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN:Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
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Option bytes
STM8S103K3 STM8S103F3 STM8S103F2
Option byte no.
Description
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
OPT4
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL:Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
OPT5
HSECNT[7:0]:HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
8.1
Alternate function remapping bits
Table 13: STM8S103K alternate function remapping bits for 32-pin devices
Option byte no.
Description(1)
OPT2
AFR7 Alternate function remapping option 7
Reserved.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate function(2)
1: Port D7 alternate function = TIM1_CH4.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate function(2)
.
.
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Description(1)
Option bytes
Option byte no.
1: Port D0 alternate function = CLK_CCO.
AFR[4:2] Alternate function remapping options 4:2
Reserved.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: Default alternate functions(2)
.
1: Port A3 alternate function = SPI_NSS; port D2 alternate function
= TIM2_CH3.
AFR0 Alternate function remapping option 0
Reserved.
(1) Do not use more than one remapping option in the same port. It is forbidden to enable
both AFR1 and AFR0.
(2) Refer to pinout description.
Table 14: STM8S103F alternate function remapping bits for 20-pin devices
Option byte no.
Description
OPT2
AFR7 Alternate function remapping option 7
0: AFR7 remapping option inactive: Default alternate
functions(1)
.
1: Port C3 alternate function = TIM1_CH1N; port C4
alternate function = TIM1_CH2N.
AFR6 Alternate function remapping option 6
Reserved.
AFR5 Alternate function remapping option 5
Reserved.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate
functions(1)
.
1: Port B4 alternate function = ADC_ETR; port B5
alternate function = TIM1_BKIN.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate
function(1)
.
1: Port C3 alternate function = TLI.
AFR2 Alternate function remapping option 2
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Option bytes
STM8S103K3 STM8S103F3 STM8S103F2
Option byte no.
Description
Reserved
AFR1 Alternate function remapping option 1(2)
0: AFR1 remapping option inactive: Default alternate
functions(1)
.
1: Port A3 alternate function = SPI_NSS; port D2
alternate function = TIM2_CH3.
AFR0 Alternate function remapping option 0(2)
0: AFR0 remapping option inactive: Default alternate
functions(1)
.
1: Port C5 alternate function = TIM2_CH1; port C6
alternate function = TIM1_CH1; port C7 alternate
function = TIM1_CH2.
(1) Refer to pinout description.
(2) Do not use more than one remapping option in the same port. It is forbidden to enable
both AFR1 and AFR0.
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Unique ID
9
Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single bytes and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:
For use as serial numbers
•
For use as security keys to increase the code security in the program memory while using
and combining this unique ID with software cryptograhic primitives and protocols before
programming the internal memory.
•
To activate secure boot processes
•
Table 15: Unique ID registers (96 bits)
Address Content
description
Unique ID bits
7
6
5
4
3
2
1
0
0x4865
0x4866
0x4867
0x4868
U_ID[7:0]
X co-ordinate
on the wafer
U_ID[15:8]
U_ID[23:16]
U_ID[31:24]
U_ID[39:32]
U_ID[47:40]
U_ID[55:48]
U_ID[63:56]
U_ID[71:64]
U_ID[79:72]
U_ID[87:80]
U_ID[95:88]
Y co-ordinate
on the wafer
0x4869 Wafer number
0x486A
0x486B
0x486C
Lot number
0x486D
0x486E
0x486F
0x4870
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Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS
.
10.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on characterization,
the minimum and maximum values refer to sample tests and represent the mean value plus
or minus three times the standard deviation (mean ± 3 Σ).
10.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
10.1.3
10.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not
tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in the following figure.
Figure 7: Pin loading conditions
STM8 PIN
50 pF
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Electrical characteristics
10.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in the following figure.
Figure 8: Pin input voltage
STM8 PIN
V
IN
10.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 16: Voltage characteristics
Symbol
Ratings
Min
Max
Unit
VDDx - VSS
Supply voltage(1)
-0.3
6.5
VIN
Input voltage on true open drain pins(2)
Input voltage on any other pin(2)
VSS - 0.3
VSS - 0.3
6.5
V
VDD + 0.3
50
|VDDx - VDD
|
Variations between different power pins
mV
|VSSx - VSS
|
Variations between all the different ground
pins
50
VESD
See "Absolute
maximum ratings
(electrical sensitivity)"
Electrostatic discharge voltage
(1) All power (VDD) and ground (VSS) pins must always be connected to the external power supply
(2)
I
must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
INJ(PIN)
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
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Electrical characteristics
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Table 17: Current characteristics
Symbol
Ratings
Unit
Max(1)
IVDD
Total current into VDD power lines (source)(2)
Total current out of VSS ground lines (sink)(2)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on NRST pin
100
80
IVSS
IIO
20
- 20
± 4
± 4
± 4
± 20
mA
(3) (4)
IINJ(PIN)
Injected current on OSCIN pin
Injected current on any other pin(5)
(3)
ΣI INJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
(1) Data based on characterization results, not tested in production.
(2) All power (VDD) and ground (VSS) pins must always be connected to the external supply.
(3)
I
must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
INJ(PIN)
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
(4) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on
another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins
which may potentially inject negative current. Any positive injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.
(5) When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum
of the positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 18: Thermal characteristics
Symbol Ratings
TSTG Storage temperature range
TJ Maximum junction temperature
Value
Unit
-65 to +150
°C
150
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Electrical characteristics
10.3
Operating conditions
Table 19: General operating conditions
Symbol
Parameter
Conditions
Min
Max Unit
fCPU
Internal CPU clock frequency
0
16
MHz
V
VDD
Standard operating voltage
2.95
5.5
VCAP
CEXT: capacitance of
external capacitor(1)
470 3300 nF
ESR of external
capacitor(1)
at 1 MHz
-
-
0.3
15
Ω
ESL of external
capacitor(1)
nH
(2)
PD
TSSOP20
-
-
-
-
-
-
-
-
-
-
238
220
220
330
526
59
SO20W
Power dissipation at TA = 85 °C
for suffix 6
UFQFPN20
LQFP32
UFQFPN32
TSSOP20
mW
SO20W
55
Power dissipation at TA = 125 °C
for suffix 3
UFQFPN20
LQFP32
55
83
UFQFPN32
Maximum power dissipation
132
TA
TA
TJ
Ambient temperature for 6 suffix
version
-40
85
Ambient temperature for 3 suffix
version
Maximum power dissipation
°C
-40
-40
125
105
6 suffix version
3 suffix version
Junction temperature range
-40 130(3)
(1) This parameter range must be respected for the full application range, and taking into account the
physical capacitor characteristics and tolerance.
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Electrical characteristics
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(2)To calculate PDmax(TA), use the formula PDmax =(TJmax- TA)/ΘJA (see Thermal characteristics ) with the
value for TJmax given in the previous table and the value for ΘJA given in Thermal characteristics.
(3)
Τ
is given by the test limit. Above this value the product behavior is not guaranteed.
Jmax
Figure 9: fCPUmax versus VDD
f
(MHz)
CPU
Functionality
16
12
8
not
guaranteed
in this area
Functionality guaranteed
@T -40 to 125 °C
A
4
0
4.0
Supply voltage
2.95
5.0
5.5
Table 20: Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD rise time rate
2
∞
tVDD
μs/V
VDD fall time rate(1)
2
∞
tTEMP
VIT+
VIT-
Reset release delay
VDD rising
1.7
2.85
2.8
ms
V
Power-on reset threshold
Brown-out reset threshold
2.6
2.5
2.7
2.65
70
VHYS(BOR) Brown-out reset hysteresis
mV
(1) Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.
10.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
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Electrical characteristics
Figure 10: External capacitor CEXT
ESL
C
ESR
R
Leak
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
10.3.2
Supply current characteristics
The current consumption is measured as described in Pin input voltage.
10.3.2.1 Total current consumption in run mode
The MCU is placed under the following conditions:
All I/O pins in input mode with a static value at VDD or VSS (no load)
•
All peripherals are disabled (clock stopped by peripheral clock gating registers) except if
explicitly mentioned.
•
Subject to general operating conditions for VDD and TA.
Table 21: Total current consumption with code execution in run mode at VDD = 5 V
Max(1)
Symbol
Parameter
Conditions
Typ
2.3
Unit
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz) 2
HSI RC osc. (16 MHz) 1.7
fCPU = fMASTER
16 MHz
=
2.35
2
fCPU = fMASTER/128 = HSE user ext. clock (16 MHz) 0.86
125 kHz
Supply current
in run mode,
code executed
from RAM
HSI RC osc. (16 MHz)
0.7
0.87
0.58
fCPU = fMASTER/128 =
15.625 kHz
IDD(RUN)
HSI RC osc. (16 MHz/8)
0.46
mA
fCPU = fMASTER
128 kHz
=
LSI RC osc. (128 kHz)
0.41
4.5
0.55
HSE crystal osc. (16 MHz)
Supply current
in run mode,
code executed
from Flash
fCPU = fMASTER
16 MHz
=
HSE user ext. clock (16 MHz) 4.3
HSI RC osc. (16 MHz) 3.7
4.75
4.5
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Max(1)
Symbol
Parameter
Conditions
Typ
Unit
fCPU = fMASTER
2 MHz
=
HSI RC osc. (16 MHz/8)(2)
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.84
1.05
fCPU = fMASTER/128 =
125 kHz
0.72
0.46
0.42
0.9
Supply current
in run mode,
code executed
from Flash
IDD(RUN)
mA
fCPU = fMASTER/128 =
15.625 kHz
0.58
0.57
fCPU = fMASTER
128 kHz
=
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Table 22: Total current consumption with code execution in run mode at VDD = 3.3 V
Symbol Parameter
Conditions
Typ
Unit
Max(1)
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
1.8
2
fCPU = fMASTER
16 MHz
=
2.3
2
1.5
0.81
0.7
fCPU = fMASTER
/
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
Supply current
in run mode,
code executed
from RAM
128 = 125 kHz
0.87
0.58
fCPU = fMASTER
/
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.46
0.41
128 = 15.625 kHz
IDD(RUN)
fCPU = fMASTER
128 kHz
=
=
=
mA
0.55
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
4
fCPU = fMASTER
16 MHz
3.9
3.7
4.7
4.5
Supply current
in run mode,
code executed
from Flash
fCPU = fMASTER
2 MHz
HSI RC osc. (16 MHz/8)(2)
HSI RC osc. (16 MHz)
0.84
0.72
1.05
0.9
fCPU = fMASTER
/
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Electrical characteristics
Symbol Parameter
Conditions
Typ
Unit
Max(1)
128 = 125 kHz
fCPU = fMASTER
/
0.46
0.42
0.58
0.57
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
128 = 15.625 kHz
fCPU = fMASTER
128 kHz
=
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
10.3.2.2 Total current consumption in wait mode
Table 23: Total current consumption in wait mode at VDD = 5 V
Symbol Parameter Conditions Typ
Unit
Max(1)
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
1.6
1.1
fCPU = fMASTER
16 MHz
=
1.3
0.89 1.1
fCPU = fMASTER/128 =
125 kHz
Supply
IDD(WFI) current in
wait mode
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)(2)
LSI RC osc. (128 kHz)
0.7
0.88
mA
fCPU = fMASTER/128 =
15.625 kHz
0.45 0.57
fCPU = fMASTER
128 kHz
=
0.4
0.54
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Table 24: Total current consumption in wait mode at VDD = 3.3 V
Symbol Parameter
Conditions
Typ
Unit
Max (1)
fCPU = fMASTER
16 MHz
=
HSE crystal osc.
(16 MHz)
Supply current
in wait mode
IDD(WFI)
1.1
mA
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Electrical characteristics
Symbol Parameter
STM8S103K3 STM8S103F3 STM8S103F2
Conditions
Typ
Unit
Max (1)
HSE user ext. clock
(16 MHz)
1.1
1.3
HSI RC osc.
(16 MHz)
0.89
0.7
1.1
fCPU = fMASTER/ 128 = HSI RC osc.
125 kHz (16 MHz)
0.88
0.57
0.54
fCPU = fMASTER/ 128 = HSI RC osc.
0.45
0.4
15.625 kHz
(16 MHz/8)(2)
fCPU = fMASTER
=
LSI RC osc.
(128 kHz)
128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
10.3.2.3 Total current consumption in active halt mode
Table 25: Total current consumption in active halt mode at VDD = 5 V
Conditions
Max Max
at 85 at 125
Main
Symbol Parameter
Typ
Unit
°C
°C
voltage
regulator
(MVR)(2)
Flash mode(3)
Clock source
(1)
(1)
Supply current
IDD(AH) in active halt
mode
HSE crystal osc.
(16 MHz)
On
On
On
On
Operating mode
Operating mode
Power-down mode
Power-down mode
1030
200
970
150
Supply current
IDD(AH) in active halt
mode
LSI RC osc.
(128 kHz)
260 300
μA
Supply current
IDD(AH) in active halt
mode
HSE crystal osc.
(16 MHz)
Supply current
IDD(AH) in active halt
mode
LSI RC osc.
(128 kHz)
200 230
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Electrical characteristics
Conditions
Main
voltage
regulator
(MVR)(2)
Max Max
at 85 at 125
Symbol Parameter
Typ
Unit
°C
°C
Flash mode(3)
Clock source
(1)
(1)
Supply current
IDD(AH) in active halt
mode
LSI RC osc.
(128 kHz)
Operating mode
66
10
85
20
110
40
Off
Supply current
IDD(AH) in active halt
mode
LSI RC osc.
(128 kHz)
Power-down mode
(1) Data based on characterization results, not tested in production
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
Table 26: Total current consumption in active halt mode at VDD = 3.3 V
Conditions
Max at Max at
Main
85 °C
125 °C
Symbol Parameter
Typ
Unit
voltage
regulator
(MVR)(2)
Flash mode(3) Clock source
(1)
(1)
Supply current
HSE crystal
IDD(AH) in active halt
mode
On
On
Operating mode osc. (16 MHz)
550
μA
LSI RC osc.
IDD(AH)
Operating mode
200
970
150
260
200
290
230
Supply current
(128 kHz)
in active halt
mode
HSE crystal
IDD(AH)
osc. (16 MHz)
Power-down
μA
mode
LSI RC osc.
(128 kHz)
IDD(AH)
Supply current
in active halt
IDD(AH)
Operating mode LSI RC osc.
66
10
80
18
105
35
mode
Off
(128 kHz)
Power-down
IDD(AH)
mode
(1) Data based on characterization results, not tested in production
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
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10.3.2.4 Total current consumption in halt mode
Table 27: Total current consumption in halt mode at VDD = 5 V
Max at Max at
85 °C(1) 125 °C(1)
Symbol
Parameter
Conditions
Typ
Unit
Supply current in
halt mode
Flash in operating mode, HSI
clock after wakeup
63
75
20
105
55
IDD(H)
μA
Flash in power-down mode, HSI
clock after wakeup
6.0
(1) Data based on characterization results, not tested in production
Table 28: Total current consumption in halt mode at VDD = 3.3 V
Max at Max at
85 °C(1) 125 °C(1)
Symbol Parameter
Conditions
Typ
Unit
Supply current in
halt mode
Flash in operating mode, HSI
clock after wakeup
60
75
17
100
30
IDD(H)
μA
Flash in power-down mode, HSI
clock after wakeup
4.5
(1) Data based on characterization results, not tested in production
10.3.2.5 Low power mode wakeup times
Table 29: Wakeup times
Max(1)
Symbol Parameter
Wakeup time from
Conditions
Typ
Unit
See
0 to 16 MHz
note(2)
wait mode to run
mode(3)
tWU(WFI)
tWU(AH)
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fCPU = fMASTER = 16 MHz
0.56
1(6)
Wakeup time active MVR voltage
HSI
Flash in operating
mode(5)
2(6)
halt mode to run
mode(3)
regulator
on(4)
(after
μs
wakeup)
Wakeup time active MVR voltage Flash in
HSI
3(6)
halt mode to run
mode(3)
regulator
on(4)
power-down
mode(5)
(after
wakeup)
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STM8S103K3 STM8S103F3 STM8S103F2
Electrical characteristics
Max(1)
Symbol Parameter
Conditions
Typ
Unit
Wakeup time active MVR voltage
HSI
Flash in operating
mode(5)
48(6)
halt mode to run
mode(3)
regulator
off(4)
(after
wakeup)
Wakeup time active MVR voltage Flash in
HSI
50(6)
halt mode to run
mode(3)
regulator
off(4)
power-down
mode(5)
(after
wakeup)
Wakeup time from
halt mode to run
mode(3)
Flash in operating mode(5)
52
54
tWU(H)
Flash in power-down mode(5)
(1) Data guaranteed by design, not tested in production.
(2)
t
= 2 x 1/fmaster + 6 x 1/fCPU.
WU(WFI)
(3) Measured from interrupt event to interrupt vector fetch.
(4) Configured by the REGAH bit in the CLK_ICKR register.
(5) Configured by the AHALT bit in the FLASH_CR1 register.
(6) Plus 1 LSI clock depending on synchronization.
10.3.2.6 Total current consumption and timing in forced reset state
Table 30: Total current consumption and timing in forced reset state
Symbol
Parameter
Conditions
Typ
Unit
Max(1)
IDD(R)
Supply current in reset
state(2)
VDD = 5 V
400
300
μA
μs
VDD = 3.3 V
tRESETBL
Reset pin release to
vector fetch
150
(1) Data guaranteed by design, not tested in production.
(2) Characterized with all I/Os tied to VSS
.
10.3.2.7 Current consumption of on-chip peripherals
Subject to general operating conditions for VDD and TA.
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HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V
Table 31: Peripheral current consumption
Symbol
Parameter
Typ.
Unit
IDD(TIM1)
210
130
50
TIM1 supply current(1)
IDD(TIM2)
IDD(TIM4)
IDD(UART1)
IDD(SPI)
TIM2 supply current(1)
TIM4 timer supply current(1)
UART1 supply current(2)
SPI supply current(2)
120
45
μA
2
IDD(I C)
65
I2C supply current(2)
IDD(ADC1)
1000
ADC1 supply current when converting(3)
(1) Data based on a differential IDD measurement between reset configuration and timer counter running
at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
(2) Data based on a differential IDD measurement between the on-chip peripheral when kept under reset
and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling.
Not tested in production.
(3) Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
10.3.2.8 Current consumption curves
The following figures show typical current consumption measured with code executing in
RAM.
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Electrical characteristics
Figure 11: Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz
Figure 12: Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V
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Figure 13: Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz
Figure 14: Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz
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Electrical characteristics
Figure 15: Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V
Figure 16: Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz
10.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 32: HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fHSE_ext
User external clock source
frequency
0
16
MHz
(1)
VHSEH
OSCIN input pin high level
voltage
0.7 x VDD
VDD + 0.3 V
V
(1)
VHSEL
ILEAK_HSE
OSCIN input pin low level
voltage
VSS
-1
0.3 x VDD
+1
OSCIN input leakage current VSS < VIN < VDD
μA
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(1) Data based on characterization results, not tested in production.
Figure 17: HSE external clocksource
V
V
HSEH
HSEL
f
HSE
External clock
source
OSCIN
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 33: HSE oscillator characteristics
Symbol
Parameter
Conditions
Min Typ Max
Unit
fHSE
External high speed
oscillator frequency
1
16
20
MHz
RF
Feedback resistor
220
kΩ
pF
C(1)
Recommended load
capacitance(2)
IDD(HSE)
HSE oscillator power
consumption
C = 20 pF,
6 (startup)
1.6 (stabilized)(3)
fOSC = 16 MHz
mA
C = 10 pF,
6 (startup)
fOSC =16 MHz
1.2 (stabilized)(3)
gm
Oscillator
5
mA/V
ms
transconductance
(4)
tSU(HSE)
Startup time
VDD is stabilized
1
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Electrical characteristics
(1) C is approximately equivalent to 2 x crystal Cload.
(2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small Rm value. Refer to crystal manufacturer for more details
(3) Data based on characterization results, not tested in production.
(4)
t
is the start-up time measured from the moment it is enabled (by software) to a stabilized 16
SU(HSE)
MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Figure 18: HSE oscillator circuit diagram
R
m
f
to core
HSE
C
O
R
g
L
m
F
C
L1
C
m
OSCIN
m
Resonator
Consumption
control
Resonator
OSCOUT
C
L2
STM8
HSE oscillator critical g m equation
gmcrit= (2 × Π × fHSE)2 × Rm(2Co + C)2
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1= CL2 = C: Grounded external capacitance
gm >> gmcrit
10.3.4
Internal clock sources and timing characteristics
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 34: HSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fHSI
Frequency
16
MHz
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STM8S103K3 STM8S103F3 STM8S103F2
Symbol
Parameter
Accuracy of HSI User-trimmed with
oscillator CLK_HSITRIMR register for
Conditions
Min
Typ
Max
Unit
ACCHSI
1.0(3)
given VDD and TA
conditions(1)
Accuracy of HSI VDD = 5 V, TA = 25°C(2)
-1.0
-2.0
1.0
2.0
%
oscillator (factory
VDD = 5 V, 25 °C ≤
calibrated)
TA ≤ 85 °C
2.95 ≤ VDD≤ 5.5 V,-40 °C
≤ TA ≤ 125 °C
-3.0(2)
3.0(2)
tsu(HSI)
HSI oscillator
wakeup time
including
1.0(3)
μs
calibration
IDD(HSI)
HSI oscillator
power
250(2)
170
μA
consumption
(1) Refer to application note.
(2) Data based on characterization results, not tested in production.
(3) Guaranteed by design, not tested in production.
Figure 19: Typical HSI accuracy at VDD = 5 V vs 5 temperatures
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Electrical characteristics
Figure 20: Typical HSI frequency variation vs VDD @ 4 temperatures
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 35: LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI
Frequency
110
128
150
kHz
tsu(LSI)
LSI oscillator wake-up time
7
μs
IDD(LSI)
LSI oscillator power consumption
5
μA
Figure 21: Typical LSI frequency variation vs VDD @ 4 temperatures
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Electrical characteristics
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10.3.5
Memory characteristics
RAM and hardware registers
Table 36: RAM and hardware registers
Symbol
Parameter
Data retention mode(1)
Conditions
Min
Unit
(2)
VRM
VIT-max
Halt mode (or reset)
V
(1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)
or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
(2) Refer to the Operating conditions section for the value of VIT-max
Flash program memory/data EEPROM memory
Table 37: Flash program memory/data EEPROM memory
Symbol Parameter
Conditions
Typ
Max
Unit
Min(1)
VDD Operating voltage
(all modes, execution/
write/erase)
fCPU ≤ 16 MHz
2.95
5.5
V
tprog
Standard programming time
(including erase) for
6
6.6
byte/word/block (1 byte/
4 bytes/64 bytes)
ms
Fast programming time for
1 block (64 bytes)
3
3
3.33
3.33
terase
Erase time for 1 block
(64 bytes)
NRW
Erase/write cycles(2)
(program memory)
TA = +85 °C
10 k
cycles
years
Erase/write cycles
(data memory)(2)
TA = +125 °C
300 k 1 M
tRET
Data retention (program
and data memory) after 10k
erase/write cycles at
TA = +55 °C
TRET = 55°C
20
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Symbol Parameter
Electrical characteristics
Conditions
Typ
Max
Unit
Min(1)
Data retention (data
memory) after 300k
erase/write cycles at
TA = +125 °C
TRET = 85°C
1
IDD
Supply current (Flash
programming or erasing
for 1 to 128 bytes)
2
mA
(1) Data based on characterization results, not tested in production.
(2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes
even when a write/erase operation addresses a single byte.
10.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All unused
pins must be kept at a fixed voltage: using the output mode of the I/O for example or an
external pull-up or pull-down resistor.
Table 38: I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
0.3 x
VDD
Unit
VIL
VDD = 5 V
Input low level voltage
-0.3 V
V
VIH
VDD
0.3
+
0.7 x
VDD
Input high level voltage
Vhys
Rpu
Hysteresis(1)
700
45
mV
kΩ
VDD = 5 V, VIN = VSS
30
60
Pull-up resistor
tR, tF
Fast I/Os
20 (2)
Rise and fall time
(10 % - 90 %)
Load = 50 pF
ns
Standard and high sink
I/Os
125 (2)
Load = 50 pF
±1 (2)
Ilkg
VSS ≤ VIN ≤VDD
μA
Digital input leakage current
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Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
±250 (2)
Ilkg ana
VSS ≤ VIN ≤ VDD
nA
Analog input leakage current
Ilkg(inj)
Injection current ±4 mA
±1 (2)
Leakage current in adjacent
I/O
μA
(1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not
tested in production.
(2)Data based on characterisation results, not tested in production.
Figure 22: Typical VIL and VIH vs VDD @ 4 temperatures
Figure 23: Typical pull-up resistance vs VDD @ 4 temperatures
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Electrical characteristics
Figure 24: Typical pull-up current vs VDD @ 4 temperatures
Table 39: Output driving current (standard ports)
Symbol Parameter
Conditions
IIO= 10 mA,
VDD = 5 V
Min
Max Unit
Output low level with 8 pins sunk
Output low level with 4 pins sunk
Output high level with 8 pins sourced
Output high level with 4 pins sourced
2.0
VOL
IIO = 4 mA,
VDD = 3.3 V
1.0(1)
V
IIO = 10 mA,
VDD = 5 V
2.8
VOH
IIO = 4 mA,
VDD = 3.3 V
2.1(1)
(1) Data based on characterization results, not tested in production
Table 40: Output driving current (true open drain ports)
Symbol Parameter
Conditions
Max
Unit
IIO = 10 mA, VDD = 5 V
VOL
VOL
VOL
1 .0
Output low level with 2 pins sunk
Output low level with 2 pins sunk
IIO = 10 mA, VDD = 3.3
V
1.5(1)
2.0(1)
V
IIO = 20 mA, VDD = 5 V
Output low level with 2 pins sunk
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(1) Data based on characterization results, not tested in production
Table 41: Output driving current (high sink ports)
Symbol Parameter
Conditions
IIO = 10 mA,
VDD = 5 V
Min
Max Unit
Output low level with 8 pins sunk
VOL
0.8
V
IIO = 10 mA,
VDD = 3.3 V
1.0(1)
1.5(1)
Output low level with 4 pins sunk
Output low level with 4 pins sunk
Output high level with 8 pins sourced
Output high level with 4 pins sourced
Output high level with 4 pins sourced
VOL
IIO = 20 mA,
VDD = 5 V
IIO = 10 mA,
VDD = 5 V
V
4.0
IIO = 10 mA,
VDD = 3.3 V
2.1(1)
3.3(1)
VOH
IIO = 20 mA,
VDD = 5 V
(1) Data based on characterization results, not tested in production
Figure 25: Typ. VOL @ VDD = 5 V (standard ports)
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Electrical characteristics
Figure 26: Typ. VOL @ VDD = 3.3 V (standard ports)
Figure 27: Typ. VOL @ VDD = 5 V (true open drain ports)
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Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2
Figure 28: Typ. VOL @ VDD = 3.3 V (true open drain ports)
Figure 29: Typ. VOL @ VDD = 5 V (high sink ports)
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Electrical characteristics
Figure 30: Typ. VOL @ VDD = 3.3 V (high sink ports)
Figure 31: Typ. VDD - VOH@ VDD = 5 V (standard ports)
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STM8S103K3 STM8S103F3 STM8S103F2
Figure 32: Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
Figure 33: Typ. VDD - VOH@ VDD = 5 V (high sink ports)
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Electrical characteristics
Figure 34: Typ. VDD - VOH@ VDD = 3.3 V (high sink ports)
10.3.7
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 42: NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input low
level voltage(1)
-0.3 V
0.3 x VDD
VIH(NRST)
VOL(NRST)
RPU(NRST)
tI FP(NRST)
tIN FP(NRST)
NRST input high
level voltage (1)
IOL=2 mA
0.7 x VDD
VDD + 0.3
V
NRST output low
level voltage (1)
0.5
60
75
NRST pull-up
resistor(2)
30
40
kΩ
ns
NRST input filtered
pulse(3)
NRST input not
filtered pulse(3)
500
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Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tOP(NRST)
NRST output
pulse (3)
μs
20
(1) Data based on characterization results, not tested in production.
(2) The RPU pull-up equivalent resistor is based on a resistive transistor
(3) Data guaranteed by design, not tested in production.
Figure 35: Typical NRST VIL and VIH vs VDD @ 4 temperatures
Figure 36: Typical NRST pull-up resistance vs VDD @ 4 temperatures
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Electrical characteristics
Figure 37: Typical NRST pull-up current vs VDD @ 4 temperatures
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below the VIL max. level specified
in the I/O port pin characteristics section. Otherwise the reset is not taken into account
internally.
Figure 38: Recommended reset pin protection
STM8
VDD
RPU
External
reset
Internal reset
NRST
Filter
circuit
0.1 μF
(optional)
10.3.8
SPI serial peripheral interface
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions.
tMASTER = 1/fMASTER
.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
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Electrical characteristics
Symbol
STM8S103K3 STM8S103F3 STM8S103F2
Table 43: SPI characteristics
Parameter
Min
Max
Unit
Conditions(1)
fSCK1/
tc(SCK)
SPI clock
frequency
Master mode
0
8
MHz
fSCK1/
tc(SCK)
fSCK1/ tc(SCK)
SPI clock frequency
0
7(2)
25
MHz
tr(SCK)
tf(SCK)
SPI clock rise and Capacitive load: C = 30 pF
fall time
(3)
tsu(NSS)
NSS setup time
Slave mode
4 x
tMASTER
(3)
th(NSS)
NSS hold time
Slave mode
70
(3)
tw(SCKH)
SCK high and low Master mode
time
tSCK
/
tSCK/
(3)
tw(SCKL)
2 - 15
2 +15
(3)
tsu(MI)
Data input setup Master mode
5
(3)
tsu(SI)
time
Slave mode
5
(3)
th(MI)
Data input hold
time
Master mode
Slave mode
Slave mode
7
(3)
th(SI)
10
(3) (4)
ns
ta(SO)
Data output
access time
3 x
tMASTER
(3) (5)
tdis(SO)
Data output
disable time
Slave mode
25
(3)
tv(SO)
Data output valid Slave mode
65(2)
30
time
(after enable edge)
(3)
tv(MO)
Data output valid Master mode
time
(after enable edge)
(3)
th(SO)
Data output hold Slave mode
27(2)
11(2)
time
(after enable edge)
(3)
th(MO)
Data output hold Master mode
time
(after enable edge)
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Electrical characteristics
(1) Parameters are given by selecting 10 MHz I/O output frequency.
(2) Data characterization in progress.
(3) Values based on design simulation and/or characterization results, and not tested in
production.
(4) Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
(5) Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
Figure 39: SPI timing diagram - slave mode and CPHA = 0
NSS input
t
t
t
h(NSS)
SU(NSS)
c(SCK)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
MSB O UT
BIT6 OUT
BIT1 IN
LSB OUT
OUT PUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134
Figure 40: SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
h(NSS)
SU(NSS)
t
c(SCK)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
MSB O UT
BIT6 OUT
LSB OUT
OUT PUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
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Figure 41: SPI timing diagram - master mode(1)
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
MSBIN
t
BIT6 IN
LSB IN
INPUT
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
10.3.9
I2C interface characteristics
Table 44: I2C characteristics
Symbol Parameter
Unit
Standard mode I2C
Fast mode I2C(1)
Min(2)
4.7
Max(2) Min(2)
Max(2)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
1.3
0.6
100
μs
4.0
250
0(3)
th(SDA)
SDA data hold time
0(4)
900(3)
300
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
300
ns
μs
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
th(STA)
START condition hold time
4.0
0.6
0.6
tsu(STA) Repeated START condition setup time 4.7
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Symbol Parameter
Electrical characteristics
Unit
Standard mode I2C
Fast mode I2C(1)
Min(2)
Max(2) Min(2)
Max(2)
tsu(STO) STOP condition setup time
4.0
0.6
1.3
tw(STO:STA) STOP to START condition time
(bus free)
4.7
μs
pF
Cb
Capacitive load for each bus line
400
400
(1)
f
, must be at least 8 MHz to achieve max fast I2C speed (400kHz)
MASTER
(2) Data based on standard I2C protocol requirement, not tested in production
(3) The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time
(4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
Figure 42: Typical application with I2C bus and timing diagram
V
V
DD
DD
STM8S
4.7kΩ
4.7kΩ
100Ω
100Ω
SDA
SCL
2
I
C bus
REPEATED
START
START
t
t
w(STO:STA)
su(STA)
START
SDA
t
t
r(SDA)
f(SDA)
t
t
h(SDA)
su(SDA)
STOP
SCL
t
t
t
t
t
su(STO)
t
h(STA)
w(SCLH)
w(SCLL)
r(SCL)
f(SCL)
ai17490
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
10.3.10 10-bit ADC characteristics
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
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Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2
Table 45: ADC characteristics
Symbol Parameter
Conditions
Min
Typ Max Unit
fADC ADC clock frequency
VDD =2.95 to 5.5 V
1
4
MHz
6
VDD =4.5 to 5.5 V
1
VAIN Conversion voltage range(1)
VSS
VDD
V
CADC Internal sample and hold
capacitor
3
pF
(1)
tS
Minimum sampling time
fADC = 4 MHz
fADC = 6 MHz
0.75
0.5
7
μs
tSTAB Wake-up time from standby
μs
tCONV Minimum total conversion time fADC = 4 MHz
(including sampling time,
3.5
2.33
14
μs
10-bit resolution)
fADC = 6 MHz
μs
1/fADC
(1) During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged
by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS. After the end of the sample time tS,
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tS depend on programming.
Table 46: ADC accuracy with RAIN < 10 kΩ , VDD= 5 V
Symbol
Parameter
Conditions
Typ
Max(1) Unit
|ET|
Total unadjusted error(2)
fADC = 2 MHz
1.6
3.5
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
2.2
2.4
1.1
4
LSB
4.5
|EO|
Offset error(2)
2.5
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STM8S103K3 STM8S103F3 STM8S103F2
Electrical characteristics
Symbol
Parameter
Conditions
Typ
Max(1) Unit
fADC = 4 MHz
1.5
3
fADC = 6 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 6 MHz
1.8
1.5
2.1
2.2
0.7
0.7
0.7
0.6
0.8
0.8
3
|EG|
Gain error(2)
3
3
4
|ED|
Differential linearity error(2)
1.5
1.5
1.5
1.5
2
|EL|
Integral linearity error(2)
2
(1) Data based on characterization results, not tested in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in the I/O
port pin characteristics section does not affect the ADC accuracy.
Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V
Symbol Parameter
Conditions
Typ
Max(1) Unit
|ET|
Total unadjusted error(2)
fADC = 2 MHz
1.6
3.5
fADC = 4 MHz
fADC = 2 MHz
1.9
1
4
LSB
|EO|
Offset error(2)
2.5
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Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2
Symbol Parameter
Conditions
Typ
Max(1) Unit
fADC = 4 MHz
1.5
2.5
|EG|
|ED|
|EL|
Gain error(2)
fADC = 2 MHz
fADC = 4 MHz
fADC = 2 MHz
fADC = 4 MHz
fADC = 2 MHz
fADC = 4 MHz
1.3
2
3
3
Differential linearity error(2)
Integral linearity error(2)
0.7
0.7
0.6
0.8
1
1.5
1.5
2
(1) Data based on characterization results, not tested in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in I/O port
pin characteristics does not affect the ADC accuracy.
Figure 43: ADC accuracy characteristics
1. Example of an actual transfer curve.
2. The ideal transfer curve
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STM8S103K3 STM8S103F3 STM8S103F2
Electrical characteristics
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer
curves.
EO = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: maximum deviation between actual steps and the ideal
one.
EL = Integral linearity error: maximum deviation between any actual transition and the end
point correlation line.
Figure 44: Typical application with ADC
V
STM8
DD
V
T
V
0.6 V
R
AIN
AIN
AINx
10-bit A/D
conversion
V
T
0.6 V
I
L
± 1 µA
C
C
AIN
ADC
10.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
10.3.11.1 Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of
the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
the IEC 61000-4-4 standard.
•
A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).
10.3.11.2 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
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Electrical characteristics
Prequalification trials
STM8S103K3 STM8S103F3 STM8S103F2
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).
Table 48: EMS data
Symbol Parameter
Conditions
Level/
class
VFESD Voltage limits to be
applied on any I/O pin to
induce a functional
2/B (1)
VDD = 3.3 V, TA = 25 °C, fMASTER = 16 MHz
(HSI clock), conforming to IEC 61000-4-2
disturbance
VEFTB
Fast transient voltage
burst limits to be applied
through 100 pF on VDD
and VSS pins to induce a
functional disturbance
4/A (1)
VDD= 3.3 V, TA = 25 °C ,fMASTER = 16 MHz
(HSI clock),conforming to IEC 61000-4-4
(1)Data obtained with HSI clock configuration, after applying HW recommendations described
in AN2860 (EMC guidelines for STM8S microcontrollers).
10.3.11.3 Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This emission test is in line with the norm SAE
IEC 61967-2 which specifies the board and the loading of each pin.
Table 49: EMI data
Conditions
(1)
Max fHSE/fCPU
Symbol Parameter
Unit
General
Monitored
16 MHz/ 16 MHz/
conditions
frequency band
8 MHz
16 MHz
Peak level VDD = 5 V
TA = 25 °C
0.1 MHz to
30 MHz
5
5
SEMI
dBμV
LQFP32
package
4
5
30 MHz to
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STM8S103K3 STM8S103F3 STM8S103F2
Electrical characteristics
Conditions
(1)
Max fHSE/fCPU
Symbol Parameter
Unit
General
Monitored
16 MHz/ 16 MHz/
conditions
frequency band
8 MHz
16 MHz
Conforming to 130 MHz
SAE IEC
61967-2
130 MHz to
5
5
1 GHz
SAE EMI
level
2.5
2.5
SAE EMI level
(1) Data based on characterisation results, not tested in production.
10.3.11.4 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, DLU and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
10.3.11.5 Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied
to the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated:
Human body model. This test conforms to the JESD22-A114A/A115A standard. For more
details, refer to the application note AN1181.
Table 50: ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum Unit
value(1)
VESD(HBM)
Electrostatic discharge
voltage
TA = 25°C, conforming to
JESD22-A114
A
4000
1000
(Human body model)
V
VESD(CDM)
Electrostatic discharge
voltage
TA LQFP32 package =
25°C, conforming to
SD22-C101
IV
(Charge device model)
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Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2
(1) Data based on characterization results, not tested in production
10.3.11.6 Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up performance:
A supply overvoltage (applied to each power supply pin)
•
A current injection (applied to each input, output and configurable I/O pin) are performed
on each sample.
•
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 51: Electrical sensitivities
Symbol Parameter
Conditions
Class(1)
TA = 25 °C
TA = 85 °C
TA = 125 °C
A
A
A
LU
Static latch-up class
(1) Class description: A Class is an STMicroelectronics internal specification. All its limits
are higher than the JEDEC specifications, that means when a device belongs to class A it
exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international
standard).
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STM8S103K3 STM8S103F3 STM8S103F2
Package information
11
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK®
is an ST trademark.
11.1
32-pin LQFP package mechanical data
Figure 45: 32-pin low profile quad flat package (7 x 7)
ccc
C
D
D1
D3
A
A2
24
17
16
25
32
L1
b
E3
E1 E
9
L
Pin 1
identification
A1
K
1
8
c
5V_ME
Table 52: 32-pin low profile quad flat package mechanical data
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
A
1.600
0.150
1.450
0.450
0.200
9.200
7.200
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
A1
A2
b
0.050
1.350
0.300
0.090
8.800
6.800
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
1.400
0.370
0.0551
0.0146
c
D
9.000
7.000
0.3543
0.2756
D1
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Package information
Dim.
STM8S103K3 STM8S103F3 STM8S103F2
inches(1)
mm
Min
Typ
Max
Min
Typ
Max
D3
E
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0.0°
0.750
0.0177
0.0°
0.0295
L1
k
7.0°
7.0°
ccc
0.100
0.0039
(1) Values in inches are converted from mm and rounded to 4 decimal digits
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Package information
11.2
32-lead UFQFPN package mechanical data
Figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5)
AOB8_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint
life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended
to connect and solder this backside pad to PCB ground.
4. Dimensions are in millimeters.
Table 53: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data
Dim.
mm
inches(1)
Min
0.500
0
Typ
Max
Min
Typ
Max
A
0.550
0.020
0.200
0.600
0.050
0.0197
0.0217
0.0008
0.0079
0.0236
0.0020
A1
A3
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Package information
Dim.
STM8S103K3 STM8S103F3 STM8S103F2
inches(1)
mm
Min
Typ
Max
Min
Typ
Max
b
0.180
4.850
3.200
4.850
3.200
0.250
5.000
3.450
5.000
3.450
0.500
0.400
0.300
5.150
3.700
5.150
3.700
0.0071
0.1909
0.1260
0.1909
0.1260
0.0098
0.1969
0.0118
0.2028
0.1457
0.2028
0.1457
D
D2
E
0.1969
0.1358
0.0197
0.0157
E2
e
L
0.300
0.500
0.080
0.0118
0.0197
0.0031
ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits.
11.3
20-lead UFQFPN package mechanical data
Figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3)
L1
D
e
ddd
L4
10
11
A3
L2
5
1
e
b
E
15
16
20
L3
A1
A
103_A0A5_ME
1. Drawing is not to scale.
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Package information
Table 54: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package
mechanical data
Dim.
mm
Min
inches(1)
Typ
Max
Min
Typ
Max
D
3.000
0.1181
E
3.000
0.550
0.020
0.152
0.500
0.550
0.350
0.150
0.200
0.250
0.1181
0.0217
0.0008
0.0060
0.0197
0.0217
0.0138
0.0059
0.0079
0.0098
A
0.500
0.000
0.600
0.050
0.0197
0.0000
0.0236
0.0020
A1
A3
e
L1
L2
L3
L4
b
0.500
0.300
0.600
0.400
0.0197
0.0118
0.0236
0.0157
0.180
0.050
0.300
0.0071
0.0020
0.0118
ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
STM8S103K3 STM8S103F3 STM8S103F2
11.4
20-pin TSSOP package mechanical data
Figure 48: 20-pin, 4.40 mm body, 0.65 mm pitch
D
20
11
c
E1
E
1
10
k
aaa
CP
A1
L
A
A2
L1
b
e
YA_ME
Table 55: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data
Dim.
mm
Min
inches(1)
Min
Typ
Max
Typ
Max
A
1.200
0.150
1.050
0.300
0.200
6.600
6.600
4.500
0.0472
0.0059
0.0413
0.0118
0.0079
0.2598
0.2598
0.1772
A1
A2
b
0.050
0.800
0.190
0.090
6.400
6.200
4.300
0.0020
0.0315
0.0075
0.0035
0.2520
0.2441
0.1693
1.000
0.0394
c
D
6.500
6.400
4.400
0.650
0.600
1.000
0.2559
0.2520
0.1732
0.0256
0.0236
0.0394
E
E1
e
L
0.450
0.750
0.0177
0.0295
L1
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Package information
Dim.
mm
inches(1)
Min
Typ
Max
8.0°
Min
Typ
Max
k
0.0°
0.0°
8.0°
aaa
0.100
0.0039
(1) Values in inches are converted from mm and rounded to 4 decimal digits
11.5
20-pin SO package mechanical data
Figure 49: 20-lead, plastic small outline (300 mils) package
D
20
11
h x 45°
C
E
H
1
10
A
ddd
A1
B
e
A1
k
L
Z7_ME
Table 56: 20-lead, plastic small outline (300 mils) mechanical data
Dim.
mm
inches(1)
Min
Typ
Max
Min
Typ
Max
A
2.350
0.100
0.330
0.230
12.600
7.400
2.650
0.300
0.510
0.320
13.000
7.600
0.0925
0.0039
0.013
0.1043
0.0118
0.0201
0.0126
0.5118
0.2992
A1
B
C
D
E
0.0091
0.4961
0.2913
e
1.270
0.0500
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Package information
Dim.
STM8S103K3 STM8S103F3 STM8S103F2
inches(1)
mm
Min
Typ
Max
Min
Typ
Max
H
10.000
0.250
0.400
0.0°
10.650
0.750
1.270
8.0°
0.3937
0.0098
0.0157
0.0°
0.4193
0.0295
0.0500
8.0°
h
L
k
ddd
0.100
0.0039
(1) Values in inches are converted from mm and rounded to 4 decimal digits
11.6
UFQFPN recommended footprint
Figure 50: Recommended footprint for on-board emulation
0.5mm
0.8mm
[0.032"]
4mm
[0.157"]
0.5mm
1.65mm [0.065"]
0.9mm
[0.035"]
0.3mm [0.012"]
4mm [0.157"]
ai15319
Bottom view
1. Drawing is not to scale
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Package information
Figure 51: Recommended footprint without on-board emulation
1. Drawing is not to scale
2. Dimensions are in millimeters
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Thermal characteristics
STM8S103K3 STM8S103F3 STM8S103F2
12
Thermal characteristics
The maximum chip junction temperature (TJ max) must never exceed the values given in
Operating conditions.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
TAmax is the maximum ambient temperature in °C
•
ΘJA is the package junction-to-ambient thermal resistance in °C/W
•
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax
)
•
PINTmax is the product of IDD andVDD, expressed in Watts. This is the maximum chip internal
power.
•
PI/Omax represents the maximum power dissipation on output pins
•
Where: PI/Omax =Σ (VOL*IOL) + Σ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and
VOH/IOH of the I/Os at low and high level in the application.
Table 57: Thermal characteristics
Symbol
Parameter(1)
Value
Unit
ΘJA
ΘJA
ΘJA
ΘJA
ΘJA
Thermal resistance junction-ambient
TSSOP20 - 4.4 mm
84
°C/W
Thermal resistance junction-ambient
SO20W (300 mils)
91
90
60
38
°C/W
°C/W
°C/W
°C/W
Thermal resistance junction-ambient
UFQFPN20 - 3 x 3 mm
Thermal resistance junction-ambient
LQFP32 - 7 x 7 mm
Thermal resistance junction-ambient
UFQFPN32 - 5 x 5 mm
(1)Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural
convection environment.
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Thermal characteristics
12.1
12.2
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural convection
(still air). Available from www.jedec.org.
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code.
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature TAmax= 75 °C (measured according to JESD51-2)
•
IDDmax = 8 mA, VDD = 5 V
•
Maximum 20 I/Os used at the same time in output at low level with
•
IOL = 8 mA, VOL= 0.4 V
PINTmax = 8 mA x 5 V = 400 mW
Amax
PDmax = 400 mW + 64 mW
•
Thus: PDmax = 464 mW
TJmax for LQFP32 can be calculated as follows, using the thermal resistance ΘJA:
TJmax = 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C
This is within the range of the suffix 6 version parts (-40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6.
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Ordering information
STM8S103K3 STM8S103F3 STM8S103F2
13
Ordering information
Figure 52: STM8S103x access line ordering information scheme
Example:
STM8
S
103
K
3
T
6
TR
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
10x = Access line
103 sub-family
Pin count
K = 32 pins
F = 20 pins
Program memory size
3 = 8 Kbytes
2 = 4 Kbytes
Package type 1
T = LQFP
U = UFQFPN
P = TSSOP
M = SO
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Package type 2
Blank = UFQFPN
Packing
No character = Tray or tube
TR = Tape and reel
1. A dedicated ordring information scheme will be released if, in the future, memory
programming service (FastROM) is required The letter "P" will be added after STM8S.
Three unique letters identifying the customer application code will also be visible in the
codification. Example: STM8SP103K3MACTR.
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please go to www.st.com or contact the ST
Sales Office nearest to you.
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Ordering information
13.1
STM8S103 FASTROM microcontroller option list
(last update: April 2010)
Customer
Address
Contact
.............................................................................................
.............................................................................................
.............................................................................................
.............................................................................................
Phone no.
Reference FASTROM codea .............................................................................................
Preferable format for programing code is .Hex (.s19 is accepted)
If data EEPROM programing is required, a seperate file must be sent with the requested data.
Important: See the option byte section in the datasheet for authorized option byte
combinations and a detailed explanation. Do not use more than one remapping option
in the same port. It is forbidden to enable both AFR1 and AFR0.
Device type/memory size/package (check only one option)
FASTROM device
LQFP32
4 Kbyte
8 Kbyte
[ ] STM8S103K3
[ ] STM8S103K3
[ ] STM8S103F3
[ ] STM8S103F3
UFQFPN32
TSSOP20
[ ] STM8S103F2
[ ] STM8S103F2
SO20W
Conditioning (check only one option)
[ ] Tape & reel or [ ] Tray
Special marking (check only one option)
[ ] No [ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character counts
are:
UFQFPN32: 1 line of 7 characters max: "_ _ _ _ _ _ _"
LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
TSSOP20/SO20: 1 line of 10 characters max: "_ _ _ _ _ _ _ _ _ _"
Three characters are reserved for code identification.
Temperature range
[ ] -40°C to +85°C or [ ] -40°C to +125°C
Padding value for unused program memory (check only one option)
[ ]0xFF
Fixed value
a
FASTROM code name is assigned by STMicroelectronics.
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Ordering information
STM8S103K3 STM8S103F3 STM8S103F2
[ ]0x83
[ ]0x75
TRAP instruction opcode
Illegal opcode (causes a reset when executed)
OPT0 memory readout protection (check only one option)
[ ] Disable or [ ] Enable
OPT1 user boot code area (UBC)
0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below.
UBC, bit0
[ ] 0: Reset
[ ] 1: Set
UBC bit1
[ ] 0: Reset
[ ] 1: Set
UBC bit2
[ ] 0: Reset
[ ] 1: Set
UBC bit3
[ ] 0: Reset
[ ] 1: Set
UBC bit4
[ ] 0: Reset
[ ] 1: Set
UBC bit5
[ ] 0: Reset
[ ] 1: Set
UBC bit6
[ ] 0: Reset
[ ] 1: Set
UBC bit7
[ ] 0: Reset
[ ] 1: Set
OPT2 alternate function remapping for STM8S103K
Do not use more than one remapping option in the same port. It is forbidden to enable both
AFR1 and AFR0.
AFR0
Reserved
AFR1
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
(check only one option)
[ ] 1: Port A3 alternate function = SPI_NSS and port D2
alternate function = TIM2_CH3
AFR2
Reserved
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Ordering information
AFR3
Reserved
Reserved
AFR4
AFR5
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
(check only one option)
[ ] 1: Port D0 alternate function = CLK_CCO
AFR6
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
(check only one option)
[ ] 1: Port D7 alternate function = TIM1_CH4
Reserved
AFR7
OPT2 alternate function remapping for STM8S103F
Do not use more than one remapping option in the same port. It is forbidden to enable both
AFR1 and AFR0.
AFR0
[ ] 0: Remapping option inactive. Default alternate functions
(check only one option)
used. Refer to pinout description
[ ] 1: Port C5 alternate function = TIM2_CH1, port C6 alternate
function = TIM1_CH1, and port C7 alternate function =
TIM1_CH2
AFR1
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
(check only one option)
[ ] 1: Port A3 alternate function = SPI_NSS and port D2 alternate
function = TIM2_CH3
AFR2
Reserved
AFR3
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
(check only one option)
[ ] 1: Port C3 alternate function = TLI
AFR4
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
(check only one option)
[ ] 1: Port B4 alternate function = ADC_ETR and port B5 alternate
function = TIM1_BKIN
AFR5
Reserved
Reserved
AFR6
AFR7
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
(check only one option)
[ ] 1: Port C3 alternate function = TIM1_CH1N and port C4
alternate function = TIM1_CH2N
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Ordering information
OPT3 watchdog
STM8S103K3 STM8S103F3 STM8S103F2
WWDG_HALT
[ ] 0: No reset generated on halt if WWDG active
[ ] 1: Reset generated on halt if WWDG active
(check only one option)
WWDG_HW
[ ] 0: WWDG activated by software
[ ] 1: WWDG activated by hardware
(check only one option)
IWDG_HW
[ ] 0: IWDG activated by software
[ ] 1: IWDG activated by hardware
(check only one option)
LSI_EN
[ ] 0: LSI clock is not available as CPU clock source
[ ] 1: LSI clock is available as CPU clock source
(check only one option)
HSITRIM
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR register
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR register
(check only one option)
OPT4 wakeup
PRSC
[ ] for 16 MHz to 128 kHz prescaler
[ ] for 8 MHz to 128 kHz prescaler
[ ] for 4 MHz to 128 kHz prescaler
(check only one option)
CKAWUSEL
[ ] LSI clock source selected for AWU
(check only one option)
[ ] HSE clock with prescaler selected as clock source for
for AWU
EXTCLK
[ ] External crystal connected to OSCIN/OSCOUT
[ ] External clock signal on OSCIN
(check only one option)
OPT5 crystal oscillator stabilization HSECNT (check only one option)
[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OPT6 is reserved
Comments:
...........................................................................................................
Supply operating range ...........................................................................................................
in the application:
Notes:
...........................................................................................................
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Ordering information
Date:
...........................................................................................................
...........................................................................................................
Signature:
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STM8 development tools
STM8S103K3 STM8S103F3 STM8S103F2
14
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards
and a low-cost in-circuit debugger/programmer.
14.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8
application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers
new advanced debugging capabilities including profiling and coverage to help detect and
eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to order
exactly what you need to meet your development requirements and to adapt your emulation
system to support existing and future ST microcontrollers.
STice key features
Occurrence and time profiling and code coverage (new features)
•
Advanced breakpoints with up to 4 levels of conditions
•
Data breakpoints
•
Program and data trace recording up to 128 KB records
•
Read/write on the fly of memory during emulation
•
In-circuit debugging/programming via SWIM protocol
•
8-bit probe analyzer
•
1 input and 2 output triggers
•
Power supply follower managing application voltages between 1.62 to 5.5 V
•
Modularity that allows you to specify the components you need to meet your development
requirements and adapt to future requirements
•
Supported by free software tools that include integrated development environment (IDE),
programming software interface and assembler for STM8.
•
14.2
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
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STM8 development tools
14.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
Seamless integration of C and ASM toolsets
•
Full-featured debugger
•
Project management
•
Syntax highlighting editor
•
Integrated programming interface
•
Support of advanced emulation features for STice such as code profiling and coverage
•
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
14.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
Cosmic C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes
of code. For more information, see www.cosmic-software.com.
•
•
•
Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which
allows you to assemble and link your application source code.
14.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to include
a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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Revision history
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15
Revision history
Table 58: Document revision history
Date
Revision
Changes
02-Mar-2009
1
Initial revision
10-Apr-2009
2
Added Table 2: Peripheral clock gating bit assignments in
CLK_PCKENR1/2 registers.
Updated Auto wakeup counter.
Modified description of PB4 and PB5 (removed X in PP column)
and added footnote concerning HS I/Os in VFQFPN32/LQFP32
pin description and STM8S103Kx UFQFPN32/LQFP32 pinout
and pin description.
Removed TIM3 and UART from Table 10: Interrupt mapping.
Updated VCAP specifications in VCAP external capacitor.
Corrected block size in Table 37: Flash program memory/data
EEPROM memory.
Updated Electrical characteristics.
Updated Table 57: Thermal characteristics.
10-Jun-2009
3
Document status changed from “preliminary data” to
“datasheet”.
Replaced WFQFPN20 package with UFQFPN package.
Replaced ‘VFQFN’ with ‘VFQFPN’.
Added bullet point on the unique identifier to Features.
Updated Auto wakeup counter.
Updated wpu and PP status of PB5/12C_SDA and
PB4/12C_SCL pins in VFQFPN32/LQFP32 pin description and
STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description.
Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin
access line devices.
Updated Figure 6: Memory map.
Updated reset status of port D CR1 register in Table 7: I/O port
hardware register map.
Updated alternate function remapping descriptions in Table
13: STM8S103K alternate function remapping bits for 32-pin
devices and Table 14: STM8S103F alternate function
remapping bits for 20-pin devices.
Added Unique ID.
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Revision history
Date
Revision
Changes
Updated Table 19: General operating conditions.
Updated name of Figure 19: Typical HSI accuracy at VDD = 5
V vs 5 temperatures.
Updated Table 43: SPI characteristics and added TBD data.
Added max values to Table 46: ADC accuracy with RAIN < 10
kΩ , VDD= 5 V and Table 47: ADC accuracy with RAIN < 10
kΩ RAIN, VDD = 3.3 V in the 10-bit ADC characteristics.
Updated EMC characteristics.
16-Oct-2009
4
Replaced VFQFPN32 package with UFQFPN32 package.
Clock controller: replaced "TIM2" and "TIM3" with "reserved"
and "TIM2" respectively in "Peripheral clock gating bit
assignments in CLK_PCKENR1/2 registers" table.
Total current consumption in halt mode: changed the maximum
current consumption limit at 125 °C (and VDD = 5 V) from 35
µA to 55 µA.
Functional EMS (electromagnetic susceptibility) : "ESD"
changed to "FESD" (functional); added name of AN1709;
replaced "IEC 1000" with "IEC 61000".
Designing hardened software to avoid noise problems: replaced
"IEC 1000" with "IEC 61000", added title of AN1015, and added
footnote to EMS data table.
Electromagnetic interference (EMI): replaced "J 1752/3" with
"IEC 61967-2" and updated data of the EMI data table.
Selecting the product temperature range: changed the value
of LQFP32 7x7 mm thermal resistance from 59 °C/W to 60
°C/W.
Added STM8S103 FASTROM microcontroller option list.
22-Apr-2010
5
Added VFQFPN32 and SO20 packages.
Updated Px_IDR reset value in Table 7: I/O port hardware
register map.
Operating conditions: updated VCAP and ESR low limit, added
ESL parameter, and Note 1 below Table 19: General operating
conditions.
Updated ACCHSI in Table 34: HSI oscillator characteristics
table. Modified IDD(H) in Table 27: Total current consumption
in halt mode at VDD = 5 V and Table 28: Total current
consumption in halt mode at VDD = 3.3 V. Removed note 3
related to Accuracy of HSI oscillator.
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Revision history
Date
STM8S103K3 STM8S103F3 STM8S103F2
Revision
Changes
Updated maximum power dissipation in Table 19: General
operating conditions.
Updated ΘJA in Table 57: Thermal characteristics.
Replaced package pitch digit by VFQFPN/UFQFPN package
digit in Figure 52: STM8S103x access line ordering information
scheme, and removed note 1.
09-Sep-2010
6
Removed VFQFPN32 package.
Updated "reset state" of Table 4: Legend/abbreviations for
pinout tables in Pinout and pin description.
Added footnote to PD1/SWIM pin in STM8S103Kx
UFQFPN32/LQFP32 pinout and pin description.
Updated pins 14 and 19 (TSSOP20/SO20) / pins 11 and 16
(UFQFPN20) in STM8S103Fx TSSOP20/SO20/UFQFPN20
pin description.
General hardware register map : Standardized all reset state
values; updated the reset state values of the RST_SR,
CLK_SWCR, CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR,
and ADC_DRx registers in the "General hardware register
map" table.
Updated AFR2 description of OPT 2 in Table 14: STM8S103F
alternate function remapping bits for 20-pin devices.
Replaced 0.01 µF with 0.1 µf in Figure 38: Recommended
reset pin protection.
Added "Typical application with I2C bus and timing diagram in
I2C interface characteristics.
Updated footnote 1 in Table 46: ADC accuracy with RAIN <
10 kΩ , VDD= 5 V and Table 47: ADC accuracy with RAIN <
10 kΩ RAIN, VDD = 3.3 V .
STM8S103 FASTROM microcontroller option list: updated
"special marking" section and AFR2 description of OPT2
alternate function remapping for STM8S103F.
32-lead UFQFPN package mechanical data: updated existing
footnote and added three additional footnotes.
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Please Read Carefully
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and services described herein at anytime, without notice.
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Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein,
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