STM8S103XX_技术文档

STM8S103xx

STM8S105xx

Access line, STM8S 8-bit MCU, up to 32 Kbytes Flash,

10-bit ADC, timers, USART, SPI, I²C

Preliminary Data

Features

Core

■ Max f

: up to 16 MHz

CPU

■ Advanced STM8 core with Harvard

architecture and 3-stage pipeline

■ Extended instruction set

LQFP48 7x7

LQFP44 10x10

Memories

■ Program memory: Up to 32 Kbytes Flash; data

retention 20 years at 85°C after 1 kcycles

■ RAM: Up to 2 Kbytes

LQFP32 7x7

TSSOP20

VFQFN32 5x5

Communications interfaces

■ USART or LINUART with clock output for

synchronous operation, smartcard mode, IrDA

mode, LIN master mode

Clock, reset and supply management

■ 3.0 to 5.5 V operating voltage

■ SPI synchronous serial interface up to 8 Mbit/s

■ I C interface up to 400 Kbit/s

■ Flexible clock control, 4 master clock sources:

– Low power crystal resonator oscillator

– External clock input

2

Analog to digital converter (ADC)

■ 10-bit, ±1 LSB ADC with up to 10 multiplexed

– Internal 16 MHz RC

channels, scan mode and analog watchdog

– Internal low power 128 kHz RC

■ Clock security system with clock monitor

■ Power management:

I/Os

■ Up to 38 I/Os on a 48-pin package including 9

high sink outputs

– Low power modes (Wait, Active-halt, Halt)

■ Highly robust I/O design, immune against

current injection

– Switch-off peripheral clocks individually

■ Permanently active, low consumption power-

on and power-down reset

Table 1.

Reference

STM8S103xx STM8S103K3

STM8S105C6, STM8S105C4,

Device summary

Interrupt management

■ Nested interrupt controller with 32 interrupts

■ Up to 37 external interrupts on 6 vectors

Root part number

Timers

STM8S105xx STM8S105K6, STM8S105K4,

STM8S105S6, STM8S105S4,

■ 2x 16-bit general purpose timers, with 2+3

CAPCOM channels (IC, OC or PWM)

■ Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-time

insertion and flexible synchronization

■ 8-bit basic timer with 8-bit prescaler

■ Auto wake-up timer

■ 2 watchdog timers: Window watchdog and

independent watchdog

June 2008

Rev 2

1/56

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

STM8S103xx, STM8S105xx

Contents

1

2

3

4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 11

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Auto wake-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.11 TIM2- 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.13 Analog/digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.14.1 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.14.2 LINUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.14.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

4.14.4 I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1

5.2

Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.1

Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/56

STM8S103xx, STM8S105xx

Contents

7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2

7.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.3.1

7.3.2

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.1

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.1.1

8.1.2

8.1.3

LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

QFN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

TSSOP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10

STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3/56

List of tables

STM8S103xx, STM8S105xx

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM8S103/105 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STM8 TIM timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pin description for STM8S105 MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pin description for STM8S103 MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

STM8S103x alternate function remapping bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

32-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . . 50

TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data . . . . . . . . . . . . . . . . . . . . 51

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4/56

STM8S103xx, STM8S105xx

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

STM8S105 access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

STM8S103 access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash memory organization (STM8S105). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Flash memory organisation (STM8S103). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STM8S105 LQFP/VQFN 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

STM8S103 LQFP/VQFN 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TSSOP20 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 12.

f

versus V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CPUmax

DD

Figure 13. Typical V and V vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

IL

IH

DD

Figure 14. Typical pull-up resistance R vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 40

PU

DD

Figure 15. Typical pull-up current I vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

pu

DD

Figure 16. Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 17. Typ. VOL @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18. Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 19. Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 20. Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 21. Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 22. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23. Typ. VDD - VOH @ VDD = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 24. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 25. Typ. VDD - VOH @ VDD = 5.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 26. Typical NRST V and V vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

IL

IH

DD

Figure 27. Typical NRST pull-up resistance R vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . 45

PU

DD

Figure 28. Typical NRST pull-up current I vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 45

pu

DD

Figure 29. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 30. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 31. 44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 32. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 33. 32-lead very thin fine pitch quad flat no-lead package (5 x 5) . . . . . . . . . . . . . . . . . . . . . . 50

Figure 34. TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 35. STM8S103/105 access line ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . 52

5/56

Introduction

STM8S103xx, STM8S105xx

1

Introduction

This datasheet contains the description of the STM8S103/105 access line features, pinout,

electrical characteristics, mechanical data and ordering information.

●

For complete information on the STM8S microcontroller memory, registers and

peripherals, please refer to the STM8S microcontroller family reference manual

(RM0016)

●

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM8S Flash programming manual (PM0051)

For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470)

For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044)

6/56

STM8S103xx, STM8S105xx

Description

2

Description

The STM8S103/105 access line 8-bit microcontrollers offer from 8 Kbytes up to 32 Kbytes of

program memory.

All devices of the STM8S103/105 access line provide the following benefits:

●

Reduced system cost

–

High system integration level with internal clock oscillators, watchdog and brown-

out reset

●

Performance and robustness

–

16 MHz CPU clock frequency

Robust I/O, independent watchdogs with separate clock source

Clock security system

●

Short development cycles

–

Applications scalability across a common family product architecture with

compatible pinout, memory map and and modular peripherals.

–

Full documentation and a wide choice of development tools

Product longevity

–

Advanced core and peripherals made in a state-of-the art technology

A family of products for applications with 3.0 V to 5.5 V operating supply

Table 2.

STM8S103/105 access line features

Device

Peripheral set

STM8S105C6 48 38⁽¹⁾37

STM8S105C4 48 38⁽¹⁾37

STM8S105S6 44 34⁽¹⁾31

STM8S105S4 44 34⁽¹⁾31

STM8S105K6 32 25⁽¹⁾23

STM8S105K4 32 25⁽¹⁾23

9

8

12 10 32K 2K

12 10 16K 2K

LINUART + extended

features (synchronous

comm. smartcard

Multipurpose timer (TIM1),

PWM timer (TIM2),

8-bit timer (TIM4),

SPI,

11

9

7

32K 2K

16K 2K

32K 2K

16K 2K

mode, IrdA mode),

PWM timer (TIM3)

I²C

USART with full

features (synchronous

1K comm. smartcard

Window WDG,

Independent WDG,

ADC + extended features

STM8S103K3 32 28⁽²⁾28

7

10

7

8

mode, IrdA mode and

single wire mode)

1. 9 high sink outputs

2. 8 high sink outputs

7/56

Block diagram

STM8S103xx, STM8S105xx

3

Block diagram

Figure 1.

STM8S105 access line block diagram

Reset block

XTAL 1-16 MHz

RC int. 16 MHz

RC int. 128 kHz

Clock controller

Reset

Detector

POR

BOR

Clock to peripherals and core

Window WDG

STM8 CORE

Independent WDG

Single wire

debug interf.

Up to 32 Kbytes

program

Debug/SWIM

Flash

Master/slave

autosynchro

LIN master

SPI emul.

LINUART

+ extended features

400 Kbit/s

2

Up to 2 Kbytes

RAM

I C

Boot ROM

10 Mbit/s

SPI

16-bit advanced control

timer (TIM1)

Up to

9 CAPCOM

channels

16-bit general purpose

timers (TIM2, TIM3)

8-bit basic timer

(TIM4)

Up to 10 channels

10-bit ADC

+ extended features

1/2/4 kHz

beep

Beeper

AWU timer

8/56

STM8S103xx, STM8S105xx

Block diagram

Figure 2.

STM8S103 access line block diagram

Reset block

Reset

XTAL 1-16 MHz

RC int. 16 MHz

RC int. 128 kHz

Clock controller

Detector

Reset

POR

BOR

Clock to peripherals and core

Window WDG

STM8 CORE

Debug/SWIM

Independent WDG

Single wire

debug interf.

Up to 8 Kbytes

program

Flash

400 Kbit/s

8 Mbit/s

2

1 Kbytes

RAM

I C

Boot ROM

SPI

16-bit advanced control

timer (TIM1)

LIN master

SPI emul.

USART

Up to

7 CAPCOM

channels

16-bit general purpose

timer (TIM2)

8-bit basic timer

(TIM4)

Up to 7 channels

10-bit ADC

+ extended features

1/2/4 kHz

beep

Beeper

AWU timer

9/56

Product overview

STM8S103xx, STM8S105xx

4

Product overview

The following section intends to give an overview of the basic features of the

STM8S103/105 access line functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual

(RM0016).

4.1

Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20

addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

●

Harvard architecture

3-stage pipeline

32-bit wide program memory bus - single cycle fetching for most instructions

X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

●

8-bit accumulator

24-bit program counter - 16-Mbyte linear memory space

16-bit stack pointer - access to a 64 K-level stack

8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

●

20 addressing modes

Indexed indirect addressing mode for look-up tables located anywhere in the address

space

●

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

●

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

10/56

STM8S103xx, STM8S105xx

Product overview

4.2

Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module and permit non-intrusive, real-time in-

circuit debugging and fast memory programming.

SWIM

Single wire interface module for direct access to the debug module and memory

programming. The interface can be activated in all device operation modes. The maximum

data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured

emulator. Beside memory and peripherals, also CPU operation can be monitored in real-

time by means of shadow registers.

●

R/W to RAM and peripheral registers in real-time

R/W access to all resources by stalling the CPU

Breakpoints on all program-memory instructions (software breakpoints)

2 advanced breakpoints, 23 predefined configurations

4.3

4.4

Interrupt controller

●

Nested interrupts with 3 software priority levels

32 interrupt vectors with hardware priority

Up to 37 external interrupts on 6 vectors including TLI

Trap and reset interrupts

Flash program memory

●

Up to 32 Kbytes of program single voltage Flash memory

User option byte area

●

11/56

Product overview

STM8S103xx, STM8S105xx

Write protection (WP)

Write protection of Flash is provided to avoid unintentional overwriting of memory that could

result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (Memory Access

Security System). MASS is always enabled and protects the main Flash program memory

and option bytes.

To perform In-Application Programming (IAP), this write protection can be removed by

writing a MASS key sequence in a control register. This allows the application to modify the

contents of main program memory or the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of

memory known as UBC (user boot code). Refer to Figure 3.

The size of the UBC is programmable through the UBC option byte (Table 8.), in increments

of 1 page, by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

●

Main program memory: Up to 32 Kbytes minus UBC

●

User-specific boot code (UBC): Configurable up to 32 Kbytes

The UBC area remains write-protected during in-application programming. This means that

the MASS keys do not unlock the UBC area. It protects the memory used to store the boot

program, specific code libraries, reset and interrupt vectors, the reset routine and usually the

IAP and communication routines.

Figure 3.

Flash memory organization (STM8S105)

Programmable area from 0.5 Kbytes

(2 first pages) up to 32 Kbytes

(1 page steps)

UBC area

Remains write protected during IAP

Up to

32 Kbytes

Flash

program

memory

Program memory area

Write access possible for IAP

12/56

STM8S103xx, STM8S105xx

Figure 4. Flash memory organisation (STM8S103)

Product overview

Programmable area from 128 bytes

(2 first pages) up to 8 Kbytes

(1 page steps)

UBC area

Remains write protected during IAP

Up to

8 Kbytes

Flash

program

memory

Program memory area

Write access possible for IAP

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory in debug

mode. Once the read-out protection is activated, any attempt to toggle its status triggers a

global erase of the program and data memory. Even if no protection can be considered as

totally unbreakable, the feature provides a very high level of protection for a general purpose

microcontroller.

4.5

Clock controller

The clock controller distributes the system clock (f

) coming from different oscillators

MASTER

to the core and the peripherals. It also manages clock gating for low power modes and

ensures clock robustness.

Features

●

Clock prescaler: to get the best compromise between speed and current consumption

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register. The clock signal is not switched until the new clock

source is ready. The design guarantees glitch-free switching.

●

Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

Master clock sources: 4 different clock sources can be used to drive the master clock:

–

1-16 MHz High Speed External crystal (HSE)

Up to 16 MHz High Speed user-external clock (HSE user-ext)

16 MHz High Speed Internal RC oscillator (HSI)

128 kHz Low Speed Internal RC (LSI)

●

Startup clock: After reset, the microcontroller restarts by default with an internal 2

MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the

application program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE

clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS

13/56

Product overview

and an interrupt can optionally be generated.

STM8S103xx, STM8S105xx

●

Configurable main clock output (CCO): This outputs an external clock for use by the

application. Available frequencies are 8 MHz, 4 MHz or 1 MHz.

4.6

Power management

For efficent power management, the application can be put in one four different low-power

modes. You can configure each mode to obtain the best compromise between lowest power

consumption, fastest start-up time and available wakeup sources.

●

Wait mode: in this mode, the CPU is stopped, but peripherals are kept running. The

wake-up is performed by an internal or external interrupt or reset.

●

Fast active halt mode: in this mode, the CPU and peripheral clocks are stopped. An

internal wake-up is generated at programmable intervals by the auto wake up unit

(AWU). The main voltage regulator is kept powered on, so current consumption is more

than in slow active halt mode, but the wake-up time is faster. Wake-up is triggered by

the internal AWU interrupt, external interrupt or reset.

●

Slow active halt mode: this mode is the same as fast active halt except that the main

voltage regulator is powered off, so the wake up time is slower.

Halt mode: in this mode the microcontroller uses the least power, CPU and peripheral

clocks are stopped, the main voltage regulator is powered off. Wake-up is triggered by

external interrupt or reset.

4.7

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the applications.

The WDG timer activity is controlled by option bytes. Once activated the watchdog can not

be disabled by the user program without reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application

perfectly.

The application software must refresh the counter before time-out and during a limited time

window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up

to 64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower then the

one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to

hardware or software failures.

14/56

STM8S103xx, STM8S105xx

Product overview

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case

of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

4.8

Auto wake-up counter

●

Used for auto wake-up from active halt mode

●

Clock source: internal 128 kHz internal low frequency RC oscillator or external clock

4.9

Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in

the range of 1, 2 or 4 kHz.

4.10

TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its

complementary outputs, dead-time control and center-aligned PWM capability, the field of

applications is extended to motor control, lighting and half-bridge driver.

●

16-bit up, down and up/down autoreload counter with 16-bit prescaler

●

4 independent capture/compare channels (CAPCOM) configurable as input capture,

output compare, PWM generation (edge and center aligned mode) and single pulse

mode output

●

Synchronization module to control the timer with external signal

Break input to force the timer outputs into a defined state

3 complementary outputs with adjustable dead time

Encoder mode

Interrupt sources: x input capture/output compare, 1 x overflow/update, 1 x break

4.11

4.12

TIM2- 16-bit general purpose timer

●

16-bit autoreload (AR) up-counter

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

Timers with 3 or 2 individually configurable capture/compare channels

PWM mode

Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

TIM4 - 8-bit basic timer

●

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

Clock source: CPU clock

Interrupt source: 1 x overflow/update

15/56

Product overview

STM8S103xx, STM8S105xx

Timer

Table 3.

Timer

STM8 TIM timer feature comparison

Counter

size

CAPCOM

channels

Counting

mode

Complem.

outputs

Ext.

trigger

synchr-

onization/

chaining

Prescaler

(bits)

TIM1

TIM2

TIM3

TIM4

16

8

Any integer from 1 to 65536

Any power of 2 from 1 to 32768

Any power of 2 from 1 to 128

Up/down

Up

4

3

2

0

3

0

Yes

No

Yes

Up

16/56

STM8S103xx, STM8S105xx

Product overview

4.13

Analog/digital converter (ADC)

●

STM8S103/105 access line products contain a 10-bit successive approximation A/D

converter with up to 10 multiplexed input channels and the following general features:

–

Input voltage range: 0 to V

DDA

Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices

Conversion time: 14 clock cycles

Single and continuous conversion modes

External trigger input

Trigger from TIM1 TRGO (STM8S105) or TIM2 TRGO (STM8S103)

End of conversion (EOC) interrupt

ADC extended features

●

STM8S103/105 access line products contain a 10-bit successive approximation A/D

converter with the following features:

–

Up to 10 (STM8S105x) or 7 (STM8S103x) multiplexed input channels

Single, continuous and buffered continuous conversion on a selected channel

Scan mode for single and continuous conversion of a sequence of channels

Analog watchdog capability with programmable upper and lower thresholds

Internal reference voltage on channel AIN7 (STM8S103 only)

Analog watchdog interrupt

4.14

Communication interfaces

The following communication interfaces are implemented:

●

USART:

–

STM8S105: no USART

STM8S103: full feature UART, single wire mode, LIN2.1 master capability

●

LINUART:

–

STM8S105: LIN2.1 master/slave capability, full feature UART, synchronous mode,

SPI master mode, Smartcard mode, IrDA mode

–

STM8S103: No LINUART

●

SPI - full and half-duplex, 8 Mbit/s

I²C - up to 400 Kbit/s

17/56

Product overview

STM8S103xx, STM8S105xx

4.14.1

USART

Main features

●

1 Mbit/s full duplex SCI

LIN master capable

SPI emulation

High precision baud rate generator

Smartcard emulation

IrDA SIR encoder decoder

Single wire half duplex mode

Asynchronous communication (UART mode)

●

Full duplex communication - NRZ standard format (mark/space)

Programmable transmit and receive baud rates up to 1 Mbit/s (f

/16) and capable of

CPU

following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

2 receiver wakeup modes:

●

–

Address bit (MSB)

Idle line (interrupt)

●

Transmission error detection with interrupt generation

Parity control

LIN master capability

●

Emission: Generates 13-bit synch break frame

Reception: Detects 11-bit break frame

Synchronous communication

●

Full duplex synchronous transfers

SPI master operation

8-bit data communication

Max. speed: 1 Mbit/s at 16 MHz (f

/16)

CPU

4.14.2

LINUART

Main features

●

LIN master/slave rev. 2.1 compliant

Auto-synchronization in LIN slave mode

High precision baud rate generator

1 Mbit full duplex SCI

LIN master

●

Emission: Generates 13-bit synch break frame

Reception: Detects 11-bit break frame

18/56

STM8S103xx, STM8S105xx

LIN slave

Product overview

●

Autonomous header handling - one single interrupt per valid message header

Automatic baud rate synchronization - maximum tolerated initial clock deviation 15 %

Synch delimiter checking

11-bit LIN synch break detection - break detection always active

Parity check on the LIN identifier field

LIN error management

Hot plugging support

Asynchronous communication (UART mode)

●

Full duplex, asynchronous communications - NRZ standard format (mark/space)

Independently programmable transmit and receive baud rates up to 500 Kbit/s

Programmable data word length (8 or 9 bits)

Low-power standby mode - 2 receiver wake-up modes:

–

Address bit (MSB)

Idle line

●

Muting function for multiprocessor configurations

Overrun, noise and frame error detection

6 interrupt sources

Tx, Rx parity control

Note:

In STM8S105, the LINUART also supports IrDA mode, Smartcard mode and synchronous

communication (SPI master mode).

4.14.3

SPI

●

Maximum speed: 8 Mbit/s (f

/2) both for master and slave

MASTER

Full duplex synchronous transfers

Simplex synchronous transfers on 2 lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

CRC calculation

1 byte Tx and Rx buffer

Slave/master selection input pin

19/56

Product overview

2

STM8S103xx, STM8S105xx

4.14.4

I C

●

I²C master features:

–

Clock generation

Start and stop generation

●

I²C slave features:

–

Programmable I²C address detection

Stop bit detection

●

Generation and detection of 7-bit/10-bit addressing and general call

Supports different communication speeds:

–

Standard speed (up to 100 kHz),

Fast speed (up to 400 kHz)

20/56

STM8S103xx, STM8S105xx

Pinouts and pin description

5

Pinouts and pin description

5.1

Package pinouts

Figure 5.

LQFP 48-pin pinout

48 47 46 45 4443424140393837

36

NRST

OSCIN/PA1

PG1

1

2

35 PG0

OSCOUT/PA2

3

34 PC7/SPI_MISO

V

33

32

31

30

29

28

27

26

25

4

5

6

7

8

9

10

11

PC6/SPI_MOSI

SSIO_1

V

SS

DDIO_2

VCAP

V

SSIO_2

V

PC5/SPI_SCK

DD

V

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1/LINUART_CK

PE5/SPI_NSS

DDIO_1

TIM2_CC3/PA3

PA4

PA5

PA6

12

24

1314 15161718192021 2223

(HS) high sink capability

21/56

Pinouts and pin description

Figure 6. LQFP 44-pin pinout

STM8S103xx, STM8S105xx

44 43 42 41 40 39 38 37 36 35 34

NRST

OSCIN/PA1

OSCOUT/PA2

1

2

3

4

5

6

7

PG1

PG0

PC7/SPI_MISO

PC6/SPI_MOSI

33

32

31

30

29

28

27

V

SSIO_1

V

SS

DDIO_2

VCAP

V

SSIO_2

V

PC5/SPI_SCK

DD

V

8

9

10

11

26 PC3 (HS)/TIM1_CC3

25 PC2 (HS)/TIM1_CC2

24 PC1 (HS)/TIM1_CC1/LINUART_CK

23 PE5/SPI_NSS

DDIO_1

PA4

PA5

PA6

121314 1516171819202122

(HS) high sink capability

22/56

STM8S103xx, STM8S105xx

Figure 7. STM8S105 LQFP/VQFN 32-pin pinout

Pinouts and pin description

32 31 30 29 28 27 26 25

24

NRST

OSCIN/PA1

OSCOUT/PA2

1

2

3

4

5

6

7

8

PC7/SPI_MISO

PC6/SPI_MOSI

PC5/SPI_SCK

PC4 (HS)/TIM1_CC4

PC3 (HS)/TIM1_CC3

PC2 (HS)/TIM1_CC2

PC1 (HS)/TIM1_CC1/LINUART_CK

PE5/SPI_NSS

23

22

21

20

19

18

17

V

SS

VCAP

V

DD

V

DDIO

AIN12/PF4

9 101112 13141516

(HS) high sink capability

23/56

Pinouts and pin description

Figure 8. STM8S103 LQFP/VQFN 32-pin pinout

STM8S103xx, STM8S105xx

32 31 30 29 28 27 26 25

24

NRST

OSCIN/PA1

OSCOUT/PA2

1

2

3

4

5

6

7

8

PC7(HS)/SPI_MISO

PC6(HS)/SPI_MOSI

PC5(HS)/SPI_SCK/TIM2_CC1

PC4(HS)/AIN2/TIM1_CC4

PC3 (HS)/TIM1_CC3/TLI/USART_CK

PC2 (HS)/TIM1_CC2

23

22

21

20

19

18

17

V

SS

VCAP

V

DD

SPI_NSS/TIM2_CC3/(HS)PA3

PF4

PC1 (HS)/TIM1_CC1

PE5(HS)/SPI_NSS

9 101112 13141516

(HS) high sink capability

Figure 9.

TSSOP20 pinout

USART_TX/AIN5/PD5

USART_RX/AIN6/PD6

NRST

PD4 (HS)/TIM2_CC1/BEEP /USART_CK

PD3 (HS)/AIN4/TIM2_CC2/ADC_ETR

PD2(HS)/AIN3/TIM2_CC3

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

PD1 (HS)/SWIM

OSCIN/PA1

PC7(HS)/SPI_MISO

OSCOUT/PA2

PC6(HS)/SPI_MOSI

V

SS

PC5 (HS)/TIM2_CC1/SPI_SCK

PC4(HS)/AIN2/TIM1_CC4/CLK_CCO

PC3(HS)/TLI/TIM1_CC3/USART_CK

VCAP

V

DD

SPI_NSS/TIM2_CC3/(HS)PA3

2

PB4/I C_SCL

I C_SDA/PB5

(HS) high sink capability

24/56

STM8S103xx, STM8S105xx

Pinouts and pin description

5.2

Pin description

Table 4.

Type

Legend/abbreviations

I= input, O = output, S = power supply

Level

Input

CM = CMOS

Output

HS = High sink

Output speed

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Port and control Input

float = floating, wpu = weak pull-up

configuration

Output

T = true open drain, OD = open drain, PP = push pull

Reset state is shown in bold.

Table 5.

Pin description for STM8S105 MCUs

Input

Pin number

Output

Alternate

Default alternate functionafter

Pin name

function

remap

[option bit]

1

2

1

2

1

2

NRST

I/O

X

Reset

Resonator/

crystal in

PA1/OSCIN

X

O1

X

Port A1

Resonator/ crystal

out

3

PA2/OSCOUT

I/O

X

Port A2

4

5

6

7

8

-

4

5

6

7

8

-

V_{SSIO_1}

V_SS

S

I/O ground

4

5

6

7

8

Digital ground

VCAP

S

1.8 V regulator capacitor

Digital power supply

I/O power supply

Port F4 Analog input 12

V_DD

S

V_{DDIO_1}

PF4/AIN12

S

I/O

X

O1

X

TIM3_CC1

[AFR1]

9

-

PA3/TIM2_CC3

I/O

X

Port A3 Timer 2 - channel3

10

9

-

PA4

PA5

PA6

V_DDA

I/O

S

X

O3

X

Port A4

11 10

12 11

13 12

Port A5

-

Port A6

9

Analog power supply

Analog ground

Port B7 Analog input 7

14 13 10 V_SSA

15 14 PB7/AIN7

S

-

I/O

X

O1

X

25/56

Pinouts and pin description

STM8S103xx, STM8S105xx

Table 5.

Pin description for STM8S105 MCUs (continued)

Pin number

Input

Output

Alternate

Default alternate functionafter

Pin name

function

remap

[option bit]

16 15

-

PB6/AIN6

I/O

X

O1

X

Port B6 Analog input 6

Port B5 Analog input 5

I²C_SDA

[AFR6]

17 16 11 PB5/AIN5

18 17 12 PB4/AIN4

19 18 13 PB3/AIN3

20 19 14 PB2/AIN2

21 20 15 PB1/AIN1

22 21 16 PB0/AIN0

I²C_SCL

[AFR6]

I/O

X

O1

X

Port B4 Analog input 4

Port B3 Analog input 3

Port B2 Analog input

Port B1 Analog input 1

Port B0 Analog input 0

TIM1_ETR

[AFR5]

TIM1_NCC3

[AFR5]

TIM1_NCC2

[AFR5]

TIM1_NCC1

[AFR5]

23

-

PE7/AIN8

PE6/AIN9

I/O

X

O1

X

Port E7 Analog input 8

Port E7 Analog input 9

24 22

SPI master/slave

select

25 23 17 PE5/SPI_NSS

I/O

X

O1

X

Port E5

Timer 1 - channel 1

Port C1 / LINUART

PC1/TIM1_CC1/

26 24 18

HS O3

LINUART_CK

synchronous clock

27 25 19 PC2/TIM1_CC2

28 26 20 PC3/TIM1_CC3

I/O

S

X

HS O3

O3

X

Port C2 Timer 1- channel 2

Port C3 Timer 1 - channel 3

Port C4 Timer 1 - channel 4

Port C5 SPI clock

29

-

21 PC4/TIM1_CC4

30 27 22 PC5/SPI_SCK

31 28

32 29

-

V_{SSIO_2}

V_{DDIO_2}

I/O ground

S

I/O power supply

SPI master out/

Port C6

33 30 23 PC6/SPI_MOSI

34 31 24 PC7/SPI_MISO

I/O

X

O3

X

slave in

SPI master in/

Port C7

slave out

35 32

36 33

-

PG0

PG1

I/O

X

O1

X

Port G0

Port G1

Timer 1 - break

input

37

-

PE3/TIM1_BKIN

PE2/I²C_SDA

I/O

X

O1

X

Port E3

38 34

26/56

O1 T⁽¹⁾

Port E2 I²C data

STM8S103xx, STM8S105xx

Pinouts and pin description

Table 5.

Pin description for STM8S105 MCUs (continued)

Pin number

Input

Output

Alternate

Default alternate functionafter

Pin name

function

remap

[option bit]

39 35

40 36

-

PE1/I²C_SCL

I/O

X

O1 T⁽¹⁾

X

Port E1 I²C clock

Configurable clock

output

PE0/CLK_CCO

O3

X

Port E0

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

41 37 25 PD0/TIM3_CC2

I/O

X

HS O3

X

Port D0 Timer 3 - channel 2

SWIM data

Port D1

42 38 26 PD1/SWIM

I/O

X

HS O4

HS O3

O1

X

interface

TIM2_CC3

[AFR1]

43 39 27 PD2/TIM3_CC1

44 40 28 PD3/TIM2_CC2

Port D2 Timer 3 - channel 1

Port D3 Timer 2 - channel 2

Port D4 Timer 2 - channel 1

ADC_ETR

[AFR0]

PD4/TIM2_CC1/BEE

BEEP output

[AFR7]

45 41 29

P

LINUART data

Port D5

46 42 30 PD5/ LINUART_TX I/O

47 43 31 PD6/ LINUART_RX I/O

transmit

LINUART data

Port D6

O1

receive

TIM1_CC4

[AFR4]

48 44 32 PD7/TLI

I/O

O1

Port D7 Top level interrupt

1. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V_DDare not

implemented)

27/56

Pinouts and pin description

STM8S103xx, STM8S105xx

Table 6.

Pin description for STM8S103 MCUs

number

Input

Output

Alternate

function

Default alternate

function

after

remap

[option

bit]

Pin name

1

2

3

4

NRST

I/O

X

Reset

Resonator/

crystal in

PA1/OSCIN

X

O1

X

Port A1

Resonator/ crystal

out

3

5

PA2/OSCOUT

I/O

X

Port A2

4

5

6

7

8

V_SS

S

Digital ground

VCAP

V_DD

1.8 V regulator capacitor

Digital power supply

SPI

7

9

PA3/TIM2_CC3/SPI_NSS

I/O

X

HS O3

X

X Port A3 Timer 2 channel 3 master/sla

ve select

8

9

-

PF4

PB7

PB6

I/O

X

O1

X

Port F4

Port B7

10

Port B6

11 10 PB5/I2C_SDA

12 11 PB4/I2C_SCL

O1 T⁽¹⁾

Port B5 I²C data

Port B4 I²C clock

Timer 1 external

trigger

13

14

-

PB3/TIM1_ETR

I/O

X

HS O3

X

Port B3

Port B2

Timer 1 - inverted

channel 3

PB2/TIM1_NCC3

HS O3

Analog input 1/

Port B1 Timer 1 - inverted

15

16

-

PB1/AIN1/TIM1_NCC2

PB0/AIN0/TIM1_NCC1

I/O

X

channel 2

Analog input 0/

Port B0 Timer 1 - inverted

channel 1

HS O3

SPI master/slave

select

17

18

19

-

PE5/SPI_NSS

PC1/TIM1_CC1

PC2/TIM1_CC2

I/O

X

HS O3

X

Port E5

Timer 1 - channel

1

Port C1

Timer 1 - channel

2

Port C2

Top level interrupt

PC3/TLI/TIM1_CC3/

USART_CK

USART

clock

20 12

I/O

X

HS O3

X

Port C3

Timer 1 - channel

3

28/56

STM8S103xx, STM8S105xx

Pinouts and pin description

Table 6.

Pin description for STM8S103 MCUs (continued)

number

Input

Output

Alternate

function

Default alternate

function

after

remap

[option

bit]

Pin name

Con-

figurable

clock

Analog input 2 /

Port C4 Timer 1 - channel

PC4/AIN2/TIM1_CC4/

CLK_CCO

21 13

I/O

X

HS O3

X

4

output

Timer 2 - channel

1

22 14 PC5/TIM2_CC1/SPI_SCK

23 15 PC6/SPI_MOSI

I/O

X

HS O3

X

Port C5

SPI clock

SPI master out/

Port C6

slave in

SPI master in/

Port C7

24 16 PC7/SPI_MISO

slave out

Con-

Timer 1 - break

input

figurable

clock

25

-

PD0/TIM1_BKIN/CLK_CCO I/O

X

HS O3

X

Port D0

output

SWIM data

Port D1

26 17 PD1/SWIM

I/O

X

HS O4

HS O3

X

interface

Analog input 3 /

Port D2 Timer 2 - channel

27 18 PD2/AIN3/TIM2_CC3

X

3

Analog input 4 /

Port D3 Timer 2 - channel external

ADC

PD3/AIN4/TIM2_CC2/ADC_

28 19

ETR

I/O

X

HS O3

X

2

trigger

USART

PD4/TIM2_CC1/BEEP/

29 20

Timer 2 - channel clock/

1

Port D4

USART_CK

BEEP

output

USART

data

transmit

30

31

32

1

2

-

PD5/AIN5/USART_TX

PD6/AIN6/USART_RX

PD7/TLI/TIM1_CC4

I/O

X

O1

X

Port D5 Analog input 5

Port D6 Analog input 6

USART

data

receive

Top level interrupt/

Port D7 Timer 1 - channel

HS O3

4

1. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V_DDare not

implemented)

29/56

Pinouts and pin description

STM8S103xx, STM8S105xx

5.2.1

Alternate function remapping

As shown in the rightmost column of the pin description table, some alternate functions can

be remapped at different I/O ports by programming one of 8 AFR (alternate function remap)

option bits. Refer to Section 6: Option bytes on page 29. When the remapping option is

active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral

registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see GPIO

section of the family reference manual, RM0016).

30/56

STM8S103xx, STM8S105xx

Option bytes

6

Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated block of the memory. Except for the

ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form

(OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the address shown in

Table 7: Option bytes below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the

ROP and UBC options that can only be toggled in ICP mode (via SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM

communication protocol and debug module user manual (UM0470) for information on SWIM

programming procedures.

Table 7.

Addr.

Option bytes

Option

byte

Option bits

Factory

default

setting

Option

name

7

6

5

4

3

2

1

0

no.

4800h Read-out

protection

OPT0

ROP[7:0]

00h

(ROP)

4801h

4802h

User boot

code(UBC)

OPT1

NOPT1

OPT2

UBC[7:0]

00h

FFh

00h

FFh

NUBC[7:0]

4803h Alternate

function

4804h

AFR7

AFR6

AFR5

AFR4

AFR3

AFR2

AFR1

AFR0

NOPT2

NAFR7

NAFR6

NAFR5

NAFR4

NAFR3

NAFR2

NAFR1

NAFR0

remapping

(AFR)

4805h Watchdog

option

OPT3

NOPT3

OPT4

Reserved

LSI

_EN

IWDG

_HW

WWDG

_HW

WWDG

_HALT

00h

FFh

00h

FFh

4806h

Reserved

NLSI

_EN

NIWDG_

HW

NWWDG

_HW

NWWG

_HALT

4807h Clock option

4808h

EXT

CLK

CKAWU

SEL

PRS

C1

PRS

C0

NOPT4

NCKAWUS

EL

NPR

SC1

NPR

SC0

4809h HSE clock

startup

OPT5

NOPT5

OPT6

HSECNT[7:0]

NHSECNT[7:0]

Reserved

00h

FFh

00h

FFh

00h

FFh

00h

FFh

480Ah

480Bh Reserved

480Ch

NOPT6

OPT7

Reserved

480Dh Flash wait

states

480Eh

Reserved

BL[7:0]

NBL[7:0]

Wait state

NOPT7

OPTBL

NOPTBL

Nwait state

487Eh Bootloader

487Fh

31/56

Option bytes

STM8S103xx, STM8S105xx

Table 8.

Option byte description

Option byte no.

Description

ROP[7:0] Memory readout protection (ROP)

AAh: Enable readout protection (write access via SWIM protocol)

Note: Refer to the family reference manual (RM0016) section on Flash

memory readout protection for details.

OPT0

UBC[7:0] User boot code area

For STM8S105 (page size 128 bytes):

00h: no UBC, no write-protection

01h: Page 0 and 1 defined as UBC, memory write-protected

02h to FFh: Pages 2 to 255 defined as UBC, memory write-protected

For STM8S103 (page size 64 bytes):

OPT1

00h: no UBC, no write-protection

01h: Page 0 and 1 defined as UBC, memory write-protected

02h to 7Fh: Pages 2 to 127 defined as UBC, memory write-protected

Note: Refer to the family reference manual (RM0016) section on Flash

write protection for more details.

Note : This remapping applies to STM8S105. For STM8S103 alternate

function remapping refer to Table 9 on page 34.

AFR7Alternate function remapping option 7

0: Port D4 alternate function = TIM2_CC1

1: Port D4 alternate function = BEEP

AFR6 Alternate function remapping option 6

0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4

1: Port B5 alternate function = I²C_SDA, port B4 alternate function =

I²C_SCL

AFR5 Alternate function remapping option 5

0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,

port B1 alternate function = AIN1, port B0 alternate function = AIN0

1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =

TIM1_NCC3, port B1 alternate function = TIM1_NCC2, port B0 alternate

function = TIM1_NCC1

OPT2

AFR4 Alternate function remapping option 4

0: Port D7 alternate function = TLI

1: Port D7 alternate function = TIM1_CC4

AFR3 Alternate function remapping option 3

0: Port D0 alternate function = TIM3_CC2

1: Port D0 alternate function = TIM1_BKIN

AFR2 Alternate function remapping option 2

0: Port D0 alternate function = TIM3_CC2

1: Port D0 alternate function = CLK_CCO

Note: AFR2 option has priority over AFR3 if both are activated

AFR1 Alternate function remapping option 1

0: Port A3 alternate function = TIM2_CC3, port D2 alternate function

TIM3_CC1

1: Port A3 alternate function = TIM3_CC1, port D2 alternate function

TIM2_CC3

OPT2 (cont’d)

AFR0 Alternate function remapping option 0

0: Port D3 alternate function = TIM2_CC2

1: Port D3 alternate function = ADC_ETR

32/56

STM8S103xx, STM8S105xx

Option bytes

Table 8.

Option byte description (continued)

Option byte no.

Description

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

OPT3

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto wake-up unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

OPT4

OPT5

PRSC[1:0] AWU clock prescaler

00: Reserved

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

This configures the stabilisation time to 0, 16, 256, 4096 HSE cycles.

OPT6

OPT7

Reserved

BL[7:0] Bootloader option byte

This option is checked by the boot ROM code after reset. Depending on

content of addresses 487Eh, 487Fh and 8000h (reset vector) the CPU

jumps to the bootloader or to the reset vector.

OPTBL

Refer to STM8S bootloader manual for more details.

33/56

Option bytes

STM8S103xx, STM8S105xx

Table 9.

STM8S103x alternate function remapping bits.

Option byte no.

Description

AFR7Alternate function remapping option 7

0: TBD

1: TBD

AFR6 Alternate function remapping option 6

0: TBD

1: TBD

AFR5 Alternate function remapping option 5

0: TBD

1: Reserved

AFR4 Alternate function remapping option 4

0: TBD

1: TBD

OPT2

AFR3 Alternate function remapping option 3

0: TBD

1: TBD

AFR2 Alternate function remapping option 2

0: TBD

1: TBD

AFR1 Alternate function remapping option 1

0: TBD

1: TBD

AFR0 Alternate function remapping option 0

0: TBD

1: TBD

34/56

STM8S103xx, STM8S105xx

Electrical characteristics

7

Electrical characteristics

7.1

Parameter conditions

Unless otherwise specified, all voltages are referred to V

.

SS

7.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100 % of the devices with an ambient temperature at T = 25 °C and T = T (given by

A

Amax

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3 Σ).

7.1.2

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 5.0 V. They are

A

DD

given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean 2 Σ).

7.1.3

7.1.4

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

Figure 10. Pin loading conditions

STM8 PIN

50pF

35/56

Electrical characteristics

STM8S103xx, STM8S105xx

7.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

Figure 11. Pin input voltage

STM8 PIN

V

IN

7.2

Absolute maximum ratings

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 10. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

(1)

V_DDx- V_SS

-0.3

6.5

Supply voltage (including V_{DDA and}V_DDIO

)

Input voltage on true open drain pins (PE1, PE2)⁽²⁾

V_SS- 0.3

V

6.5

V_DD+ 0.3

50

V_IN

Input voltage on any other pin⁽²⁾

|V_DDx- V_SS

|

Variations between different power pins

|

Variations between all the different ground pins

mV

|V_SSx- V_SS

50

1. All power (V_DD, V_DDIO, V_DDA) and ground (V_SS, V_SSIO, V_SSA) pins must always be connected to the

external power supply

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS. For true open-drain pads,

there is no positive injection current, and the corresponding V_INmaximum must always be respected

36/56

STM8S103xx, STM8S105xx

Electrical characteristics

Table 11. Current characteristics

Symbol

I_VDD

Ratings

Max.

60

Unit

Total current into V_DDpower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

I_VSS

60

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on NRST pin

20

- 20

4

I_IO

mA

(2)(3)

Injected current on OSCIN pin

4

I_INJ(PIN)

Injected current on any other pin⁽⁴⁾

4

(2)

Total injected current (sum of all I/O and control pins)⁽⁴⁾

20

ΣI_INJ(PIN)

1. All power (V_DD, V_DDIO, V_DDA) and ground (V_SS, V_SSIO, V_SSA) pins must always be connected to the

external supply.

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS. For true open-drain pads,

there is no positive injection current, and the corresponding V_INmaximum must always be respected

3. Negative injection disturbs the analog performance of the device.

4. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterization with ΣI_INJ(PIN)maximum current injection on four I/O port pins of the device.

Table 12. Thermal characteristics

Symbol

T_STG

T_J

Ratings

Value

-65 to +150

150

Unit

Storage temperature range

Maximum junction temperature

°C

37/56

Electrical characteristics

STM8S103xx, STM8S105xx

7.3

Operating conditions

(1)

Table 13. General operating conditions

Symbol

f_CPU

Parameter

Conditions

Min

0

Max

Unit

MHz

V

Internal CPU clock frequency

Standard operating voltage

16

V_DD/V_{DD_IO}

3.0

5.5

TBD

85

LQFP48

LQFP44

LQFP32

Power dissipation at

T_A= 85° C for suffix 6

or T_A= 125° C for suffix 3

P_D

mW

VFQFN32

TSSOP20

Maximum power dissipation

Low power dissipation⁽²⁾

Maximum power dissipation

Low power dissipation ⁽²⁾

6 suffix version

-40

°C

Ambient temperature for 6

suffix version

105

125

TBD

105

TBD

T_A

Ambient temperature for 3

suffix version

T_J

Junction temperature range

3 suffix version

1. TBD = to be determined.

2. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax

Figure 12. f

versus V

CPUmax

DD

f_CPU[MHz]

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

16

12

8

FUNCTIONALITY

GUARANTEED

@ T_A-40 to 125 °C

4

0

3.0

4.0

5.0

5.5

SUPPLY VOLTAGE [V]

38/56

STM8S103xx, STM8S105xx

Electrical characteristics

7.3.1

I/O port pin characteristics

General characteristics

Subject to general operating conditions for V and T unless otherwise specified. All

DD

A

unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

(1)

Table 14. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input low level

voltage

V_IL

-0.3 V

TBD

V

Input high level

voltage

V_DD= 5.0 V

V_IH

0.7 x V_DD

V_DD+ 0.3 V

V

V_hys

R_pu

Hysteresis⁽²⁾

700

45

mV

Pull-up resistor

V_DD= 5 V, V_IN=V_SS

30

60

kΩ

Fast I/Os

Load = 50 pF

20 ⁽³⁾

ns

Rise and fall time

(10% - 90%)

t_R, t_F

Standard and high sink I/Os

Load = 50 pF

125 ⁽³⁾

Input leakage

current,

analog and digital

I_lkg

^V_SS≤V_IN≤V_DD

1 ⁽³⁾

µA

Analog input

leakage current

I_{lkg ana}

I_lkg(inj)

^V_SS≤V_IN≤V_DD

250 ⁽³⁾

1⁽³⁾

nA

µA

Leakage current in

adjacent I/O⁽³⁾

Injection current 4 mA

1. TBD = to be determined.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

3. Data based on characterization results, not tested in production.

39/56

Electrical characteristics

Figure 13. Typical V and V vs V @ 4 temperatures

STM8S103xx, STM8S105xx

IL

IH

DD

6

5

4

3

2

1

0

-40°C

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 14. Typical pull-up resistance R vs V @ 4 temperatures

PU

DD

60

55

50

45

40

35

30

-40°C

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 15. Typical pull-up current I vs V @ 4 temperatures

pu

DD

140

120

100

80

-40°C

25°C

85°C

125°C

60

40

20

0

1

2

3

4

5

6

V_DD[V]

Note: The pull-up is a pure resistor (slope goes through 0).

40/56

STM8S103xx, STM8S105xx

Electrical characteristics

Table 15. Output driving current (standard ports)

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level with 4 pins sunk

Output low level with 8 pins sunk

I_IO= 4 mA,V_DD= 3.3 V

I_IO= 10 mA,V_DD= 5.0 V

1000⁽¹⁾

2000

V_OL

mV

Output high level with 4 pins sourced I_IO= 4 mA, V_DD= 3.3 V

Output high level with 8 pins sourced I_IO= 10 mA, V_DD= 5.0 V

2.1⁽¹⁾

2.8

V_OH

V

1. Data based on characterization results, not tested in production

Table 16. Output driving current (true open drain ports)

Symbol

Parameter

Conditions

Min

Max

Unit

I_IO= 10 mA, V_DD= 3.3 V

I_IO= 10 mA, V_DD= 5.0 V

I_IO= 20 mA, V_DD= 5.0 V

1500⁽¹⁾

V_OL

Output low level with 2 pins sunk

1000

mV

TBD⁽¹⁾

1. Data based on characterization results, not tested in production

Table 17. Output driving current (high sink ports)

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level with 4 pins sunk

Output low level with 8 pins sunk

Output low level with 4 pins sunk

Output high level with 4 pins sourced

Output high level with 8 pins sourced

Output high level with 4 pins sourced

I_IO= 10 mA,V_DD= 3.3 V

I_IO= 10 mA,V_DD= 5.0 V

I_IO= 20 mA,V_DD= 5.0 V

I_IO= 10 mA, V_DD= 3.3 V

I_IO= 10 mA, V_DD= 5.0 V

I_IO= 20 mA, V_DD= 5.0 V

1000⁽¹⁾

V_OL

800

mV

1500⁽¹⁾

2.1⁽¹⁾

4.0

V_OH

V

3.3⁽¹⁾

1. Data based on characterization results, not tested in production

41/56

Electrical characteristics

STM8S103xx, STM8S105xx

Figure 16. Typ. V @ V = 3.3 V (standard

Figure 17. Typ. V @ V = 5.0 V (standard

OL DD

OL

DD

ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

1.5

1.25

1

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

I

_OL[mA]

I_OL[mA]

Figure 18. Typ. V @ V = 3.3 V (true open Figure 19. Typ. V @ V = 5.0 V (true open

OL

DD

OL

DD

drain ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OL[mA]

Figure 20. Typ. V @ V = 3.3 V (high sink

Figure 21. Typ. V @ V = 5.0 V (high sink

OL DD

OL

DD

ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

1.5

1.25

1

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OL[mA]

42/56

STM8S103xx, STM8S105xx

Electrical characteristics

Figure 22. Typ. V

V

@ V = 3.3 V

Figure 23. Typ. V

V

@ V = 5.0 V

DD - OH

DD

DD - OH DD

(standard ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

I_OH[mA]

Figure 24. Typ. V

V

@ V = 3.3 V (high Figure 25. Typ. V

V

@ V = 5.0 V (high

DD - OH

DD

DD - OH DD

sink ports)

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

2

1.75

1.5

1.25

1

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

0.75

0.5

0.25

0

2

4

6

8

10

12

14

0

5

10

15

20

25

I_OH[mA]

43/56

Electrical characteristics

STM8S103xx, STM8S105xx

7.3.2

Reset pin characteristics

Subject to general operating conditions for V and T unless otherwise specified.

DD

A

(1)

Table 18. NRST pin characteristics

Typ

1)

Symbol

Parameter

Conditions

Min

Max

Unit

NRST Input low level voltage ⁽²⁾

NRST Input high level voltage ⁽²⁾

NRST Output low level voltage ⁽²⁾

NRST Pull-up resistor ⁽³⁾

V_IL(NRST)

V_IH(NRST)

V_OL(NRST)

R_PU(NRST)

V_F(NRST)

V_SS

TBD

V_DD

TBD

V

I_OL=TBD mA

TBD

60

30

40

TBD

kΩ

ns

µs

NRST Input filtered pulse ⁽⁴⁾

NRST Input not filtered pulse ⁽⁴⁾

V_NF(NRST)

1. TBD = to be determined.

2. Data based on characterization results, not tested in production.

3. The R_PUpull-up equivalent resistor is based on a resistive transistor

4. Data guaranteed by design, not tested in production.

Figure 26. Typical NRST V and V vs V @ 4 temperatures

IL

IH

DD

-40°C

6

5

4

3

2

1

0

25°C

85°C

125°C

2.5

3

3.5

4

4.5

5

5.5

6

V

_DD[V]

44/56

STM8S103xx, STM8S105xx

Electrical characteristics

Figure 27. Typical NRST pull-up resistance R vs V @ 4 temperatures

PU

DD

-40°C

25°C

85°C

125°C

60

55

50

45

40

35

30

2.5

3

3.5

4

4.5

5

5.5

6

V_DD[V]

Figure 28. Typical NRST pull-up current I vs V @ 4 temperatures

pu

DD

140

120

100

80

60

-40°C

25°C

85°C

125°C

40

20

0

1

2

3

4

5

6

V_DD[V]

The reset network shown in Figure 29 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below the V max. level specified in

IL

Table 14. Otherwise the reset is not taken into account internally.

Figure 29. Recommended reset pin protection

STM8

V_DD

R_PU

External

reset

circuit

NRST

Internal reset

Filter

0.01µF

45/56

Package characteristics

STM8S103xx, STM8S105xx

8

Package characteristics

®

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These packages have a lead-free second level interconnect. The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label.

®

ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.

46/56

STM8S103xx, STM8S105xx

Package characteristics

8.1

Package mechanical data

8.1.1

LQFP package mechanical data

Figure 30. 48-pin low profile quad flat package (7 x 7)

A

D

A2

D1

A1

b

e

E1

E

c

L1

L

θ

Table 19. 48-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.0630

0.0059

0.0571

0.0106

0.0079

0.05

1.35

0.17

0.09

0.0020

0.0531

0.0067

0.0035

1.40

0.22

0.0551

0.0087

C

D

9.00

7.00

9.00

7.00

0.50

3.5°

0.60

1.00

0.3543

0.2756

0.3543

0.2756

0.0197

3.5°

D1

E

E1

e

q

0°

7°

0°

7°

L

0.45

0.75

0.0177

0.0236

0.0394

0.0295

L1

1. Values in inches are converted from mm and rounded to 4 decimal digits

47/56

Package characteristics

Figure 31. 44-pin low profile quad flat package (10 x 10)

STM8S103xx, STM8S105xx

A

D

A2

D1

A1

b

e

E1

E

c

L1

L

h

Table 20. 44-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.45

0.20

0.0630

0.0059

0.0571

0.0177

0.0079

0.05

1.35

0.30

0.09

0.0020

0.0531

0.0118

0.0035

1.40

0.37

0.0551

0.0146

C

D

12.00

10.00

12.00

10.00

0.80

0.4724

0.3937

0.4724

0.3937

0.0315

3.5°

D1

E

E1

e

q

0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.0177

0.0236

0.0394

0.0295

L1

1.00

1. Values in inches are converted from mm and rounded to 4 decimal digits

48/56

STM8S103xx, STM8S105xx

Figure 32. 32-pin low profile quad flat package (7 x 7)

Package characteristics

D

A

A2

D1

A1

e

b

E1

E

c

L1

L

h

Table 21. 32-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.45

0.20

0.0630

0.0059

0.0571

0.0177

0.0079

0.05

1.35

0.30

0.09

0.0020

0.0531

0.0118

0.0035

1.40

0.37

0.0551

0.0146

C

D

9.00

7.00

9.00

7.00

0.80

3.5°

0.60

1.00

0.3543

0.2756

0.3543

0.2756

0.0315

3.5°

D1

E

E1

e

q

0°

7°

0°

7°

L

0.45

0.75

0.0177

0.0236

0.0394

0.0295

L1

1. Values in inches are converted from mm and rounded to 4 decimal digits

49/56

Package characteristics

STM8S103xx, STM8S105xx

8.1.2

QFN package mechanical data

Figure 33. 32-lead very thin fine pitch quad flat no-lead package (5 x 5)

Seating plane

C

ddd

C

A

A1

A3

D

e

16

9

17

8

b

E

E2

24

1

L

32

Pin # 1 ID

R = 0.30

D2

L

Bottom view

42_ME

Table 22. 32-lead very thin fine pitch quad flat no-lead package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A3

b

0.80

0

0.90

0.02

0.20

0.25

5.00

3.45

5.00

3.45

0.50

0.40

1.00

0.05

0.0315

0.0354

0.0008

0.0079

0.0098

0.1969

0.0394

0.0020

0.18

4.85

3.20

4.85

3.20

0.30

5.15

3.70

5.15

3.70

0.0071

0.1909

0.1260

0.1909

0.1260

0.0118

0.2028

0.1457

0.2028

0.1457

D

D2

E

0.1969

0.1358

0.0197

0.0157

E2

e

L

0.30

0.50

0.08

0.0118

0.0197

0.0031

ddd

1. Values in inches are converted from mm and rounded to 4 decimal digits

1. TBD = to be determined.

50/56

STM8S103xx, STM8S105xx

Package characteristics

8.1.3

TSSOP package mechanical data

Figure 34. TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch

D

20

11

c

E1

E

1

10

α

A1

L

A

A2

L1

CP

b

e

TSSOP20-M

Table 23. TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.2

0.15

1.05

0.3

0.1

0.2

6.6

4.5

-

0.0472

0.0059

0.0413

0.0118

0.0039

0.0079

0.2598

0.1772

-

0.05

0.8

0.002

0.0315

0.0075

1

0.0394

0.19

CP

c

0.09

6.4

6.2

4.3

-

0.0035

0.252

0.2441

0.1693

-

D

6.5

6.4

4.4

0.65

0.6

1

0.2559

0.252

E

E1

e

0.1732

0.0256

0.0236

0.0394

L

0.45

0.75

0.0177

0.0295

L1

a

0°

8°

0°

8°

1. Values in inches are converted from mm and rounded to 4 decimal digits

51/56

Ordering information

STM8S103xx, STM8S105xx

9

Ordering information

Figure 35. STM8S103/105 access line ordering information scheme

Example:

STM8

S

103

F

3

P

6

B

Product class

STM8 microcontroller

Family type

S = Standard

Sub-family type

105 = intermediate peripheral set

103 = small peripheral set

Pin count

F = 20 pins

K = 32 pins

S = 44 pins

C = 48 pins

R = 64 pins

Program memory size

2 = 4 Kbytes

3 = 8 Kbytes

4 = 16 Kbytes

6 = 32 Kbytes

Package type

P = TSSOP

U = VFQFPN

T = LQFP

Temperature range

6 = -40 °C to 85 °C

Package pitch

no character = 0.5 mm

B = 0.65 mm

C = 0.8 mm

Packing

no character = tray or tube

TR = tape and reel

For a list of available options (e.g. memory size, package) and orderable part numbers or for

further information on any aspect of this device, please go to www.st.com or contact the ST Sales

Office nearest to you.

52/56

STM8S103xx, STM8S105xx

STM8 development tools

10

STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation

system supported by a complete software tool package including C compiler, assembler and

integrated development environment with high-level language debugger. In addition, the

STM8 is to be supported by a complete range of tools including starter kits, evaluation

boards and a low-cost in-circuit debugger/programmer.

10.1

Emulation and in-circuit debugging tools

The STM8 tool line includes the full-featured STice emulation system offering a complete

range of emulation and in-circuit debugging features on a platform that is designed for

versatility and cost-effectiveness. In addition, STM8 application development is supported

by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It

offers new advanced debugging capabilities including profiling and coverage to help detect

and eliminate bottlenecks in application execution and dead code when fine tuning an

application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via

the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an

application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to

order exactly what you need to meet your development requirements and to adapt your

emulation system to support existing and future ST microcontrollers.

STice key features

●

Occurrence and time profiling and code coverage (new features)

Advanced breakpoints with up to 4 levels of conditions

Data breakpoints

Program and data trace recording up to 128 K records

Read/write on the fly of memory during emulation

In-circuit debugging/programming via SWIM protocol

8-bit probe analyzer

1 input and 2 output triggers

Power supply follower managing application voltages between 1.62 to 5.5 V

Modularity that allows you to specify the components you need to meet your

development requirements and adapt to future requirements

●

Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8

53/56

STM8 development tools

STM8S103xx, STM8S105xx

10.2

Software tools

STM8 development tools are supported by a complete, free software package from STMi-

croelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer

(STVP) software interface. STVD provides seamless integration of the cosmic C compiler for

STM8, which is available in a free version that outputs up to 16 Kbytes of code.

10.2.1

STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming

software is available for free download at www.st.com/mcu. This package includes:

ST visual develop – Full-featured integrated development environment from ST, featuring

●

Seamless integration of C and ASM toolsets

Full-featured debugger

Project management

Syntax highlighting editor

Integrated programming interface

Support of advanced emulation features for STice such as code profiling and coverage

ST visual programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,

write and verify of your STM8 microcontroller’s Flash memory. STVP also offers project

mode for saving programming configurations and automating programming sequences.

10.2.2

C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated

development environment, making it possible to configure and control the building of your

application directly from an easy-to-use graphical interface.

Available toolchains include:

●

Cosmic C compiler for STM8 – Available in a free version that outputs up to

16 Kbytes of code. For more information, see www.cosmic-software.com.

Raisonance C compiler for STM8 – Available in a free version that outputs up to

16 Kbytes of code. For more information, see www.raisonance.com.

ST7/STM8 assembler linker – Free assembly toolchain included in the ST7/STM8

toolset, which allows you to assemble and link your application source code.

10.3

Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash

microcontroller on your application board via the SWIM protocol. Additional tools are to

include a low-cost in-circuit programmer as well as ST socket boards, which provide

dedicated programming platforms with sockets for programming your STM8.

For production environments, programmers will include a complete range of gang and

automated programming solutions from third-party tool developers already supplying

programmers for the STM8 family.

54/56

STM8S103xx, STM8S105xx

Revision history

11

Revision history

Table 24. Document revision history

Date

Revision

Changes

05-Jun-2008

1

Initial release.

Corrected number of high sink outputs to 9 in I/Os on page 1.

23-Jun-2008

2

Updated part numbers in Table 2: STM8S103/105 access line

features on page 7.

55/56

STM8S103xx, STM8S105xx

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56/56


型号：	STM8S103XX
厂家：	ST
描述：	Access line, STM8S 8-bit MCU, up to 32 Kbytes Flash, 10-bit ADC, timers, USART, SPI, IC 接入线路， STM8S系列8位MCU ，最多32 KB闪存， 10位ADC ，定时器， USART ， SPI ， IC 闪存
文件：	总56页 (文件大小：1071K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM8S103XX [STMICROELECTRONICS]

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