STP1N120 [STMICROELECTRONICS]

channel 1200V - 30ヘ - 500mA - TO-220 Zener - protected SuperMESH⑩ Power MOSFET; 通道1200V - 30ヘ - 500毫安 - TO- 220齐纳 - 保护SuperMESH⑩功率MOSFET
STP1N120
型号: STP1N120
厂家: ST    ST
描述:

channel 1200V - 30ヘ - 500mA - TO-220 Zener - protected SuperMESH⑩ Power MOSFET
通道1200V - 30ヘ - 500毫安 - TO- 220齐纳 - 保护SuperMESH⑩功率MOSFET

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STP1N120  
N-channel 1200V - 30- 500mA - TO-220  
Zener - protected SuperMESH™ Power MOSFET  
PRELIMINARY DATA  
General features  
Type  
VDSS  
RDS(on)  
ID  
PW  
STP1N120  
1200V  
< 38500mA  
45W  
100% avalanche tested  
Extremely high dv/dt capability  
ESD improved capability  
New high voltage benchmark  
Gate charge minimized  
3
2
1
TO-220  
Description  
The SuperMESH™ series is obtained through an  
extreme optimization of ST’s well established  
strip-based PowerMESH™ layout. In addition to  
pushing on-resistance significantly down, special  
care is taken to ensure a very good dv/dt  
capability for the most demanding applications.  
Such series complements ST full range of high  
voltage Power MOSFETs including revolutionary  
MDmesh™ products.  
Internal schematic diagram  
Applications  
Switching application  
Order codes  
Part number  
Marking  
Package  
Packaging  
STP1N120  
P1N120  
TO-220  
Tube  
September 2006  
Rev 1  
1/10  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
10  
Contents  
STP1N120  
Contents  
1
2
3
4
5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
2/10  
STP1N120  
Electrical ratings  
1
Electrical ratings  
Table 1.  
Absolute maximum ratings  
Symbol  
Parameter  
Value  
1200  
30  
Unit  
V
VDS  
VGS  
ID  
Drain-source voltage (VGS=0)  
Gate-source voltage  
V
Drain current (continuous) at TC = 25°C  
Drain current (continuous) at TC = 100°C  
500  
mA  
mA  
ID  
315  
(1)  
Drain current (pulsed)  
2
A
IDM  
Derating factor  
0.36  
45  
W/°C  
W
PTOT  
Total dissipation at TC = 25°C  
dv/dt (2)  
Peak diode recovery voltage slope  
Tbd  
V/ns  
Tj  
Operating junction temperature  
Storage temperature  
-55 to 150  
°C  
Tstg  
1. Pulse width limited by safe operating area  
2. ISD 1A, di/dt 200A/µs, VDD 960  
Table 2.  
Thermal data  
Symbol  
Parameter  
Value  
2.78  
Unit  
°C/W  
°C/W  
Rthj-case Thermal resistance junction-case max  
Rthj-amb (1)  
Thermal resistance junction-amb max  
62.5  
Maximum lead temperature for soldering  
Tl  
300  
°C  
purpose  
1. When mounted on 1inch² FR-4 board, 2 oz Cu  
Table 3.  
Symbol  
Avalanche characteristics  
Parameter  
Max value  
Unit  
Avalanche current, repetitive or not-  
repetitive (pulse width limited by Tj max)  
IAS  
Tbd  
A
Single pulse avalanche energy  
EAS  
Tbd  
mJ  
(starting Tj=25°C, ID=IAS, VDD= 50V)  
3/10  
Electrical characteristics  
STP1N120  
2
Electrical characteristics  
(T  
=25°C unless otherwise specified)  
CASE  
Table 4.  
On/off states  
Parameter  
Symbol  
Test conditions  
ID = 1mA, VGS= 0  
Min. Typ. Max. Unit  
Drain-source breakdown  
voltage  
V(BR)DSS  
1200  
V
V
DS = Max rating,  
DS = Max rating,Tc=125°C  
1
µA  
µA  
Zero gate voltage drain  
current (VGS = 0)  
IDSS  
V
50  
Gate body leakage current  
(VDS = 0)  
IGSS  
VGS = 20V  
10  
µA  
VGS(th)  
RDS(on)  
VDS= VGS, ID = 50µA  
VGS= 10V, ID= 0.25A  
Gate threshold voltage  
3
3.75  
30  
4.5  
38  
V
Static drain-source on  
resistance  
Table 5.  
Dynamic  
Symbol  
Parameter  
Test conditions  
VDS =25V, f=1MHz, VGS=0  
VDD=960V, ID = 500mA  
Min. Typ. Max. Unit  
Input capacitance  
Ciss  
Coss  
Crss  
130  
22  
3
pF  
pF  
pF  
Output capacitance  
Reverse transfer  
capacitance  
Qg  
Qgs  
Qgd  
Total gate charge  
Gate-source charge  
Gate-drain charge  
7
nC  
nC  
nC  
VGS =10V  
Tbd  
Tbd  
(see Figure 2)  
4/10  
STP1N120  
Electrical characteristics  
Table 6.  
Switching times  
Symbol  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
td(on)  
tr  
td(off)  
tf  
Turn-on delay time  
Rise time  
Tbd  
Tbd  
Tbd  
Tbd  
ns  
ns  
ns  
ns  
Tbd  
Turn-off delay time  
Fall time  
Table 7.  
Source drain diode  
Symbol  
Parameter  
Test conditions  
Min Typ. Max Unit  
ISD  
Source-drain current  
500  
2
mA  
A
ISDM  
Source-drain current (pulsed)  
(1)  
ISD=1A, VGS=0  
Forward on voltage  
Tbd  
V
VSD  
trr  
ISD=1A, VDD=100V  
Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
Tbd  
Tbd  
Tbd  
ns  
nC  
A
Qrr  
di/dt = 50A/µs,Tj=25°C  
IRRM  
(see Figure 6)  
trr  
ISD=1A,VDD=100V  
Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
Tbd  
Tbd  
Tbd  
ns  
nC  
A
Qrr  
di/dt=50A/µs,Tj=150°C  
IRRM  
(see Figure 6)  
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%  
Table 8.  
Gate-source zener diode  
Symbol  
Parameter  
Test conditions  
Min Typ. Max Unit  
30  
(1)  
Gate-source breakdown voltage Igs 1mA, (open drain)  
V
BVGSO  
1. The built-in-back zener diodes have specifically been designed to enhance not only the device’s ESD  
capability, but also to make them safely absorb possibile voltage transients that may occasionally be  
applied from gate to source. In this respect the zener voltage is appropriate to achieve an efficient and ost-  
effective intervention to protect the device’s integrity. These integrated zener diodes thus avoid the usage  
of external components.  
5/10  
Test circuit  
STP1N120  
3
Test circuit  
Figure 1. Switching times test circuit for  
resistive load  
Figure 2. Gate charge test circuit  
Figure 3. Test circuit for inductive load  
switching and diode recovery times  
Figure 4. Unclamped inductive load test  
circuit  
Figure 5. Unclamped inductive waveform  
Figure 6. Switching time waveform  
6/10  
STP1N120  
Package mechanical data  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. These packages have a Lead-free second level interconnect . The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering  
conditions are also marked on the inner box label. ECOPACK is an ST trademark.  
ECOPACK specifications are available at: www.st.com  
7/10  
Package mechanical data  
STP1N120  
TO-220 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
4.40  
0.61  
1.15  
0.49  
15.25  
10  
TYP  
MAX.  
4.60  
0.88  
1.70  
0.70  
15.75  
10.40  
2.70  
5.15  
1.32  
6.60  
2.72  
14  
MIN.  
0.173  
0.024  
0.045  
0.019  
0.60  
MAX.  
A
b
0.181  
0.034  
0.066  
0.027  
0.620  
0.409  
0.106  
0.202  
0.052  
0.256  
0.107  
0.551  
0.154  
b1  
c
D
E
0.393  
0.094  
0.194  
0.048  
0.244  
0.094  
0.511  
0.137  
e
2.40  
4.95  
1.23  
6.20  
2.40  
13  
e1  
F
H1  
J1  
L
L1  
L20  
L30  
øP  
Q
3.50  
3.93  
16.40  
28.90  
0.645  
1.137  
3.75  
2.65  
3.85  
2.95  
0.147  
0.104  
0.151  
0.116  
8/10  
STP1N120  
Revision history  
5
Revision history  
Table 9.  
Date  
14-Sep-2006  
Revision history  
Revision  
Changes  
1
First release  
9/10  
STP1N120  
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10/10  

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