STS17NH3LL [STMICROELECTRONICS]
N-channel 30V - 0.004OHM - 17A - SO-8 STripFET Power MOSFET for DC-DC conversion; N沟道30V - 0.004ohm - 17A - SO-8的STripFET功率MOSFET用于DC-DC转换型号: | STS17NH3LL |
厂家: | ST |
描述: | N-channel 30V - 0.004OHM - 17A - SO-8 STripFET Power MOSFET for DC-DC conversion |
文件: | 总9页 (文件大小:191K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STS17NH3LL
N-channel 30V - 0.004Ω - 17A - SO-8
STripFET™ Power MOSFET for DC-DC conversion
TARGET SPECIFICATION
General features
Type
VDSS
RDS(on)
ID
STS17NH3LL
30V
<0.0057Ω
17A(1)
1. This value is rated according to Rthj-pcb
■ Optimal R
x Qg trade-off @ 4.5 V
DS(on)
■ Conduction losses reduced
SO-8
■ Improved junction-case thermal resistance
■ Low threshold device
Description
This device utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology.
This process coupled to unique metallization
techniques realizes the most advanced low
voltage Power MOSFET in SO-8 ever produced.
Internal schematic diagram
Applications
■ Switching application
Order codes
Part number
Marking
Package
Packaging
STS17NH3LL
S17NH3LL
SO-8
Tape & reel
August 2006
Rev 1
1/9
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
www.st.com
9
Electrical ratings
STS17NH3LL
1
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
VGS
Drain-source voltage (VGS = 0)
Gate- source voltage
30
16
V
V
(1)
ID
Drain current (continuous) at TC = 25°C
Drain current (continuous) at TC = 100°C
Drain current (pulsed)
17
A
ID
10.6
68
A
(2)
IDM
A
(1)
Ptot
Total dissipation at TC = 25°C
Storage temperature
2.7
W
Tstg
Tj
-55 to 150
°C
Operating junction temperature
1. This value is rated according to Rthj-pcb
2. Pulse width limited by safe operating area
Table 2.
Thermal resistance
Symbol
Parameter
Value
Unit
Rthj-pcb(1) Thermal resistance junction-ambient Max
1. When mounted on 1inch² FR-4 board, 2oz of Cu and t< 10sec
47
°C/W
2/9
STS17NH3LL
Electrical characteristics
2
Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 3.
On/off states
Parameter
Symbol
Test conditions
Min
Typ.
Max Unit
Drain-source
V(BR)DSS
ID = 250 µA, VGS = 0
30
V
breakdown voltage
VDS = Max rating
1
IDSS
Zero gate voltage
drain current (VGS = 0)
µA
µA
VDS = Max rating @125°C
10
Gate-body leakage
current (VDS = 0)
IGSS
VGS
=
16V
100
nA
V
VGS(th) Gate threshold voltage
VDS = VGS, ID = 250µA
1
VGS = 10V, ID = 8.5A
VGS = 4.5V, ID = 8.5A
0.004 0.0057
0.005 0.0075
Ω
Ω
Static drain-source on
resistance
RDS(on)
Table 4.
Dynamic
Parameter
Symbol
Test conditions
Min
Typ.
Max
Unit
Input capacitance
Output capacitance
Reverse transfer
capacitance
1810
565
41
Ciss
Coss
Crss
pF
pF
pF
VDS=25V, f=1MHz, VGS
0
=
18
4.8
5.3
24
3
VDD=15V, ID=17A
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
nC
nC
nC
VGS=4.5V
(see Figure 2)
f=1 MHz Gate DC Bias = 0
Test signal level = 20mV
open drain
RG
Gate input resistance
0.5
1.5
Ω
3/9
Electrical characteristics
STS17NH3LL
Table 5.
Switching times
Parameter
Symbol
Test conditions
Min Typ. Max Unit
V
DD = 15V, ID = 8.5A
8
ns
ns
td(on)
tr
Turn-on delay time
Rise time
RG = 4.7Ω , VGS = 10V
(see Figure 1)
65
V
DD = 15V, ID = 8.5A
38
20
ns
ns
td(off)
tf
Turn-off delay time
Fall time
RG = 4.7Ω , VGS = 10V
(see Figure 1)
Table 6.
Source drain diode
Symbol
Parameter
Test conditions
Min Typ. Max Unit
17
68
A
A
ISD
ISDM
Source-drain current
Source-drain current (pulsed)
(1)
VSD
Forward on voltage
ISD = 17A, VGS = 0
1.3
V
22
32
ns
nC
A
ISD = 17A, di/dt = 100A/µs
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
VDD = 15V, Tj = 25°C
(see Figure 6)
1.9
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
4/9
STS17NH3LL
Test circuit
3
Test circuit
Figure 1. Switching times test circuit for
resistive load
Figure 2. Gate charge test circuit
Figure 3. Test circuit for inductive load
switching and diode recovery times
Figure 4. Unclamped inductive load test
circuit
Figure 5. Unclamped inductive waveform
Figure 6. Switching time waveform
5/9
Package mechanical data
STS17NH3LL
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
6/9
STS17NH3LL
Package mechanical data
SO-8 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
1.75
0.25
1.65
0.85
0.48
0.25
0.5
MIN.
TYP.
MAX.
0.068
0.009
0.064
0.033
0.018
0.010
0.019
A
a1
a2
a3
b
0.1
0.003
0.65
0.35
0.19
0.25
0.025
0.013
0.007
0.010
b1
C
c1
D
45 (typ.)
4.8
5.8
5.0
6.2
0.188
0.228
0.196
0.244
E
1.27
3.81
e
0.050
0.150
e3
F
3.8
0.4
4.0
1.27
0.6
0.14
0.157
0.050
0.023
L
0.015
M
S
8 (max.)
7/9
Revision history
STS17NH3LL
5
Revision history
Table 7.
Date
01-Aug-2006
Revision history
Revision
Changes
1
First release
8/9
STS17NH3LL
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9/9
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