STV0056A_技术文档

STV0056A

SATELLITE SOUND AND VIDEO PROCESSOR

ADVANCE DATA

SOUND

.

TWO INDEPENDENT SOUND DEMODULA-

TORS

PLL DEMODULATION WITH 5-10MHz FRE-

QUENCY SYNTHESIS

PROGRAMMABLE FM DEMODULATOR

BANDWIDTH ACCOMODATING FM DEVIA-

TIONS FROM ±30kHz TILL ±400kHz

PROGRAMMABLE 50/75µs, J17 OR NO DE-

EMPHASIS

WEGENER PANDA SYSTEM

TWO AUXILIARY AUDIO INPUTS AND OUT-

PUTS

GAIN CONTROLLED AND MUTEABLE

AUDIO OUTPUTS

HIGH IMPEDANCE MODE AUDIO OUTPUTS

FOR TWIN TUNER APPLICATIONS

.

SHRINK56

(Plastic Package)

.

ORDER CODE : STV0056A

.

PIN CONNECTIONS

.

FC R

1

A GND R

FC L

56

55

54

53

52

51

PK IN R

LEVEL R

2

PK IN L

LEVEL L

PK OUT L

PK OUT R

I_REF

3

S1 VID RTN

S3 VID RTN

VOL R

4

VIDEO

5

.

COMPOSITE VIDEO 6-bit 0 to 12.7dB GAIN

CONTROL

COMPOSITE VIDEO SELECTABLE IN-

VERTER

TWO SELECTABLE VIDEO DE-EMPHASIS

NETWORKS

6

S3 VID OUT

S1 VID OUT

S2 VID OUT

VOL L

7

50

49

48

47

46

45

.

CPUMP R

U75 R

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DET R

AMPLK R

A 12V

S2 VID RTN

S2 OUT L

CLAMP IN

S2 OUT R

UNCLDEEM

VIDEEM2/22kHz

V 12V

.

6 x 3 VIDEO MATRIX

BLACK LEVEL ADJUSTABLE OUTPUT FOR

ON-BOARD VIDEOCRYPT DECODER

HIGH IMPEDANCE MODE VIDEO OUTPUTS

FOR TWIN TUNER APPLICATIONS

V_REF

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

A GND L

AGC R

AMPLK L

U75 L

.

MISCELLANEOUS

.

22kHz TONE GENERATION FOR LNB CON-

VIDEEM1

V GND

DET L

TROL

CPUMP L

GND 5V

V_DD5V

XTL

2

.

I C BUS CONTROL

B-BAND IN

S2 RTN L

S2 RTN R

FM IN

CHIP ADDRESSES = 06_HEXOR 46_HEX

LOW POWER STAND-BY MODE WITH AC-

TIVE AUDIO AND VIDEO MATRIXES

J17 L

S3 RTN L

S3 RTN R

AGC L

J17 R

DESCRIPTION

HA

SDA

The STV0056ABICMOS integrated circuit realizes

all the necessary signal processing from the tuner

to the Audio/Video input and output connectors

regardless the satellite system.

S3 OUT L

S3 OUT R

SCL

I/O/22kHz

1/26

September 1996

This is advance informationon a new product now in development or undergoingevaluation. Detailsare subject to change without notice.

STV0056A

PIN ASSIGNMENT

Pin Number

Name

FC R

Function

1

Audio Roll-off Right

2

PK IN R

LEVEL R

S1 VID RTN

S3 VID RTN

VOL R

Noise Reduction Peak Detector Input Right

Noise Reduction Level Right

TV-Scart 1 Video Return

3

4

5

Decoder-Scart Video Return

Volume Controlled Audio Out Right

Decoder-Scart Video Output

TV-Scart 1 Video Output

6

7

S3 VID OUT

S1 VID OUT

S2 VID OUT

VOL L

8

9

VCR-Scart 2 Video Output

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

Volume Controlled Audio Out Left

VCR-Scart 2 Video Return

S2 VID RTN

S2 OUT L

CLAMP IN

S2 OUT R

UNCL DEEM

VIDEEM2/22kHz

V 12V

Fixed Level Audio Output Left (to VCR)

Sync-Tip Clamp Input

Fixed Level Audio Output Right (to VCR)

Unclamped Deemphasized Video Output

Video Deemphasis 2 or 22kHz Output

Video 12V Supply

VIDEEM1

V GND

Video Deemphasis 1

Video Ground

B-BAND IN

S2 RTN L

S2 RTN R

FM IN

Base Band Input

Auxiliary Audio Return Left (from VCR)

Auxiliary Audio Return Right (from VCR)

FM Demodulator Input

S3 RTN L

S3 RTN R

AGC L

Auxiliary Audio Return Left (from decoder)

Auxiliary Audio Return Right (from decoder)

AGC Peak Detector Capacitor Left

Auxiliary Audio Output L (to decoder)

Auxiliary Audio Output R (to decoder)

Digital Input/Output or 22kHz Output

I²C Bus Clock

S3 OUT L

S3 OUT R

I/O/22kHz

SCL

SDA

I²C Bus Data

HA

Hardware Address

J17 R

J17 Deemphasis Time Constant Right

J17 Deemphasis Time Constant Left

4/8MHz Quartz Crystal or Clock Input

Digital 5V Power Supply

J17 L

XTL

V_DD5V

GND 5V

CPUMP L

DET L

Digital Power Ground

FM PLL Charge Pump Capacitor Left

FM PLL Filter Left

U75 L

Deemphasis Time Constant Left

Amplitude Detector Capacitor Left

AGC Peak Detector Capacitor Right

Audio Ground

AMPLK L

AGC R

A GND L

V_REF

2.4V Reference

2/26

STV0056A

PIN ASSIGNMENT (continued)

Pin Number

Name

A 12V

Function

45

46

47

48

49

50

51

52

53

54

55

56

Audio 12V Supply

AMPLK R

DET R

Amplitude Detector Capacitor Left

FM PLL Filter Right

U75 R

Deemphasis Time Constant Right

FM PLL Charge Pump Capacitor Right

Current Reference Resistor

CPUMP R

I_REF

PK OUT R

PK OUT L

LEVEL L

PK IN L

FC L

Noise Reduction Peak Detector Output Right

Noise Reduction Peak Detector Output Left

Noise Reduction Level Left

Noise Reduction Peak Detector Input

Audio Roll-off Left

A GND R

Audio Ground

PIN DESCRIPTION

SOUND DETECTION

FMIN

DET L, DET R

Respectively the outputs of the FM phasedetector

left and right.

This is for the connection of an external loop filter

for the PLL. The output is a push-pull current

source.

This is the input to the two FM demodulators. It

feeds two AGC amplifiers with a bandwidth of at

least 5-10MHz. There is one amplifier for each

channel both with the same input. The AGC ampli-

fiers have a 0dB to +40dB range.

CPUMP L, CPUMP R

Z_IN= 5kΩ, Min input = 2mV_PPper subcarrier.

Max input = 500mV_PP(max when all inputs are

added together,when their phasescoincide).

The output from the frequency synthesizer is a

push-pullcurrent sourcewhich requiresacapacitor

to ground to derive a voltage to pull the VCO to the

target frequency.The output is ±100µA to achieve

lockand±2µAduring lock toprovidea trackingtime

constant of approximately10Hz.

AGC L, AGC R

AGC amplifiers peak detector capacitor connec-

tions. The output current has an attack/decayratio

of 1:32. That is the ramp up current is approxi-

mately 5µA and decay current is approximately

160µA. 11V gives maximum gain. These pins are

also driven by a circuit monitoring the voltage on

AMPLK L and AMPLK R respectively.

V_REF

This is the audio processor voltage referenceused

through out the FM/audio section of the chip. As

such it is essential that it is well decoupled to

ground to reduce as far as possible the risk of

crosstalk and noise injection. This voltage is de-

rived directly from the bandgap reference of 2.4V.

The V_REFoutput can sink up to 500µA in normal

operation and 100µAwhen in stand-by.

AMPLK L, AMPLK R

The outputs of amplitude detectors LEFT and

RIGHT. Each requires a capacitor and a resistor to

GND. The voltage across this is used to decide

whether there is a signal being received by the FM

detector. The level detector output drives a bit in

the detectorI²C bus control block.

I_REF

This is a buffered V_REFoutputto an off-chip resistor

to produce an accurate current reference, within

the chip, for the biasing of amplifiers with current

outputs into filters. It is also required for the Noise

reduction circuit to provide accurate roll-off fre-

quencies. This pin should not be decoupledas it

would inject current noise. The target current is

50µA ±2% thus a 47.5kΩ ±1% is required.

AMPLK L and AMPLK R drive also respectively

AGC L and AGC R. For instance when the voltage

on AMPLKL is > (V_REF+ 1 V_BE) it sinks current to

V_REFfrom pin AGCL to reduce the AGC gain.

3/26

STV0056A

PIN DESCRIPTION (continued)

A 12V

serieswith a capacitoris connectedto groundfrom

these two pins.

Double bonded main power pin for the audio/FM

section of the chip. The two bond connectionsare

to the ESD and to power the circuit and on chip

regulators/references.

J17 L, J17 R

The external J17 de-emphasisnetworks for chan-

nels left and right. The amplifier for this filter is

voltage input, current output. Output with ±500mV

input will be ±55µA.

To performJ17 de-emphasiswith the STV0042,an

external circuit is required.

A GND L

This ground pin is double bonded :

1) to channelLEFT : RF section & VCO,

2) to both AGC amplifiers, channel LEFT and

RIGHT audio filter section.

U75 L, U75 R

External deemphasis networks for channels left

and right. Foreachchannelacapacitorand resistor

in parallel of 75µs time constant are connected

betweenhere andV_REFto provide75µs de-empha-

sis. Internallyselectable is an internal resistor that

can be programmed tobe added in parallel thereby

converting the network to approx 50µs de-empha-

sis (see control block map). The value of the inter-

nal resistors is 54kΩ ±30 %. The amplifier for this

filter is voltage input, current output ; with ±500mV

input the output will be ±55µA.

A GND R

This ground pin is double bonded :

1) to the volume control, noise reduction system,

ESD + Mux + V_REF

2) to channel right : RF section & VCO

BASEBAND AUDIO PROCESSING

PK OUT L, PK OUT R, PK OUT

The noise reduction control loop peak detector

output requires a capacitorto ground from this pin,

and a resistor to V_REFpin to give some accurate

decaytimeconstant.Anonchip5kΩ ±25 %resistor

and external capacitor give the attack time.

VOL L, VOL R

The main audio output from the volume control

amplifier the signal to get output signals as high as

2V_RMS(+12dB) on a DC bias of 4.8V. Control is

from +12dB to -26.75dB plus Mute with 1.25dB

steps.This amplifier hasshortcircuitprotectionand

is intendedto drive a SCARTconnector directlyvia

AC coupling and meets the standardSCART drive

requirements. These outputs feature high imped-

ance mode for parallel connection.

PK IN L, PK IN R or PK IN

Each ofthesepinsis an inputto acontrollooppeak

detector and is connected to the output of the

offchip control loop bandpass filter.

LEVEL L, LEVEL R

Respectively the audio left and right signals of the

FM demodulatorsare output to level L and level R

pins through an input follower buffer. The off-chip

filters driven by these pins must include AC cou-

pling to the next stage (PK IN L and PK IN R pins

respectively).

S2 OUT L, S2 OUT R, S3 OUT L, S3 OUT R

These audio outputs are sourced directly from the

audio MUX, and as a result do not include any

volume control function. They will output a 1V_RMS

signal biased at 4.8V. They are short circuit pro-

tected. These outputs feature high impedance

mode for parallel connection and meet SCART

drive requirement.

FC L, FC R

The variable bandwidth transconductance ampli-

fier hasa current output which is variable depend-

ing on the input signal amplitude as defined by the

control loop of the noise reduction. The output

current is then dumped into an off-chip capacitor

which togetherwith the accurate current reference

define the min/max rolloff frequencies. Aresistor in

S2 RTN L, S2 RTN R, S3 RTN L, S3 RTN R

These pins allow auxiliary audio signals to be con-

nected to the audio processor and hence makes

use of the on-chip volume control. For additional

details please refer to the audio switching table.

4/26

STV0056A

PIN DESCRIPTION (continued)

VIDEO PROCESSING

B-BAND IN

a 150Ω load. The average DC voltage to be 1.5V

on the O/P. The signal is video 2.0V_PP5.5MHz BW

with sync tip = 1.2V. These pins get signals from

the Video Matrix. The signal selected from the

Video Matrix for output on this pin is controlled by

a control register. This output also feature a high

impedance mode for parallel connection.

AC-coupled video input from a tuner.

Z_IN> 10kΩ ±25%. This drives an on-chip video

amplifier. The other input of this amp is AC

grounded by being connected to an internal V_REF

.

The video amplifier has selectable gain from 0dB

to 12.7dB in 63 steps and its output signal can be

selected normal or inverted.

S3 VID OUT

This output can drive for instance a decoder.Also

it is able to pass 10MHz ; Z_OUT< 75Ω. Video on

this pin will be 2V_PP. The black level of the ouput

video signal can be adjusted through I²C bus con-

trol to easily interface with on-board Videocrypt

decoder. This output feature an high impedance

mode for parallelconnection.

UNCL DEEM

Deemphasizedstill unclamped output. It is also an

input of the video matrix.

VIDEEM1

Connected to an external de-emphasis network

(for instance 625 lines PAL de-emphasis).

V 12V

+ 12Vdouble bonded: ESD+guardrings and video

circuit power.

VIDEEM2 / 22kHz

Connected to an external de-emphasis network

(for instance525 lines NTSC orother video de-em-

phasis). Alternativelya precise 22kHz tone may be

output by I²C bus control.

V GND

Doubled bonded.Clean VID IN GND. Strategically

placed video power ground connection to reduce

video currents getting into the rest of the circuit.

CLAMP IN

This pin clamps the most negative extreme of the

input (the sync tips) to 2.7V_DC(or appropriate volt-

age). The video at the clamp input is only 1V_PP.

This clamped video which is de-emphasised, fil-

tered and clamped (energy dispersal removed) is

normal, negative syncs, video. This signal drives

the VideoMatrix input called Normal Video.

It has a weak (1.0µA ±15 %) stable current source

pulling the inputtowards GND. Otherwise the input

impedance is very high at DC to 1kHz Z_IN> 2MΩ.

Video bandwidth through this is -1dB at 5.5MHz.

The CLAMPinput DC restore voltage is then used

as a means for getting the correct DC voltage on

the SCART outputs.

CONTROL BLOCK

GND 5V

The main power ground connection for the control

logic, registers, the I²C bus interface, synthesizer

& watchdogand XTLOSC.

V

_DD5V

Digital +5V power supply.

SCL

Thisis theI²C busclockline. Clock= DC to 100kHz.

Requires external pull up eg. 10kΩ to 5V.

SDA

This is the I²C bus data line. Requires external pull

up eg. 10kΩ to 5V.

S3 VID RTN

This input can be driven for instance by the de-

coder. This input has a DC restoration clamp on its

input. The clamp sink current is 1µA±15% with the

buffer Z_IN> 1MΩ.

I/O / 22kHz

General purpose input output pin or 22kHz output.

XTL

This pin allows forthe on-chiposcillator tobe either

used with a crystal to ground of 4MHz or 8MHz, or

to be driven by an external clock source. The

external source can be either 4MHz or 8MHz. A

programmablebit in the controlblock removesa÷2

block when the 4MHz option is selected.

S2 VID RTN, S1 VID RTN

External videoinput1.0V_ppACcoupled75Ω source

impedance. This input has a DC restoration clamp

on its input. The clamp sink current is 1µA ±15%

with the buffer Z_IN> 1MΩ. This signal is an input to

the VideoMatrix.

HA

S1 VID OUT, S2 VID OUT

Video drivers for SCART 1 and SCART 2. An

external emitter follower buffer is required to drive

Hardware address with internal 135µA pull down.

Chip address is 06 when this pin is grouded and

chip address is 46 when connected to V_DD

.

5/26

STV0056A

GENERAL BLOCK DIAGRAM

B-BAND

Video

Processing

2

4

From Tuner

6 x 3

Video

Matrix

3

From TV,

VCR/Decoder

2

To TV, VCR/Decoder

FM

From Tuner

Demodulation

2 Channels

Audio

Matrix

+

Volume

Wegener

Panda +

Deemphasis

I²C Bus

Interface

22kHz to LNB

Active in Stand-by

STV0056A

VIDEO PROCESSING BLOCK DIAGRAM

LPF

NTSC

PAL

UNCL DEEM

15

VIDEEM2/22kHz

16

VIDEEM1

18

29

20

I/O/22kHz

22kHz

TONE

Deemphasized

2

B-BAND IN

CLAMP IN

± 1

G

Baseband

Normal

CLAMP

13

5

Decoder Return

VCR Return

TV Return

CLAMP

S3 VID RTN

11

4

S2 VID RTN

S1 VID RTN

BLACK LEVEL

ADJUST

STV0056A

7

8

9

S3 VID OUT

To Decoder

S2 VID OUT

To VCR

To TV

6/26

STV0056A

AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL RIGHT)

STV0056A

K2

a

b

a

b

K1

c

a

AUDIO

DEEMPHASIS

c

ANRS

4

AUDIO R

MONO

STEREO

K3

b

K4

b

a b

c

a

b c

a

K5

K6

6dB

14

-6dB

22

47

28

25 51

2

3

1

33

48

6

PLL

FILTER

Audio

Decoder Out

Audio

Decoder Return

DECODER

VCR

TV

AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL LEFT)

STV0056A

K2

a

b

a

b

K1

c

a

AUDIO

DEEMPHASIS

c

ANRS

4

AUDIO L

MONO

STEREO

K3

b

K4

b

a

b c

a b

c

a

K5

K6

6dB

27

6dB

12

-6dB

21

39

24 52 54 53 55

32

40

10

PLL

FILTER

Audio

Decoder Out

Audio

Decoder Return

DECODER

VCR

TV

7/26

STV0056A

AUDIO SWITCHING

AUDIO

K_1a

K_5b

K_5c

K_5a

K_6c

K₄: a → ANRS input non-scrambled audio

b → ANRS input descrambled audio

DEEMPHASIS

+ ANRS

K₂

K₃

AUDIO PLL

DEC RTN

AUX IN

K_6a

a

b₁

b₂

c

a

No ANRS, No De-emphasis

No ANRS, 50µs

No ANRS, 75µs

No ANRS, J17

K_1b

a

b₁

b₂

c

b

ANRS, No De-emphasis

ANRS, 50µs

ANRS, 75µs

K_1c

K_6b

ANRS, J17

VOL OUT AUX OUT DEC OUT

FM DEMODULATION BLOCK DIAGRAM

Phase

Detect

DET R

SW1

AGC

FM IN

AGC R

AUDIO R

FM dev.

Select.

LEVEL

DETECTOR 1

Bias

CPUMP R

LEVEL

DETECTOR 2

V_REF

Amp. Detect

AMPLKR

90

VCO

0

SW2

SW4

WATCHDOG

V_REF

Reg8 b4

SYNTHESIZER

AUDIO L

Phase

Detect

DET L

SW3

AGC

FM dev.

Select.

LEVEL

DETECTOR 1

Bias

AGC L

CPUMP L

LEVEL

DETECTOR 2

V_REF

Amp. Detect

AMPLK L

90

VCO

0

WATCHDOG

V_REF

Reg8 b0

STV0042/STV0056A

8/26

STV0056A

CIRCUIT DESCRIPTION

Video Section

a synchronous amplitude detector, which is also

used for the audio input AGC.

In order to maintain constant amplitude of the

recovered audio regardless of variations between

satellites or subcarriers, the PLL loop gain may be

programmed from 56 values.

The compositevideo is first set to a standardlevel

by means of a 64 step gain controlled amplifier. In

the casethatthe modulationisnegative,an inverter

can be switched in.

One of two different external video de-emphasis

networks (for instance PAL and NTSC) is select-

able by an integrated bus controlled switch.

Any frequency deviation can be accomodated

(from ±30kHz till ±400kHz).

Two different networks can be permanently con-

nected for either 75µs or J17 de-emphasis. If 50µs

de-emphasisis required, this can be inserted by an

internal switch, thus allowing a worldwide applica-

tion.

Then energy dispersal is removed by a sync tip

clamping circuit, which is used on all inputs to a

video switching matrix, thus making sure that no

DC steps occur when switching video sources.

The matrix can be used to feed video to and from

decoders, VCR’s and TV’s.

The STV0056A is intended to be compatible with

Wegener Panda System.

A bus controlled black level adjustment circuit is

provided on the decoder output allowing a direct

connection to an on-board Videocrypt decoder.

Two types of audio outputs are provided: one is a

fixed 1V_RMSand the other is a gain controlled

2V_RMSmax. The control range being from +12dB

to -26.75dBwith1.25dBsteps.This outputcanalso

be muted.

Additionaly all the video outputs are tristate type

(high impedance mode is supported), allowing a

simple parallel connections to the scarts (Twin

tuner applications).

A matrix is implemented to feed audio to and from

decoders VCR’s and TV’s.

Noise reduction system and de-emphasis can be

inserted or by-passed through bus control.

Also all the audio outputs are tristate-type (high

impedance mode is supported), allowing a simple

parallelconnectionsto thescarts (Twin tuner appli-

cations).

Audio Section

The two audio channels are totally independent

except for the possibility given to output on both

channelsonly oneofthe selectedinputaudiochan-

nels.

To allow a very cost effective application, each

channel uses PLL demodulation. Neither external

complex filter nor ceramic filters are needed.

Others

A 22kHz tone is generated for LNB control.

The frequency of the demodulated subcarrier is

chosen by a frequencysynthesizer which sets the

frequency of the internal local oscillator by com-

paring its phase with the internally generated

reference. When the frequency is reached, the

microprocessor switches in the PLL and the de-

modulationstarts. Atany momentthemicroproces-

sor can read from the device (watchdog registers)

the actualfrequency to which the PLL is locked. It

can alsoverify thatacarrieris presentatthewanted

frequency (by reading AMPLK status bit) thanksto

It is selectable by bus control and available on one

of the two pins connected to the external video

de-emphasis networks. One general purpose I/O

is also available on the STV0056A.

By means of the I²C bus there is the possibility to

drive the ICs into a low power consumption mode

with active audio and video matrixes. Inde-

pendantly from the main power mode, each indi-

vidual audio and video outputcan be driven to high

impedance mode.

9/26

STV0056A

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V_CC

V_DD

Supply Voltage

15

7.0

V

P_tot

T_oper

T_stg

Total Power Dissipation

900

mW

^oC

Operating Ambient Temperature

Storage Temperature

0, + 70

-55, + 150

THERMAL DATA

Symbol

Parameter

Thermal Resistance Junction-ambient

Value

Unit

^oC/W

Rth(j-a)

Max.

55

DC AND AC ELECTRICAL CHARACTERISTICS

(V_CC= 12V, V_DD= 5V, T_amb= 25^oC unless otherwise specified)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

V_CC

V_DD

Sypply Voltage

Supply Current

11.4

4.75

12

12.6

5.25

V

5.0

IQ_CC

IQ_DD

All audio and all video outputs

activated

55

8

70

15

mA

IQLP_CCSupply Current at Low Power Mode

IQLP_DD

All audio and all video outputs

are in high impedance mode

27

6

35

9

mA

AUDIO DEMODULATOR

FMIN

DETH

FM Subcarrier Input Level

(Pin FMIN for AGC action)

VCO locked on carrier at 6MHz

560kΩ load on AMPLOCK Pins

180kΩ load on DET Pins

5

500 mV_PP

Detector 1 and 2 (AMPLOCK Pins)

(Threshold for activating Level Detector 2) Carrier without modulation

8mV_PP≤ FMIN ≤ 500mV_PP

2.90 3.10 3.30

V

VCOMI VCO Mini Frequency

VCOMA VCO Maxi Frequency

V_CC: 11.4 to 12.6V,

T_amb: 0 to 70^oC

5

MHz

V_PP

10

AP50

1kHz Audio Level at PLL output

(DET Pins)

0.5V_PP50kHz dev. FM input,

Coarse deviation set to 50kHz

0.6

1

1.35

(Reg. 05 = 36_HEX

)

APA50 1kHz Audio Level at PLL output

(DET Pins)

0.5V_PP50kHz dev. FM input,

Coarse and fine settings used

0.92

0

1

1.08

1

V_PP

dB

FMBW FM Demodulator Bandwidth

Gain at 12kHz versus 1kHz

180kΩ, 82kΩ 22pF on DET Pins

0.3

60

DPCO Digital Phase Comparator Output

Current (CPUMP Pins)

Average sink and source

current to external capacitor

µA

AUTOMATIC NOISE REDUCTION SYSTEM

LRS

Output Level (Pins LEVEL)

1V_PPon left and right channel

0.9

4.0

1

1.1

6.8

V_PP

LDOR Level Detector Output Resistance

(Pins PK OUT)

5.4

kΩ

NDFT

Level Detector Fall Time Constant

(Pins PK OUT)

External 22nF to GND and

1.2MΩ to V_REF

26.4

ms

NDLL

LLCF

Bias Level (Pins PK OUT)

No audio in

2.40

0.85

V

Noise Reduction Cut-off Frequency at

Low Level Audio

100mV_PPon DET Pins, External

capacitor 330pF (FC Pins)

kHz

HLCF

Noise Reduction Cut-off Frequency at

High Level Audio

1V_PPon DET Pins, External

capacitor 330pF (FC Pins)

7

kHz

10/26

STV0056A

DC AND AC ELECTRICAL CHARACTERISTICS (continued)

(V_CC= 12V, V_DD= 5V, T_amb= 25^oC unless otherwise specified)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

AUDIO OUTPUT (Pins VOL OUT R, VOL OUT L)

DCOL

AOLN

DC Output Level

4.8

V

Audio Output Level

with Reg 00 = 1A

FM input as for APA50

1.5

2.0

60

1.9 2.34 V_PP

No de-emphasis, No pre-emphasis

No noise reduction

AOL50 Audio Output Level

with Reg 00 = 1A

FM input as for APA50

50µs de-emphasis, 27kΩ//2.7nF load

No pre-emphasis, No noise reduction

3.3

3.2

4.0

V_PP

AOL75 Audio Output Level

with Reg 00 = 1A

FM input as for APA50

75µs de-emphasis, 27kΩ//2.7nF load

No pre-emphasis, No noise reduction

AOL17 Audio Output Level

with Reg 00 = 1A

FM input as for APA50

J17 de-emphasis, 36kΩ 4.7kΩ 8.2nF load

No pre-emphasis, No noise reduction

AMA1

MXAT

Audio Output Attenuation

with Mute-on. Reg 00 = 00.

1V_PP- 1kHz from S2 RTN Pins

65

dB

Max Attenuation before Mute.

Reg 00 = 01.

1kHz, from S2 RTN Pins

32.75

MXAG Audio Gain. Reg 00 = 1F.

1kHz, from S2 RTN Pins

1kHz

5

6

7

dB

ASTP

Attenuation of each of the 31

steps

1.25

THDA1 THD with Reg 00 = 1A

THDA2 THD with Reg 00 = 1A

THDFM THD with Reg 00 = 1A

1V_PP-1kHz from S2 RTN Pins

2V_PP-1kHz from S2 RTN Pins

0.15

0.3

%

1

FM input as for APA50

75µs de-emphasis, ANRS ON

0.3

ACS

Audio Channel Separation

1V_PP-1kHz on S2 RTN Pins

60

74

60

dB

ACSFM Audio Channel Separation at 1kHz - 0.5 V_PP- 50kHz deviation FM input on

one channel

- 0.5V_PPno deviation FM input on the

other channel

- Reg 05 = 36_HEX

- 75µs de-emphasis, no ANRS

SNFM

Signal to Noise Ratio

FM input as for APA50,

75µs de-emphasis,

56

69

dB

no ANRS, Unweighted

SNFMNR Signal to Noise Ratio

FM input as for APA50

75µs de-emphasis,

ANRS ON, Unweighted

Z_OUTL

Z_{OUT H}

Audio Output Impedance

Low impedance mode

High impedance mode

18

44

Ω

kΩ

30

55

AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L, S3 OUT R, S3 OUT L)

DCOLAO DC output level

Aux. input pins open circuit

4.8

2

V

AOLNS Audio Output Level

on S2 and S3

FM input as for APA50

No de-emphasis, No pre-emphasis

No noise reduction

1.55

2.0

-1

2.42 V_PP

AOL50S Audio Output Level

on S2 and S3

FM input as for APA50

50µs de-emphasis, 27kΩ//2.7nF load

No pre-emphasis, No noise reduction

3.4

3.3

4.0

V_PP

AOL75S Audio Output Level

on S2 and S3

FM input as for APA50

75µs de-emphasis, 27kΩ//2.7nF load

No pre-emphasis, No noise reduction

AOL17S Audio Output Level

on S2 and S3

FM input as for APA50

J17 de-emphasis, 36kΩ 4.7kΩ 8.2nF load

No pre-emphasis, No noise reduction

AGAO S2 to S3 Audio Gain

and S3 to S2 Audio Gain

1kHz

0

+1

dB

%

THDA02 THD on S2, Input in S3

2V_PP- 1kHz from Aux input pins

0.04

0.2

11/26

STV0056A

DC AND AC ELECTRICAL CHARACTERISTICS (continued)

(V_CC= 12V, V_DD= 5V, T_amb= 25^oC unless otherwise specified)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L, S3 OUT R, S3 OUT L) (continued)

THDAOFM THD on S2 or S3

FM input as for APA50

75µs de-emphasis, no ANRS

0.3

1

%

Z_{OUT L}

Z_{OUT H}

Audio Output Impedance

Low impedance mode

High impedance mode

60

44

100

55

Ω

kΩ

30

I/O

V_IL

V_IH

Low Level Input

High Level Input

0.8

0.4

V

2.4

3.2

V_OL

V_OH

Low Level Output

High Level Output

I_sink= 2mA

I_source= 2mA

0.2

4.6

V

LNB_T

LNB_D

Tone Frequency

22.2 22.2 22.2 kHz

Tone Signal Duty Cycle

No load connected on I/O

49

50

51

%

RESET

RTCCU

End of Reset Threshold for V_CCV_DD= 5V, V_CCgoing up

Start of Reset Threshold for V_CCV_DD= 5V, V_CCgoing down

End of Reset Threshold for V_DDV_CC= 12V, V_DDgoing up

Start of Reset Threshold for V_DDV_CC= 12V, V_DDgoing down

8.7

7.9

3.8

3.5

V

RTCCD

RTDDU

RTDDD

COMPOSITE SIGNAL PROCESSING

VIDC

ZVI

VID IN

External load current < 1µA

2.25 2.45 2.65

11 14

V

kΩ

V

VID IN Input Impedance

DC Output Level (Pins VIDEEM)

7

DEODC

DEOMX

2.25 2.45 2.65

2

Max AC Level before Clipping

(Pins VIDEEM)

GV = 0dB, Reg 01 = 00

V_PP

DGV

INVG

Gain error vs GV @ 100kHz

Inverter Gain

GV = 0 to 12.7dB, Reg 01 = 00 → 3F

-0.5

-0.9

-1

0

-1

0

0.5

-1.1

1

dB

VISOG

Video Input to SCART Outputs

Gain

De-emphasis amplifier mounted in unity

gain, Normal video selected

dB

MHz

%

DEBW

DFG

Bandwidth for 1V_PPinput

measured on Pins VIDEEM

@ - 3dB with GV = 0dB, Reg 01 = 00

10

Differential Gain on Sync Pulses GV = 0dB, 1V_PPCVBS + 0.5V_PP

measured on Pins VIDEEM

1

25Hz sawtooth (input : VID IN)

ITMOD

Intermodulation of FM subcar-

riers with chroma subcarrier

7.02 and 7.2MHz sub-carriers,

12.2dB lower than chroma

-60

dB

CLAMP STAGES (Pins CLAMP IN, S1, S2, S3 VID RTN)

ISKC

ISCC

Clamp Input Sink Current

V

_IN= 3V

_IN= 2V

0.5

40

1

1.5

60

µA

Clamp Input Source Current

50

VIDEO MATRIX

XTK

BFG

Output Level on any Output

@ 5MHz

-60

2

dB

when 1V_PPCVBS input is

selected for any other output

Output Buffer Gain (Pins S1 VID

OUT, S2 VID OUT, S2 VID OUT)

@ 100kHz

1.87

16

2.13

DCOLVH DC Output Level

High impedance mode

0

0.2

30

V

kΩ

V

Z_{OUT HV}

VCL

Video Output Impedance

High impedance mode

23

Sync Tip Level on Selected

Outputs (Pins S1 VID OUT, S2

VID OUT)

1V_PPCVBS through 10nF on input

1.05 1.3 1.55

VCL S3

Sync Tip Level at S3 VID OUT

with Black Level Adjust

Register 4

b6 b7

0

1

0

1

0

1

1.36

1.52

1.67

1.84

V

12/26

STV0056A

PIN INTERNAL CIRCUITRY

S1 VID RTN, S2 VID RTN, S3 VID RTN,

CLAMP IN

50µA source is active only when VIDIN < 2.7V.

UNCL DEEM

Same as above but with no black level adjustment

and slightly different gain.

Figure 4

Figure 1

V_DD9V

60Ω

50µA

V_CC12V

S1 VID RTN

S2 VID RTN

10kΩ

4

S3 VID RTN

CLAMPIN

UNCL DEEM

V_REF2.4V

1

1µA

2.3mA

IN

10kΩ

25kΩ

1

GND 0V

V

_DD5V

16.7kΩ

GND 0V

S3 VID OUT

I blacklevelisI²C programmablefromsource16µA

to sink 33µA equivalent to an offset voltage of

-150mV to + 300mV.

The 60Ω collector resistor is for short cct. protec-

tion.

VIDEEM1

Ron of the transistor gate is ≈10kΩ.

Figure 5

Figure 2

6µ/2µ

60Ω

V_CC12V

10µ/2µ

VIDEEM1

4

1

S3 VID OUT

125µA

2.3mA

VID MUX

10kΩ

25kΩ

GND 0V

V_REF2.4V

16.7kΩ

I Black Level

VIDEEM2 / 22kHz

Ron of the transistor gate is ≈10kΩ.

GND 0V

Figure 6

S1 VID OUT, S2 VID OUT

Same asabove but with no black level adjustment.

6µ/2µ

10µ/2µ

Figure 3

60Ω

VIDEEM2/22kHz

1

V

_CC12V

125µA

4

S1 VID OUT

S2 VID OUT

V_DD5V

2.3mA

VID MUX

10kΩ

20kΩ

100µ/2µ

60µ/2µ

22kHz

GND 0V

V_REF2.4V

20kΩ

GND 0V

13/26

STV0056A

PIN INTERNAL CIRCUITRY (continued)

VID IN

Figure 7

V_REF2.4V

S2 OUT L, S2 OUT R, S3 OUT L, S3 OUT R

Same as above but with gain fixed at +6dB.

Figure 11

S2 OUT L

S2 OUT R

S3 OUT L

Audio

2.4V Bias

10kΩ

S3 OUT R

VID IN

1

20kΩ

Ω

6.5k

+

0.5pF

85µA

GND 0V

20kΩ

PK OUT R, PK OUT L

Figure 8

GND 0V

S2 RTN L, S2 RTN R, S3 RTN L, S3 RTN R

4.8V bias voltage is the same as the bias level on

the audio outputs.

V_DD9V

Clamp

3.4V

Audio

1

Figure 12

1

5kΩ

Peak Detector

PK OUT R

PK OUT L

25kΩ

4.8V

S2 RTN L

S2 RTN R

S3 RTN L

S3 RTN R

FC L, FC R

1

Ivar is controlled by the peak det audio level max.

±15µA (1V_PPaudio).

50µA

Figure 9

V_DD9V

FM IN

Theotherinputforeachchannelis internallybiased

FC L

FC R

in the same way via 10kΩ to the 2.4V V_REF

.

1

Figure 13

1

10kΩ

2.4V

Left Channel

Ivar

FM IN

10kΩ

1

50µA

VOL OUT R, VOL OUT L

1

Right Channel

Audio output with volume and scart driver with

+12dB of gain for up to 2V_RMS. The opamp has a

push-pull output stage.

50µA

Figure 10

I_REF

Audio

2.4V Bias

VOL OUT R

VOL OUT L

The optimum value if I_REFis 50µA ±2% so an

external resistor of 47.5kΩ ±1% is required.

30kΩ

Figure 14

30kΩ

4.8V

2.4V

15kΩ

1

I_REF

GND 0V

14/26

STV0056A

PIN INTERNAL CIRCUITRY (continued)

I/O / 22kHz

HA

The input is TTL compatible.

The outputis tri-stateable.

Figure 15

Pull-down current for SDIP42.

Input with CMOS levels.

Figure 19

25µ/2µ

10µ/2µ

180µ/2µ

100µ/2µ

10µ/2µ

91µ/2µ

205Ω

I/O/22kHz

205Ω

HA

MUX

IIC Reg

ESD

150µA

22kHz

ESD

GND 0V

SCL

XTL

This is the input to a Schmittinput buffer made with

a CMOS amplifier.

Figure 20

Figure 16

3

460Ω

205Ω

SCL

24µ/4µ

2

XTL

5pF

ESD

GND 0V

750µA

500µA

CPUMP L, CPUMP R

SDA

Input same as above.

Output pull down only : relies on external resistor

for pull-up.

An offset on the PLL loop filter will cause an offset

in the two 1µA currents that will prevent the PLL

from drifting-off frequency.

Figure 21

Figure 17

SDA

100µA

205Ω

24µ/4µ

ESD

CPUMP L

CPUMP R

600µ/2µ

1µA

GND 0V

Dig Synth

Loop Filter Tracking

1µA

J17 L, J17 R, U75 L, U75 R

I1 - I2 = 2 x audio / 18kΩ.

eg 1V_PPaudio : ±55µA.

VCO Input

100µA

The are internal switches to match the audio level

of the different standards.

DET L, DET R

I2 - I1 = f (phaseerror).

Figure 18

Figure 22

I1

J17 L

I2

J17 R

U75 L

U75 R

DET L

DET R

I2

I1

15/26

STV0056A

PIN INTERNAL CIRCUITRY (continued)

AMPLK L, AMPLK R, AGC L, AGC R

V GND

I2 and I1 from the amplitude detectingmixer.

Doubled bonded:

- Onepad is connectedtopower-up allof thevideo

mux and I/O.

- The second pad is only as a low noise GND for

the video input.

Figure 23

To VCA

I2

I1

5µA

AMPLK L

AMPLK R

AGC L

AGC R

V_DD5V, GND 5V

Connected to XTL oscillator and the bulk of the

CMOS logic and 5V ESD.

2

10kΩ

A GND

160µA

Doubled bonded:

V_REF2.4V

- One pad connected to the left VCO, dividers,

mixers and guard ring. the guard connection is

star connected directly to the pad.

- The second pad is connected to both AGC amps

and the deemphasis amplifiers, frequency syn-

thesis and FM deviation selection circuit for both

channels.

V_REF

The 400µA source is off during stand-by mode.

Figure 24

V_REF(2.4V)

Vbg 1.2V

4

10kΩ

A 12V

Doubled bonded:

400µA

- One pad connected to the ESD and guard ring.

- The second pad is connected to the main power

for all of the audio parts.

10kΩ

GND 0V

A GND R

Boubled bonded :

LEVEL L, LEVEL R

Figure 25

- One pad connected to the right VCO, dividers,

mixers and guard ring. The guard connection is

star connected directly to the pad.

- The second pad is connected to the bias block,

audio noise reduction, volume, mux and ESD.

V

_REF2.4V

SW

1

LEVEL R

LEVEL L

A third bond wire on this pin is connected directly

to the die pad (substrate).

Audio

49kΩ

50kΩ

100µA

Figure 27

PK IN L, PK IN R

Figure 26

V 12V

Video Pads

V_REF2.4V

V GND

V_DD5V

1

PK IN R

PK IN L

To Peak Det

100µA

Vpp

BIP 10vpl

Vmm

205Ω

67kΩ

Digital Pads

DZPN1

GND 5V

V 12V

A GND L

A 12V

Doubled bonded (two bond wires and two pads for

one package pin) :

- One pad is connected to all of the 12V ESD and

video guard rings.

- The second pad is connected to power up the

video block.

+

BIP

12V

-

Audio Pads

Substrate

A GND R

16/26

STV0056A

I²C PROTOCOL

1) WRITING to the chip

S-Start Condition

P-Stop Condition

CHIP ADDR - 7 bits. Programmable 06H or 46H (STV0056A only) with Pin HA.

W-Write/Read bit is the 8th bit of the chip address.

A-ACKNOWLEDGE after receiving8 bits of data/adress.

REG ADDR

Address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are ’X’ or

don’t care ie only the first 3 bits are used.

DATA

8 bitsof data being written to the register. All8 bits must be written to atthe same

time.

REG ADDR/A/DATA/A can be repeated, the write process can continue untill terminated with a STOP

condition. If the REG ADDR is higher than 07 then IIC PROTOCOL will still be

met (ie an A generated).

Example :

S

06

W

A

00

A

55

A

01

A

8F

A

P

2) READING from the chip

When reading,there is an auto-incrementfeature. This means anyread command always starts by reading

Reg 8 and will continue to read the following registers in orderafter each acknowledgeor until there is no

acknowledge or a stop. This function is cyclic that is it will read the same set of registers without

re-addressing the chip. There are two modes of operation as set by writing to bit 7 of register 0. Read 3

registers in a cyclic fashion or all 5 registers in a cyclic fashion. Note only the last 5 of the 11 registers can

be read.

Reg0 bit 7 =L

Start / chip add / R / A/ Reg8 / A / Reg 9 / A/ Reg 0A/ A/ Reg 8 / A/ Reg 9 / A / Reg 0A

/... / P /

Reg0 bit 7 =H

Start / chip add / R / A/ Reg 8 / A / Reg 9 / A/ Reg0A / A / Reg 7 / A / Reg 6 / A / Reg 8

/ A/ Reg 9 / A / Reg 0A / A/ Reg 7 / A/ Reg 6 / ... / P /

CONTROL REGISTERS

Reg 0

write only

Bit (default 00_HEX

)

0

1

2

3

4

5

6

7

L

Select 5 bits audio volume control 00H = MUTE

Select 5 bits audio volume control 01H = -26.75dB

Select 5 bits audio volume control : : : :

:

Select 5 bits audio volume control 1.25dB steps up to

Select 5 bits audio volume control 1FH = +12dB

Audio mux switch K4 - ANRS I/P select (L = PLL)

Audio mux switch K3 - ANRS select (L = no ANRS, H = ANRS)

L = read 3 registers, H = read 5 registers

Reg 1

write only

Bit (default 00_HEX

)

0

1

2

3

4

5

6

7

L

Select video gain bits

00H = 0dB

01H = +0.202dB

02H = +0.404dB

n

= + 0.202 dB * n

3FH = + 12.73 dB

Selected video invert (H = inverted, L = non inverted)

Video deemphasis 1 / Video deemphasis2 (L : V_IDDe-em 1)

17/26

STV0056A

CONTROL REGISTERS (continued)

Reg 2

write only

Bit (default F7_HEX

)

0

1

2

3

4

5

6

7

H

L

H

Select video source for scart 1 O/P

Select 4.000MHz or 8.000MHz clock speed (L = 8MHz)

Select audio source for volume output (Switch K1)

Select Left/Right/Stereofor volume output

Reg 3

write only

Bit (default F7_HEX

)

0

1

2

3

4

5

6

7

H

L

H

Select video source for scart 2 O/P

Video deemphais 2 / 22kHz(H : 22kHz)

Select audio source for Scart 2 output (Switch K5)

Audio deemphasisselect (Switch K2)

Reg 4

write only

Bit (default BF_HEX

)

0

1

2

3

4

5

6

7

H

L

Select source for video decoder O/P

Stand-by or low power mode (H = low power)

Select audio source for Scart 3 output (Switch K6)

Black level adjust on Scart 3 video

H

Black level adjust on Scart 3 video

Reg 5

write only

Bit (default B5_HEX

)

0

1

2

3

4

5

6

7

H

L

H

L

H

L

FM deviation selection -- default value for 50kHz modulation

FM deviation selection

FM deviation selection (L = double the FM deviation)

Select 22kHz for I/O (Pin 29 / STV0056A)

Select TP50a (H) or I/O (Pin 29 / STV0056A). TP50a for test only.

H

Reg 6

write/read

Bit (default 86_HEX

)

0

1

2

3

4

5

6

7

L

Status of I/O

H

L

H

Select data direction of I/O1 ( H = output)

Select frequency synthesizer 1 OFF/ON (L = OFF)

Select frequency synthesizer 2 OFF/ON (L = OFF)

Select RF source (L = OFF) to FM det 1

Select RF source (L = OFF) to FM det 2

Select frequency for PLLsynthesizer - LSB (bit 0) of 10-bit value

Select frequency for PLLsynthesizer - bit 1 of 10-bit value

18/26

STV0056A

CONTROL REGISTERS (continued)

Reg 7 write/read

Bit (default AF_HEX

)

0

1

2

3

4

5

6

7

H

L

H

L

Select frequency for PLLsynthesizer - bit 2 of 10-bit value

Select frequency for PLLsynthesizer

Select frequency for PLLsynthesizer - bit 9, MSB (10th bit) of 10-bit value

H

Reg 8

read only

Bit

0

1

Subcarrier detection (DET 1) (L = No subcarrier)

Not used

2

3

4

5

Read frequency of watchdog 1 - LSB (bit 0) of 10-bit value

Read frequency of watchdog 1 - bit 1 of 10-bit value

Subcarrier detection (DET 2) (L = No subcarrier)

Not used

6

7

Read frequency of watchdog 2 - bit 0 of 10-bit value

Read frequency of watchdog 2 - bit 1 of 10-bit value

Reg 9

read only

Bit (default AF_HEX

)

0

1

2

3

4

5

6

7

Read frequency of watchdog 1 - bit 2 of 10-bit value

Read frequency of watchdog 1

Read frequency of watchdog 1 - bit 9, MSB (10th bit) of 10-bit

Reg 0A read only

Bit

0

1

2

3

4

5

6

7

Read frequency of watchdog 2 - bit 2 of 10-bit value

Read frequency of watchdog 2

Read frequency of watchdog 2 - bit 9, MSB (10th bit) of 10-bit

19/26

STV0056A

CONTROL REGISTERS (continued)

Video Mux Truth Tables

Register 2 <0:2>

Register 3 <0:2>

Register 4 <0:2>

Scart 1 video output control

Scart 2 video output control

Scart 3 decoder output control

The truth table for the three scart outputs are the same.

Register 2/3/4

Video Output

Bit<2>

Bit<1>

Bit<0>

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Baseband video

De-emphasized video

Normal video

Scart 3 return

Scart 2 return

Scart 1 return

Nothing selected

High Z or low power (default)

Register 4

Black Level Adjust on Scart 3

Bit <7>

Bit <6>

0

1

0

1

0

1

-150mV

0 (default)

+150mV

+300mV

Audio Mux Truth Tables

Register 2

Switch K1/Audio Source Selection for Volume Output

Bit <5>

Bit <4>

Volume Output

0

1

0

1

0

1

A

C

B

-

Audio deemphasis (K2 switch O/P)

Scart 2 return

Scart 3 return

High Z or low power (default)

Register 3

Switch K2/Audio Deemphasis

Bit <7>

Bit <6>

Audio Deemphasis

No deemphasis

J17

0

1

0

1

0

1

A

C

B

50µs

75µs (default)

Register 0

Switch K3 & K4

Bit <6>

Bit <5>

ANRS I/O Select

Noise reduction OFF

Noise reduction ON (default)

I/P = PLL

0

1

X

0

1

A

B

A

B

X

I/P = Scart 3 return

Register 3

Switch K5/Audio Source Selection for Scart 2

Bit <5>

Bit <4>

Aux Audio Output

0

1

0

1

0

1

C

A

B

-

PLL output

Scart 3 return

Audio deemphasis (K2 switch O/P)

High Z or low power state (default)

Register 4

Switch K6/Audio Source Selection for Scart 3

Bit <5>

Bit <4>

Audio Decoder Output

PLL output

Audio deemphasis (K2 switch O/P)

Scart 2 return

High Z or low power state (default)

0

1

0

1

0

1

A

C

B

-

20/26

STV0056A

CONTROL REGISTERS (continued)

Register 2

Left / Right / Stereo on Volume Output

Bit <7>

Bit <6>

0

1

0

1

Mono left / channel 1

Mono right / channel 2

Stereo left & right (default)

Register 5 : FM Deviation Selection

Selected Nominal Carrier Modulation

Bit 5 = 1

4

3

2

1

0

Bit 5 = 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Do not use

Cal. set. (2V)

592kHz

534kHz

484kHz

436kHz

396kHz

358kHz

322kHz

292kHz

266kHz

240kHz

218kHz

196kHz

179kHz

161kHz

146kHz

122kHz

120kHz

109kHz

98kHz

cal : do not use = 0.3373V offset on VCO

cal : do not use = 0.3053V offset on VCO

cal : do not use = 0.2763V offset on VCO

calibration setting (1V offset on VCO)

296kHz modulation

267kHz modulation

242kHz

218kHz

198kHz

179kHz

161kHz

146kHz

133kHz

120kHz

109kHz

98.3kHz

89.7kHz

80.9kHz

73.1kHz

66.0kHz

60.0kHz

54.4kHz = default power up state

49.1kHz

89kHz

44.3kHz

78kHz

39.8kHz

71kHz

35.9kHz

65kHz

32.4kHz

58kHz

29.1kHz

53kHz

26.7kHz

48.6kHz

43.8kHz

39.6kHz

24.3kHz

21.9kHz

19.7kHz

Example : Default power up state 54.4kHz

±54.4kHz.

Register 1

Bit <7>

Register 3

Bit <3>

Video Deemphasis/22kHz

0

1

0

1

0

1

Deemphasis 1 (default)

Deemphasis 1 + 22kHz

Deemphasis 2

Register 5

Digital I/O (STV0056A pin 29)

Bit <7>

Bit <6>

0

1

0

1

0

1

I/O (refer to Register 6 Bit <0> Bit <1>)

22kHz

Do not use (for test only) (default)

22kHz

21/26

STV0056A

FM DEMODULATION SOFTWARE ROUTINE

With the STV0056A circuit, for eachchannel, three

steps are required to acheive a FM demodulation :

- 1^ststep :To set the demodulation parameters :

• FM deviation selection,

two completesequenceshavetobe doneone after

the other when demodulating stereo pairs.

Detailed Description

• Subcarrier frequency selection.

Conventions:

- R = Stands for Register

- B = Stands for Bit

- 2^ndstep : To implement a waiting loop to check

the actual VCO frequency.

- 3^rdstep :To close the demodulationphase locked

loop (PLL).

Example : R05 B2 = Register 05, Bit 2

Refering to the FM demodulation block diagram

(page 12), the frequency synthesis block is com-

mon tobothchannels(leftand right); consequently

For clarity, the explanationsare based on the fol-

lowing example : stereo pair 7.02MHz/L

7.20MHz/R, deviation ±50kHz max.

1st STEP (LEFT) : SETTING THE DEMODULATION PARAMETERS

A. The FM deviationis selected by loading R5 with

The Table 1 givesthe settingfor themost common

the appropriatevalue. (see R5 truth table).

subcarrier frequencies.

NB : Very wide deviations (up to ±592kHz) can be

accomodatedwhen R5 B5 is low.

Table 1 : Frequency Synthesis Register Setting

for the Most Common SubcarrierFrequencies

Corresponding bandwidth can be calculated as

follows :

Bw ≈ 2 (FM deviation + audio bandwidth)

Bw ≈ 2 (value given in table + audio bandwidth)

Register 6

Subcarrier Frequency

(MHz)

Register 7

(Hex)

Bit 7 Bit 6

In the example :

5.58

5.76

5.8

8B

90

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R5Bits 7

X

6

X

5

1

4

1

3

0

2

1

0

91

B. The subcarrier frequency is selected by

launchinga frequencysynthesis (the VCOis driven

to the wanted frequency). This operation requires

two actions :

- To connect the VCO to the frequency synthesis

loop.Referingto the FMblockdiagram(page12):

5.94

6.2

94

9B

9D

A0

A2

A5

A6

AA

AB

AF

B4

B5

B8

BD

C1

C4

C6

CD

D8

6.3

6.4

6.48

6.5

• SW4 closed

• SW3 to bias

• SW2 to bias

• SW1 opened

R6 B2 = H

R6 B4 = L

R6 B3 = L

R6 B5 = L

6.6

6.65

6.8

- To load R7 and R6 B6 B7 with the value corre-

sponding to the left channel frequency. This 10

bits value is calculated as follows :

Subcarrierfrequency = coded value x 10kHz

(10kHz is the minimum step of the frequency

synthesis function)

Considering that the tunning range is comprised

between5to 10MHz,thecodedvalueis anumber

between 500 and 1000 (2¹⁰= 1024) then 10 bits

are required.

6.85

7.02

7.20

7.25

7.38

7.56

7.74

7.85

7.92

8.2

Example :

7.02MHz = 702 x 10kHz

702

1010 1111 10

AF + 10

8.65

R7 is loaded with AF and R6 B6 : L, R6 B7 : H.

22/26

STV0056A

FM DEMODULATION SOFTWARE ROUTINE (continued)

2^ndSTEP (LEFT) :

VCO FREQUENCY CHECKING (VCO)

In practice :

- SW3 closed

- SW4 opened R6 B2 = L

R6 B4 = H

This second step is actuallya waiting loop in which

the actual running frequency of the VCO is meas-

ured.

After this sequence of 3 steps for left channel,

a similar sequence is neededfor the right channel.

To exit of this loop is allowed when : Subcarrier

Frequency - 10kHz ≤ Measured Frequency ≤ Sub-

carrier Frequency + 10kHz (± 10kHz is the maxi-

mum dispersion of the frequency synthesis

function).

Note :

In the sequence for the right, there is no need to

again select the FM deviation (once is enough for

the pair).

General Remark

In practice, R8 B2 B3 and R9 are read and com-

pared to the value loaded in R6 B6 B7 and R7

±1 bit.

Before to enable the demodulated signal to the

audiooutput, it isrecommandedto keepthe muting

and to check whether a subcarrier is present at the

wantedfrequency.Suchan informationis available

in R8 B0 and R8 B4 which can be read.

Note :

The duration of this step depends on how large is

frequency difference between the start frequency

and the targeted frequency. Typically :

- the rate of change of the VCO frequencyis about

3.75MHz/s (C_pump= 10µF)

- In addition to this settling time, 100ms must be

addedto takeinto accountthe samplingperiodof

the watchdog.

Two differentstrategies can be adoptedwhen ena-

bling the output :

- Eitherboth left andright demodulatedsignals are

simultaneously authorized when both channel

are ready.

- Orwhile the right channelsequenceis running,the

already ready left signal is sentto the left and right

outputs and the real stereo sound L/R is output

when bothchannelsare ready. This second option

gives sound a fewhundredsof ms before the first

one.

3^rdSTEP (LEFT)

The FMdemodulationcan bestartedbyconnecting

the VCO to the phase locked loop (PLL).

23/26

STV0056A

TYPICAL APPLICATION (3 SCARTS, PAL/SECAM Europe Apllication)

24/26

STV0056A

TWIN TUNER APPLICATION

Easy parallel connectionof the outputs to the scarts without any additionalswitching hardware.

This configuration is possible due to the high impedance mode that can be selected for each audio and

video outputs.

Video

8

S

T

V

0

TUNER 1

9

7

TV

SCART

Audio

2

6-10

0

32

5

12-14

27-28

6

I²C Bus

A

Video

VCR

SCART

Audio

2

Video

8

9

7

S

T

V

0

TUNER 2

DECODER

SCART

Audio

2

6-10

0

5V 32

5

12-14

27-28

6

A

25/26

STV0056A

PACKAGE MECHANICAL DATA

56 PINS - PLASTIC SHRINK DIP

mm

Typ

inches

Typ

Dim.

Min

Max

Min

Max

A

5.08

0.200

A1

B

0.51

0.35

0.75

0.20

0.020

0.014

0.030

0.008

0.59

1.42

0.36

0.023

0.056

0.014

B1

C

D

52.12

–

2.052

–

D1

E

–

0.730

0.540

–

18.54

E1

K1

K2

L

13.72

–

2.54

3.81

.100

0.150

e1

1.78

0.070

Number of Pins

56

N

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility

for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result

from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.

Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all

information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life

support devices or systems without express written approval of SGS-THOMSON Microelectronics.

Purchase of I²C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips

I²C Patent. Rights to use these components in a I²C system, is granted provided that the system conforms to

the I²C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil -Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco

The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

26/26


型号：	STV0056A
厂家：	ST
描述：	SATELLITE SOUND AND VIDEO PROCESSORS 卫星声音和视频处理器
文件：	总26页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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