STV7617D [STMICROELECTRONICS]
PLASMA DISPLAY PANEL SCAN DRIVER; 等离子显示面板扫描驱动器
| 型号： | STV7617D |
| 厂家： | 
ST |
| 描述： | PLASMA DISPLAY PANEL SCAN DRIVER |
| 文件： | 总17页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STV7617, STV7617D, STV7617U
PLASMA DISPLAY PANEL SCAN DRIVER
FEATURE
■ 64/65 SELECTABLE OUTPUT PLASMA
DISPLAY DRIVER
■ 100 V ABSOLUTE MAXIMUM SUPPLY
■ 5 V SUPPLY FOR LOGIC
■ 100/850 mA SOURCE/SINK OUTPUT
■ 700 mA SOURCE/SINK OUTPUT DIODE
■ 65-bit BIDIRECTIONAL SHIFT REGISTER
(8 MHz)
TQFP100 (14 x 14 x 1.4 mm Slug-down)
■ HIGH IMPEDANCE OUTPUT CONTROL
■ BCD TECHNOLOGY
(Thin Plastic Quad Flat Pack)
ORDER CODE: STV7617D
■ 100-PIN TQFP PACKAGE WITH
INTEGRATED HEATSINK
TQFP100 (14 x 14 x 1.4 mm)
(Thin Plastic Quad Flat Pack)
ORDER CODE: STV7617
DESCRIPTION
The STV7617 is a scan driver for Plasma Display
Panel (PDP) implemented in ST’s proprietary
BCD technology. Using a 65-bit cascadable
8 MHz shift register, it drives 65 high current &
high voltage outputs. The STV7617 can be config-
ured either in 64 or 65 outputs depending on the
SEL input Pin.
By serially connecting several STV7617, any ver-
tical pixel definition can be performed. The
STV7617 is supplied with a separated 90V power
output supply and a 5 V logic supply. All command
inputs are CMOS compatible. The STV7617 pack-
age is a 100-pin TQFP with integrated heatsink lo-
cated on the bottom (STV7617D) or top
(STV7617U) of the package. It is also available
without heatsink (STV7617).
TQFP100 (14 x 14 x 1.4 mm Slug-up)
(Thin Plastic Quad Flat Pack)
ORDER CODE: STV7617U
Version 4.1
June 2000
1/17
This ispreliminary information on a new product in development or undergoing evaluation. Detailsare subject to change without notice.
1
TABLE OF CONTENTS
PIN CONNECTIONS (SLUG-UP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PIN CONNECTIONS (SLUG-DOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PIN CONNECTIONS (NO SLUG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AC TIMING REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AC TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
INPUT/OUTPUT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL DATA (SLUG-DOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL DATA (SLUG-UP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PACKAGE MECHANICAL DATA (NO SLUG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
2/17
2
STV7617, STV7617D, STV7617U
PIN CONNECTIONS (SLUG-UP)
(TQFP100 Slug-up)
OUT63
OUT62
OUT61
OUT60
OUT59
OUT58
OUT57
OUT56
OUT55
OUT54
OUT33
OUT52
OUT51
OUT50
OUT49
OUT48
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
OUT40
OUT39
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OUT3
2
OUT4
3
OUT5
4
OUT6
5
OUT7
6
OUT8
7
OUT9
8
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT24
OUT25
OUT26
OUT27
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
STV7617U
TQFP100
(Top View)
3/17
3
STV7617, STV7617D, STV7617U
PIN CONNECTIONS (SLUG-DOWN)
(TQFP100 Slug-down)
OUT3
OUT4
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OUT63
OUT62
OUT61
OUT60
OUT59
OUT58
OUT57
OUT56
OUT55
OUT54
OUT33
OUT52
OUT51
OUT50
OUT49
OUT48
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
OUT40
OUT39
2
OUT5
3
OUT6
4
OUT7
5
OUT8
6
OUT9
7
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT24
OUT25
OUT26
OUT27
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
STV7617D
TQFP100
(Top View)
4/17
3
STV7617, STV7617D, STV7617U
PIN CONNECTIONS (NO SLUG)
(TQFP100)
OUT3
OUT4
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OUT63
OUT62
OUT61
OUT60
OUT59
OUT58
OUT57
OUT56
OUT55
OUT54
OUT33
OUT52
OUT51
OUT50
OUT49
OUT48
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
OUT40
OUT39
2
OUT5
3
OUT6
4
OUT7
5
OUT8
6
OUT9
7
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT24
OUT25
OUT26
OUT27
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
STV7617
TQFP100
(Top View)
5/17
3
STV7617, STV7617D, STV7617U
PIN ASSIGNMENT
(TQFP100)
Pin Number
Symbol
Type
Function
TQFP100 Slug-down/
TQFP100 No slug
TQFP100 Slug-up
88
88
V
Supply 5 V Logic Supply
CC
34-35-41-42
34-35-41-42
V
Supply High Voltage Supply of power outputs
PP
78-79-97-98
30-31-44-45
78-79-97-98
30-31-32-45
V
Ground Ground of power outputs
SSP
46-81-82-94-95
83-93
46-81-82-94-95
83-93
V
Ground Logic Ground
Ground Substrate Ground
Output Power Output
SSLOG
V
SSSUB
32
44
77 to 48, 40 to 36,
99-100, 1 to 28,
OUT1 to OUT 65
28 to 1, 100-99
36 to 40, 48 to 77
91
90
89
87
86
85
84
92
85
86
87
89
90
91
92
84
SOUT (SIN)
CLK
Output Shift Register Data Output
Input
Input
Input
Input
Input
Input
Input
-
Clock of data shift register
Latch of data to outputs
Power Output Blanking Control
Power Output High Impedance Control
Shift Register Data Input
Selection of number of power outputs
Selection of shift direction
Not connected
STB
BLK
HIZ
SIN (SOUT)
SEL
F/R
NC
29-33-43-47-80-96
29-33-43-47-80-96
PIN ASSIGNMENT (Power Outputs)
Pin Number
Output
Pin Number
Pin Number
Output
Output
Slug-down/
No slug
77
Slug-down/
No slug
55
Slug-down/
Number
Number
Number
Slug-up
Slug-up
Slug-up
No slug
19
18
17
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
99
100
1
2
3
4
5
6
7
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
21
22
23
24
25
26
27
28
36
37
38
39
40
48
49
50
51
52
53
54
55
56
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
54
53
52
51
50
49
48
40
39
38
37
36
28
27
26
25
9
10
11
12
13
14
15
16
17
18
19
20
21
22
8
9
10
11
12
13
14
15
18
17
18
19
20
8
7
6
5
4
3
2
1
60
59
58
57
24
23
22
21
100
99
56
20
6/17
3
STV7617, STV7617D, STV7617U
BLOCK DIAGRAM
F/R
SWITCH
SEL
CLK
65-BIT SHIFT REGISTER
SOUT (SIN)
P1
P65
SIN (SOUT)
S1
S65
LATCH
STB
Q1 Q2
Q64Q65
VCC
VCC
BLK
VSSSUB
VSSP
VSSLOG
VPP
VCC
HIZ
VSSP
VPP
VSSP
VPP
STV7617
OUT1
OUT64 OUT65
CIRCUIT DESCRIPTION
The STV7617 contains all the logic and the power
circuits necessary to drive rows of a Plasma Dis-
play Panel (PDP). Data is shifted at each low to
high transition of the (CLK) shift clock. After 64 or
65 shifts (depending on SEL) the first bit presented
at (SIN) is available at the serial output (SOUT).
This output can be used to cascade several driv-
ers to perform any vertical resolution. CLK, STB,
SIN and SOUT inputs are Smith trigger inputs.
BLK and HIZ logical inputs are internally pulled to
level ”1”. The maximum frequency of the shift
clock is 8 MHz.
Sustain current must not be sunk in the power out-
puts to VPP when the power supply is applied and
output state is in HIZ or at high state. V
and
SSSUB
V
must be connected as close as possible to
SSLOG
the logical reference ground of the application.
Table 2 : Shift Register Truth Table
F/R
CLK
SIN
SOUT
Out
Out
In
Comments
Forward Shift
Steady
H
Rise
In
H
L or H
Rise
In
L
Out
Out
Reverse Shift
Steady
L
L or H
In
Shift register outputs (P1, ... P65) are transferred
from the shift register into the latch stage when the
latch input (STB) is at low level.
Table 3 : Power Output Configuration
Number of
SEL
F/R
Comments
Table 1 : Output State Configuration
Outputs
STB
BLK
HIZ
Output State
Out 1 is in Hi-Z mode (out-
puts 65 to 2 powered)
L
L
64
*
L
L
High impedance
Out 65 is in Hi-Z mode (out-
puts 1 to 64 powered)
Inverted copy of input
data
L
H
64
L
L
H
H
H
L
65
65
Out 65 to Out 1 powered
Out 1 to Out 65 powered
H
*
L
H
H
H
L
Data latched
Low level
H
*
H
High Level
7/17
3
STV7617, STV7617D, STV7617U
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
-0.3, +7
Unit
V
V
Logic Supply (Pin 88)*
CC
OUTi
VIN
Output Pins (1 to 28, 36 to 40, 48 to 77, 99, 100)
Logic Input Voltage (Pins 84, 86, 87, 89, 90, 91, 92)*
-0.3, +100
V
-0.3, V +0.3
V
CC
*
VOUT
Logic Output Voltage (Pin 85)
-0.3, V + 0.3
V
CC
V
Driver Output Voltage (scanning mode)
Driver Output Current (1) (4)
Diode Output Current (3) (4)
Junction Temperature
-0.3, +100
-100, +1 A
±700
V
POUT
I
mA
mA
°C
°C
°C
POUT
I
DOUT
Tjmax
+150
Toper
Tstg
Operating Temperature
-20, +85
-20, +150
Storage Temperature
* In case of STV7617D
THERMAL DATA
Symbol
Parameter
Value
20
Unit
Rth(j-a)
Junction-ambient Thermal Resistance (1)
Maximum Operating Junction (1)
°C/W
°C
T
125
40
joper
Rth(j-a)
Junction-ambient Thermal Resistance (5)
°C/W
Note 1 For TQFP100 packaging and slug soldered on printed circuit board.
Note 2 Through one power output.
Note 3 Through all power outputs (see test diagram): with Power dissipation lower or equal than Ptot and Junction tem-
perature lower or equal than T and V
V
PP = SSP.
jmax
Note 4 These parameters are measured during ST’s internal qualification which includes temperature characterisation
on standard batches and on corners batches of the process. These parameters are not tested on the parts.
Note 5 TQFP soldered on 4 layers Printed Circuit Board.
8/17
3
STV7617, STV7617D, STV7617U
ELECTRICAL CHARACTERISTICS
(V
= 5 V, V = 90 V, V
= 0 V, V
= 0 V, V
= 0 V, T
= 25°C, f
= 8 MHz, unless
CLK
CC
PP
SSP
SSLOG
SSSUB
amb
otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY
V
Logic Supply Voltage
4.5
5
-
5.5
100
-
V
µA
mA
V
CC
I
Logic Supply Current
-
-
CCH
I
f
= 8 MHz
CLK
Logic Supply Current
5
-
CCL
V
Power Output Supply Voltage
20
-
90
PP
Power Output Supply Current
(steady outputs)
I
-
100
µA
PPH
OUTPUT
OUT1-OUT65
V
V
I
= - 20 mA
POUTH
Power Output High Level
Power Output High Level
Power Output Low Level
83
30
-
86
33
-
-
V
V
V
V
V
V
POUTH
POUTH
I
= - 15mA, V = 40 V
POUTH
PP
V
I
= + 400 mA
POUTL
2.5
-
5
POUTL
V
I
= 850 mA (6)
Power Output Low Level-pulsed mode
Output Diode High Level
-
15
5
POUTL-P
POUTL-P
V
I
= +400 mA (7) (8)
= - 400 mA (7)(8)
-
1.7
-1.2
DOUTH
DOUTH
V
I
DOUTL
Output Diode Low Level
-
-5
DOUTL
SOUT
V
I
= -1 mA
Logic Output High Level
Logic Output Low Level
4
-
4.2
0.1
-
V
V
OH
OH
V
I
= +1 mA
0.4
OL
OL
INPUT (CLK, STB, BLK, HIZ, SIN, SEL)
V
0.8 V
Input High Level
-
-
-
-
V
V
IH
CC
V
I
0.2V
Input Low Level
-
-
IL
CC
V
= V
CC
High Level Input Current
10
µA
IH
IH
I
Low Level Input Current
CLK, SIN, STB, SEL,
BLK, HIZ
V = 0 V
IL
IL
-
-
-
-
-10
-40
µA
µA
Note 6 Peak current - Pulse mode 720 Hz - 0.2%. Duty cycle - V = 5.5 V ± 0.2 V.
CC
Note 7 Compatible with power dissipation and T
Note 8 See test diagram page 12.
≤ 125°C.
joper
9/17
3
STV7617, STV7617D, STV7617U
AC TIMING REQUIREMENTS
(V = 4.5 Vto 5.5 V, T
= -20 to +85°C, input signals max leading edge & trailing edge (t , t ) = 10 ns)
R F
CC
amb
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
Duration of clock (CLK) pulse at high level
40
40
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
WHCLK
t
Duration of clock (CLK) pulse at low level
WLCLK
t
Set-up Time of data input before clock (low to high) transition
Hold Time of data input after clock (low to high) transition
Minimum Delay to latch STB after clock (low to high) transition
Set-up Time STB before clock (low to high) transition
Latch STB Low Level Pulse Duration
10
SDAT
t
20
HDAT
t
25
DSTB
t
10
SSTB
t
20
STB
t
Blanking (BLK) Pulse Duration
500
500
BLK
t
High Impedance HIZ Pulse Duration
HIZ
AC TIMING CHARACTERISTICS
(V
= 5 V, V = 90 V V
= 0 V, V
= 0 V, V
= 0 V, T
= 25°C, V
= 0.2 Vcc,
CC
PP
,
SSP
SSLOG
SSSUB
amb
ILMax.
V
= 0.8 V , V = 4.0 V, V = 0.4 V, unless otherwise specified)
CC OH OL
IHMin.
Symbol
Parameter
Min. Typ. Max. Unit
t
Data Clock Period
125
-
-
ns
ns
ns
ns
CLK
t
Logical Data Output Rise Time
Logical Data Output Fall Time
-
-
-
12
10
37
20
20
50
RDAT
t
FDAT
t
Delay of logic data output (high to low transition) after clock (CLK) transition
PHL1
(CL=10pF)
Delay of logic data output (low to high transition) after clock (CLK) transition
(CL=10 pF)
-
42
60
ns
t
PLH1
t
t
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition
-
-
110 180 ns
115 180 ns
PHL2
PLH2
t
t
Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition
-
-
80 165 ns
95 165 ns
PHL3
PLH3
t
t
Delay of power output change (high to low transition) to blank (BLK) transition
Delay of power output change (low to high transition) to blank (BLK) transition
-
-
75 160 ns
75 160 ns
PHL4
PLH4
t
t
Delay of power output change (high to Hi-Z transition) after high impedance (HIZ)(9)
Delay of power output change (low to Hi-Z transition) after high impedance (HIZ)(9)
-
-
40 160 ns
80 160 ns
PHZ5
PLZ5
t
t
Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (9)
Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (9)
-
-
75 160 ns
40 160 ns
PZH5
PZL5
t
Power Output Rise Time (10)
Power Output Fall Time (10)
-
-
175 350 ns
35 150 ns
ROUT
t
FOUT
Note 9 See test diagram page 12.
Note 10 One output among 64, loading capacitor C
= 200pF, other outputs at low level.
OUT
10/17
3
STV7617, STV7617D, STV7617U
Figure 1: AC Characteristics Waveform
tCLK
tWHCLK
tWLCLK
”1”
CLK
SIN
50%
50%
50%
”0”
”1”
tSDAT
tHDAT
50%
50%
”0”
”1”
tFDAT
90%
tPHL1
90%
SOUT
10%
10%
”0”
”1”
tRDAT
tPLH1
tSSTB
tSTB
tDSTB
STB
50%
50%
tPHL3
”0”
”1”
tPHL2
90%
90%
tPLH3
OUTn
10%
10%
”0”
”1”
tPLH2
tBLK/POL
HIZ (BLK = H)
50%
tPLH4
50%
”0”
”1”
tPHL4
90%
OUTn
10%
”0”
”1”
tHIZ
HIZ (BLK = L)
50%
50%
”0”
”1”
tROUT
tPHZ5
tPZH5
60%
90%
10%
90%
10%
90%
10%
OUTn
40%
tPZL5
”0”
tFOUT
tPLZ5
11/17
3
STV7617, STV7617D, STV7617U
Figure 2: Test Configuration
VPP
V
VPP VSSP
=
=
SSP
VDOUTH
IDOUTH
VDOUTL
IDOUTL
VSSP
VSSP
Output sinking current as positive value, sourcing current as negative value
VPP
R
VPP/2
OUT
VDOUT
12/17
3
STV7617, STV7617D, STV7617U
INPUT/OUTPUT CHARACTERISTICS
Figure 3: BLK, HIZ Input
Figure 5: SIN, SOUT Input
VCC
VCC
VCC
VCC
SIN, SOUT
VCC
BLK, HIZ
GNDLOG
GNDSUB
GNDLOG
GNDSUB
Figure 4: F/R, SEL, CLK, STB Input
Figure 6: Power Output
VCC
VPP
VCC
F/R, SEL
CLK, STB
OUT1 to
OUT 65
GNDLOG
VSSP
GNDSUB
13/17
3
STV7617, STV7617D, STV7617U
PACKAGE MECHANICAL DATA (SLUG-DOWN)
100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
A
A2
S1
A1
e
100
76
0,075 mm
0.03 inch
SEATING PLANE
75
1
51
25
26
50
D3
D1
D
0,25 mm
.010 inch
GAGE PLANE
K
Millimeters
Typ.
Inches
Typ.
Dimensions
Min.
Max.
1.60
0.15
1.45
0.27
0.20
Min.
Max.
0.063
0.006
0.057
0.011
0.008
A
A1
A2
B
0.05
1.35
0.17
0.09
0.002
0.053
0.007
0.004
1.40
0.22
0.055
0.009
C
D
16.00
14.00
12.00
0.50
0.630
0.551
0.472
0.20
D1
D3
e
E
16.00
14.00
12.00
0.60
0.630
0.551
0.472
0.024
0.039
E1
E3
L
0.45
0.75
0.018
0.030
L1
K
1.00
0° (Min.), 7° (Max.)
Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm
H
S
9.85
0.388
8.80
8.80
0.346
0.346
S1
14/17
3
STV7617, STV7617D, STV7617U
PACKAGE MECHANICAL DATA (SLUG-UP)
100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
A
A2
S1
A1
e
100
76
0,075 mm
0.03 inch
SEATING PLANE
1
75
25
51
26
50
D3
D1
D
0,25 mm
.010 inch
GAGE PLANE
K
Millimeters
Typ.
Inches
Dimensions
Min.
Max.
1.60
0.15
1.45
0.27
0.20
Min.
Typ.
Max.
0.063
0.006
0.057
0.011
0.008
A
A1
A2
B
0.05
1.35
0.17
0.09
0.002
0.053
0.007
0.004
1.40
0.22
0.055
0.009
C
D
16.00
14.00
12.00
0.50
0.630
0.551
0.472
0.20
D1
D3
e
E
16.00
14.00
12.00
0.60
0.630
0.551
0.472
0.024
0.039
E1
E3
L
0.45
0.75
0.018
0.030
L1
K
1.00
0° (Min.), 7° (Max.)
Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm
H
S
9.85
0.388
8.80
8.80
0.346
0.346
S1
15/17
3
STV7617, STV7617D, STV7617U
PACKAGE MECHANICAL DATA (NO SLUG)
100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
A
A2
A1
0,075 mm
e
100
76
0.03 inch
SEATING PLANE
75
1
51
25
26
50
D3
D1
D
0,25 mm
.010 inch
GAGE PLANE
K
Millimeters
Typ.
Inches
Typ.
Dimensions
Min.
Max.
1.60
0.15
1.45
0.27
0.20
Min.
Max.
0.063
0.006
0.057
0.011
0.008
A
A1
A2
B
0.05
1.35
0.17
0.09
0.002
0.053
0.007
0.004
1.40
0.22
0.055
0.009
C
D
16.00
14.00
12.00
0.50
0.630
0.551
0.472
0.20
D1
D3
e
E
16.00
14.00
12.00
0.60
0.630
0.551
0.472
0.024
0.039
E1
E3
L
0.45
0.75
0.018
0.030
L1
K
1.00
0° (Min.), 7° (Max.)
16/17
STV7617, STV7617D, STV7617U
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responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change
without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics.
2000 STMicroelectronics - All Rights Reserved
2
2
Purchase of I C Components of STMicroelectronics, conveys a license under the Philips I C Patent.
2
2
Rights to use these components in a I C system, is granted provided that the system conforms to the I C
Standard Specifications as defined by Philips.
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17/17
4
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