STV8130A [STMICROELECTRONICS]
DUAL OUTPUT, FIXED/ADJUSTABLE POSITIVE REGULATOR, PSFM9, PLASTIC, SIP-9;
| 型号： | STV8130A |
| 厂家： | 
ST |
| 描述： | DUAL OUTPUT, FIXED/ADJUSTABLE POSITIVE REGULATOR, PSFM9, PLASTIC, SIP-9 局域网 输出元件 调节器 |
| 文件： | 总14页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STV8130AD
Adjustable and +3.3 V dual voltage regulator with
disable and reset functions
Features
■ Input voltage range: 5 V to 18 V
■ Output currents up to 750 mA
■ Fixed precision output 1 voltage: 3.3 V 2ꢀ
■ Adjustable output 2 voltage: 2.8 to 16 V
■ Output 1 with reset function
SIP9 (plastic package)
DIP16 (8 + 8)
■ Output 2 with disable function by TTL Input
■ Short-circuit protection at both outputs
■ Thermal protection
Table 1.
Device summary
■ Low dropout voltage
Order code
Packaging
Description
STV8130A#
STV8130AD
Tray
Tray
The STV8130A# and STV8130AD are monolithic
dual positive voltage regulators designed to
provide a fixed precision output voltage of 3.3 V
and an adjustable voltage between 2.8 and 16 V
for currents up to 750 mA.
An internal reset circuit generates a reset pulse
when the voltage of output 1 drops below the
regulated voltage value.
Output 2 can be disabled via the TTL input.
Short-circuit and thermal protctions are
included.
Figure 1.
STV8130A# and STV8130AD
INPUT1
1
2
3
4
5
6
7
8
GROUND
9
8
7
6
5
4
3
2
1
OUTPUT1
OUTPUT2
PROGRAM
RESET
GROUND
DISABLE
DELAY CAPACITOR
INPUT2
INPUT1
16
15
14
13
12
11
INPUT2
DELAY CAPACITOR
DISABLE
GROUND
GROUND
GROUND
GROUND
GROUND
RESET
PROGRAM
OUTPUT2
OUTPUT1
GROUND
GROUND
10
9
Tab is connected to GROUND
March 2009
Rev 3
1/14
www.st.com
1
Contents
STV8130AD
Contents
1
2
3
4
5
6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power dissipation and layout indications . . . . . . . . . . . . . . . . . . . . . . . . 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1
Environmentally-friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/14
STV8130AD
Description
1
Description
Figure 2.
STV8130A# block diagram
DELAY CAPACITOR
3
RESET
6
9
Reference
INPUT1
1
Regulator 1
Regulator 2
OUTPUT1
Protection
OUTPUT2
INPUT2
2
4
8
7
DISABLE
PROGRAM
5
GROUND
Figure 3.
STV8130AD block diagram
DELAY CAPACITOR
3
5
8
RESET
Reference
INPUT1
1
Regulator 1
Regulator 2
OUTPUT1
Protection
OUTPUT2
INPUT2
2
4
7
6
DISABLE
PROGRAM
Pins 9 to 16
GROUND
3/14
Electrical characteristics
STV8130AD
2
Electrical characteristics
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VIN
DC input voltage at pins INPUT1 and INPUT2
Disable input voltage at pin DISABLE
Output voltage at pin RESET
Output currents
20
20
20
V
V
V
VDIS
VRST
IOUT1,2
Pt
Internally limited
Internally limited
-65 to +150
Power dissipation
TSTG
TJ
Storage temperature
°C
°C
Junction temperature
0 to +150
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
STV8130A#
9
15
RthJC
RthJA
Thermal resistance (junction-to-case)
°C/W
STV8130AD
Thermal resistance (1) (junction-to-
ambient)
STV8130A#
STV8130AD
50
56
°C/W
TJ
Maximum recommended junction temperature
Operating free air temperature range
140
°C
°C
TOPER
0 to +70
1. Mounted on board. For more information, refer to Section 5.
Table 4.
Symbol
Electrical characteristics
Parameter
Output voltage
Test conditions
IOUT1 = 10 mA
Min.
3.23
2.8
Typ.
3.30
Max.
Unit
VOUT1
VOUT2
VIO1,2
3.37
16.0
1.4
V
V
V
Output voltage
Dropout voltage
IOUT2 = 10 mA
IOUT1,2 = 750 mA
6 V < VIN1 < 12 V
12 V < VIN2 < 18 V
IOUT1,2 = 200 mA
50
100
VO1,2LI
Line regulation
mV
5 mA < IOUT1 < 600 mA
5 mA < IOUT2 < 600 mA
100
200
VO1,2LO
IQ
Load regulation
mV
mA
IOUT1 = 10 mA, OUTPUT2
Disabled
Quiescent current
2
VO1RST
VRTH
Reset threshold voltage(1)
Reset threshold hysteresis
K = VOUT1, IOUT1 ≥ 50 mA
K - 0.4 K - 0.25 K - 0.1
V
See circuit description
20
50
25
75
mV
Ce = 100 nF
See circuit description
tRD
Reset pulse delay
ms
4/14
STV8130AD
Electrical characteristics
Table 4.
Symbol
Electrical characteristics (continued)
Parameter
Test conditions
IRESET = 5 mA
RESET = 10 V
Min.
Typ.
Max.
0.4
Unit
Saturation voltage in reset
condition
VRL
IRH
V
Leakage current in normal
condition
V
10
µA
ΔV0 ⋅ 106
K0 = ---------------------------
ΔT ⋅ V0
KOUT1, 2
Output voltage thermal drift
100
ppm/°C
TJ = 0 to + 125°C
VIN1 = 7 V, VIN2 = 10 V
VIN1,2 = 16 V(2)
1.6
1.0
IOUT1,2SC
VDISH
VDISL
IDIS
VREF
TJSD
Short circuit output current
A
V
Disable voltage when pin DISABLE is high (OUTPUT2
active)
2
Disable voltage when pin DISABLE is low (OUTPUT2
disabled)
0.8
2
V
Disable bias current
0 V < VDIS < 7 V
-100
µA
V
Reference voltage at
PROGRAM pin
2.44
145
Junction temperature for thermal shutdown
°C
1. This reset signal is activated by a decrease of VOUT1 voltage which can be due to an overload of pin OUT1 or by a lack of
Input Voltage (VIN1).
2. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption of power
occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent short-circuit protection is
only guaranteed for input voltages up to 16 V.
Note:
T
= 25° C, V
= 7 V, V
= 10 V, unless otherwise specified.
IN2
AMB
IN1
5/14
Circuit description
STV8130AD
3
Circuit description
The STV8130A# and STV8130AD are dual-voltage regulators with reset and disable
functions.
The two regulation parts are supplied from a single voltage reference circuit trimmed by
zener zapping during EWS testing. Since the supply voltage of this voltage reference is
connected to pin INPUT1 (V ), the second regulator will not work if pin INPUT1 is not
IN1
supplied.
The adjustable voltage of pin OUTPUT2 (V
) is defined by output bridge resistors (R1,
OUT2
R2): the values of these resistors are calculated to obtain, with the targetted value for V
,
OUT2
the reference voltage (V
= 2.44 V) on the median point connected to pin PROGRAM.
REF
The output stages are designed using a Darlington configuration with a typical dropout
voltage of 1.2 V.
The disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin
DISABLE.
The reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below V
-
OUT1
0.25 V (3.05 V Typ.), the "a" comparator (Figure 4) rapidly discharges the external capacitor
(Ce) and the reset output immediately switches to low. This drop can be caused by a
parasitic loading condition on pin OUTPUT1 or by a too low value of V (short powering
IN
off). When the voltage at pin OUTPUT1 exceeds V
- 0.2 V (3.1 V Typ.), the V voltage
OUT1
Ce
increases linearly to the reference voltage (V
= 2.44 V) corresponding to a reset pulse
REF
delay (t ) as shown in Figure 5.
RD
Ce × 2.44V
tRD = -----------------------------
10μA
Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second
comparator "b" has a large hysteresis (1.84 V).
Figure 4.
Reset diagram
10 µA
RESET
b
VREF
a
50
-
+
+
-
OUTPUT1
3
REG
Ce
VREF
0.6V
VREF = 2.44 V
6/14
STV8130AD
Circuit description
Figure 5.
Internal reset diagram
V
OUT1
K
V
O1RST
V
RTH
RESET
K = Actual Value of V
OUT1
t
t
RD
Power Off
RD
Power On
7/14
Application diagrams
STV8130AD
4
Application diagrams
Figure 6.
STV8130A# typical application
RESET
R1 + R2
--------------------
VO2 = VREF
Ce
0.1 µF
R1
6
3
R1 Value (typ.) = 10 k
Ω
DELAY
RESET
CAPACITOR
V
= 2.44 V
REF
INPUT1
OUTPUT1
VIN1
1
2
9
8
VOUT1
STV8130A
#
VIN2
OUTPUT2
VOUT2
INPUT2
GROUND DISABLE PROGRAM
5
4
7
C4
R2
C1
C2
C3
DISABLE
R1
C1 to C4 = 10 µF
Figure 7.
STV8130AD typical application
RESET
R1 + R2
--------------------
VO2 = VREF
Ce
0.1 µF
R1
R1 Value (typ.) = 10 k
5
3
Ω
DELAY
RESET
CAPACITOR
V
= 2.44 V
REF
INPUT1
OUTPUT1
VIN1
1
2
8
7
VOUT1
STV8130AD
INPUT2
OUTPUT2
VIN2
VOUT2
DISABLE PROGRAM
GROUND
4
6
C4
R2
C1
C2
C3
DISABLE
R1
C1 to C4 = 10 µF
8/14
STV8130AD
Power dissipation and layout indications
5
Power dissipation and layout indications
The power is mainly dissipated by the two device buffers. It can be calculated by the
equation:
P = (V -V
) x I
+ (V -V
) x I
IN1 OUT1
OUT1
IN2 OUT2 OUT2
The following table lists the different R
values of these packages with or without a heat
thJA
sink and the corresponding maximum power dissipation assuming:
●
Maximum ambient temperature = 70° C
Maximum Junction temperature = 140° C
●
Table 5.
Power dissipation
Device Heat sink
RthJA in °C/W
PMAX in W
No
50
20
1.4
3.5
STV8130A#
Yes
No
56 to 40
32
1.25 to 1.75
2.2
STV8130AD
Yes
Figure 8.
Thermal resistance (junction-to-ambient) of DIP16 package without heatsink
To optimize the thermal conductivity of the copper layer
and the exchanges with the air, the solder must cover
the maximum amount of this area
60
55
50
45
Test board with
“on board” square heat sink area.
40
0
6
2
4
8
10
12
Copper area (cm²) (35 µm plus solder) board is face-down
Figure 9.
Metal plate mounted near the STV8130AD for heatsinking
Top View
Bottom View
9/14
Package mechanical data
STV8130AD
6
Package mechanical data
Figure 10. 9-pin plastic single in-line package
Table 6.
Dim.
9-pin plastic single in-line package dimensions
mm
Inches
Typ.
Min.
Typ.
Max.
Min.
Max.
A
7.1
3
0.280
a1
B
2.7
0.106
0.118
0.976
24.8
b1
b3
C
0.5
3.3
0.020
0.85
1.6
0.033
0.063
0.835
0.130
0.017
0.052
c1
c2
D
0.43
1.32
21.2
d1
e
14.5
2.54
20.32
0.571
0.100
0.800
e3
L
3.1
1.122
L1
L2
3
0.116
0.693
17.6
10/14
STV8130AD
Package mechanical data
9-pin plastic single in-line package dimensions (continued)
Table 6.
Dim.
mm
Inches
Typ.
Min.
Typ.
Max.
0.25
Min.
Max.
L3
M
N
0.010
3.2
1
0.126
0.039
Figure 11. 16-pin plastic dual in-line package, 300-mil width
Table 7.
Dim.
16-pin plastic dual in-line package dimensions
mm
Inches
Typ.
Min.
Typ.
Max.
Min.
Max.
A
5.33
0.210
A1
A2
b
0.38
0.015
0.115
0.014
2.92
0.36
3.30
4.95
0.56
1.78
0.36
19.69
0.130
0.195
0.022
0.070
0.014
0.775
b2
c
1.52
0.25
19.18
2.54
6.35
3.30
0.060
0.010
0.755
0.100
0.250
0.130
0.20
0.008
0.735
D
18.67
e
E1
L
6.10
2.92
7.11
3.81
0.240
0.115
0.280
0.150
11/14
Package mechanical data
STV8130AD
6.1
Environmentally-friendly packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance.
ECOPACK specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
12/14
STV8130AD
Revision history
7
Revision history
Table 8.
Date
Document revision history
Revision
Changes
General Update; DISABLE pin renamed DISABLE (function remains
unchanged)
August 2001
1.8
September
2001
1.9
Thermal Data updated
September
2001
2.0
2.1
2.2
Addition of DIP16 package
October 2001
Thermal Data updated. Figure 2 and Figure 3 updated
31 January
2002
Order code changed from STV8130A and STV8130D to STV8130A#
and STV8130AD. Update of VO1RST values in Section 2
Preliminary data banner removed, template updated and Section 6.1
added
05-Mar-2009
3
13/14
STV8130AD
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14/14
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