STVM100DC6F [STMICROELECTRONICS]
I²C LCD/e-paper VCOM calibrator;
| 型号： | STVM100DC6F |
| 厂家： | 
ST |
| 描述： | I²C LCD/e-paper VCOM calibrator CD |
| 文件： | 总27页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STVM100
I2C LCD VCOM calibrator
Features
2
■ I C interface, slave address: 1001111
■ 7-bit adjustable sink current output
TDFN8 (3mm x 3mm) (DC)
TSSOP8 (3mm x 3mm) (DS)
■ 2.25V to 3.6V logic supply voltage V
DD
■ AV operating voltages
DD
– 4.5V to 20V for V from 2.6V to 3.6V
DD
– 4.5V to 13V for V from 2.25V to 3.6V
DD
■ EEPROM for storing the optimum V
setting
COM
■ Guaranteed monotonic output over operating
range
Description
■ 400kHz maximum interface bus speed
■ Operating temperature: –40°C to 85°C
The STVM100 is a programmable VCOM adjust-
ment solution for thin-film transistor (TFT) liquid-
crystal displays (LCDs) to remove “flickers”. It can
replace a mechanical potentiometer, so that the
factory operator can physically view the front
screen when performing the VCOM adjustment.
This significantly reduces labor costs, increases
reliability, and enables automation.
■ Available in an 8-pin 3mm x 3mm TDFN8 or
3mm x 3mm TSSOP8 Package
Applications
■ TFT-LCD panels
2
STVM100 provides a digital I C interface to con-
trol the sink current output (I
). This output
OUT
drives an external resistive voltage divider, which
can then be applied to an external V buffer.
COM
Three external resistors R , R , and R deter-
1
2
SET
mine the highest and lowest value of the V
.
COM
An increase in the output sink current will lower
the voltage on the external divider so that the
V
can be adjusted by 128 steps within this
COM
range. Once the desired V
setting is
COM
achieved, it can be stored in the internal
EEPROM that will be automatically recalled dur-
ing each power-up.
STVM100 is available in an 8-pin, 3mm x 3mm
TDFN8 or 3mm x 3mm TSSOP8 package.
Table 1.
Device summary
Order code
Optimum temperature range
Package
Packing
STVM100DC6E
STVM100DS6F
-40°C to 85°C
-40°C to 85°C
TDFN
ECOPACK package, tubes
TSSOP
ECOPACK package, tape and reel
July 2007
Rev 6
1/27
www.st.com
1
Contents
STVM100
Contents
1
2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2-wire bus characteristics and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
2.3
2.4
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VDD power supply ramp-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
5
6
7
8
9
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
STVM100
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Bit P read and write mode values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MLPD-DFN 3 x 3 x .75mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . 23
TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data. . . . . . . . . . . . . . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
List of figures
STVM100
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connections diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read/write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R , R , and R connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1
2
SET
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
supply current v’s V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DD
DD
Figure 11. AV supply current v’s AV
DD
DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 12.
V
supply current v’s temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DD
Figure 13. AV supply current v’s temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DD
Figure 14.
I
error v’s temperature (STVM100 at middle scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OUT
Figure 15. Total unadjusted error v’s DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Differential non-linearity v’s DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Integral non-linearity v’s DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. AV power-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DD
Figure 19. Full scale-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Full scale-down response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. MLPD-DFN 3 x 3 x.75mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . 23
Figure 22. TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data. . . . . . . . . . . . . . . . 24
4/27
STVM100
Device overview
1
Device overview
Figure 1.
Logic diagram
V
DD
AV
SDA
SCL
WP
DD
OUT
SET
STVM100
GND
AI12272
Table 2.
Name
Pin names and functions
Type
Function
Adjustable sink current output pin. (1)
OUT
Analog
Supply
See Section 3: Application information on page 11.
High-voltage analog supply.
AVDD
Bypass to GND with a 0.1µF capacitor.
WRITE protectection.
Active-low. To enable write operations to the DAC or to the EEPROM
writing, connect to 0.7VDD or greater. Internally pulled down by a 130kΩ
resistor.
WP
Input
GND
VDD
Supply ground.
System power supply input.
Supply
Bypass to GND with a 0.1µF capacitor.
SDA
SCL
In/Out
Input
I2C serial data input/output.
I2C serial clock input.
Maximum sink current adjustment point.
Connect a resistor from SET to GND to set the maximum adjustable sink
current of the OUT pin. The maximum adjustable sink current is equal to
AVDD /20 divided by RSET (see Figure 4 on page 6).
SET
Analog
1. See SET pin function in this table for the maximum adjustable sink current setting.
5/27
Device overview
Figure 2.
STVM100
Connections diagram
SET
SCL
SDA
OUT
AV
1
2
3
4
8
7
6
5
DD
WP
GND
V
DD
AI12273
Figure 3.
Block diagram
V
AV
DD
DD
19R
OUT
SET
7
2
SDA
SCL
R
I C
DAC
+
Interface
–
7
EEPROM
Block
WP
GND
AI12274
Figure 4.
Hardware hookup
V
V
AV
3.3V
DD
DD
0.1µF
DD
0.1µF
SDA
AV
DD
STVM100
R
R
MCU
1
2
+
–
SCL
WP
OUT
SET
VCOM
GND
R
SET
AI12275
6/27
STVM100
Device operation
2
Device operation
The STVM100 operates as a slave device on the serial bus. Access is obtained by
implementing a Start condition, followed by the 7-bit slave address (1001111), and the
eighth bit for READ/WRITE identification. The volatile DAC register and non-volatile
EEPROM values can be read out or written in.
2.1
2-wire bus characteristics and conditions
This bus is intended for communication between different ICs. It consists of two lines:
●
a bi-directional data signal (SDA).
a clock signal (SCL).
●
The SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor. The following protocols have been defined:
●
●
●
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
2.1.1
2.1.2
Bus not busy
Both data and clock lines remain High.
Start data transfer
A change in the data line state from high-to-low while the clock is high indicate the Start
condition.
2.1.3
Stop data transfer
A change in the data line state from low-to-high while the clock is high indicates the Stop
condition.
7/27
Device operation
STVM100
2.1.4
Data valid
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or
LOW state of the data line can only change when the clock signal on the SCL line is low
(see Figure 5). The data on the line may be changed during the clock signal low period.
There is one clock pulse per bit of data.
Each data transfer is initiated with a Start condition and terminated with a Stop condition.
The number of data bytes transferred between the Start and Stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges transmission with
a ninth bit.
By definition, the device that gives out a message is called “transmitter”, the device that gets
the message is called “receiver”. The device that controls the message is called the
“master”. The devices controlled by the master are called “slave” devices.
Figure 5.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
8/27
STVM100
Device operation
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge bit. This Acknowledge bit is a low
level signal put on the bus by the receiver, whereas the master generates an extra
acknowledge-related clock pulse (see Figure 6). A slave receiver which is addressed is
obliged to generate an acknowledge signal after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges transmissions has to pull down the SDA line during the
acknowledge clock pulse in such a way, that the SDA line is a stable low during the high
period of the acknowledge-related clock pulse. The setup and hold times must be taken into
account. A master receiver must signal an end of transmitted data to the slave transmitter
by not generating an acknowledge on the last byte that has been clocked out of the slave. In
this case, the transmitter must leave the data line high to enable the master to generate the
Stop condition.
Figure 6.
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
AI00601
9/27
Device operation
STVM100
2.2
Read mode
In READ mode, after the Start condition, the master sets the slave address (see Figure 7).
Followed by the READ/WRITE Mode Control bit (R/W=1) and the Acknowledge bit, the
value in DAC register will be transmitted and the master receiver will send an Acknowledge
bit to the slave transmitter. Finally the Stop condition will terminate the READ operation. In
READ mode, the valid data is the first 7 bits and the P bit (the eight bit) is don’t care.
2.3
Write mode
In WRITE mode the master transmits to the STVM100 slave receiver. The bus protocol is
shown in Figure 7. Following the Start condition and slave address, a logic '0' (R/W = 0) is
placed on the bus to identify a WRITE operation. After the acknowledgement by the slave,
the data will be transmitted to the slave with the 7-bit which indicates the data is valid as well
as the eighth bit “P” for the register’s identification. When P = 1, the DAC register is written
to, and when P = 0, the EEPROM is written to (Programming). After receiving the data, the
slave will generate an acknowledge signal, then a Stop condition will terminate the WRITE
operation. STVM100 is pre-programmed with 80H in the EEPROM after manufacturing.
A period of tW (see Table 8) is needed for EEPROM programming. During this period, the
slave will not acknowledge any WRITE operation.
The bit P values in both READ and WRITE modes are shown in Table 3.
Figure 7.
Read/write mode sequence
START
SLAVE ADDRESS
R/W
A
A
STOP
1
0
0
0
1
1
1
1
1
6
5
4
3
2
1
0
P
SCL
SDA
1
0
1
1
1
R/W
A
6
5
4
3
2
1
0
P
A
START
STOP
AI12276_b
Table 3.
Bit P read and write mode values
Operation
P-bit value
Description
READ
X
1
Don’t care
DAC register WRITE
WRITE
EEPROM WRITE
(programming)
0
2.4
VDD power supply ramp-up
The ramp-up from 10% V to 90%V level should be achieved in less than or equal to
DD
DD
10ms to ensure that the EEPROM and power-on reset circuits are synchronized, and the
correct value is read from the EEPROM.
10/27
STVM100
Application information
3
Application information
The STVM100 is a programmable V
provides a digital I C interface to control the sink current output. This output drives an
external resistive voltage divider, which can then be applied to an external V buffer.
calibrator for the TFT-LCD to remove flickers. It
COM
2
COM
The highest and lowest V
value is determined by three resistors, R , R , and R . The
1 2 SET
COM
connection is shown in Figure 8.
The sink current from the STVM100 OUT pin is given in Equation 1. This current then flows
through R . This current must be less than 120µA (see I
value in Table 7 on page 15).
SET
SET
Figure 8.
R , R , and R
connection
SET
1
2
AV
DD
AV
DD
AV
DD
R1
STVM100
+
–
OUT
SET
V
COM
I
OUT
R2
R
SET
AI12933
Equation 1
AV
D + 1
------------- -------------------------
DD
I
=
⋅
OUT
128 20(R
)
SET
Note:
“D” is a user-selected value, an integer ranging from 0 to 127.
The V value can be obtained in Equation 2.
COM
Equation 2
R
R
D + 1
2
1
⎛
⎝
⎞
--------------------
------------- -------------------------
V
=
⋅ AV
1 –
⋅
COM
DD
⎠
R + R
128 20(R
)
1
2
SET
11/27
Application information
STVM100
If the user-selected value is 0 (zero scale), the minimum current is sunk. The maximum
value is obtained in Equation 3.
V
COM
Equation 3
R
R
1
1
2
⎛
⎝
⎞
⎠
--------------------
--------- -------------------------
⋅
V
=
⋅ AV
1 –
COM(max)
DD
R + R
128 20(R
)
SET
1
2
If the user-selected value is 127 (full scale), the maximum current is sunk and the minimum
value is obtained in Equation 4.
V
COM
Equation 4
R
R
2
1
⎛
⎝
⎞
⎠
--------------------
V
=
⋅ AV
1 –
-------------------------
20(R
COM(min)
DD
R + R
)
1
2
SET
During operation, the V
and V
range is set, based on different TFT-LCD
COM(min)
COM(max)
processes.The R1 value is given based on the acceptable power loss from the AV supply
DD
rail. Using Equation 3 and Equation 4, the R and R
values can be calculated. If R
is
2
SET
SET
put into Equation 1 on page 11 and maximum I
≥ 120µA, then R should be increased.
OUT
1
12/27
STVM100
Maximum rating
4
Maximum rating
Stressing the device above the ratings listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TSTG
Storage temperature (VDD Off, AVDD Off)
Lead solder temperature for 10 seconds
Maximum junction temperature (plastic package)
Output voltage (OUT pin to GND)
VDD to GND
–55 to 150
260
°C
°C
°C
V
(1)
TSLD
TJ
150
VOUT
VDD
–0.3 to 20
+5.5
V
AVDD
VSET
AVDD input voltage to GND
–0.3 to 20
–0.3 to 5.5
2.66
V
Output voltage (SET pin to GND)
V
TDFN8
W
W
PDIS
Power dissipation
TSSOP8
0.53
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
13/27
DC and AC parameters
STVM100
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 5, Operating and ac Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
Conditions
Unit
V
DD supply voltage
2.25 to 3.6
2.25 to 3.6
4.5 to 20
V
V
VDD EEPROM programming supply voltage
AVDD reference voltage
V
Ambient operating temperature (TA)
–40 to 85
°C
Table 6.
Symbol
Capacitances
Parameter(1)(2)
Min
Max
Unit
Cb
Bus capacitive load
400
10
pF
pF
pF
pF
CSDA
Capacitance on SDA
WP = 0
WP = 1
10
CS
Capacitance on SCL
22
1. Effective capacitance measured with power supply at 3V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
14/27
STVM100
DC and AC parameters
Table 7.
Sym
DC and AC characteristics
Description
Test Condition(1)
Supply voltage
Min
Typ
Max
Unit
2.25
3.6
V
EEPROM
programming supply
voltage
VDD
2.25
3.6
V
(2)
IDD
VDD supply current
50
20
13
25
µA
V
VDD = 2.6V to 3.6V
4.5
4.5
AVDD Analog supply voltage
VDD = 2.25V to 3.6V
V
(3)
IAVDD
AVDD supply current
µA
Bits
SETVR SET voltage resolution
7
SET differential
SETDN
Monotonic over
temperature
1
LSB
nonlinearity
SETZSE SET zero scale error
2
8
LSB
LSB
µA
SETFSE SET full scale error
(4)
ISET
SET current
Through RSET
120
200
45
To GND, AVDD = 20V
To GND, AVDD = 4.5V
10
kΩ
SET external
resistance
SETER
2.25
kΩ
AVDD to AVDD to SET voltage
SET
attenuation(5)
20
8
V/V
µs
V
OUTST OUT settling time
VSET
0.5V
+
VOUT OUT voltage
13
SETVD SET voltage drift(5)
T = 25°C to 55°C
<10
mV
V
SDA, SCL, WP input
0.7VDD
VIH
logic high
SDA, SCL, WP input
logic low
0.3VDD
VIL
V
SDA, SCL hysteresis(5)
V
0.22VDD
25
IIL(WPN) WPN input current
15
35
µA
SDA, SCL output logic
VOL(s)
low
At 3mA
0.4
V
1. Valid for ambient operating temperature: TA = –40 to 85°C; VDD = 3V; AVDD = 10V; typical TA = 25°C;
OUT = 1/2AVDD; RSET = 24.9kΩ (except where noted).
2. Simulated maximum current draw when Programming EEPROM is 23mA; should be considered when
designing a power supply.
3. Tested at AVDD = 20V.
4. A typical Current of 20µA is calculated using AVDD = 10V and RSET = 24.9kΩ. The maximum suggested
SET current should be 120µA.
5. Simulated and determined via design and NOT directly tested.
15/27
DC and AC parameters
Figure 9.
STVM100
Bus timing requirements sequence
SDA
SCL
tBUF
tHD:STA
tR
tHD:STA
tF
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:ST
P
P
S
tLOW
SR
AI00589
Table 8.
Sym
AC characteristics
Description
Test Condition(1)
Min
Typ
Max
Unit
fSCL
tLOW
tHIGH
SCL clock frequency
Clock low period
0
400
kHz
µs
µs
ns
ns
ns
ns
1.3
0.6
100
0
Clock high period
tSU:DAT Data setup time
tHD:DAT Data hold time
900
300
300
tR
tF
SDA and SCL rise time
Dependent on load (see
Table 6 on page 14)
20 +
0.1Cb
SDA and SCL fall time
Bus free time before
new transmission can
start
tBUF
1.3
µs
I2C spike rejection filter
pulse width
tDSP
0
50
ns
µs
µs
Repeated start
condition setup time
tSU:STA
tHD:STA
tSU:STO
tW
0.6
0.6
0.6
Repeated start
condition hold time
Stop condition setup
time
µs
WRITE cycle time
100
ms
1. Valid for ambient operating temperature: TA = –40 to 85°C; VDD = 3.0V to 3.6V; AVDD = 10V;
OUT = 1/2AVDD; RSET = 24.9kΩ (except where noted, see Figure 9).
16/27
STVM100
Typical operating characteristics
6
Typical operating characteristics
Typical operating characteristics for the STVM100 are T = 25°C, V = 3V, AV = 10V,
A
DD
DD
OUT = 1/2
, and R
= 24.9kΩ except where noted.
AVDD
SET
Figure 10. V supply current v’s V
DD
DD
27.5
27
26.5
26
25.5
25
24.5
24
.2.2
2.4
2.6
2.8
V
3.0
(V)
3.2
3.4
3.6
DD
AI13362
Figure 11. AV supply current v’s AV
DD
DD
10
9
8
7
6
5
4
3
2
1
0
4.5
6
7.5
9
10.5
12
13.5
(V)
15 16.5
18
19.5
AV
DD
AI13363
17/27
Typical operating characteristics
Figure 12. V supply current v’s temperature
STVM100
DD
35
30
25
20
15
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature˚C
AI13364
Figure 13. AV supply current v’s temperature
DD
4.95
4.9
4.85
4.8
4.75
4.7
4.65
4.6
4.55
4.5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature˚C
AI13365
18/27
STVM100
Typical operating characteristics
error v’s temperature (STVM100 at middle scale)
Figure 14. I
OUT
0.06
0.05
0.04
0.03
0.02
0.01
0
-40
-20
0
20
40
60
80
Temperature˚C
AI13366
Figure 15. Total unadjusted error v’s DAC setting
0.022474
0.020395
0.018316
0.016237
0.014158
0.012079
0.01
1
17 33 49
65 81 97 113
DAC settling (decimal)
AI13367
19/27
Typical operating characteristics
Figure 16. Differential non-linearity v’s DAC setting
STVM100
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
1
17
33
49
65
81
97 113
DAC setting (decimal)
AI13368
Figure 17. Integral non-linearity v’s DAC setting
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
1
17 33 49 65 81 97 113
DAC setting (decimal)
AI13369
20/27
STVM100
Typical operating characteristics
Figure 18. AV power-up response
DD
AV
DD
V
DD
VOUT
V
ai13370
SET
5ms/DIV
AV : 5V/DIV, V : 5V/DIV, V
: 1V/DIV, V : 1V/DIV
SET
DD
DD
OUT
Figure 19. Full scale-up response
SCL
SDA
VOUT
V
SET
ai13371
20µs/DIV
SCL: 5V/DIV, SDA: 5V/DIV, V
: 1V/DIV, V
: 1V/DIV
SET
OUT
21/27
Typical operating characteristics
Figure 20. Full scale-down response
STVM100
SCL
SDA
VOUT
V
SET
ai13372
20µs/DIV
SCL: 5V/DIV, SDA: 5V/DIV, V
: 1V/DIV, V
: 1V/DIV
OUT
SET
22/27
STVM100
Package mechanical
7
Package mechanical
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 21. MLPD-DFN 3 x 3 x.75mm, pitch 0.65, package mechanical data
D
D2
1
8
L
E
E2
e
b
A
A3 A1
0.08
EZ_ME
1. Drawing is not to scale.
Table 9.
Sym
MLPD-DFN 3 x 3 x .75mm, pitch 0.65, package mechanical data
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A3
b
0.75
0.02
0.20
0.30
3.00
2.38
3.00
1.64
0.65
0.40
0.70
0.00
0.80
0.05
0.0295
0.0008
0.0079
0.0118
0.1181
0.0937
0.1181
0.0646
0.0256
0.0157
0.0276
0.0000
0.0315
0.0020
0.25
2.23
0.35
2.48
0.0098
0.0878
0.0138
0.0976
D
D2
E
E2
e
1.49
–
1.74
–
0.0587
–
0.0685
–
L
0.30
0.50
0.0118
0.0197
23/27
Package mechanical
STVM100
Figure 22. TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note:
Drawing is not to scale.
Table 10. TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data
mm
Min
inches
Min
Sym
Typ
Max
Typ
Max
A
A1
A2
b
1.100
0.150
0.950
0.400
0.230
0.100
3.100
–
0.0433
0.0059
0.0374
0.0157
0.0091
0.0039
0.1220
–
0.050
0.750
0.250
0.130
0.0020
0.0295
0.0098
0.0051
0.850
0.0335
c
CP
D
3.000
0.650
4.900
3.000
0.550
0.950
2.900
–
0.1181
0.0256
0.1929
0.1181
0.0217
0.0374
0.1142
–
e
E
4.6500
2.900
0.400
5.150
3.100
0.700
0.1831
0.1142
0.0157
0.2028
0.1220
0.0276
E1
L
L1
α
0°
8
6°
0°
8
6°
N
24/27
STVM100
Part numbering
8
Part numbering
Table 11. Ordering information scheme
Example:
STVM100
DC
6
F
Device type
STVM100, VCOM calibrator with 7-bit DAC and I2C interface
Package
DC = TDFN8
DS = TSSOP8
Temperature range
6 = –40 to 85°C
Shipping method
E = ECOPACK package, tubes
F = ECOPACK package, tape & reel
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
25/27
Revision history
STVM100
9
Revision history
Table 12. Revision history
Date
Revision
Changes
09-May-2006
14-Jul-2006
1
2
Initial release.
Graphical and textual updates
Document status upgraded to Preliminary Data; changed the
wording of Input function to include ‘WRITE operations’ instead of
‘programming’ in Table 2: Pin names and functions; deleted some
bracketed text and modified the P bit function in Section 2.2: Read
mode; ensured that all of Equation 2 and Equation 3 were visible;
amalgamated 2 cells containing the same information (VDD) in
Table 7: DC and AC characteristics; deleted footnotes 2 and 3 of
Table 8: AC characteristics; updated package mechanical
information in Figure 21, Table 9, and Table 10.
08-Nov-2006
3
Reformatted Inside Cover Page according to new template; renamed
section 1 Device overview and section 2 Device operation; deleted
Signal names table; moved and renamed Table 2: Pin names and
functions, addedSection 6: Typical operating characteristics and
Figure 10 to Figure 20.
12-Feb-2007
4
20-Apr-2007
24-Jul-2007
5
6
Value added in Section 2.3: Write mode.
Document status upgraded to full datasheet.
26/27
STVM100
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27/27
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