TSA1002_04_技术文档

TSA1002

10-BIT, 50MSPS, 50mW A/D CONVERTER

NOT FOR NEW DESIGN

m 10-bit A/D converter in deep submicron

ORDER CODE

CMOS technology

m Single supply voltage: 2.5V

m Input range: 2Vpp differential

m 50Msps sampling frequency

m Ultra low power consumption: 50mW @

50Msps

m ENOB=9.6 @ 40Msps, Fin=24MHz

m SFDR typically up to 72dB @ 50Msps,

Fin=5MHz

Temperature

Part Number

Package

Conditioning

Marking

Range

TSA1002CF

TSA1002CFT

TSA1002IF

0 C to +70 C

-40 C to +85 C

TQFP48

Tray

SA1002C

SA1002I

Tape & Reel

Tray

TSA1002IFT

EVAL1002/AA

Tape & Reel

Evaluation board

m Built-in reference voltage with external bias

capability

PIN CONNECTIONS (top view)

m Pinout compatibility with TSA0801, TSA1001

and TSA1201

DESCRIPTION

index

37

corner

48 47 46 45 44 43 42 41 40 39 38

The TSA1002 is a 10-bit, 50Msps sampling

frequency Analog to Digital converter using a

CMOS technology combining high performances

and very low power consumption.

The TSA1002 is based on a pipeline structure and

digital error correction to provide excellent static

linearity and guarantee 9.6 effective bits at

Fs=40Msps, and Fin=24MHz.

NC

36

35

IPOL

1

NC

VREFP

2

3

34

VREFM

AGND

4

5

33 D0 (LSB)

32

D1

VIN

31

D2

6

7

AGND

30

29

28

D3

D4

D5

D6

D7

D8

VINB

AGND

INCM

TSA1002

8

9

A voltage reference is integrated in the circuit to

simplify the design and minimize external

components. It is nevertheless possible to use the

circuit with an external reference.

27

26

AGND 10

AVCC

11

12

25

13 14 15 16 17 18 19 20 21 22 23 24

Especially designed for high speed, low power

applications, the TSA1002 only dissipates 50mW

at 50Msps. A tri-state capability, available on the

output buffers, enables to address several slave

ADCs by a unique master.

The output data can be coded into two different

formats. A Data Ready signal is raised as the data

is valid on the output and can be used for

synchronization purposes.

PACKAGE

7 x 7 mm TQFP48

The TSA1002 is available in commercial (0 to

+70 C) and extended (-40 to +85 C) temperature

range, in a small 48 pins TQFP package.

APPLICATIONS

m Medical imaging and ultrasound

m Portable instrumentation

m Cable Modem Receivers

m High resolution fax and scanners

m High speed DSP interface

April 2004

1/20

TSA1002

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Values

0 to 3.3

Unit

V

1)

AVCC

DVCC

Analog Supply voltage

1)

V

Digital Supply voltage

1)

VCCB

IDout

Tstg

0 to 3.3

-100 to 100

+150

V

mA

C

Digital buffer Supply voltage

Digital output current

Storage temperature

Electrical Static Discharge

- HBM

ESD

2

1.5

A

KV

- CDM-JEDEC Standard

2)

Latch-up

Class

1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages

must never exceed -0.3V or VCC+0V

2) Corporate ST Microelectronics procedure number 0018695

OPERATING CONDITIONS

Symbol

Parameter

Min

Typ

Max

Unit

AVCC Analog Supply voltage

DVCC Digital Supply voltage

VCCB Digital buffer Supply voltage

2.25

0.5

2.5

1

2.7

1.8

V

1)

VREFP

VREFM

Forced top reference voltage

1)

0

0.5

1.1

V

Forced bottom reference voltage

INCM Forced input common mode voltage

0.2

0.5

1)Condition VRefP-VRefM>0.3V

BLOCK DIAGRAM

VREFP

+2.5V

GNDA

VIN

Reference

circuit

stage

INCM

stage

2

stage

n

IPOL

1

VINB

VREFM

DFSB

OEB

Sequencer-phase shifting

Digital data correction

CLK

Timing

DR

DO

TO

Buffers

D9

OR

GND

2/20

TSA1002

PIN CONNECTIONS (top view)

index

corner

37

48 47 46 45 44 43 42 41 40 39 38

NC

36

35

IPOL

1

VREFP

2

3

34

33

32

VREFM

AGND

4

5

D0 (LSB)

D1

VIN

31

30

29

28

6

7

D2

D3

D4

D5

D6

D7

D8

AGND

VINB

AGND

INCM

TSA1002

8

9

27

26

10

11

12

AGND

AVCC

25

13 14 15 16 17 18 19 20 21 22 23 24

PIN DESCRIPTION

Pin No

Name

Description

Observation

Pin No

Name

Description

Digital output

Observation

1

2

IPOL

Analog bias current input

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

D8

D7

D6

D5

D4

D3

D2

D1

CMOS output (2.5V)

VREFP Top voltage reference

1V

Digital output

3

VREFM Bottom voltage reference

0V

4

AGND

VIN

Analog ground

0V

5

Analog input

1Vpp

0V

6

AGND

VINB

Analog ground

7

Inverted analog input

Analog ground

1Vpp

0V

8

AGND

INCM

AGND

AVCC

DVCC

DGND

CLK

9

Input common mode

Analog ground

0.5V

0V

D0(LSB) Least Significant Bit output CMOS output (2.5V)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

NC

Non connected

Data Ready output

Analog power supply

Digital power supply

Digital ground

2.5V

0V

NC

DR

CMOS output (2.5V)

VCCB

GNDB

VCCB

NC

Digital Buffer power supply 2.5V

Digital Buffer ground 0V

Clock input

2.5V compatible CMOS input

0V

DGND

NC

Digital ground

Digital Buffer power supply 2.5V

Non connected

DGND

GNDB

VCCB

OR

Digital ground

0V

NC

Non connected

Digital buffer ground

OEB

DFSB

AVCC

AGND

Output Enable input

Data Format Select input

Analog power supply

Analog ground

2.5V compatible CMOS input

Digital buffer power supply 2.5V

Out Of Range output CMOS output (2.5V)

CMOS output (2.5V)

2.5V

0V

D9(MSB) Most Significant Bit output

3/20

TSA1002

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25 C (unless otherwise specified)

TIMING CHARACTERISTICS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

FS

DC

Sampling Frequency

Clock Duty Cycle

0.5

40

9

50

60

Msps

%

50

10

TC1

TC2

Clock pulse width (high)

Clock pulse width (low)

ns

9

ns

Data Output Delay (Fall of Clock 10pF load capacitance

to Data Valid)

Tod

Tpd

Ton

5

5.5

1

ns

cycles

ns

Data Pipeline delay

Falling edge of OEB to digital

output valid data

Rising edge of OEB to digital

output tri-state

Toff

1

ns

TIMING DIAGRAM

N+3

N+6

N+7

N+2

N-1

N+1

N+8

N

CLK

Tpd + Tod

OEB

Ton

N+1

Toff

Tod

DATA

OUT

N-7

N-3

N-5

N-4

N-1

N-2

N-6

N+2

DR

HZ state

4/20

TSA1002

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25 C (unless otherwise specified)

ANALOG INPUTS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

VIN-VINB Full scale reference voltage

2.0

13

Vpp

kΩ

Req

Cin

Equivalent input resistance

Input capacitance

5.0

pF

BW

Analog Input Bandwidth

Vin@ Full scale, FS=50Msps

1000

60

MHz

1)

ERB

Effective Resolution Bandwidth

1) See parameters definition for more information

REFERENCE VOLTAGE

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

0.91

0.88

1.20

1.18

50

1.03

1.14

1.16

1.35

1.36

100

V

VREFP Top internal reference voltage

1)

Tmin= -40 C to Tmax= 85 C

1.27

Vpol

Analog bias voltage

1)

Tmin= -40 C to Tmax= 85 C

Normal operating mode

Shutdown mode

Ipol

Analog bias current

70

0

µA

V

0.47

0.46

0.57

0.68

0.66

VINCM Input common mode voltage

1)

V

Tmin= -40 C to Tmax= 85 C

1) Not fully tested over the temperature range. Guaranteed by sampling.

5/20

TSA1002

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25 C (unless otherwise specified)

POWER CONSUMPTION

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

1)

15.6

18

mA

ICCA

Analog Supply current

2)

21

2

mA

Tmin= -40 C to Tmax= 85 C

1)

1.3

2.5

ICCD

Digital Supply Current

2

Tmin= -40 C to Tmax= 85 C

1)

5

ICCB

ICCBZ

Pd

Digital Buffer Supply Current

5

Tmin= -40 C to Tmax= 85 C

1)

Digital Buffer Supply Current in

High Impedance Mode

40

48

100

µA

1)

60

62

mW

Power consumption in normal

operation mode

2)

Tmin= -40 C to Tmax= 85 C

1)

Power consumption in High

Impedance mode

PdZ

43

80

48

mW

C/W

Junction-ambient thermal resis-

tor (TQFP48)

Rthja

1) Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF

2) Not fully tested over the temperature range. Guaranteed by sampling.

DIGITAL INPUTS AND OUTPUTS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Digital inputs

VIL

Logic "0" voltage

Logic "1" voltage

0.8

V

VIH

2.0

Digital Outputs

VOL

VOH

IOZ

Logic "0" voltage

Logic "1" voltage

Iol=10µA

Ioh=-10µA

0.4

V

2.4

High Impedance leakage current OEB set to VIH

Output Load Capacitance

-1.5

1.5

15

µA

pF

C

L

ACCURACY

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Fin= 2MHz, VIN@+1dBFS

OE

DNL

INL

Offset Error

-40

-0.7

-0.8

-2

40

mV

LSB

Differential Non Linearity

Integral Non Linearity

±0.2

±0.3

+0.7

+0.8

Fin= 2MHz, VIN@+1dBFS

Monotonicity and no missing

codes

-

Guaranteed

6/20

TSA1002

CONDITIONS

AVCC = DVCC = 2.5V, Fs= 40Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25 C (unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol

Parameter

Test conditions

Fin= 5MHz

Min

Typ

Max

Unit

-79.2

-77

-65.5

-68.5

-63.4

1)

2)

1)

2)

1)

2)

dBc

Fin= 10MHz

Fin= 24MHz

-69

SFDR Spurious Free Dynamic Range

Fin= 5MHz

-61.5

-62.8

-58.5

dBc

dB

Fin= 10MHz

Fin= 24MHz

Fin= 5MHz

58.5

58.3

57.4

59.5

59.4

59.0

Fin= 10MHz

Fin= 24MHz

SNR

Signal to Noise Ratio

Fin= 5MHz

57.9

57.1

55.9

dB

Fin= 10MHz

Fin= 24MHz

Fin= 5MHz

-77.8

-76

-63.5

-67.4

-62.5

dB

Fin= 10MHz

Fin= 24MHz

-68.1

THD

Total Harmonic Distortion

Fin= 5MHz

-62.3

-60.7

-57.6

dB

Fin= 10MHz

Fin= 24MHz

Fin= 5MHz

58.5

58.2

57.0

59.4

59.3

58.5

1)

dB

Fin= 10MHz

Fin= 24MHz

Signal to Noise and Distortion

Ratio

SINAD

Fin= 5MHz

57.8

56.9

55.3

2)

dB

Fin= 10MHz

Fin= 24MHz

Fin= 5MHz

9.6

9.5

9.3

9.76

9.71

9.60

1)

bits

Fin= 10MHz

Fin= 24MHz

ENOB Effective Number of Bits

Fin= 5MHz

9.4

9.3

9

2)

Fin= 10MHz

Fin= 24MHz

1) Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF

2) Tmin= -40 C to Tmax= 85 C. Not fully tested over the temperature range. Guaranteed by sampling.

7/20

TSA1002

DEFINITIONS OF SPECIFIED PARAMETERS

STATIC PARAMETERS

Signal to Noise Ratio (SNR)

The ratio of the rms value of the fundamental

component to the rms sum of all other spectral

components in the Nyquist band (f /2) excluding

DC, fundamental and the first five harmonics.

SNR is reported in dB.

s

Static measurements are performed through

method of histograms on a 2MHz input signal,

sampled at 40Msps, which is high enough to fully

characterize the test frequency response. The

input level is +1dBFS to saturate the signal.

Signal to Noise and Distortion Ratio (SINAD)

Similar ratio as for SNR but including the harmonic

distortion components in the noise figure (not DC

signal). It is expressed in dB.

From the SINAD, the Effective Number of Bits

(ENOB) can easily be deduced using the formula:

Differential Non Linearity (DNL)

The average deviation of any output code width

from the ideal code width of 1 LSB.

SINAD= 6.02 × ENOB + 1.76 dB.

When the applied signal is not Full Scale (FS), but

Integral Non linearity (INL)

has an A amplitude, the SINAD expression

becomes:

An ideal converter presents a transfer function as

being the straight line from the starting code to the

ending code. The INL is the deviation for each

transition from this ideal curve.

0

SINAD =SINAD

+ 20 log (2A /FS)

0

2Ao

Full Scale

SINAD =6.02 × ENOB + 1.76 dB + 20 log (2A /

2Ao

0

FS)

The ENOB is expressed in bits.

DYNAMIC PARAMETERS

Dynamic measurements are performed by

spectral analysis, applied to an input sine wave of

various frequencies and sampled at 40Msps.

Analog Input Bandwidth

The maximum analog input frequency at which the

spectral response of a full power signal is reduced

by 3dB. Higher values can be achieved with

smaller input levels.

The input level is -1dBFS to measure the linear

behavior of the converter. All the parameters are

given without correction for the full scale ampli-

tude performance except the calculated ENOB

parameter.

Effective Resolution Bandwidth (ERB)

The band of input signal frequencies that the ADC

is intended to convert without loosing linearity i.e.

the maximum analog input frequency at which the

SINAD is decreased by 3dB or the ENOB by 1/2

bit.

Spurious Free Dynamic Range (SFDR)

The ratio between the power of the worst spurious

signal (not always an harmonic) and the amplitude

of fundamental tone (signal power) over the full

Nyquist band. It is expressed in dBc.

Pipeline delay

Delay between the initial sample of the analog

input and the availability of the corresponding

digital data output, on the output bus. Also called

data latency. It is expressed as a number of clock

cycles.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first five harmonic

distortion components to the rms value of the

fundamental line. It is expressed in dB.

8/20

TSA1002

Static parameter: Integral Non Linearity

Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts

0 .8

0 .6

0 .4

0 .2

0

-0 .2

-0 .4

-0 .6

-0 .8

0

2 00

4 0 0

60 0

8 00

1 0 00

O u tp u t C o d e

Static parameter: Differential Non Linearity

Fs=50MSPS;Fin=1MHz;Icc=20mA;N=131072pts

0 .5

0 .4

0 .3

0 .2

0 .1

0

-0 .1

-0 .2

-0 .3

-0 .4

-0 .5

0

2 0 0

4 0 0

6 0 0

8 0 0

1 0 0 0

O u tp u t C o d e

Linearity vs. Fs

Distortion vs. Fs

Fin=5MHz; Rpol adjustment

-30

-40

-50

-60

100

10

9

90

ENOB

80

70

8

THD

-70

-80

7

SNR

60

SFDR

6

-90

SINAD

50

40

30

-100

-110

-120

5

4

25

35

45

55

25

35

45

55

Fs (MHz)

9/20

TSA1002

Linearity vs. Fs

Distortion vs. Fs

Fin=15MHz; Rpol adjustment

100

10

9

-30

-40

-50

90

ENOB

80

70

THD

8

-60

-70

7

SNR

SINAD

SFDR

-80

60

50

-90

6

-100

-110

-120

5

40

30

4

25

35

45

55

25

35

45

55

Fs (MHz)

Linearity vs. Fin

Distortion vs. Fin

Fs=50MSPS; Icca=20mA

80

10

-30

-40

-50

-60

9.5

9

75

ENOB

70

8.5

8

65

THD

SNR

SINAD

60

7.5

7

-70

-80

55

50

45

40

SFDR

6.5

6

-90

5.5

5

-100

0

20

40

60

0

20

40

60

Fin (MHz)

Linearity vs.Temperature

Distortion vs. Temperature

Fs=50MSPS; Icca=20mA; Fin=5MHz

Fs=50MSPS; Icca=20mA; Fin=5MHz;

90

85

70

10

9.8

9.6

9.4

9.2

9

8.8

8.6

8.4

8.2

8

ENOB

65

80

SFDR

75

SNR

60

70

THD

65

55

SINAD

60

55

50

45

50

45

-40

10

60

-40

10

60

Temperature ( C)

10/20

TSA1002

Linearity vs. AVcc

Distortion vs. AVcc

Fs=50MSPS; Icca=20mA; Fin=1MHz

-50

-55

-60

-65

64

63

62

10

9.9

9.8

9.7

9.6

9.5

9.4

9.3

9.2

9.1

9

61

SFDR

-70

ENOB

60

-75

THD

-80

SNR

59

58

57

56

-85

-90

SINAD

-95

-100

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

AVCC (V)

Linearity vs. DVcc

Distortion vs. DVcc

Fs=50MSPS; Icca=20mA; Fin=1MHz

64

62

10

-40

-50

-60

9.9

9.8

9.7

9.6

9.5

9.4

SNR

60

58

ENOB

SFDR

-70

56

-80

THD

54

SINAD

-90

52

50

-100

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

DVCC (V)

Linearity vs. VccB

Distortion vs. VccB

Fs=50MSPS; Icca=20mA; Fin=1MHz

70

68

66

10

-40

-50

-60

9.9

9.8

9.7

9.6

9.5

9.4

9.3

9.2

9.1

9

ENOB

64

62

-70

-80

THD

SNR

60

58

56

54

SFDR

SINAD

-90

-100

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

VCCB (V)

11/20

TSA1002 APPLICATION NOTE

DETAILED INFORMATION

couple for each stage. The corrected data are

outputted through the digital buffers.

Input signal is sampled on the rising edge of the

clock while digital outputs are delivered on the

falling edge of the Data Ready signal.

The advantages of such a converter reside in the

combination of pipeline architecture and the most

advanced technologies. The highest dynamic

performances are achieved while consumption

remains at the lowest level.

The TSA1002 is a high speed analog to digital

converter based on a pipeline architecture and the

latest deep submicron CMOS process to achieve

the best performances in terms of linearity and

power consumption.

The pipeline structure consists of 9 internal

conversion stages in which the analog signal is

fed and sequentially converted into digital data.

Some functionalities have been added in order to

simplify as much as possible the application

board. These operational modes are described in

the following table.

The TSA1002 is pin to pin compatible with the

8bits/40Msps TSA0801, the 10bits/25Msps

TSA1001 and the 12bits/50Msps TSA1201. This

ensures a conformity within the product family and

above all, an easy upgrade of the application.

Each 8 first stages consists of an Analog to Digital

converter, a Digital to Analog converter, a Sample

and Hold and a gain of 2 amplifier. A 1.5bit

conversion resolution is achieved in each stage.

The latest stage simply is a comparator. Each

resulting LSB-MSB couple is then time shifted to

recover from the conversion delay. Digital data

correction completes the processing by

recovering from the redundancy of the (LSB-MSB)

OPERATIONAL MODES DESCRIPTION

Inputs

Outputs

Analog input differential level

DFSB

OEB

OR

DR

Most Significant Bit (MSB)

(VIN-VINB)

>

RANGE

H

L

H

CLK

HZ

D9

-RANGE

RANGE>

(VIN-VINB)

-RANGE

>

(VIN-VINB)

>-RANGE

RANGE

D9

(VIN-VINB)

L

D9

>

H

Complemented D9

HZ

>

(VIN-VINB)

X

(VIN-VINB)

>-RANGE

L

H

RANGE>

L

X

HZ

Data Format Select (DFSB)

When OEB is set to low level again, the data is

then valid on the output with a very short Ton

delay.

The timing diagram page 4 summarizes this

operating cycle.

When set to low level (VIL), the digital input DFSB

provides a twoís complement digital output MSB.

This can be of interest when performing some

further signal processing.

When set to high level (VIH), DFSB provides a

standard binary output coding.

Out of Range (OR)

This function is implemented on the output stage

in order to set up an "Out of Range" flag whenever

the digital data is over the full scale range.

Typically, there is a detection of all the data being

at í0í or all the data being at í1í. This ends up with

an output signal OR which is in low level state

(VOL) when the data stay within the range, or in

high level state (VOH) when the data are out of the

range.

Output Enable (OEB)

When set to low level (VIL), all digital outputs

remain active and are in low impedance state.

When set to high level (VIH), all digital outputs

buffers are in high impedance state. This results in

lower consumption while the converter goes on

sampling.

12/20

TSA1002

Data Ready (DR)

The VREFP, VREFM voltages set the analog

dynamic at the input of the converter that has a full

scale amplitude of 2*(VREFP-VREFM).

The Data Ready output is an image of the clock

being synchronized on the output data (D0 to D9).

This is a very helpful signal that simplifies the

synchronization of the measurement equipment or

the controlling DSP.

As digital output, DR goes in high impedance state

when OEB is asserted to High level as described

in the timing diagram page 4.

In case of analog dynamic lower than 2Vpp, the

best linearity and distortion performance is

achieved while increasing the VREFM voltage

instead of lowering the VREFP one.

The INCM is the mid voltage of the analog input

signal.

It is possible to use an external reference voltage

device for specific applications requiring even

REFERENCES AND COMMON MODE

CONNECTION

better

linearity,

accuracy

or

enhanced

temperature behavior.

VREFM must be always connected externally.

Using the STMicroelectronics TS821 or

TS4041-1.2 Vref leads to optimum performances

when configured as shown on Figure 2.

Internal reference and common mode

In the default configuration, the ADC operates with

its own reference and common mode voltages

generated by its internal bandgap. VREFM pin is

connected externally to the Analog Ground while

VREFP (respectively INCM) is set to its internal

voltage of 1.03V (respectively 0.57V). It is

recommended to decouple the VREFP in order to

minimize low and high frequency noise (refer to

Figure 1)

Figure 2 : External reference setting

1kΩ

330pF 10nF 4.7uF

VCCA VREFP

VIN

TS821

TS4041

TSA1002

Figure 1 : Internal reference and common mode

setting

VINB

external

reference

VREFM

1.03V

330pF 10nF 4.7uF

VREFP

VIN

TSA1002

0.57V

INCM

At 15Msps sampling frequency, 1MHz input

frequency and -1dBFS amplitude signal,

performances can be improved up to 2dB on

SFDR and 0.3dB on SINAD. At 50Msps sampling

frequency, 1MHz input frequency and -1dBFS

amplitude signal, performances can be improved

up to 1dBc on SFDR and 0.6dB on SINAD.

330pF 10nF 4.7uF

VINB

VREFM

External reference and common mode

This can be very helpful for example for

multichannel application to keep a good matching

among the sampling frequency range.

Each of the voltages VREFM, VREFP and INCM

can be fixed externally to better fit to the

application needs (Refer to Table íOPERATING

CONDITIONSí p2 for min and max values).

13/20

TSA1002

DRIVING THE ANALOG INPUT

Differential inputs

Figure 4 represents the biasing of a differential

input signal in AC-coupled differential input

configuration. Both inputs VIN and VINB are

centered around the common mode voltage, that

can be let internal or fixed externally.

The TSA1002 has been designed to obtain

optimum performances when being differentially

driven. An RF transformer is a good way to

achieve such performances.

Figure 5 shows a DC-coupled configuration with

forced INCM to the DC analog input (mid-voltage)

while VREFM is connected to ground and VREFP

is let internal (1V); we achieve a 2Vpp differential

amplitude.

Figure 3 describes the schematics. The input

signal is fed to the primary of the transformer,

while the secondary drives both ADC inputs.

Figure 3 : Differential input configuration with

transformer

Figure 5 : DC-coupled 2Vpp differential analog

input

ADT1-1

Analog source

1:1

analog

AC+DC

VREFP

VIN

DC

TSA1002

VINB

50Ω

100pF

TSA1002

VINB

INCM

VREFM

INCM

330pF

10nF

4.7uF

10nF

330pF

4.7uF

VREFP-VREFM = 1 V

The common mode voltage of the ADC (INCM) is

connected to the center-tap of the secondary of

the transformer in order to bias the input signal

around this common voltage, internally set to

0.57V. The INCM is decoupled to maintain a low

noise level on this node. Our evaluation board is

mounted with a 1:1 ADT1-1WT transformer from

Single-ended input configuration

The single-ended input configuration of the

TSA1002 requires particular biasing and driving.

The structure being fully differential, care has to

be taken in order to properly bias the inputs in sin-

gle ended mode. Figure 6 summarizes the link

from the differential configuration to the sin-

gle-ended one; a wrong configuration is also pre-

sented.

Minicircuits. You might also use

a higher

impedance ratio (1:2 or 1:4) to reduce the driving

requirement on the analog signal source. For

example, with internal references, each analog

input can drive a 1Vpp amplitude input signal, so

the resultant differential amplitude is 2Vpp.

- With differential driving, both inputs are centered

around the INCM voltage.

- The transition to single-ended configuration

implies to connect the unused input (VINB for

instance) to the DC component of the single input

(Vin) and also to the input common mode in order

to be well balanced. The mid-code is achieved at

the crossing between VIN and VINB, therefore

inputs are conveniently biased.

Figure 4 : AC-coupled differential input

VIN

10nF

50Ω

100kΩ

TSA1002

33pF

INCM

common

- Unlikely other structures of converters in which

the unused input can be grounded; in our case it

will end with unbalanced inputs and saturation of

the internal amplifiers leading to a non respect of

the output codes.

mode

100kΩ

VINB

10nF

50Ω

14/20

TSA1002

Figure 6 : Input dynamic range for the various configurations

Differential configuration

Single-ended configuration:

balanced inputs

Single-ended configuration:

unbalanced inputs

+FS: code 1023

+FS + offset: code > 1023

VIN - VINB

+FS: code 1023

VIN - VINB

VIN

VINB

VIN

0: code 511

VINB

INCM

VIN

0: code 511

-FS: code 0

-FS + offset: code > 0

-FS: code 0

Ao + ac

VIN

VINB

INCM

Ao

Wrong configuration!

The applications requiring single-ended inputs

can be configured like reported on Figure 7 for an

AC-coupled input or on Figure 8 and 9 for a

DC-coupled input.

Figure 8 : DC-coupled 2Vpp analog input

Analog

AC+DC

VREFP

VIN

DC

TSA1002

In the case of AC-coupled analog input, the

analog inputs Vin and Vinb are biased to the same

voltage that is the common mode voltage of the

circuit (INCM). The INCM and reference voltages

may remain at their internal level but can also be

fixed externally.

VINB

VREFM

INCM

330pF

10nF

4.7uF

VREFP-VREFM = 1 V

Figure 7 : AC-coupled Single-ended input

Figure 9 : DC-coupled 1Vpp analog input

Signal source

Analog

AC+DC

10nF

VIN

DC

100kΩ

50Ω

33pF

TSA1002

VINB

INCM

VINB

VREFM

INCM

common

mode

0.5V power supply

In the case of DC-coupled analog input with 1V

DC signal, the DC component of the analog input

set the common mode voltage. As an example fig-

ure 8, INCM is set to the 1V DC analog input while

VREFM is connected to ground and VREFP let in-

ternal; we achieve a 2Vpp differential amplitude.

330pF

10nF

4.7uF

VREFP-VREFM = 0.5 V

Dynamic characteristics, while not being as

remarkable as for differential configuration, are

still of very good quality. Measurements done at

50Msps, 2MHz input frequency, -1dBFS input

level sum up these performances. An SFDR of

-64.5dBc, a SNR of 57.8dB and an ENOB Full

Scale of 9.3bits are achieved.

Figure 9 describes a configuration for a 1Vpp

analog signal with a 0.5V DC input. In this case,

while VREFP is kept internally at 1V, VREFM is

connected to VINB and INCM externally to 0.5V;

the dynamic is then 1Vpp (VREFP-VREFM=0.5V).

15/20

TSA1002

Power consumption

Distortion vs. Duty cycle

Fs=50MSPS; consumption optimized; Fin=1MHz

The internal architecture of the TSA1002 enables

to optimize the power consumption according to

the sampling frequency of the application. For this

purpose, a resistor is placed between IPOL and

the analog Ground pins. The figure 10 sums up

the relevant data.

The TSA1002 will combine highest performances

and lowest consumption at 50Msps when Rpol is

in the range of 12kΩ to 20kΩ.

-30

70

-40

60

-50

-60

50

THD

-70

40

SFDR

-80

At lower sampling frequency, this value of resistor

may be changed and the consumption will

decrease as well.

-90

-100

-110

-120

30

20

10

IccA

Figure 10 : Analog Current consumption vs. Fs

According value of Rpol polarization resistance

30

40

50

60

70

Duty Cycle (%)

60

50

40

30

20

10

0

20

18

16

14

12

10

8

RPOL

Linearity vs. Duty cycle

Fs=50MSPS; Icca=20mA; Fin=10MHz

80

10

9.5

9

ENOB

75

6

ICCA

70

65

4

2

8.5

8

SNR

0

60

25

35

45

55

65

75

55

7.5

7

SINAD

Fs (MHz)

50

45

40

35

30

6.5

6

Linearity, distortion performance towards

Clock Duty Cycle variation

5.5

5

40

45

50

55

60

The TSA1002 has an outstanding behaviour

towards clock duty cycle variation and it may be

also reinforced with adjustment of analog current

consumption.

Duty Cycle (%)

Distortion vs. Duty cycle

Fs=50MSPS; Icca=20mA; Fin=10MHz

Linearity vs. Duty cycle

Fs=50MSPS; consumption optimized; Fin=1MHz

0

-10

-20

-30

-40

80

70

60

50

40

30

20

10

0

10

9

ENOB

SNR

SINAD

8

7

-50

THD

-60

6

IccA

-70

SFDR

5

-80

-90

4

-100

3

40

45

50

55

60

30

40

50

60

70

Duty Cycle (%)

16/20

TSA1002

Clock input

- Proper termination of all inputs and outputs is

needed; with output termination resistors, the

amplifier load will be only resistive and the stability

of the amplifier will be improved. All leads must be

wide and as short as possible especially for the

analog input in order to decrease parasitic

capacitance and inductance.

The quality of your converter is very dependant on

your clock input accuracy, in terms of aperture

jitter; the use of low jitter crystal controlled

oscillator is recommended.

The clock power supplies must be separated from

the ADC output ones to avoid digital noise

modulation at the output.

- To keep the capacitive loading as low as

possible at digital outputs, short lead lengths of

routing are essential to minimize currents when

the output changes. To minimize this output

capacitance, buffers or latches close to the output

pins will relax this constraint.

It is recommended to keep the circuit clocked, to

avoid random states, before applying the supply

voltages.

Layout precautions

- Choose component sizes as small as possible

(SMD).

To use the ADC circuits in the best manner at high

frequencies, some precautions have to be taken

for power supplies:

EVAL1002 evaluation board

- First of all, the implementation of 4 separate

proper supplies and ground planes (analog,

digital, internal and external buffer ones) on the

PCB is recommended for high speed circuit

applications to provide low inductance and low

resistance common return.

The characterization of the board has been made

with a fully ADC devoted test bench as shown on

Figure 11. The analog signal must be filtered to be

very pure.

The dataready signal is the acquisition clock of the

logic analyzer.

The separation of the analog signal from the

digital part is essential to prevent noise from

coupling onto the input signal.

The ADC digital outputs are latched by the

74LCX573 octal buffers.

- Power supply bypass capacitors must be placed

as close as possible to the IC pins in order to

improve high frequency bypassing and reduce

harmonic distortion.

All characterization measurement has been made

with an input amplitude of +0.2dB for static

parameters and -0.5dB for dynamic parameters.

Figure 11 : Analog to Digital Converter characterization bench

HP8644

Data

ADC

evaluation

board

Vin

Sine Wave

Generator

Logic

Analyzer

PC

Clk

Pulse

HP8133

HP8644

Generator

Sine Wave

Generator

17/20

TSA1002

Figure 12: TSA1002 Evaluation board schematic

+

18/20

TSA1002

Figure 13: Printed circuit of evaluation board

Printed circuit board - List of components

P art

Design Footprint

ator

P art

Type

D esign Foo tprint

ator

P art

D esign F ootprint

ato r

P art

D esign Footprint

ato r

Type

10 uF

Type

C 2 4

C 2 3

C 4 1

C 2 9

12 10

6 0 3

603

ID C 32

330pF C 33

330pF C 20

330pF C 8

330pF C 2

330pF C 5

330pF C 11

330pF C 30

330pF C 17

330pF C 14

603

C A P

805

470nF

C 7

805

A VC C

C LJ/ SM B

A GN D

D FSB

J12

J4

FIC H E2M M

SM B / H

C 16

C 19

C 3

805

J19

J9

FIC H E2M M

AD T

805

10 0 pF C 1

47K

Ω

R 12

R 14

R 11

R aj1

R 10

R 19

R 13

R 15

R 16

R 17

R 18

R 3

603

D GN D

D VC C

GndB1

GndB2

J20

J15

J22

J21

10 nF

C 12

C 3 9

C 15

C 4 0

C 2 7

C 4

603

VR5

603

M es com mode J8

47uF

C 36

C 34

C 35

C 42

603

OEB

J10

603

R egl co m mode J7

C 2 1

C 3 1

C 6

603

T2-A T1-1WT

VccB 1

T2

T1

J18

J17

J1

603

AD T

470nF C 22

470nF C 32

470nF C 37

470nF C 38

470nF C 13

470nF C 28

470nF C 10

603

FIC H E2M M

SM B / H

C 9

603

VD D B UFF3V

Vin

C 18

R2

50

Ω

603

1K

Ω

R 1

603

VrefM

J5

FIC H E2M M

TQFP 48

32P IN J6

74LC X573 U3

74LC X573 U2

T SSOP 20

SIP 2

VrefP

J2

330pF C25

330pF C26

603

TSA 1002

U1

CON 2

J16

19/20

TSA1002

PACKAGE MECHANICAL DATA

48 PINS - PLASTIC PACKAGE

A

A2

A1

e

48

37

0,10 mm

.004 inch

SEATING PLANE

1

36

25

12

c

13

24

D3

D1

D

0,25 mm

.010 inch

GAGE PLANE

K

Millimeters

Typ.

Inches

Typ.

Dim.

Min.

Max.

Min.

Max.

A

1.60

0.15

1.45

0.27

0.20

0.063

0.006

0.057

0.011

0.008

A1

A2

B

0.05

1.35

0.17

0.09

0.002

0.053

0.007

0.004

1.40

0.22

0.055

0.009

C

D

9.00

7.00

5.50

0.50

9.00

7.00

5.50

0.60

1.00

0.354

0.276

0.216

0.0197

0.354

0.276

0.216

0.024

0.039

D1

D3

e

E

E1

E3

L

0.45

0.75

0.018

0.030

L1

K

0 (min.), 7 (max.)

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia

Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States

20/20


型号：	TSA1002_04
厂家：	ST
描述：	10-BIT, 50MSPS, 50mW A/D CONVERTER 10位， 50MSPS ， 50mW的A / D转换器转换器
文件：	总20页 (文件大小：239K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSA1002_04 [STMICROELECTRONICS]

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