VND5050AJ-E_08 [STMICROELECTRONICS]
Double channel high side driver with analog current sense for automotive applications; 具有模拟电流检测用于汽车应用的双通道高侧驱动器
| 型号： | VND5050AJ-E_08 |
| 厂家： | 
ST |
| 描述： | Double channel high side driver with analog current sense for automotive applications |
| 文件： | 总38页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5050AJ-E
VND5050AK-E
Double channel high side driver with analog current sense
for automotive applications
Features
Max transient supply voltage
Operating voltage range
VCC
41V
VCC 4.5 to 36V
Max On-State resistance (per ch.) RON
50 mΩ
18 A
2 µA(1)
PowerSSO-12 PowerSSO-24
Current limitation (typ)
ILIMH
IS
Off state supply current
Application
1. Typical value with all loads connected
■ All types of resistive, inductive and capacitive
■ Main
loads
– Inrush current active management by
power limitation
■ Suitable as LED driver
– Very low stand-by current
Description
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/ec
european directive
The VND5050AJ-E, VND5050AK-E is a
monolithic device made using STMicroelectronics
VIPower M0-5 technology. It is intended for driving
resistive or inductive loads with one side
connected to ground. Active V pin voltage
CC
■ Diagnostic Functions
clamp protects the device against low energy
spikes (see ISO7637 transient compatibility
table).
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
■ Protections
When CS_DIS is driven high, the current sense
pin is in a high impedance condition.
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Thermal shut down
– Reverse battery protection (see Application
schematic)
– Electrostatic discharge protection
February 2008
Rev 7
1/38
www.st.com
38
Contents
VND5050AJ-E / VND5050AK-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1
3.1.2
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21
Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
4.2
PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
5.2
5.3
5.4
5.5
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-24™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/38
VND5050AJ-E / VND5050AK-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 8.
Table 7.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8V<V <16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PowerSSO-12™ thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24™ thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3/38
List of figure
VND5050AJ-E / VND5050AK-E
List of figure
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6.
Figure 7.
Figure 8.
Figure 9.
I
/I
Vs. I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT SENSE
OUT
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On state resistance Vs. T
Figure 18. On state resistance Vs. V
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Vs. T
I
LIMH
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Maximum turn Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 24
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel ON) . . . 25
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 27
Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one channel ON) . . 28
Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28
Figure 36. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 37. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 38. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TM
Figure 40. PowerSS0-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TM
Figure 41. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4/38
VND5050AJ-E / VND5050AK-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
V
CC
UNDERVOLTAGE
V
CC
CLAMP
OUTPUT1
PwCLAMP 1
CURRENT
SENSE1
GND
DRIVER 1
I
1
LIM
PwCLAMP 2
INPUT1
DRIVER 2
V
1
LOGIC
OUTPUT2
DSLIM
Pwr
1
LIM
I
2
LIM
CURRENT
SENSE2
OVERTEMP. 1
K 1
V
2
DSLIM
INPUT2
CS_DIS
I
OUT1
OVERTEMP. 2
K 2
I
OUT2
Pwr
2
LIM
Table 1.
Name
Pin function
Function
VCC
Battery connection.
OUTPUT1,2 Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor
network.
GND
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
INPUT1,2
CURRENT
SENSE1,2
Analog current sense pin, delivers a current proportional to the load current
Active high CMOS compatible pin, to disable the current sense pin.
CS_DIS
5/38
Block diagram and pin description
Figure 2. Configuration diagram (top view)
VND5050AJ-E / VND5050AK-E
TAB = V
cc
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
V
CC
GND
N.C.
INPUT2
N.C.
INPUT1
12
11
10
9
8
7
GND
V
1
2
3
4
5
6
cc
INPUT2
INPUT1
CURRENT SENSE1
CURRENT SENSE2
CS_DIS
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
V
cc
CS_DIS.
V
CC
TAB = VCC
PowerSSO-12
PowerSSO-24
Table 2.
Suggested connections for unused and N.C. pins
Connection / pin
Current Sense
N.C.
Output
Input
CS_DIS
Floating
N.R.(1)
X
X
X
X
Through 1KΩ
Through 10KΩ
Through10KΩ
To ground
X
N.R.(1)
resistor
resistor
resistor
1. Not recommended.
6/38
VND5050AJ-E / VND5050AK-E
Electrical specifications
2
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VCC
VFn
IOUT1
ICSD
OUTPUT1
CS_DIS
INPUT1
INPUT2
VOUT1
VCSD
ISENSE1
CURRENT
SENSE1
IIN1
VSENSE1
VIN1
IOUT2
IIN2
VIN2
OUTPUT2
VOUT2
ISENSE2
CURRENT
SENSE2
GND
VSENSE2
IGND
Note:
V
= V
- V during reverse battery condition.
Fn
OUTn CC
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
DC supply voltage
41
0.3
V
V
-VCC
Reverse DC supply voltage
-IGND DC reverse ground pin current
200
mA
A
IOUT
-IOUT
IIN
DC output current
Internally limited
12
Reverse DC output current
DC input current
A
-1 to 10
-1 to 10
200
mA
mA
mA
ICSD
DC current sense disable input current
-ICSENSE DC reverse CS pin current
V
CC-41
V
V
VCSENSE Current sense maximum voltage
+VCC
Maximum switching energy
EMAX
104
mJ
(L= 3mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C; IOUT = IlimL(Typ.))
7/38
Electrical specifications
VND5050AJ-E / VND5050AK-E
Table 3.
Symbol
Absolute maximum ratings (continued)
Parameter
Value
Unit
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
4000
2000
4000
5000
5000
V
V
V
V
V
– INPUT
– CURRENT SENSE
– CS_DIS
VESD
– OUTPUT
– VCC
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
°C
Tstg
2.2
Thermal data
Table 4.
Thermal data
Value
Symbol
Parameter
Unit
PowerSSO-12
PowerSSO-24
Thermal resistance junction-case (Max.)
(with one channel ON)
Rthj-case
2.7
2.7
°C/W
°C/W
Thermal resistance junction-ambient
(Max.)
Rthj-amb
See Figure 29
See Figure 33
8/38
VND5050AJ-E / VND5050AK-E
Electrical specifications
2.3
Electrical characteristics
8V<V <36V; -40°C<T <150°C, unless otherwise specified.
CC
j
Table 5.
Symbol
Power section
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
Undervoltage shutdown
4.5
13
36
V
V
VUSD
3.5
4.5
Undervoltage shut-down
hysteresis
VUSDhyst
0.5
V
IOUT= 2A; Tj= 25°C
50
100
65
mΩ
mΩ
mΩ
RON
On state resistance (2)
Clamp voltage
IOUT= 2A; Tj= 150°C
IOUT= 2A; VCC= 5V; Tj= 25°C
Vclamp
IS= 20mA
41
46
52
V
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
IS
Supply current
2(1)
3
5(1)
6
µA
On State; VCC=13V; VIN=5V;
IOUT= 0A
mA
VIN=VOUT=0V; VCC=13V;
Tj= 25°C
0
0
0.01
3
Off state output
current(2)
IL(off)
µA
V
VIN=VOUT=0V; VCC=13V;
Tj= 125°C
5
Output - V diode
CC
VF
-IOUT=4A; Tj=150°C
0.7
(2)
voltage
1. PowerMOS leakage included.
2. For each channel.
Table 6.
Symbol
Switching (V = 13V; T = 25°C)
CC j
Parameter
Test conditions
Min. Typ. Max. Unit
td(on)
td(off)
Turn-On delay time
Turn-Off delay time
Turn-On voltage slope
Turn-Off voltage slope
RL= 6.5Ω (see Figure 8)
RL= 6.5Ω (see Figure 8)
RL= 6.5Ω
25
µs
µs
35
dV
dV
/dt
See Figure 21
See Figure 22
V/ µs
V/ µs
OUT (on)
/dt
RL= 6.5Ω
OUT (off)
Switching energy losses
during twon
WON
RL= 6.5Ω (see Figure 8)
RL= 6.5Ω (see Figure 8)
0.24
0.2
mJ
mJ
Switching energy losses
during twoff
WOFF
9/38
Electrical specifications
VND5050AJ-E / VND5050AK-E
Min. Typ. Max. Unit
Table 7.
Symbol
Logic input
Parameter
Test conditions
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
0.9
V
µA
V
VIN= 0.9V
1
VIH
2.1
IIH
VIN= 2.1V
10
µA
V
VI(hyst)
0.25
5.5
IIN= 1mA
IIN= -1mA
7
V
V
VICL
VCSDL
ICSDL
Input clamp voltage
-0.7
CS_DIS low level voltage
0.9
V
Low level CS_DIS
current
VCSD= 0.9V
1
µA
CS_DIS high level
voltage
VCSDH
ICSDH
VCSD(hyst)
2.1
V
µA
V
High level CS_DIS
current
V
CSD= 2.1V
10
7
CS_DIS hysteresis
voltage
0.25
5.5
I
CSD= 1mA
V
V
VCSCL
CS_DIS clamp voltage
ICSD= -1mA
-0.7
(1)
Table 8.
Symbol
Protections and diagnostics
Parameter
Test conditions
CC= 13V
Min.
Typ.
Max.
Unit
V
12
18
24
24
A
A
IlimH
DC short circuit current
5V<VCC<36V
Short circuit current
during thermal cycling
IlimL
VCC=13V; TR<Tj<TTSD
7
A
TTSD
TR
Shutdown temperature
Reset temperature
150
175
200
°C
°C
T
+ 1 TRS + 5
RS
Thermal reset of
STATUS
TRS
135
°C
°C
V
Thermal hysteresis
THYST
7
(T
-T )
R
TSD
Turn-off output voltage
clamp
VDEMAG
IOUT=2A; VIN=0; L=6mH VCC-41 VCC-46 VCC-52
IOUT=0.1A;
Output voltage drop
limitation
VON
Tj= -40°C...+150°C
25
mV
(see Figure 9)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/38
VND5050AJ-E / VND5050AK-E
Electrical specifications
Table 9.
Symbol
Current sense (8V<V <16V)
CC
Parameter
Test conditions
Min. Typ. Max. Unit
IOUT=0.05A;
VSENSE=0.5V;VCSD=0V;
K0
K1
IOUT/ISENSE
1270 2360 3450
Tj= -40°C...150°C
IOUT=1A; VSENSE=0.5V;VCSD=0V;
Tj= -40°C
IOUT/ISENSE
1470 2020 2610
1570 2020 2470
Tj= 25°C...150°C
IOUT=1A; VSENSE= 0.5V;
VCSD=0V;
Current sense ratio
drift
(1)
dK1/K1
-7
+7
%
%
%
TJ=-40 °C to 150 °C
IOUT=2A; VSENSE=4V;VCSD=0V;
Tj= -40°C
K2
IOUT/ISENSE
1740 2020 2320
1790 2020 2250
Tj= 25°C...150°C
IOUT=2 A; VSENSE= 4 V;
VCSD=0V;
Current sense ratio
drift
(1)
dK2/K2
-4
+4
TJ=-40 °C to 150 °C
IOUT=4A; VSENSE=4V;VCSD=0V;
Tj=-40°C
K3
IOUT/ISENSE
1880 2010 2160
1900 2010 2120
Tj=25°C...150°C
IOUT=4 A; VSENSE= 4 V;
VCSD=0V;
Current sense ratio
drift
(1)
dK3/K3
-2
+2
TJ=-40 °C to 150 °C
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V;
Tj=-40°C...150°C
0
0
1
2
µA
µA
VCSD=0V; VIN=5V;
Tj=-40°C...150°C
Analog sense
leakage current
ISENSE0
IOUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V;
Tj=-40°C...150°C
0
4
1
µA
Openload ON state
current detection
threshold
IOL
VIN = 5V, ISENSE= 5 µA
IOUT=4A; VCSD=0V
20
mA
Max analog sense
output voltage
VSENSE
5
V
V
Analog sense
output voltage in
overtemperature
condition
VSENSEH
VCC=13V; RSENSE=10KΩ
9
11/38
Electrical specifications
VND5050AJ-E / VND5050AK-E
Min. Typ. Max. Unit
Table 9.
Symbol
Current sense (8V<V <16V) (continued)
CC
Parameter
Test conditions
Analog sense
output current in
overtemperature
condition
ISENSEH
tDSENSE1H
tDSENSE1L
VCC=13V; VSENSE=5V
8
mA
µs
Delay response
time from falling
edge of CS_DIS
pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=90% of ISENSE max
(see Figure 4)
50
100
Delay response
time from rising
edge of CS_DIS
pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSE max
(see Figure 4)
5
20
µs
µs
VSENSE<4V, 0.5A<Iout<4A
ISENSE=90% of ISENSE max
(see Figure 4)
Delay response
tDSENSE2H time from rising
edge of INPUT pin
80
250
Delay response
time between rising
edge of output
current and rising
edge of current
sense
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX=2A (see Figure 5)
∆tDSEN
65
µs
µs
SE2H
VSENSE<4V, 0.5A<Iout<4A
Delay response
tDSENSE2L time from falling
edge of INPUT pin
ISENSE=10% of ISENSE max
100
250
(see Figure 4)
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
12/38
VND5050AJ-E / VND5050AK-E
Figure 5.
Electrical specifications
Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
V
IN
∆t
DSENSE2H
t
t
t
I
OUT
I
OUTMAX
90% I
OUTMAX
I
SENSE
I
SENSEMAX
90% I
SENSEMAX
13/38
Electrical specifications
Figure 6.
VND5050AJ-E / VND5050AK-E
I
/I
Vs. I
OUT SENSE OUT
IOUT/ISENSE
3000
2500
2000
1500
1000
500
M ax-40°C to 150°C
M ax25°C to 150°C
Typ 25°C
M in 25°C to 150°C
M in -40°C to 150°C
1
2
3
4
5
IOUT (A)
Figure 7.
Maximum current sense ratio drift vs load current
dk/k(%)
10
5
0
-5
-10
1
2
3
4
I
(A)
OUT
Note:
Parameter guaranteed by design; it is not tested.
14/38
VND5050AJ-E / VND5050AK-E
Electrical specifications
Sense (VCSD=0V)(1)
Table 10. Truth table
Conditions
Input
Output
L
L
0
Normal operation
Overtemperature
Undervoltage
H
H
Nominal
L
L
L
0
H
VSENSEH
L
L
L
0
0
H
L
H
H
L
L
L
0
Short circuit to GND
0 if Tj < TTSD
(Rsc ≤10 mΩ)
VSENSEH if Tj > TTSD
L
H
H
0
Short circuit to VCC
H
< Nominal
Negative output voltage
clamp
L
L
0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Figure 8.
Switching characteristics
VOUT
t
t
Won
Woff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
tf
tr
t
INPUT
td(on)
td(off)
t
Figure 9.
Output voltage drop limitation
V
-V
cc out
o
o
T =150 C
j
T =25 C
j
o
T =-40 C
j
V
on
I
out
V
/R
on on(T)
15/38
Electrical specifications
Table 11. Electrical transient requirements
VND5050AJ-E / VND5050AK-E
Test levels (1)
ISO 7637-2:
2004(E)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III
IV
Test pulse
5000
pulses
1
-75V
-100V
+50V
0.5 s
0.2 s
5 s
5 s
2 ms, 10 Ω
50 µs, 2 Ω
5000
pulses
2a
+37V
3a
3b
-100V
+75V
-150V
+100V
1h
1h
90 ms
90 ms
100 ms
100 ms
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01
4
-6V
-7V
1 pulse
1 pulse
Ω
5b (2)
+65V
+87V
400 ms, 2 Ω
Test level results(1)
ISO 7637-2:
2004(E)
III
IV
Test pulse
1
2a
C
C
C
C
C
C
C
C
C
C
C
C
3a
3b
4
5b (2)
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
16/38
VND5050AJ-E / VND5050AK-E
Figure 10. Waveforms
Electrical specifications
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
OVERLOAD OPERATION
TTSD
TR
Tj
TRS
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
SENSE CURRENT
VSENSEH
thermal cycling
SHORTED LOAD
current
limitation
power
limitation
NORMAL LOAD
17/38
Electrical specifications
VND5050AJ-E / VND5050AK-E
2.4
Electrical characteristics curves
Figure 11. Off state output current
Figure 12. High level input current
Iloff (uA)
1
Iih (uA)
5
4.5
4
0.875
Vin=2.1V
Off State
0.75
0.625
0.5
Vcc=13V
Vin=Vout=0V
3.5
3
2.5
2
0.375
0.25
0.125
0
1.5
1
0.5
0
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C )
Tc (°C )
Figure 13. Input clamp voltage
Figure 14. Input high level
Vih (V)
4
Vicl (V)
7
6.8
3.5
3
Iin=1mA
6.6
6.4
6.2
6
2.5
2
5.8
5.6
5.4
5.2
5
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 15. Input low level
Figure 16. Input hysteresis voltage
Vil (V)
2
Vhyst (V)
1
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C )
Tc (°C )
18/38
VND5050AJ-E / VND5050AK-E
Electrical specifications
Figure 17. On state resistance Vs. T
Figure 18. On state resistance Vs. V
CC
case
Ron (mOhm)
100
Ron (mOhm)
100
90
80
70
60
50
40
30
20
10
0
90
Io ut=2A
Vcc=13V
Tc=150°C
80
70
60
50
40
30
20
10
0
Tc=125°C
Tc=25°C
Tc=- 40°C
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125 150
175
175
175
Vcc (V)
Tc (°C )
Figure 19. Undervoltage shutdown
Figure 20. I
Vs. T
LIMH
case
Ilimh (A)
25
Vusd (V)
16
22.5
20
14
12
10
8
Vcc=13V
17.5
15
12.5
10
6
4
7.5
5
2
0
-50
-25
0
25
50
75
100
125 150
175
-50
-25
0
25
50
75
100
125
150
Tc (°C )
Tc (°C )
Figure 21. Turn-On voltage slope
Figure 22. Turn-Off voltage slope
(dVout/dt)on (V/ms)
1000
(dVout/dt)off (V/ms)
1000
900
900
Vcc=13V
RI=6.5Ohm
Vcc=13V
RI=6.5Ohm
800
800
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
-50
-25
0
25
50
75
100 125 150
-50
-25
0
25
50
75
100 125 150
175
Tc (°C )
Tc (°C )
19/38
Electrical specifications
VND5050AJ-E / VND5050AK-E
Figure 23. STAT_DIS clamp voltage
Figure 24. Low level STAT_DIS voltage
Vsdcl(V)
Vsdl(V)
8
14
12
7
6
5
4
3
2
1
Is d=1mA
10
8
6
4
2
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 25. High level STAT_DIS voltage
Vsdh(V)
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
20/38
VND5050AJ-E / VND5050AK-E
Application information
3
Application information
Figure 26. Application schematic
+5V
V
CC
R
prot
CS_DIS
D
ld
R
µC
INPUT
prot
OUTPUT
R
prot
CURRENT SENSE
GND
R
SENSE
R
GND
V
C
D
GND
EXT
GND
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1 : resistor in the ground line (R
only)
GND
This can be used with any type of load.
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤600mV / (I
).
GND
GND
S(on)max
≥ (−V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V <0: during reverse battery situations) is:
CC
GND
2
P = (-V ) /R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
will produce a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
.
GND
21/38
Application information
VND5050AJ-E / VND5050AK-E
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2 : diode (D
) in the ground line
GND
A resistor (R
inductive load.
=1kΩ) should be inserted in parallel to D if the device drives an
GND
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to
prot
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-V
/I
≤R
≤(V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation example:
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
5kΩ ≤R
≤180kΩ.
prot
Recommended values: R
=10kΩ, C
=10nF.
EXT
prot
22/38
VND5050AJ-E / VND5050AK-E
Application information
3.4
Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn Off current versus inductance (for each channel)
100
10
1
A
C
B
0,1
1
10
100
L (mH)
A:
T
= 150°C single pulse
jstart
B: Tjstart = 100°C repetitive pulse
C: = 125°C repetitive pulse
T
jstart
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R =0 Ω. In case of repetitive pulses, T
(at beginning of each
jstart
L
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
23/38
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
4
Package and PCB thermal data
4.1
PowerSSO-12™ thermal data
Figure 28. PowerSSO-12™ PC board
Note:
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4
th th
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
2
Copper areas: from minimum pad lay-out to 8cm ).
Figure 29.
R
Vs. PCB copper area in open box free air condition (one channel
thj-amb
ON)
RTHj_amb(°C/W)
70
65
60
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
24/38
VND5050AJ-E / VND5050AK-E
Package and PCB thermal data
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
Footprint
100
10
1
2 cm2
8 cm2
0,1
0,0001
0,001
0,01
0,1
Time (s)
1
10
100
1000
Equation 1: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THδ
TH
THtp
where δ = t /T
P
(a)
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/38
Package and PCB thermal data
Table 12. PowerSSO-12™ thermal parameter
VND5050AJ-E / VND5050AK-E
Area/island (cm2)
Footprint
2
8
R1= R7 (°C/W)
R2= R8 (°C/W)
R3 (°C/W)
0.7
2.8
4
R4 (°C/W)
8
8
7
R5 (°C/W)
22
15
20
10
15
R6 (°C/W)
26
C1= C7 (W.s/°C)
C2= C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0025
0.05
0.2
0.1
0.8
6
0.1
1
0.27
3
9
26/38
VND5050AJ-E / VND5050AK-E
Package and PCB thermal data
4.2
PowerSSO-24™ thermal data
Figure 32. PowerSSO-24™ PC board
Note:
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4
th th
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
2
Copper areas: from minimum pad lay-out to 8cm ).
Figure 33.
R
Vs. PCB copper area in open box free air condition (one channel
thj-amb
ON)
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
27/38
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one
channel ON)
Equation 2: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THδ
TH
THtp
where δ = t /T
P
(b)
Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™
b. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
28/38
VND5050AJ-E / VND5050AK-E
Table 13. PowerSSO-24™ thermal parameter
Package and PCB thermal data
Area/island (cm2)
Footprint
2
8
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
0.4
2
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0022
0.025
0.75
1
4
5
9
2.2
17
29/38
Package and packing information
VND5050AJ-E / VND5050AK-E
5
Package and packing information
5.1
ECOPACK® packages
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
PowerSSO-12™ package information
Figure 36. PowerSSO-12™ package dimensions
30/38
VND5050AJ-E / VND5050AK-E
Package and packing information
Table 14. PowerSSO-12™ mechanical data
Millimeters
Typ.
Symbol
Min.
1.25
0
Max.
1.62
0.1
A
A1
A2
B
1.10
0.23
0.19
4.8
1.65
0.41
0.25
5.0
C
D
E
3.8
4.0
e
0.8
H
5.8
0.25
0.4
0°
6.2
0.5
1.27
8°
h
L
k
X
1.9
3.6
2.5
4.2
0.1
Y
ddd
31/38
Package and packing information
VND5050AJ-E / VND5050AK-E
5.3
PowerSSO-24™ package information
Figure 37. PowerSSO-24™ package dimensions
Table 15. PowerSSO-24™ mechanical data
Millimeters
Symbol
Min.
2.15
2.15
0
Typ.
Max.
2.47
2.40
0.075
0.51
0.32
10.50
7.6
A
A2
a1
b
0.33
0.23
10.10
7.4
c
D
E
e
0.8
8.8
e3
G
0.1
G1
0.06
32/38
VND5050AJ-E / VND5050AK-E
Package and packing information
Table 15. PowerSSO-24™ mechanical data (continued)
Millimeters
Typ.
Symbol
Min.
Max.
10.5
0.4
H
h
10.1
L
0.55
0.85
10deg
4.7
N
X
Y
4.1
6.5
7.1
33/38
Package and packing information
VND5050AJ-E / VND5050AK-E
5.4
PowerSSO-12™ packing information
Figure 38. PowerSSO-12™ tube shipment (no suffix)
B
Base Q.ty
100
C
Bulk Q.ty
2000
Tube length ( 0.5)
532
1.85
6.75
0.6
A
A
B
C ( 0.1)
All dimensions are in mm.
Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
8
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.5
1.5
5.5
4.5
2
Compartment Depth
Hole Spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
34/38
VND5050AJ-E / VND5050AK-E
Package and packing information
5.5
PowerSSO-24™ packing information
Figure 40. PowerSS0-24TM tube shipment (no suffix)
Base Qty
49
Bulk Qty
1225
C
Tube length ( 0.5)
A
532
3.5
B
B
13.8
0.6
C ( 0.1)
All dimensions are in mm.
A
Figure 41. PowerSSO-24TM tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C ( 0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
12
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.55
1.5
11.5
2.85
2
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
No components
500mm min
Top
cover
tape
No components Components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
35/38
Order codes
VND5050AJ-E / VND5050AK-E
6
Order codes
Table 16. Device summary
Package
Order codes
Part number (Tube)
Part number (Tape & Reel)
PowerSSO-12
PowerSSO-24
VND5050AJ-E
VND5050AK-E
VND5050AJTR-E
VND5050AKTR-E
36/38
VND5050AJ-E / VND5050AK-E
Revision history
7
Revision history
Table 17. Document revision history
Date
Revision
Changes
30-Mar-2006
14-Apr-2006
1
2
Initial release.
PowerSSO-24 dimensions table update.
Reformatted
26-Apr-2007
14-May-2007
3
4
Figure 31 title corrected
Table 3 : corrected EMAX value.
Table 9 : added dk1/k1, dk2/k2, dk3/k3, ∆tDSEN
Added Figure 5.
.
SE2H
Updated Figure 6.
Added Figure 7.
Table 11 : Updated test level values III and IV for test pulse 5b and
notes.
Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V).
Figure 31: Thermal fitting model of a double channel HSD in
PowerSSO-12™, Figure 35: Thermal fitting model of a double channel
HSD in PowerSSO-24™: added notes.
01-Jun-2007
5
Updated Table 9: Current sense (8V<VCC<16V) :
– changed tDSENSE2H max value from 300 µs to 250µs.
– added IOL parameter.
Updated Section 4.1: PowerSSO-12™ thermal data:
– changed Figure 29: Rthj-amb Vs. PCB copper area in open box free
air condition (one channel ON).
4-Dec-2007
12-Feb-2008
6
7
– changed Figure 30: PowerSSO-12™ thermal impedance junction
ambient single pulse (one channel ON).
– updated Table 12: PowerSSO-12™ thermal parameter:
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.
Corrected typing error in Table 9: Current sense (8V<VCC<16V) :
changed IOL test condition from VIN = 0V to VIN = 5V.
37/38
VND5050AJ-E / VND5050AK-E
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