VND5050K-E [STMICROELECTRONICS]
Double channel high side driver with analog current sense for automotive applications; 具有模拟电流检测用于汽车应用的双通道高侧驱动器
| 型号： | VND5050K-E |
| 厂家： | 
ST |
| 描述： | Double channel high side driver with analog current sense for automotive applications |
| 文件： | 总28页 (文件大小：757K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5050J-E
VND5050K-E
Double channel high side driver with analog current sense
for automotive applications
Features
General
Max supply voltage
VCC
41V
PowerSSO-12 PowerSSO-24
Operating voltage range
VCC 4.5 to 36V
Max On-State resistance (per ch.) RON
50 mΩ
19 A
2 µA(*)
■ Self limiting of fast thermal transients
■ Protection against loss of ground and loss of
Current limitation (typ)
Off state supply current
ILIMH
IS
V
CC
■ Thermal shut down
(*) Typical value with all loads connected
■ Reverse battery protection (see Figure 28)
■ Electrostatic discharge protection
Application
■ All types of resistive, inductive and capacitive
loads
Description
Main
The VND5050K-E and VND5050J-E is a
■ Inrush current active management by power
monolithic device made using STMicroelectronics
VIPower M0-5 technology. It is intended for driving
resistive or inductive loads with one side
limitation
■ Very low stand-by current
■ 3.0V CMOS compatible input
■ Optimized electromagnetic emission
■ Very low electromagnetic susceptibility
connected to ground. Active V pin voltage
CC
clamp protects the device against low energy
spikes (see ISO7637 transient compatibility
table). The device detects open load condition
both in on and off state, when STAT_DIS is left
■ In compliance with the 2002/95/ec european
directive
Diagnostic Functions
■ Open drain status output
open or driven low. Output shorted to V is
detected in the off state.
CC
■ On state open load detection
■ Off state open load detection
■ Thermal shutdown indication
When STAT_DIS is driven high, STATUS pin is in
high impedance state.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears..
Protections
■ Undervoltage shut-down
■ Overvoltage clamp
■ Output stuck to V detection
CC
■ Load current limitation
Order codes
Package
Part number (Tube)
Part number (Tape & Reel)
PowerSSO-12
PowerSSO-24
VND5050J-E
VND5050K-E
VND5050J-E13TR
VND5050K-E13TR
March 2006
Rev 1
1/28
www.st.com
28
Contents
VND5050J-E / VND5050K-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
2.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1
3.1.2
Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
µC I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
5
6
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
4.2
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
5.2
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
VND5050J-E / VND5050K-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block Diagram
VCC
VCC
CLAMP
GND
UNDERVOLTAGE
CLAMP 1
INPUT1
STATUS1
STAT_DIS
DRIVER 1
OUTPUT1
LOGIC
OVERTEMP. 1
INPUT2
CURRENT LIMITER 1
OPENLOAD ON 1
STATUS2
VCC
OPENLOAD OFF 1
INPUT2
CONTROL & PROTECTION
EQUIVALENT TO
CHANNEL1
STATUS2
OUTPUT2
PWRLIM
1
Table 1.
Name
Pin Function
Function
VCC
Battery connection
Power output
OUTPUTn
GND
Ground connection. Must be reverse battery protected by an external diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
Open drain digital diagnostic pin
INPUTn
STATUSn
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin
Figure 2. Configuration diagram (top view) & suggested connections for unused and n.c. pins
TAB = V
cc
V
CC
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
GND.
N.C.
STAT_DIS
INPUT1
STATUS1
N.C.
STATUS2
N.C.
INPUT2
12
11
10
9
8
7
GND
STAT_DIS
INPUT 1
STATUS 1
STATUS 2
INPUT 2
V
1
2
3
4
5
6
cc
OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
V
cc
N.C.
V
CC
TAB = V
CC
PowerSSO-12
PowerSSO-24
Connection / Pin
Status
N.C.
Output
Input
STAT_DIS
Floating
X
X
X
X
X
X
To Ground
N.R.
N.R.
10KΩ resistor
10KΩ resistor
N.R. = Not recommended
3/28
Electrical specifications
VND5050J-E / VND5050K-E
2
Electrical specifications
Figure 3. Current and Voltage Conventions
IS
VCC
VCC
ISD
IOUTn
STAT_DIS
INPUTn
OUTPUTn
STATUSn
VSD
VOUTn
IINn
ISTATn
VINn
VSTATn
GND
IGND
during reverse battery condition
V
= V
- V
OUTn CCn
Fn
2.1
Absolute Maximum Ratings
Table 2.
Symbol
VCC
Absolute Maximum Ratings
Parameter
Value
Unit
DC Supply Voltage
41
0.3
200
V
V
- VCC Reverse DC Supply Voltage
- IGND DC Reverse Ground Pin Current
mA
Internally
Limited
IOUT
DC Output Current
A
- IOUT Reverse DC Output Current
15
A
IIN
DC Input Current
DC Status Current
+10 / -1
+10 / -1
+10 / -1
mA
mA
mA
ISTAT
ISTAT_DIS DC Status Disable Current
Maximum switching energy
EMAX
51
mJ
(L=1.5mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )
Electrostatic Discharge (Human Body Model: R=1.5KΩ;
C=100pF)
4000
4000
4000
5000
5000
V
V
V
V
V
- INPUT
- STATUS
- STAT_DIS
- OUTPUT
- VCC
VESD
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction Operating Temperature
Storage Temperature
750
V
-40 to 150
- 55 to 150
°C
°C
Tstg
4/28
VND5050J-E / VND5050K-E
Electrical specifications
2.2
Thermal Data
Table 3.
Thermal Data
Value
Symbol
Parameter
Unit
PowerSSO-12
PowerSSO-24
Thermal resistance junction-case (Max.)
(with one channel ON)
Rthj-case
2.8
2.8
°C/W
°C/W
Rthj-amb Thermal resistance junction-ambient (Max.)
See Figure 31
See Figure 35
2.3
Electrical Characteristics
8V<V <36V; -40°C<T <150°C, unless otherwise specified.
CC
j
Table 4.
Symbol
Power section
Parameter
Test Conditions
Min.
4.5
Typ. Max. Unit
VCC
Operating supply voltage
Undervoltage shutdown
13
36
V
V
VUSD
3.5
4.5
Undervoltage shut-down
hysteresis
VUSDhyst
0.5
46
V
IOUT=2A; Tj=25°C
50
100
65
mΩ
mΩ
mΩ
RON
Vclamp
IS
On state resistance(2)
Clamp Voltage
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
IS=20mA
41
52
V
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V; IOUT=0A
Supply current
2(1)
3
5(1)
6
µA
mA
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
0
0
0.01
3
5
IL(off1)
Off state output current(2)
Off state output current(2)
µA
V
IL(off2)
VF
VIN=0V; VOUT=4V
-75
0
(2)
Output - V diode voltage
-IOUT=4A; Tj=150°C
0.7
CC
(1) PowerMOS leakage included.
(2) For each channel
Table 5.
Symbol
td(on)
td(off)
Switching (V =13V)
CC
Parameter
Test Conditions
Min.
Typ. Max. Unit
Turn-on delay time
Turn-off delay time
RL=6.5Ω (see Figure 5)
RL=6.5Ω (see Figure 5)
RL=6.5Ω
20
40
µs
µs
dVOUT/dt(on) Turn-on voltage slope
dVOUT/dt(off) Turn-off voltage slope
see Figure 22
see Figure 24
V/µs
V/µs
RL=6.5Ω
5/28
Electrical specifications
VND5050J-E / VND5050K-E
Table 5.
Symbol
Switching (V =13V) (continued)
CC
Parameter
Test Conditions
Min.
Typ. Max. Unit
Switching energy losses
during twon
WON
RL=6.5Ω (see Figure 5)
0.21
0.28
mJ
mJ
Switching energy losses
during twoff
WOFF
RL=6.5Ω (see Figure 5)
Table 6.
Symbol
Status Pin (V =0V)
SD
Parameter
Test Conditions
Min
Typ
Max
Unit
Status Low Output
Voltage
VSTAT
ILSTAT
CSTAT
VSCL
I
STAT= 1.6 mA, VSD=0V
0.5
V
Normal Operation or VSD=5V,
VSTAT= 5V
Status Leakage Current
10
µA
Status Pin Input
Capacitance
Normal Operation or VSD=5V,
VSTAT= 5V
100
7
pF
I
STAT= 1mA
5.5
V
V
Status Clamp Voltage
ISTAT= - 1mA
-0.7
(1)
Table 7.
Symbol
Protections
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VCC=13V
12
18
24
24
A
A
IlimH
DC Short circuit current
5V<VCC<36V
VCC=13V
Short circuit current during
thermal cycling
IlimL
7
A
TR<Tj<TTSD
TTSD
TR
Shutdown temperature
Reset temperature
150
175
200
°C
°C
°C
TRS + 1 TRS + 5
135
TRS
Thermal reset of STATUS
Thermal hysteresis (TTSD
TR)
-
THYST
tSDL
VDEMAG
7
°C
µs
V
Status Delay in Overload
Conditions
Tj>TTSD (see Figure 4)
20
VCC-41 VCC-46 VCC-52
Turn-off output voltage
clamp
I
OUT=2A; VIN=0; L=6mH
Output voltage drop
limitation
IOUT=0.1A; Tj= -40°C...+150°C
VON
25
mV
(see Figure 6)
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must
limit the duration and number of activation cycles
6/28
VND5050J-E / VND5050K-E
Electrical specifications
Table 8.
Symbol
Openload Detection
Parameter
Test Conditions
Min
Typ
Max
Unit
Openload ON State
Detection Threshold
See
Figure 19
IOL
VIN = 5V ,8V<VCC<18V
10
70
mA
Openload ON State
Detection Delay
tDOL(on)
I
= 0A, V =13V (see Figure 4)
200
µs
µs
OUT
CC
Delay between INPUT falling
edge and STATUS rising
edge in Openload condition
tPOL
IOUT = 0A (see Figure 4)
200
500
1000
Openload OFF State Voltage
Detection Threshold
See
Figure 20
VOL
VIN = 0V, 8V<VCC<16V
2
4
V
Output Short Circuit to VCC
Detection Delay at Turn Off
tDSTKON
(see Figure 4)
180
tPOL
µs
Table 9.
Logic input
Parameter
Symbol
Test Conditions
Min.
Typ. Max. Unit
VIL
IIL
Input Low Level
0.9
V
µA
V
Low Level Input Current
Input High Level
VIN =0.9 V
VIN = 2.1 V
1
VIH
2.1
IIH
High Level Input Current
Input Hysteresis Voltage
10
µA
V
VI(hyst)
0.25
5.5
I
IN = 1mA
7
V
V
VICL
Input Clamp Voltage
IIN = -1mA
-0.7
VSDL
ISDL
VSDH
ISDH
STAT_DIS low level voltage
0.9
V
µA
V
Low level STAT_DIS current VSD = 0.9 V
STAT_DIS high level voltage
1
2.1
High level STAT_DIS current VSD = 2.1 V
STAT_DIS hysteresis voltage
10
7
µA
V
VSD(hyst)
0.25
5.5
I
SD=1mA
V
V
VSDCL
STAT_DIS clamp voltage
ISD=-1mA
-0.7
7/28
Electrical specifications
Figure 4. Status Timings
VND5050J-E / VND5050K-E
OPEN LOAD STATUS TIMING (with external pull-up)
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
IOUT < IOL
VIN
VIN
VOUT > VOL
VOUT < VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OVER TEMP STATUS TIMING
OUTPUT STUCK TO VCC
Tj > TTSD
IOUT > IOL
VIN
VIN
VOUT > VOL
VSTAT
VSTAT
tDOL(on)
tSDL
tDSTKON
tSDL
Table 10. Truth table
CONDITIONS
INPUT
OUTPUT
SENSE (VCSD=0V)(1)
L
L
H
H
Normal Operation
H
H
L
L
H
H
Current Limitation
Overtemperature
Undervoltage
H
X
L
L
L
H
L
H
L
L
L
X
X
H
L
H
H
L(2)
H
Output Voltage > VOL
Output Current < IOL
H
L
L
H (3)
L
H
H
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
(2) The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
(3) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
8/28
VND5050J-E / VND5050K-E
Figure 5. Switching characteristics
Electrical specifications
VOUT
90%
tf
80%
tr
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
INPUT
td(on)
td(off)
t
Figure 6. Output Voltage Drop Limitation
V
-V
cc out
Tj=150oC
Tj=25oC
Tj=-40oC
V
on
I
out
V
/R
on on(T)
9/28
Electrical specifications
VND5050J-E / VND5050K-E
Table 11. Electrical Transient Requirements
ISO 7637-2:
2004(E)
TEST LEVELS
Number of
pulses or
test times
Burst cycle/pulse repetition
time
Delays and
Impedance
III
IV
Test Pulse
1
2a
3a
3b
4
-75V
+37V
-100V
+75V
-6V
-100V
+50V
-150V
+100V
-7V
5000 pulses
5000 pulses
1h
1h
1 pulse
1 pulse
0.5 s
0.2 s
90 ms
90 ms
5 s
5 s
100 ms
100 ms
2 ms, 10 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
5b(1)
+40V
+40V
ISO 7637-2:
2004(E)
TEST LEVEL RESULTS
III
IV
Test Pulse
1
2a
3a
3b
4
C
C
C
C
C
C
C
C
C
C
C
C
5b(1)
CLASS
CONTENTS
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
E
(1) For load dump exceeding the above value a centralized suppressor must be adopted.
10/28
VND5050J-E / VND5050K-E
Figure 7. Waveforms
Electrical specifications
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
V
USDhyst
V
CC
V
USD
INPUT
STAT_DIS
LOAD CURRENT
STATUS
undefined
OPEN LOAD with external pull-up
INPUT
STAT_DIS
V
OUT
>V
OL
LOAD VOLTAGE
STATUS
V
OL
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
LOAD CURRENT
STATUS
I
<I
OUT OL
t
POL
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
I >I
OUT OL
V
OUT
>V
OL
LOAD VOLTAGE
STATUS
V
OL
t
DSTKON
OVERLOAD OPERATION
T
TSD
T
T
R
j
T
RS
INPUT
STAT_DIS
I
LIMH
I
LIML
LOAD CURRENT
STATUS
thermal cycling
SHORTED LOAD
current
limitation
power
limitation
NORMAL LOAD
11/28
Electrical specifications
VND5050J-E / VND5050K-E
2.4
Electrical characteristics curves
Figure 8. Off State Output Current
Figure 9. High Level Input Current
Iloff1 (uA)
1
lih (uA)
5
4.5
4
0.875
Vin=2.1V
Off state
0.75
0.625
0.5
Vcc=13V
Vin=Vout=0V
3.5
3
2.5
2
0.375
0.25
0.125
0
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
125
125
150
150
150
175
175
175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C)
Tc (°C)
Figure 10. Input Clamp Voltage
Figure 11. Input High Level
Vih (V)
4
Vicl (V)
8
3.5
3
7.75
lin=1mA
7.5
2.5
2
7.25
7
1.5
1
6.75
6.5
6.25
6
0.5
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C)
Figure 12. Input Low Level
Figure 13. Input Hysteresis Voltage
Vil (V)
4
Vihyst (V)
2
3.5
3
1.75
1.5
1.25
1
2.5
2
1.5
1
0.75
0.5
0.25
0
0.5
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C)
12/28
VND5050J-E / VND5050K-E
Electrical specifications
Figure 14. Status Low Output Voltage
Figure 15. On State Resistance Vs T
case
Ron (mOhm)
100
Vstat (V)
0.9
90
80
70
60
50
40
30
20
10
0
0.8
Iout=2A
Vcc=13V
Istat=1.6mA
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 16. Status Leakage Current
Figure 17. On State Resistance Vs V
CC
Ron (mOhm)
100
Ilstat (uA)
0.055
90
0.05
Tc= 150°C
80
Vstat=5V
70
Tc= 125°C
0.045
60
50
40
30
20
10
0
Tc= 25°C
Tc= -40°C
0.04
0.035
0.03
0.025
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
150
175
Vcc (V)
Tc (°C)
Figure 18. Status Clamp Voltage
Figure 19. Openload On State Detection
Threshold
Vscl (V)
9
Iol (mA)
100
8.5
90
Istat=1mA
Vin=5V
8
80
7.5
7
70
60
50
40
30
20
10
0
6.5
6
5.5
5
4.5
4
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
13/28
Electrical specifications
VND5050J-E / VND5050K-E
Figure 20. Openload Off State Voltage
Detection Threshold
Figure 21. I
Vs T
LIM case
Ilimh (A)
25
Vol (V)
5
22.5
20
4.5
Vcc=13V
Vin=0V
4
17.5
15
3.5
3
12.5
10
2.5
2
7.5
5
1.5
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C)
Tc (°C)
Figure 22. Turn-on Voltage Slope
Figure 23. Undervoltage Shutdown
dVout/dt(on) (V/ms)
1000
Vusd (V)
14
12
10
8
900
Vcc=13V
800
RI=6.5Ohm
700
600
500
400
300
200
100
0
6
4
2
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 24. Turn-off Voltage Slope
Figure 25. STAT_DIS Clamp Voltage
dVout/dt(off) (V/ms)
1000
Vsdcl(V)
14
12
900
Vcc=13V
800
RI=6.5Ohm
Isd=1mA
700
10
600
500
400
300
200
100
0
8
6
4
2
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
14/28
VND5050J-E / VND5050K-E
Electrical specifications
Figure 26. High Level STAT_DIS Voltage
Figure 27. Low Level STAT_DIS Voltage
Vsdh(V)
8
Vsdl(V)
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
15/28
Application information
VND5050J-E / VND5050K-E
3
Application information
Figure 28. Application schematic
+5V
+5V
VCC
Rprot
STAT_DIS
INPUT
Dld
Rprot
µC
OUTPUT
STATUS
Rprot
GND
RGND
VGND
DGND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1:
Resistor in the ground line (R
only). This can be used with any type of load.
GND
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤ 600mV / (I
).
S(on)max
GND
GND
≥ (−V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V <0: during reverse battery situations) is:
CC
GND
2
P = (-V ) /R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
will produce a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
.
GND
16/28
VND5050J-E / VND5050K-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2:
A diode (D
) in the ground line.
GND
A resistor (R
=1kΩ) should be inserted in parallel to D
if the device drives an
GND
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
µC I/Os protection:
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to
prot
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-V
/I
≤ R
≤ (V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation example:
For V = - 100V and I
≥ 20mA; V ≥ 4.5V
OHµC
CCpeak
latchup
5kΩ ≤ R
≤ 180kΩ.
prot
Recommended values: R
=10kΩ, C
=10nF.
EXT
prot
3.4
Open load detection in off state
Off state open load detection requires an external pull-up resistor (R ) connected between
PU
OUTPUT pin and a positive supply voltage (V ) like the +5V line used to supply the
PU
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open load indication when load is connected: in this case we have to avoid
V
V
to be higher than V
; this results in the following condition
OUT
OUT
Olmin
=(V /(R +R ))R <V .
PU
L
PU
L
Olmin
2. no misdetection when load is disconnected: in this case the V
has to be higher than
OUT
V
; this results in the following condition R <(V –V
)/I
.
OLmax
PU
PU OLmax L(off2)
17/28
Application information
Because I
VND5050J-E / VND5050K-E
may significantly increase if V is pulled high (up to several mA), the pull-
s(OFF)
out
up resistor R should be connected to a supply that is switched OFF when the module is in
PU
standby.
The values of V
section.
, V
and I
are available in the Electrical Characteristics
OLmin OLmax
L(off2)
Figure 29. Open Load detection in off state
V batt.
V
PU
VCC
RPU
DRIVER
+
IL(off2)
INPUT
LOGIC
OUT
+
-
R
STATUS
VOL
R
L
GROUND
18/28
VND5050J-E / VND5050K-E
Package and PCB thermal data
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 30. PowerSSO-12 PC Board
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm ).
th
th
2
Figure 31. R
Vs. PCB copper area in open box free air condition
thj-amb
RTHj_amb(°C/W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 32. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse
ZTH (˚C/W)
1000
Footprint
100
2
2 cm
2
8 cm
10
1
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Pulse Calculation Formula
= R ⋅ δ + Z (1 – δ)
Z
THδ
TH
THtp
where δ = t /T
P
19/28
Package and PCB thermal data
VND5050J-E / VND5050K-E
Figure 33. Thermal Fitting Model of a Double Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
Footprint
2
8
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
0.7
2.8
7
R4 (°C/W)
10
10
15
20
9
R5 (°C/W)
22
10
15
R6 (°C/W)
26
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0025
0.05
0.2
0.1
0.8
6
0.1
1
0.27
3
9
20/28
VND5050J-E / VND5050K-E
Package and PCB thermal data
4.2
PowerSSO-24 thermal data
Figure 34. PowerSSO-24 PC Board
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm ).
th
th
2
Figure 35. R
Vs. PCB copper area in open box free air condition
thj-amb
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 36. PowerSSO-24 Thermal Impedance Junction Ambient Single Pulse
ZTH (˚C/W)
1000
Footprint
100
2
2 cm
2
8 cm
10
1
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Pulse Calculation Formula
= R ⋅ δ + Z (1 – δ)
Z
THδ
TH
THtp
where δ = t /T
P
21/28
Package and PCB thermal data
VND5050J-E / VND5050K-E
Figure 37. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
Footprint
2
8
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
0.4
2
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0022
0.025
0.75
1
4
5
9
2.2
17
22/28
VND5050J-E / VND5050K-E
Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.1
Package Mechanical
Figure 38. PowerSSO-12™ Package Dimensions
D
0.25 mm
GAUGE PLANE
C
h x 45˚
A
A2
B
C
C
SEATING
PLANE
L
A1
K
ddd
12
7
X
H
E
BOTTOM
VIEW
Y
1
6
e
Table 12. PowerSSO-12™ Mechanical Data
millimeters
Typ
Symbol
Min
Max
A
A1
A2
B
C
D
1.250
0.000
1.100
0.230
0.190
4.800
3.800
1.620
0.100
1.650
0.410
0.250
5.000
4.000
E
e
0.800
H
h
L
k
5.800
0.250
0.400
0°
6.200
0.500
1.270
8°
X
Y
ddd
1.900
3.600
2.500
4.200
0.100
23/28
Package information
Figure 39. PowerSSO-24™ Package Dimensions
VND5050J-E / VND5050K-E
Table 13. PowerSSO-24™ Mechanical Data
millimeters
Typ
Symbol
Min
Max
2.47
2.40
0.075
0.51
0.32
10.50
7.6
A
A2
a1
b
2.15
2.15
0
0.33
0.23
10.10
7.4
c
D
E
e
0.8
8.8
e3
G
G1
H
h
0.1
0.06
10.5
0.4
10.1
0.55
L
0.85
10deg
4.7
N
X
4.1
6.5
Y
7.1
24/28
VND5050J-E / VND5050K-E
Package information
5.2
Packing information
Figure 40. PowerSSO-12 Tube Shipment (No Suffix)
B
Base Q.ty
100
2000
532
C
Bulk Q.ty
Tube length ( 0.5)
A
1.85
6.75
0.6
A
B
C ( 0.1)
All dimensions are in mm.
Figure 41. PowerSSO-12 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
8
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.5
1.5
5.5
4.5
2
Compartment Depth
Hole Spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
25/28
Package information
VND5050J-E / VND5050K-E
Figure 42. PowerSSO-24 Tube Shipment (No Suffix)
Base Q.ty
Bulk Q.ty
Tube length ( 0.5)
A
49
1225
532
3.5
C
B
B
13.8
0.6
C ( 0.1)
All dimensions are in mm.
A
Figure 43. PowerSSO-24 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
P0 ( 0.1)
P
D ( 0.05) 1.55
D1 (min)
F ( 0.1)
24
4
12
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
1.5
11.5
2.85
2
Compartment Depth K (max)
Hole Spacing
P1 ( 0.1)
End
All dimensions are in mm.
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
26/28
VND5050J-E / VND5050K-E
Revision history
6
Revision history
Table 14. Document revision history
Date
Revision
Changes
30-Mar-2006
1
Initial release.
27/28
VND5050J-E / VND5050K-E
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
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third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
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SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2006 STMicroelectronics - All rights reserved
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28/28
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