VND5160AJ-E [STMICROELECTRONICS]
Double channel high side driver with analog current sense for automotive applications; 具有模拟电流检测用于汽车应用的双通道高侧驱动器
| 型号： | VND5160AJ-E |
| 厂家： | 
ST |
| 描述： | Double channel high side driver with analog current sense for automotive applications |
| 文件： | 总31页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5160AJ-E
Double channel high side driver with analog current sense
for automotive applications
Features
Max supply voltage
VCC
41 V
Operating voltage range
VCC 4.5 to 36V
PowerSSO-12
Max on-state resistance (per ch.) RON
160 mΩ
5 A
– Reverse battery protection (see Application
schematic)
– Electrostatic discharge protection
Current limitation (typ)
Off state supply current
ILIMH
IS
2 µA(1)
1. Typical value with all loads connected.
Application
■ General features
■ All types of resistive, inductive and capacitive
– Inrush current active management by
power limitation
loads
■ Suitable as LED driver
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
Description
The VND5160AJ-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
– In compliance with the 2002/95/EC
European directive
with one side connected to ground. Active V pin
voltage clamp protects the device against low
energy spikes (see ISO7637 transient
CC
■ Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
■ Protection
compatibility table). This device integrates an
analog current sense which delivers a current
proportional to the load current (according to a
known ratio) when CS_DIS is driven low or left
open. When CS_DIS is driven high, the
CURRENT SENSE pin is in a high impedance
condition. Output current limitation protects the
device in overload condition. In case of long
overload duration, the device limits the dissipated
power to safe level up to thermal shut-down
intervention. Thermal shut-down with automatic
restart allows the device to recover normal
operation as soon as fault condition disappears.
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
cc
– Thermal shut down
Table 1. Device summary
Order codes
Package
Tube
Tape and Reel
PowerSSO-12
VND5160AJ-E
VND5160AJTR-E
February 2008
Rev 5
1/31
www.st.com
31
Contents
VND5160AJ-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1
3.1.2
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21
Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4
5
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
5.2
5.3
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
VND5160AJ-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
VND5160AJ-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Iout/isense vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On state resistance vs. T
Figure 18. On state resistance vs. V
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21.
I
vs. T
LIMH case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Maximum turn-Off current versus inductance (for each channel). . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 24
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel ON) . . . 25
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/31
VND5160AJ-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
VCC
UNDERVOLTAGE
VCC
CLAMP
OUTPUT1
PwCLAMP 1
CURRENT
SENSE1
GND
DRIVER 1
ILIM
1
PwCLAMP 2
INPUT1
DRIVER 2
VDSLIM
1
LOGIC
OUTPUT2
PwrLIM
1
ILIM
2
CURRENT
SENSE2
OVERTEMP. 1
VDSLIM
2
INPUT2
CS_DIS
IOUT1
K 1
OVERTEMP. 2
K 2
IOUT2
PwrLIM
2
Table 2.
Pin function
Name
Function
VCC
Battery connection.
Power output.
OUTPUTn
Ground connection. Must be reverse battery protected by an external
diode/resistor network.
GND
Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state.
INPUTn
CURRENT SENSEn Analog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
5/31
Block diagram and pin description
Figure 2. Configuration diagram (top view)
VND5160AJ-E
TAB = V
N.C.
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
N.C.
cc
12
11
10
9
8
7
1
2
3
4
5
6
GND
INPUT2
INPUT1
CURRENT SENSE1
CURRENT SENSE2
CS_DIS
PowerSSO-12
Note:
The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The
new pinout is backaward compatible with existing PCB layouts where pins #7 and 12 are
connected to Vcc. For new PCB designs, these pins should be left unconnected.
Table 3.
Suggested connections for unused and N.C. pins
Connection / Pin
Current Sense
N.C.
Output
Input
CS_DIS
Floating
N.R.(1)
X
X
X
X
Through10kΩ Through 10kΩ
resistor resistor
To ground
Through 1kΩ resistor
X
N.R.(1)
1. Not recommended.
6/31
VND5160AJ-E
Electrical specifications
2
Electrical specifications
Figure 3.
Current and voltage conventions
I
S
(1)
Fn
V
CC
V
V
CC
I
OUTn
I
CSD
OUTPUTn
CS_DIS
INPUTn
V
OUTn
V
CSD
I
SENSEn
I
INn
CURRENT
V
SENSEn
V
SENSEn
INn
GND
I
GND
Note:
V
= V
- V during reverse battery condition.
Fn
OUTn CC
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
DC supply voltage
41
V
V
-VCC
Reverse DC supply voltage
0.3
200
- IGND DC reverse ground pin current
IOUT DC output current
- IOUT Reverse DC output current
mA
A
Internally limited
6
A
IIN
DC input current
-1 to 10
-1 to 10
200
mA
mA
mA
ICSD
DC current sense disable input current
-ICSENSE DC reverse CS pin current
VCC-41
+VCC
V
V
VCSENSE Current sense maximum voltage
Maximum switching energy (single pulse)
EMAX
34
mJ
(L=12mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )
7/31
Electrical specifications
VND5160AJ-E
Table 4.
Symbol
Absolute maximum ratings (continued)
Parameter
Value
Unit
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
- INPUT
4000
2000
4000
5000
5000
V
V
V
V
V
- CURRENT SENSE
- CS_DIS
VESD
- OUTPUT
- VCC
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
°C
Tstg
2.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Max value
Unit
Rthj-case Thermal resistance junction-case (MAX) (With one channel ON)
Rthj-amb Thermal resistance junction-ambient (MAX)
8
°C/W
See Figure 29 °C/W
8/31
VND5160AJ-E
Electrical specifications
2.3
Electrical characteristics
The values specified in this section are for 8V<V <36V; -40°C<T <150°C, unless otherwise
CC
j
stated.
Table 6.
Symbol
Power section
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
4.5 13
3.5
36
V
V
VUSD Undervoltage shutdown
4.5
Undervoltage shut-down
hysteresis
VUSDhyst
0.5
V
IOUT= 0.5A; Tj= 25°C
160 mΩ
320 mΩ
210 mΩ
RON
On state resistance (1)
IOUT= 0.5A; Tj= 150°C
IOUT= 0.5A; VCC= 5V; Tj= 25°C
Vclamp Clamp voltage
IS= 20 mA
41
46
52
V
Off State; VCC= 13V; Tj= 25°C;
VIN=VOUT=VSENSE=VCSD=0V
IS
Supply current
2(2) 5(2) µA
On State; VCC=13V; VIN=5V; IOUT=0A
3
6
mA
µA
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
0
0
0.01
3
5
Off state output
current (1)
IL(off)
Output - VCC diode
voltage (1)
VF
-IOUT= 0.6A; Tj=150°C
0.7
V
1. For each channel.
2. PowerMOS leakage included.
Table 7.
Symbol
td(on)
td(off)
Switching (V =13V, T =25°C)
CC j
Parameter
Test conditions
Min.
Typ.
Max. Unit
Turn- On delay time
Turn- Off delay time
RL= 26Ω (see Figure 8.)
RL= 26Ω (see Figure 8.)
10
15
µs
µs
Turn- On voltage
slope
See
Figure 20.
(dVOUT/dt)on
(dVOUT/dt)off
WON
RL= 26Ω
V/µs
V/µs
mJ
Turn- Off voltage
slope
See
Figure 22.
RL= 26Ω
Switching energy
losses during twon
RL= 26Ω (see Figure 8.)
RL= 26Ω (see Figure 8.)
0.03
0.02
Switching energy
losses during twoff
WOFF
mJ
9/31
Electrical specifications
VND5160AJ-E
Table 8.
Symbol
Logic input
Parameter
Test conditions
Min. Typ. Max. Unit
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
V
µA
V
VIN= 0.9V
VIN= 2.1V
1
VIH
IIH
2.1
10
µA
V
VI(hyst) Input hysteresis voltage
VICL Input clamp voltage
0.25
5.5
IIN= 1mA
IIN= -1mA
7
V
V
-0.7
VCSDL CS_DIS low level voltage
ICSDL Low level CS_DIS current
VCSDH CS_DIS high level voltage
ICSDH High level CS_DIS current
0.9
V
µA
V
VCSD= 0.9V
VCSD= 2.1V
1
2.1
10
7
µA
V
VCSD(hyst) CS_DIS hysteresis voltage
0.25
5.5
I
CSD= 1mA
V
V
VCSCL CS_DIS clamp voltage
ICSD= -1mA
-0.7
(1)
Table 9.
Symbol
Protection and diagnostics
Parameter
Test conditions
CC= 13V
Min.
Typ.
Max. Unit
V
3.8
5
7.5
7.5
A
A
IlimH
DC short circuit current
5V<VCC<36V
Short circuit current during
thermal cycling
IlimL
VCC= 13V; TR<Tj<TTSD
2
A
TTSD Shutdown temperature
150
175
200
°C
°C
°C
°C
TR
Reset temperature
TRS + 1 TRS + 5
TRS
Thermal reset of STATUS
135
THYST Thermal hysteresis (TTSD-TR)
VDEMAG Turn-Off output voltage clamp
7
VCC-41 VCC-46 VCC-52
I
OUT= 1A; VIN= 0;
L= 20mH
OUT= 0.03A;
V
I
Output voltage drop
VON
Tj= -40°C...150°C
25
mV
limitation
(see Figure 9.)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/31
VND5160AJ-E
Electrical specifications
Min. Typ. Max. Unit
Table 10. Current sense (8V<VCC<16V)
Symbol
Parameter
Test conditions
IOUT= 0.025A; VSENSE= 0.5V; VCSD=0V;
Tj= -40°C...150°C
K0
IOUT/ISENSE
260 500 750
IOUT= 0.35A; VSENSE=0.5V; VCSD=0V;
Tj= -40°C...150°C
320 450 590
360 450 540
K1
IOUT/ISENSE
IOUT=0.35A; VSENSE=0.5V; VCSD=0V;
Tj= 25°C...150°C
IOUT= 0.35A; VSENSE= 0.5V;
VCSD=0V;
Current sense ratio
drift
(1)
dK1/K1
-13
+13
%
%
%
TJ= -40 °C to 150 °C
IOUT= 0.5A; VSENSE= 4V; VCSD= 0V;
Tj= -40°C...150°C
360 440 540
380 440 510
K2
IOUT/ISENSE
IOUT= 0.5A; VSENSE= 4V; VCSD= 0V;
Tj= 25°C...150°C
IOUT= 0.5 A; VSENSE= 4 V;
VCSD= 0V;
Current sense ratio
drift
(1)
dK2/K2
-8
+8
TJ= -40 °C to 150 °C
IOUT= 1.5A; VSENSE=4V; VCSD=0V;
Tj= -40°C...150°C
410 440 480
420 440 460
K3
IOUT/ISENSE
IOUT=1.5A; VSENSE=4V; VCSD=0V;
Tj= 25°C...150°C
IOUT= 1.5 A; VSENSE= 4 V;
VCSD=0V;
Current sense ratio
drift
(1)
dK3/K3
-4
+4
TJ= -40 °C to 150 °C
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C
VCSD=0V; VIN=5V; Tj=-40°C...150°C
0
0
1
2
µA
µA
Analog sense
leakage current
ISENSE0
IOUT=0.6A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj= -40°C...150°C
0
1
1
5
µA
Openload ON state
current detection
threshold
IOL
VIN = 5V, ISENSE= 5 µA
mA
Max analog
senseoutput
voltage
VSENSE
IOUT=1.5A; VCSD=0V;
5
V
V
Analog sense
output voltage in
overtemperature
condition
VSENSEH
VCC=13V; RSENSE= 3.9KΩ;
9
8
Analog sense
output current in
overtemperature
condition
ISENSEH
VCC=13V; VSENSE= 5V;
mA
11/31
Electrical specifications
Table 10. Current sense (8V<VCC<16V) (continued)
VND5160AJ-E
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Delay response
time from falling
edge of CS_DIS
pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=90% of ISENSE max
(see Figure 4.)
tDSENSE1H
50 100 µs
Delay response
time from rising
edge of CS_DIS
pin
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=10% of ISENSE max
(see Figure 4.)
tDSENSE1L
5
20
µs
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=90% of ISENSE max
Delay response
tDSENSE2H time from rising
edge of INPUT pin
80 150 µs
(see Figure 4.)
Delay response
time between rising
edge of output
current and rising
edge of current
sense
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX=2A (see Figure 5)
∆tDSEN
20
µs
SE2H
VSENSE<4V, 0.08A<Iout<1.5A
ISENSE=10% of ISENSE max
(see Figure 4.)
Delay response
tDSENSE2L time from falling
edge of INPUT pin
100 250 µs
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H tDSENSE1L
tDSENSE1H
tDSENSE2L
12/31
VND5160AJ-E
Figure 5.
Electrical specifications
Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
V
IN
∆t
DSENSE2H
t
t
t
I
OUT
I
OUTMAX
90% I
OUTMAX
I
SENSE
I
SENSEMAX
90% I
SENSEMAX
13/31
Electrical specifications
VND5160AJ-E
Figure 6.
I
/ I
vs. I
(see Table 10 for details)
out sense
out
Iout / Isense
700
650
600
550
500
450
400
350
300
250
200
max Tj = -40 °C to 150 °C
max Tj = 25 °C to 150 °C
typical value
min Tj = 25 °C to 150 °C
min Tj = -40 °C to 150 °C
0,35
0,58
0,81
1,04
1,27
1,5
IOUT (A)
Figure 7.
Maximum current sense ratio drift vs load current
dk/k(%)
15
10
5
0
-5
-10
-15
0,1 0,3 0,5 0,7 0,9 1,1 1,3 1,5 1,7
I
(A)
OUT
Note:
Parameter guaranteed by design; it is not tested.
14/31
VND5160AJ-E
Electrical specifications
SENSE (VCSD=0V)(1)
Table 11. Truth table
Conditions
INPUT
OUTPUT
L
L
0
Normal operation
H
H
Nominal
L
L
L
0
Overtemperature
Undervoltage
H
VSENSEH
L
L
L
0
0
H
L
H
H
L
L
L
0
Short circuit to GND
0 if Tj < TTSD
(R ≤10 mΩ)
VSENSEH if Tj > TTSD
sc
L
H
H
0
Short circuit to VCC
H
< Nominal
Negative output voltage clamp
L
L
0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Figure 8.
Switching characteristics
V
OUT
t
t
Woff
Won
90%
80%
dV
/dt
dV
/dt
OUT (off)
OUT (on)
10%
t
f
t
r
t
INPUT
t
t
d(on)
d(off)
t
Figure 9.
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Iout
Von/Ron(T)
15/31
Electrical specifications
Table 12. Electrical transient requirements
VND5160AJ-E
Test levels (1)
ISO 7637-2:
2004(E)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III
IV
Test pulse
5000
pulses
1
-75V
-100V
+50V
0.5 s
0.2 s
5 s
5 s
2 ms, 10 Ω
50 µs, 2 Ω
5000
pulses
2a
+37V
3a
3b
-100V
+75V
-150V
+100V
1h
1h
90 ms
90 ms
100 ms
100 ms
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01
4
-6V
-7V
1 pulse
1 pulse
Ω
5b (2)
+65V
+87V
400 ms, 2 Ω
Test level results(1)
ISO 7637-2:
2004(E)
III
IV
Test pulse
1
2a
C
C
C
C
C
C
C
C
C
C
C
C
3a
3b
4
5b (2)
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
16/31
VND5160AJ-E
Figure 10. Waveforms
Electrical specifications
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
OVERLOAD OPERATION
TTSD
TR
Tj
TRS
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
SENSE CURRENT
VSENSEH
thermal cycling
SHORTED LOAD
current
power
limitation
limitation
NORMAL LOAD
17/31
Electrical specifications
VND5160AJ-E
2.4
Electrical characteristics curves
Figure 11. Off state output current
Figure 12. High level input current
Iloff (uA)
0.3
Iih (uA)
5
4.5
Vin=2.1V
0.25
Off State
4
Vcc=13V
Vin=Vout=0V
3.5
3
0.2
0.15
0.1
0.05
0
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
125
125
150
150
150
175
175
175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C )
Tc (°C )
Figure 13. Input clamp voltage
Figure 14. Input low level
Vicl (V)
7
Vil (V)
2
6.8
1.8
1.6
1.4
1.2
1
lin=1mA
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Tc (°C )
Tc (°C )
Figure 15. Input high level
Figure 16. Input hysteresis voltage
Vih (V)
4
Vihyst (V)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Tc (°C )
Tc (°C )
18/31
VND5160AJ-E
Electrical specifications
Figure 17. On state resistance vs. T
Figure 18. On state resistance vs. V
CC
case
Ron (mOhm)
300
Ron (mOhm)
300
280
275
250
225
200
175
150
125
100
75
Io u t=0. 5A
Vcc=13V
260
Tc=150°C
240
220
200
180
160
140
120
100
80
Tc=125°C
Tc=25°C
Tc=-40°C
0
5
10
15
20
25
30
35
40
175
175
-50
-25
0
25
50
75
100
125
150
175
175
175
Vcc (V)
Tc (°C )
Figure 19. Undervoltage shutdown
Figure 20. Turn-On voltage slope
Vusd (V)
16
(dVout/dt)on (V/ms)
1000
900
14
12
10
8
Vcc=13V
RI=26Ohm
800
700
600
500
400
300
200
100
0
6
4
2
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Tc (°C )
Tc (°C )
Figure 21. I
vs. T
Figure 22. Turn-Off voltage slope
LIMH
case
Ilimh (A)
16
(dVout/dt)off (V/ms)
1000
900
14
12
10
8
Vcc=13V
RI=26Ohm
Vcc=13V
800
700
600
500
400
300
200
100
0
6
4
2
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Tc (°C )
Tc (°C )
19/31
Electrical specifications
VND5160AJ-E
Figure 23. CS_DIS high level voltage
Figure 24. CS_DIS clamp voltage
Vcsdh (V)
4
Vcsdcl (V)
8
3.5
3
7.5
Ic s d =1mA
7
2.5
2
6.5
6
1.5
1
5.5
5
0.5
0
4.5
4
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 25. CS_DIS low level voltage
Vcsdl (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
20/31
VND5160AJ-E
Application information
3
Application information
Figure 26. Application schematic
+5V
V
CC
R
prot
CS_DIS
D
ld
R
µC
IINPUT
prot
OUTPUT
R
CURRENT SENSE
prot
GND
R
R
GND
SENSE
V
C
D
GND
GND
EXT
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1 : resistor in the ground line (R
only)
GND
This can be used with any type of load.
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤600mV / (I
).
GND
GND
S(on)max
≥ (−V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V <0: during reverse battery situations) is:
CC
GND
2
P = (-V ) /R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
will produce a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
.
GND
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
21/31
Application information
VND5160AJ-E
3.1.2
Solution 2 : diode (D
) in the ground line
GND
A resistor (R
inductive load.
=1kΩ) should be inserted in parallel to D if the device drives an
GND
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to
prot
prevent the MCU I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of MCU and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of MCU
I/Os.
-V
/I
≤R
≤(V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation example:
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
5kΩ ≤R
≤180kΩ.
prot
Recommended values: R
=10kΩ, C
=10nF.
EXT
prot
22/31
VND5160AJ-E
Application information
3.4
Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn-Off current versus inductance (for each channel)
10
A
B
C
1
0,1
0,1
1
L (mH)
10
100
A:
T
= 150°C single pulse
jstart
B: Tjstart = 100°C repetitive pulse
C: = 125°C repetitive pulse
T
jstart
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R = 0 Ω.
L
In case of repetitive pulses, T
(at beginning of each demagnetization) of every pulse
jstart
must not exceed the temperature specified above for curves A and B.
23/31
Package and PC board thermal data
VND5160AJ-E
4
Package and PC board thermal data
4.1
PowerSSO-12™ thermal data
Figure 28. PowerSSO-12™ PC board
Note:
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4
th th
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
2
Copper areas: from minimum pad lay-out to 8cm ).
Figure 29.
R
vs. PCB copper area in open box free air condition (one channel ON)
thj-amb
RTHj_amb(°C/W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
24/31
VND5160AJ-E
Package and PC board thermal data
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
100
Footprint
2
2 cm
2
8 cm
10
1
0,001
0,01
0,1
1
10
100
1000
Time (s)
Equation 1: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THδ
TH
THtp
where δ = t /T
P
(a)
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/31
Package and PC board thermal data
VND5160AJ-E
8
Table 13. Thermal parameters
Area/island (cm2)
R1= R7 (°C/W)
R2= R8 (°C/W)
R3 (°C/W)
Footprint
2
1.2
6
3
R4 (°C/W)
8
8
7
R5 (°C/W)
22
15
20
10
15
R6 (°C/W)
26
C1= C7 (W.s/°C)
C2= C8 (W.s/°C)
C3 (W.s/°C)
0.0008
0.0016
0.0166
0.2
C4 (W.s/°C)
0.1
0.8
6
0.1
1
C5 (W.s/°C)
0.27
3
C6 (W.s/°C)
9
26/31
VND5160AJ-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
Package mechanical data
Figure 32. PowerSSO-12™ package dimensions
27/31
Package and packing information
VND5160AJ-E
Table 14. PowerSSO-12™ mechanical data
Millimeters
Typ.
Symbol
Min.
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Max.
1.620
0.100
1.650
0.410
0.250
5.000
4.000
A
A1
A2
B
C
D
E
e
0.800
H
5.800
0.250
0.400
0°
6.200
0.500
1.270
8°
h
L
k
X
2.200
2.900
2.800
3.500
0.100
Y
ddd
28/31
VND5160AJ-E
Package and packing information
5.3
Packing information
Figure 33. PowerSSO-12™ tube shipment (no suffix)
Base Q.ty
100
2000
532
B
C
Bulk Q.ty
Tube length ( 0.5)
A
1.85
6.75
0.6
A
B
C ( 0.1)
All dimensions are in mm.
Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
8
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.5
1.5
5.5
4.5
2
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
No components
Top
cover
tape
No components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
29/31
Revision history
VND5160AJ-E
6
Revision history
Table 15. Document revision history
Date
Revision
Changes
13-Sep-2004
1
Initial release.
Layout changed.
10-Apr-2006
01-Mar-2007
2
3
Major update to Section 2: Electrical specifications.
Reformatted.
Contents, List of tables and List of figures added.
Added Section 3.4: Maximum demagnetization energy
(VCC = 13.5V).
®
ECOPACK package information added.
Document reformatted and restructured.
Updated Figure 2: Configuration diagram (top view) : pins 7-12 left
unconnected (N.C) and added note.
Table 4: Absolute maximum ratings : corrected EMAX value from 14
to 34 mJ.
Added Figure 5: Delay response time between rising edge of ouput
current and rising edge of current sense (CS enabled).
Updated Figure 6: Iout/ Isense vs. Iout (see Table 10 for details).
Added Figure 7: Maximum current sense ratio drift vs load current.
Updated Table 10: Current sense (8V<VCC<16V) :
– changed tDSENSE2H max value from 300 µs to 150 µs.
– added dk1/k1, dk2/k2, dk3/k3, ∆tDSEN 2H , IOL parameters.
Table 12: Electrical transient requirements : updated test level values
SE
10-Dec-2007
4
III and IV for test pulse 5b and notes.
Updated Section 4.1: PowerSSO-12™ thermal data:
– changed Figure 29: Rthj-amb vs. PCB copper area in open box
free air condition (one channel ON).
– changed Figure 30: PowerSSO-12™ thermal impedance junction
ambient single pulse (one channel ON).
– Figure 31: Thermal fitting model of a double channel HSD in
PowerSSO-12™: added note.
– updated Table 13: Thermal parameters:
R3 value changed from 7 to 3 °C/W.
R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.
C3 value changed from 0.05 to 0.0166 W.s/°C.
Corrected typing error in Table 10: Current sense (8V<VCC<16V) :
12-Feb-2008
5
changed IOL test condition from VIN = 0V to VIN = 5V.
30/31
VND5160AJ-E
Please Read Carefully:
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