VND5160J-E [STMICROELECTRONICS]
Double channel high side driver for automotive applications; 用于汽车应用的双通道高侧驱动器
| 型号： | VND5160J-E |
| 厂家： | 
ST |
| 描述： | Double channel high side driver for automotive applications |
| 文件： | 总31页 (文件大小：530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5160J-E
Double channel high side driver for automotive applications
Features
Max supply voltage
VCC
41V
Operating voltage range
Max on-state resistance
Current limitation (typ)
Off state supply current (typ)
VCC 4.5 to 36V
PowerSSO-12
RON
ILIMH
IS
160 mΩ
5A
2 µA(1)
– Electrostatic discharge protection
Application
1. Typical value with all loads connected.
■ General
■ All types of resistive, inductive and capacitive
loads
– Inrush current active management by
power limitation
– Very low stand-by current
Description
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
The VND5160J-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active V pin voltage clamp protects the
CC
device against low energy spikes (see ISO7637
transient compatibility table).
■ Diagnostic functions
– Open drain status output
– On state open load detection
– Off state open load detection
– Thermal shutdown indication
The device detects open load condition in both
ON and OFF states, when STAT_DIS is left open
or driven low. Output shorted to V is detected in
CC
the OFF state.
■ Protection
When STAT_DIS is driven high, the STATUS pin is
in a high impedance condition.
– Undervoltage shut-down
– Overvoltage clamp
– Output stuck to Vcc detection
– Load current limitation
Output current limitation protects the device in
overload condition. In case of long duration
overload, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Thermal shut down
– Reverse battery protection (see Figure 28)
Table 1.
Device summary
Order codes
Package
Part number (Tube)
Part number (Tape & Reel)
PowerSSO-12
VND5160J-E
VND5160JTR-E
December 2007
Rev 5
1/31
www.st.com
31
Contents
VND5160J-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1
3.1.2
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 20
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
3.2
3.3
3.4
3.5
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
5.2
5.3
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
VND5160J-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin (V =0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SD
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
VND5160J-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. On state resistance vs T
Figure 18. On state resistance vs V
Figure 19. Openload On state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. Openload Off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. Turn - On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. Turn - Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CC
Figure 23.
I
vs T
LIM case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 24. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. Maximum turn Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 31. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 24
Figure 33. PowerSSO-12™ Thermal impedance junction ambient single pulse (one channel ON) . . 25
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 35. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 36. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 37. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/31
VND5160J-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
VCC
OUTPUT1
V
CC
GND
INPUT1
CLAMP
UNDERVOLTAGE
CLAMP 1
CLAMP 2
DRIVER 2
STATUS1
STAT_DIS
INPUT2
DRIVER 1
LOGIC
ILIM
1
ILIM
2
PWRLIM
1
VDSLIM
1
VDSLIM
2
STATUS2
OPENLOAD ON 1
OPENLOAD OFF 1
OPENLOAD ON 2
OVERTEMP. 1
OVERTEMP. 2
OPENLOAD OFF 2
OUTPUT2
PWRLIM
2
Table 2.
Pin functions
Name
VCC
Function
Battery connection.
Power output.
OUTPUTn
GND
Ground connection. Must be reverse battery protected by an external diode/
resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
INPUTn
STATUSn
STAT_DIS
Open Drain digital diagnostic pin.
Active high CMOS compatible pin, to disable the STATUS pin.
5/31
Block diagram and pin description
Figure 2. Configuration diagram (top view)
VND5160J-E
TAB = Vcc
Vcc
GND
12
11
10
9
8
7
1
2
3
4
5
6
OUTPUT 1
OUTPUT 1
STAT_DIS
INPUT 1
STATUS 1
OUTPUT 2
OUTPUT 2
Vcc
STATUS 2
INPUT 2
Table 3.
Suggested connections for unused and N.C. pins
Connection / Pin
STATUS
N.C.
OUTPUT
INPUT
STAT_DIS
Floating
X
X
X
X
X
Through 10kΩ
Through 10kΩ
To ground
N.R.(1)
X
N.R.
resistor
resistor
1. Not recommended.
6/31
VND5160J-E
Electrical specifications
2
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VCC
VFn
IOUTn
ISD
OUTPUTn
STATUSn
STAT_DIS
INPUTn
VSD
VOUTn
IINn
ISTATn
VINn
VSTATn
GND
IGND
Note:
V
= V
- V
during reverse battery condition.
CCn
Fn
OUTn
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
-VCC
-IGND
IOUT
-IOUT
IIN
DC supply voltage
41
0.3
V
V
Reverse DC supply voltage
DC reverse ground pin current
DC output current
200
mA
A
Internally limited
6
Reverse DC output current
DC input current
A
+10 / -1
+10 / -1
+10 / -1
mA
mA
mA
ISTAT
DC status current
ISTAT_DIS DC status disable current
Maximum switching energy
EMAX
(L=12mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C;
IOUT = IlimL(Typ.) )
33
mJ
7/31
Electrical specifications
VND5160J-E
Unit
Table 4.
Symbol
Absolute maximum ratings (continued)
Parameter
Value
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
– INPUT
4000
4000
4000
5000
5000
V
V
V
V
V
– STATUS
– STAT_DIS
– OUTPUT
– VCC
VESD
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
°C
Tstg
2.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Max value
Unit
Rthj-case Thermal resistance junction-case (max.) (with one channel ON)
Rthj-amb Thermal resistance junction-ambient
8
°C/W
°C/W
See Figure 32
8/31
VND5160J-E
Electrical specifications
2.3
Electrical characteristics
Values specified in this section are for 8V<V <36V; -40°C<T <150°C, unless otherwise
CC
j
stated.
.
Table 6.
Power section
Parameter
Symbol
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
4.5
13
36
V
V
VUSD Undervoltage shutdown
3.5
4.5
Undervoltage Shut-down
hysteresis
V
0.5
46
V
USDhyst
I
OUT= 1A; Tj= 25°C
160 mΩ
320 mΩ
210 mΩ
RON
On state resistance(2)
IOUT= 1A; Tj= 150°C
IOUT= 1A; VCC= 5V; Tj= 25°C
Vclamp Clamp voltage
IS= 20mA
41
52
V
Off State; VCC=13V; VIN=VOUT=0
Tj= 25°C;
IS
Supply current
2(1) 5(1) µA
On State; VCC=13V; VIN=5V;
IOUT= 0A
3
6
mA
µA
V
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
0
0
0.01
3
5
IL(off1)
IL(off2)
VF
Off state output current(2)
VIN=0V; VOUT=4V
-75
0
Output - V diode
CC
-IOUT=0.6A; Tj=150°C
0.7
(2)
voltage
1. PowerMOS leakage included.
2. For each channel.
Table 7.
Symbol
Switching (V = 13V; T = 25°C)
CC j
Parameter
Test conditions
Min. Typ. Max. Unit
td(on)
td(off)
Turn-On delay time
Turn-Off delay time
RL=13Ω (see Figure 6)
RL=13Ω (see Figure 6)
RL=13Ω
10
15
µs
µs
dVOUT/dt(on) Turn-On voltage slope
dVOUT/dt(off) Turn-Off voltage slope
See Figure 21
See Figure 22
0.07
V/ µs
V/ µs
mJ
RL=13Ω
WON
Switching energy losses during twon RL=13Ω (see Figure 6)
Switching energy losses during twoff RL=13Ω (see Figure 6)
WOFF
0.04
mJ
9/31
Electrical specifications
VND5160J-E
Table 8.
Symbol
Status pin (V =0)
SD
Parameter
Test conditions
Min. Typ. Max. Unit
VSTAT
ILSTAT
CSTAT
Status low output voltage
Status leakage current
ISTAT= 1.6 mA, VSD=0V
0.5
10
V
Normal operation or VSD=5V,
VSTAT= 5V
µA
Normal operation or VSD=5V,
VSTAT= 5V
Status pin input capacitance
Status clamp voltage
100
7
pF
I
STAT= 1mA
5.5
V
V
VSCL
ISTAT= - 1mA
-0.7
(1)
Table 9.
Symbol
Protection
Parameter
Test conditions
Min.
Typ. Max. Unit
VCC= 13V
3.5
5
7.5
7.5
A
A
IlimH
DC short circuit current
5V<VCC<36V
Short circuit current during
thermal cycling
IlimL
VCC= 13V TR<Tj<TTSD
2
A
TTSD
TR
Shutdown temperature
Reset temperature
150
175
200
°C
°C
°C
°C
T
+ 1
T
+ 5
RS
RS
TRS
Thermal reset of STATUS
135
THYST Thermal hysteresis (T
-T )
7
TSD
R
Status delay in overload
conditions
tSDL
Tj>TTSD
20
µs
V
Turn-Off output voltage
clamp
VDEMAG
IOUT=1A; VIN=0; L=20mH
V
-41
V
-46
V
-52
CC
CC
CC
I
OUT= 0.03A;
Output voltage drop
limitation
VON
Tj= -40°C...+150°C
25
mV
(see Figure 5)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/31
VND5160J-E
Electrical specifications
Table 10. Openload detection
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
Openload On state
detection threshold
See
Figure 19
IOL
VIN = 5V, 8V<VCC<18V
10
40
mA
µs
Openload On state
detection delay
IOUT = 0A, VCC=13V
(see Figure 4)
tDOL(on)
200
Delay between INPUT falling
edge and STATUS rising
edge in Openload condition
tPOL
IOUT = 0A (see Figure 4) 200
500
1000
µs
Openload Off state voltage
detection threshold
See
Figure 20
VOL
VIN = 0V, 8V<VCC<16V
2
4
V
Output short circuit to Vcc
detection delay at turn Off
tDSTKON
See Figure 4
180
tPOL
µs
Table 11. Logic input
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
V
µA
V
VIN= 0.9V
VIN= 2.1V
1
VIH
IIH
2.1
10
µA
V
VI(hyst) Input hysteresis voltage
0.25
5.5
IIN= 1mA
IIN= -1mA
7
V
V
VICL
Input clamp voltage
-0.7
VSDL
ISDL
VSDH
ISDH
STAT_DIS low level voltage
Low level STAT_DIS current
STAT_DIS high level voltage
High level STAT_DIS current
0.9
V
µA
V
VCSD= 0.9V
VCSD= 2.1V
1
2.1
10
7
µA
V
VSD(hyst) STAT_DIS hysteresis voltage
VSDCL STAT_DIS clamp voltage
0.25
5.5
ISD= 1mA
V
V
ISD= -1mA
-0.7
11/31
Electrical specifications
Figure 4.
VND5160J-E
Status timings
OPEN LOAD STATUS TIMING (without external pull-up)
< I
OPEN LOAD STATUS TIMING (with external pull-up)
< I
I
I
OUT
OL
OUT
OL
V
V
V
IN
IN
V
< V
OL
V
> V
OL
OUT
OUT
V
STAT
STAT
t
t
DOL(on)
DOL(on)
t
POL
OUTPUT STUCK TO Vcc
> I
OVER TEMP STATUS TIMING
T > T
I
j
TSD
OUT
OL
V
IN
V
V
IN
V
> V
OL
OUT
V
STAT
STAT
t
t
DOL(on)
t
SDL
DSTKON
t
SDL
Figure 5.
Output voltage drop limitation
Vcc-Vout
o
o
T =150 C
j
T =25 C
j
o
T =-40 C
j
Von
Iout
Von/Ron(T)
12/31
VND5160J-E
Electrical specifications
STATUSn (VSD=0V)(1)
Table 12. Truth table
Conditions
INPUTn
OUTPUTn
L
L
H
H
Normal operation
Current limitation
Overtemperature
Undervoltage
H
H
L
L
H
H
H
X
L
L
L
H
L
H
L
L
L
X
X
H
L
H
H
L(2)
H
Output Voltage > VOL
Output Current < IOL
H
L
L
H(3)
L
H
H
1. If the VSD is high, the STATUS pin is in a high impedance.
2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
Figure 6.
Switching characteristics
V
OUT
t
t
Won
Woff
90%
80%
dV
/dt
dV
/dt
OUT (off)
OUT (on)
10%
t
f
t
r
t
INPUT
t
d(on)
t
d(off)
t
13/31
Electrical specifications
VND5160J-E
Table 13. Electrical transient requirements
ISO 7637-2:
2004(E)
Test levels(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III
IV
test pulse
1
2a
3a
3b
4
-75V
+37V
-100V
+75V
-6V
-100V
+50V
-150V
+100V
-7V
5000 pulses
5000 pulses
1h
0.5 s
0.2 s
5 s
2 ms, 10 Ω
50 µs, 2 Ω
5 s
90 ms
90 ms
100 ms
100 ms
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
1h
1 pulse
1 pulse
5b(2)
+65V
+87V
ISO 7637-2:
2004(E)
Test level results(1)
III
IV
test pulse
1
2a
3a
3b
4
C
C
C
C
C
C
C
C
C
C
C
C
5b(2)
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
14/31
VND5160J-E
Figure 7.
Electrical specifications
Waveforms
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
V
USDhyst
V
CC
V
USD
INPUT
STAT_DIS
LOAD CURRENT
STATUS
undefined
OPEN LOAD with external pull-up
INPUT
STAT_DIS
V
>V
OUT OL
LOAD VOLTAGE
STATUS
V
OL
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
LOAD CURRENT
STATUS
I
<I
OUT OL
POL
t
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
I
>I
OUT OL
V >V
OUT OL
LOAD VOLTAGE
STATUS
V
OL
t
DSTKON
OVERLOAD OPERATION
T
TSD
T
T
R
j
T
RS
INPUT
STAT_DIS
I
LIMH
I
LIML
LOAD CURRENT
STATUS
thermal cycling
SHORTED LOAD
current power
limitation
limitation
NORMAL LOAD
15/31
Electrical specifications
VND5160J-E
2.4
Electrical characteristics curves
Figure 8.
Off state output current
Figure 9.
Input clamp voltage
Iloff1 (uA)
Vicl (V)
8
0.25
0.2
0.15
0.1
7.75
7.5
Off state
Vcc=13V
Vin=Vout=0V
Ii n =1mA
7.25
7
6.75
6.5
0.05
0
6.25
6
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C )
Tc (°C )
Figure 10. High level input current
Figure 11. Input high level
Iih (uA)
5
Vih (V)
4
4.5
3.5
3
Vin=2.1V
4
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C)
Figure 12. Input low level
Figure 13. Input hysteresis voltage
Vil (V)
4
Vihyst (V)
2
3.5
3
1.75
1.5
1.25
1
2.5
2
1.5
1
0.75
0.5
0.25
0
0.5
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C )
16/31
VND5160J-E
Electrical specifications
Figure 14. Status low output voltage
Figure 15. Status leakage current
Ilstat (uA)
0.08
Vstat (V)
0.9
0.8
0.072
0.064
0.056
0.048
0.04
Istat=1.6mA
Vstat=5V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.032
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 16. Status clamp voltage
Figure 17. On state resistance vs T
case
Ron (mOhm)
300
Vscl (V)
9
270
8.5
Istat=1mA
Io ut=1A
Vcc=13V
240
8
210
7.5
7
180
150
120
90
6.5
6
5.5
5
60
30
4.5
4
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 18. On state resistance vs V
Figure 19. Openload On state detection
threshold
CC
Ron (mOhm)
300
Iol (mA)
100
275
90
Tc=150°C
Tc=125°C
Vin=5V
250
225
200
175
150
125
100
75
80
70
60
50
40
30
20
10
0
Tc=25°C
Tc=-40°C
50
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
150
175
Vcc (V)
Tc (°C )
17/31
Electrical specifications
VND5160J-E
Figure 20. Openload Off state voltage
detection threshold
Figure 21. Turn - On voltage slope
Vol (V)
5
dVout/dt(on) (V/ms)
1000
4.5
900
Vin=0V
Vcc=13V
Ri=6.5Ohm
4
800
3.5
3
700
600
500
400
300
200
100
0
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 22. Turn - Off voltage slope
Figure 23. I
vs T
LIM
case
Ilimh (A)
10
dVout/dt(off) (V/ms)
1000
9
8
7
6
5
4
3
2
1
0
900
800
700
Vcc=13V
Vcc=13V
600
Ri=13Ohm
500
400
300
200
100
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 24. Undervoltage shutdown
Figure 25. STAT_DIS clamp voltage
Vusd (V)
14
Vsdcl (V)
14
12
10
8
12
Is d =1mA
10
8
6
4
2
0
6
4
2
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
18/31
VND5160J-E
Electrical specifications
Figure 26. High level STAT_DIS voltage
Figure 27. Low level STAT_DIS voltage
Vsdh (V)
8
Vsdl (V)
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
19/31
Application information
VND5160J-E
3
Application information
Figure 28. Application schematic
+5V
+5V
V
CC
R
prot
STAT_DIS
D
ld
R
INPUT
prot
µC
OUTPUT
STATUS
R
prot
GND
R
GND
V
D
GND
GND
Note:
Channels 2, has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1 : resistor in the ground line (R
only)
GND
This can be used with any type of load.
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤600mV / (I
).
GND
GND
S(on)max
≥ (−V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V <0: during reverse battery situations) is:
CC
GND
2
P = (-V ) /R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
will produce a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
.
GND
20/31
VND5160J-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2: a diode (D
) in the ground line
GND
A resistor (R
inductive load.
=1kΩ) should be inserted in parallel to D if the device drives an
GND
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage transient suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to
prot
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-V
/I
≤R
≤(V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation example:
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
5kΩ ≤R
≤180kΩ.
prot
Recommended R
values is 10kΩ.
prot
3.4
Open load detection in Off state
Off state open load detection requires an external pull-up resistor (R ) connected between
PU
OUTPUT pin and a positive supply voltage (V ) like the +5V line used to supply the
PU
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open load indication when load is connected: in this case we have to avoid
V
V
to be higher than V
; this results in the following condition
OUT
OUT
Olmin
=(V /(R +R ))R <V .
PU
L
PU
L
Olmin
2. no misdetection when load is disconnected: in this case the V has to be higher than
out
V
; this results in the following condition R <(V –V
)/I
.
OLmax
PU
PU OLmax L(off2)
21/31
Application information
Because I
VND5160J-E
may significantly increase if V is pulled high (up to several mA), the pull-
s(OFF)
out
up resistor R should be connected to a supply that is switched OFF when the module is in
PU
standby.
The values of V
section.
, V
and I
are available in the Electrical characteristics
OLmin OLmax
L(off2)
Figure 29. Open load detection in Off state
V batt.
V
PU
VCC
R
PU
DRIVER
+
INPUT
IL(off2)
LOGIC
OUT
+
-
R
STATUS
V
OL
R
L
GROUND
22/31
VND5160J-E
Application information
3.5
Maximum demagnetization energy (VCC = 13.5V)
Figure 30. Maximum turn Off current versus inductance (for each channel)
10
A
B
C
1
0,1
0,1
1
L (mH)
10
100
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R = 0Ω.
L
In case of repetitive pulses, T
(at beginning of each demagnetization) of every pulse
jstart
must not exceed the temperature specified above for curves A and B.
23/31
Package and PCB thermal data
VND5160J-E
4
Package and PCB thermal data
4.1
PowerSSO-12™ thermal data
Figure 31. PowerSSO-12™ PC board
Note:
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4
th th
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
2
Copper areas: from minimum pad lay-out to 8cm ).
Figure 32. R
vs. PCB copper area in open box free air condition (one channel
thj-amb
ON)
RTHj_amb(°C/W)
65
60
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
24/31
VND5160J-E
Package and PCB thermal data
Figure 33. PowerSSO-12™ Thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
100
Footprint
2
2 cm
2
8 cm
10
1
0,1
0,0001
0,001
0,01
0,1
Time (s)
1
10
100
1000
Pulse calculation formula
= R ⋅ δ + Z (1 – δ)
Z
THδ
TH
THtp
where δ = t /T
P
(a)
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/31
Package and PCB thermal data
VND5160J-E
8
Table 14. Thermal parameters
Area/island (cm2)
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
Footprint
2
1.2
6
7
R4 (°C/W)
10
10
15
20
9
R5 (°C/W)
22
10
15
R6 (°C/W)
26
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.0008
0.0016
0.05
0.2
0.1
0.8
6
0.1
1
0.27
3
9
26/31
VND5160J-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
PowerSSO-12™ package information
Figure 35. PowerSSO-12™ package dimensions
27/31
Package and packing information
VND5160J-E
Table 15. PowerSSO-12™ mechanical data
Millimeters
Typ.
Symbol
Min.
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Max.
1.620
0.100
1.650
0.410
0.250
5.000
4.000
A
A1
A2
B
C
D
E
e
0.800
H
5.800
0.250
0.400
0°
6.200
0.500
1.270
8°
h
L
k
X
1.900
3.600
2.500
4.200
0.100
Y
ddd
28/31
VND5160J-E
Package and packing information
5.3
Packing information
Figure 36. PowerSSO-12™ tube shipment (no suffix)
B
Base Q.ty
100
2000
532
C
Bulk Q.ty
Tube length ( 0.5)
A
1.85
6.75
0.6
A
B
C ( 0.1)
All dimensions are in mm.
Figure 37. PowerSSO-12™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
8
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.5
1.5
5.5
4.5
2
Compartment Depth
Hole Spacing
All dimensions are in mm.
End
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
29/31
Revision history
VND5160J-E
6
Revision history
Table 16. Document revision history
Date
Revision
Changes
7-Jan-2004
3-Feb-2006
1
2
Initial release.
Major series of updates incorporated.
Reformatted.
Added list of tables and list of figures.
20-Mar-2007
01-Jun-2007
3
4
Added Section 3.5: Maximum demagnetization energy
(VCC = 13.5V).
Added new disclaimer.
Updated Table 4: Absolute maximum ratings: EMAX entries.
Updated Table 13: Electrical transient requirements :Test level
values III and IV for test pulse 5b and notes.
Figure 34: Thermal fitting model of a double channel HSD in
PowerSSO-12™ added note.
Updated Section 4.1: PowerSSO-12™ thermal data:
– Changed Figure 32: Rthj-amb vs. PCB copper area in open
box free air condition (one channel ON).
– Changed Figure 33: PowerSSO-12™ Thermal impedance
junction ambient single pulse (one channel ON).
– Updated Table 14: Thermal parameters:
R1 and R7 values changed from 1.2 to 0.1 °C/W.
R2 = R8 values changed from 6 to 0.2 °C/W.
R3 value changed from 7 to 4 °C/W.
17-Dec-2007
5
R4 values changed from 10/10/9 to 8/8/7 °C/W.
C1=C7 values changed from 0.0008 to 0.0001 °C/W.
C2=C8 values changed from 0.0016 to 0.002 °C/W.
30/31
VND5160J-E
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
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Information in this document supersedes and replaces all information previously supplied.
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