VND670SP [STMICROELECTRONICS]
Dual high-side switch with dual Power MOSFET gate driver(bridge configuration); 采用双功率MOSFET栅极驱动器（网桥配置）的双高边开关
| 型号： | VND670SP |
| 厂家： | 
ST |
| 描述： | Dual high-side switch with dual Power MOSFET gate driver(bridge configuration) |
| 文件： | 总20页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND670SP
Dual high-side switch with dual Power MOSFET
gate driver (bridge configuration)
Features
Type
RDS(on)
IOUT
15A(1)
VCC
10
(1)
VND670SP
30mΩ
40V
1. Per each channel.
1
PowerSO-10
■ 5V logic level compatible inputs
■ Gate drive for two external power MOSFET
■ Undervoltage and overvoltage shutdown
■ Overvoltage clamp
Description
The VND670SP is a monolithic device made
using STMicroelectronics VIPower technology
M0-3, intended for driving motors in full bridge
configuration. The device integrates two 30 mW
Power MOSFET in high-side configuration, and
provides gate drive for two external Power
MOSFET used as low side switches. IN and IN
allow to select clockwise or counter clockwise
drive or brake; DIAG /EN , DIAG /EN allow to
■ Thermal shutdown
■ Cross-conduction protection
■ Current limitation
■ Very low standby power consumption
■ PWM operation up to 10 KHz
■ Protection against loss of ground and loss of
A
B
A
A
B
B
V
CC
disable one half bridge and feedback diagnostic.
Built-in thermal shutdown, combined with a
current limiter, protects the chip in
■ Reverse battery protection
overtemperature and short circuit conditions.
Short to battery protects the external connected
low-side Power MOSFET.
Table 1.
Device summary
Package
Order codes
Tape and reel
Tube
VND670SP
PowerSO-10
VND670SP13TR
December 2008
Rev 2
1/20
www.st.com
20
Contents
VND670SP
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
2.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
3.2
3.3
Normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Fault conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
VND670SP
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Truth table in fault conditions (detected on OUT ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
A
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
List of figures
VND670SP
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test conditions for high-side switching times measurement. . . . . . . . . . . . . . . . . . . . . . . . . 9
Test conditions for external Power MOSFET switching times measurement . . . . . . . . . . 10
Definition of the external Power MOSFET turn-on dead time tdel . . . . . . . . . . . . . . . . . . . 10
Typical application circuit for DC to 10 KHz PWM operation . . . . . . . . . . . . . . . . . . . . . . . 11
Typical application circuit for a 20 KHz PWM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Waveforms (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Waveforms (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. PowerSO-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. PowerSO-10 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/20
VND670SP
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
VCC
Undervolt.
INTERNAL
SUPPLY
INA
OUTA
Short to battery
INB
LOGIC
DIAGA/ENA
OUTB
Short to battery
DIAGB/ENB
PWM
GATEA
Current
Limiter B
Current
Overtemp. Overtemp.
GATEB
Limiter A
A
B
GND
Figure 2.
Configuration diagram (top view)
OUTPUT B
GATE B
GROUND
GATE A
5
4
3
6
7
8
9
INPUT B
DIAGB/ENB
PWM
DIAGA/ENA
INPUT A
2
1
OUTPUT A
10
11
VCC
Table 2.
Suggested connections for unused and not connected pins
Connection / pin
Status
N.C.
Output
Input
Floating
X
X
X
X
Through 10KΩ
To ground
X
resistor
5/20
Electrical specifications
VND670SP
2
Electrical specifications
Figure 3.
Current and voltage conventions
ICC
VCC
IINA
IINB
IENA
VCC
IOUTA
INA
OUTA
OUTB
IOUTB
INB
VOUTA
IgsA
DIAGA/ENA
GATEA
GATEB
GND
IgsB
VOUTB
IENB
DIAGB/ENB
PWM
VgsA
VgsB
Ipw
IGND
VENB
VINA VINB
Vpw
VENA
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
Imax1
Imax2
IR
Supply voltage
-0.3..40
15
V
A
Maximum output current (continuous)
Maximum output current (250ms pulse duration)
Reverse DC output current
Input current
20
A
- 15
A
IIN
+/- 10
+/- 10
+/- 10
+/- 20
2000
mA
mA
mA
mA
V
IEN
Enable pin current
Ipw
PWM pin current
Igs
Output gate current
VESD
Tj
Electrostatic discharge ( R = 1.5KΩ; C = 100pF)
Junction operating temperature
Storage temperature
- 40 to 150
- 55 to 150
°C
°C
Tstg
6/20
VND670SP
Electrical specifications
2.2
Thermal data
Table 4.
Symbol
Thermal data (per island)
Parameter
Max. value
Unit
Rthj-case Thermal resistance junction-case
Rthj-amb Thermal resistance junction-ambient
1.4
°C/W
°C/W
50(1)
1. When mounted using the recommended pad size on FR-4 board (see AN515 Application Note).
2.3
Electrical characteristics
Values specified in this section are for 9V < V < 18V; -40°C < T < 150°C, unless
CC
j
otherwise stated.
Table 5.
Symbol
VCC
Power
Parameter
Test conditions
Min. Typ. Max. Unit
Operating supply voltage
5.5
36
V
I
LOAD = 12A
50
30
mΩ
mΩ
RON
On-state resistance
Supply current
ILOAD = 12A
Tj = 25°C
26
On-state
Off-state
15
40
mA
µA
Is
Vgate
Vgs,cl
Gate output voltage
5.0
6.0
8.5
8.0
V
V
Gate output clamp voltage
Igs= - 1 mA
6.8
Table 6.
Switching (V = 13V, R
= 1.1Ω)
CC
LOAD
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
tD(on)
tD(off)
tr
Turn-on delay time
50
45
150
135
150
120
µs
µs
µs
µs
Turn-off delay time
Output voltage rise time
Output voltage fall time
50
Input rise time < 1µs
(see Figure 4)
tf
40
(dVOUT/dt)on Turn-on voltage slope
(dVOUT/dt)off Turn-off voltage slope
160
230
0.5
2.6
1.0
2.2
500 V/ ms
1200 V/ ms
tdong
trg
tdoffg
tfg
Vgsturn-on delay time
Vgs rise time
2
µs
µs
µs
µs
C1=4.7nF
10
5.0
10
Break to ground
configuration
Vgsturn-off delay time
Vgs fall time
(see Figure 5)
External MOSFET
turn-on dead time
tdel
(see Figure 6)
600
1800
µs
7/20
Electrical specifications
VND670SP
Table 7.
Symbol
Protection and diagnostic
Parameter
Test conditions
Min. Typ. Max. Unit
VUSD
VOV
ILIM
Undervoltage shutdown
Overvoltage shutdown
Current limitation
5.5
V
V
A
36
30
43
45
Thermal shutdown
temperature
TTSD
VIN = 3.25 V
150
170
200
°C
V
Output turn-off clamp
voltage
VCC
-
VCC
41
-
Vocl
ILOAD = 12A, L = 6mH
55
External MOSFET
saturation voltage
detection threshold
Vsat
2.5
4.2
5.5
V
Table 8.
Symbol
PWM
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Vpwl
Ipwl
Vpwh
Ipwh
PWM low level voltage
PWM pin current
1.5
V
µA
V
Vpw = 1.5V
1
PWM high level voltage
PWM pin current
3.25
Vpw = 3.25V
10
µA
PWM hysteresis
voltage
Vpwhhyst
0.5
V
I
pw = 1 mA
V
CC+0.3 VCC+0.7 VCC+1.0
V
V
Vpwcl
PWM clamp voltage
Ipw = -1 mA
-5.0
-3.5
-2.0
Test mode PWM pin
voltage
Vpwtest
Ipwtest
-3.5
-2.0
-0.5
V
Test mode PWM pin
current
Vpwtest = -2.0 V
-2000
-500
µA
Table 9.
Symbol
Logic inputs
Parameter
Test conditions
Min.
Typ.
Max. Unit
VIL
IINL
Input low level voltage
Input current
1.5
V
µA
V
VIN = 1.5 V
1
VIH
Input high level voltage
Input current
3.25
IINH
VIN = 3.25 V
10
µA
V
VIHYST
Input hysteresis voltage
0.5
IIN=1mA
IIN=-1mA
6.0
6.8
8.0
V
V
VICL
Input clamp voltage
-1.0
-0.7
-0.3
8/20
VND670SP
Electrical specifications
Table 10. Enable
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
Normal operation
VENL
Enable low level voltage
Enable pin current
1.5
V
µA
V
(DIAGX/ENX pin acts
as an input pin)
IENL
VEN = 1.5 V
1
Normal operation
VENH
Enable high level voltage
Enable pin current
3.25
(DIAGX/ENX pin acts
as an input pin)
IENH
VEN = 3.25 V
10
µA
V
Normal operation
VEHYST
Enable hysteresis voltage
0.5
(DIAGX/ENX pin acts
as an input pin)
I
EN = 1mA
6.0
6.8
8.0
V
V
VENCL
Enable clamp voltage
IEN = -1mA
-1.0
-0.7
-0.3
Fault operation
Enable output low level
voltage
(DIAGX/ENX pin acts
as an input pin)
VDIAG
0.4
V
IEN = 1.6 mA
Figure 4.
Test conditions for high-side switching times measurement
VOUTA, B
90%
80%
(dVOUT/dt)off
(dVOUT/dt)on
10%
t
VINA, B
td(off)
tf
td(on)
tr
t
9/20
Electrical specifications
Figure 5.
VND670SP
Test conditions for external Power MOSFET switching times
measurement
V
gsA, B
90%
80%
20%
10%
t
V
pw
t
t
dong
t
doffg
t
rg
fg
t
Figure 6.
Definition of the external Power MOSFET turn-on dead time t
del
INA
INB
OUTA
VgsA
tdel
10/20
VND670SP
Application information
3
Application information
Figure 7.
Typical application circuit for DC to 10 KHz PWM operation
+5V
R1
+5V
R1
VCC
Rprot
1K
Rprot
1K
DIAGB/ENB
DIAGA/ENA
VND670SP
Rprot
1K
GND
OUTA
OUTB
PWM
INA
Rgnd(*)
Rprot
1K
Rprot
1K
INB
UP
M
GATEA
GATEB
DOWN
External Power Mos A
External Power Mos B
Note:
1
2
Reverse battery protection: series relay in V line: R =0 Ohms; series fuse in V line
CC gnd CC
with antiparallel diode between ground and V : R =10 Ohms.
CC
gnd
Layout hints: the connection between GND pin of the VN670SP and the Power MOSFET
SOURCE connections should be kept short enough to ensure that the dynamic difference
between these two points never exceed 1V for the bridge to operate properly.
11/20
Application information
Figure 8.
VND670SP
Typical application circuit for a 20 KHz PWM operation
+5V
+5V
R1
R1
V
CC
R
R
B
prot
1K
prot
1K
DIAG /EN
DIAG /EN
B
A
A
VND670SP
R
prot
1K
OUT
OUT
INA
A
B
R
(*)
gnd
R
prot
1K
R
prot
1K
PWM
INB
UP
M
GATE
GATE
B
A
D1
D2
DOWN
27Ω
27Ω
External
Power Mos B
External
Power Mos A
Note:
1
Reverse battery protection: series relay in V line: R
= 0 Ohms; series fuse in V line
gnd CC
CC
with antiparallel diode between ground and V : R =10 Ohms.
CC
gnd
3.1
Normal operating conditions
Table 11. Truth table in normal operating conditions
INA
INB
DIAGA/ENA DIAGB/ENB OUTA OUTB GATEA GATEB
Comment
1
1
0
0
X
1
0
X
X
1
0
1
0
X
X
X
1
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0
1
1
H
H
L
L
L
H
L
L
L
H
L
H
L
L
L
L
H
L
L
L
L
H
L
Brake to VCC
Clockwise
Counter cw
Brake to GND
Stand by
H
H
L
H
L
L
L
HSA only
H
L
L
MOSA only
HSB only
L
L
H
MOSB only
Note:
1
2
In normal operating conditions the DIAG /EN pin is considered as an input pin by the
X X
device. This pin must be externally pulled high.
PWM pin usage:
In all cases, a “0” on the PWM pin will turn-off both GATE and GATE outputs. When PWM
A
B
rises back to “1”, GATE or GATE turn on again depending on the input pin state.
A
B
12/20
VND670SP
Application information
3.2
Fault conditions
In case of a fault conditions the DIAG /EN pin is considered as an output pin by the device.
X
X
The fault conditions are:
●
overtemperature on one or both high-sides;
●
short to battery condition on the output (saturation detection on the external connected
Power MOSFET).
Possible origins of fault conditions may be:
●
OUT is shorted to ground ---> overtemperature detection on high-side A.
A
●
OUT is shorted to V ---> external Power MOSFET saturation detection (driven by
A
CC
GATE ).
A
When a fault condition is detected, the user can know which power element is in fault by
monitoring the IN , IN , DIAG /EN and DIAG /EN pins.
A
B
A
A
B
B
In any case, when a fault is detected, the faulty half bridge is latched off. To turn-on the
respective output (GATE or OUT ) again, the input signal must rise from low to high level.
X
X
Table 12. Truth table in fault conditions (detected on OUT )
A
INA
INB
DIAGA/ENA DIAGB/ENB
OUTA
OUTB
GATEA
GATEB
1
1
0
0
X
1
0
X
X
1
0
1
0
X
X
X
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
Open
Open
Open
Open
Open
Open
Open
Open
Open
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Open
H
Open
Open
Open
Open
H
Open
3.3
Test mode
The PWM pin allows to test the load connection between two half-bridges. In the test mode
(V =-2V) the external Power Mos gate drivers are disabled. The IN or IN inputs allow to
pwm
A
B
turn-on the high-side A or B, respectively, in order to connect one side of the load at V
CC
voltage. The check of the voltage on the other side of the load allow to verify the continuity of
the load connection. In case of load disconnection the DIAD /EN pin corresponding to the
X
X
faulty output is pulled down.
13/20
Application information
VND670SP
Table 13. Electrical transient requirements
ISO T/R
7637/1
Test level
I
II
III
IV
Delays and impedance
Test pulse
1
2
- 25V(1)
+ 25V(1)
- 25V(1)
+ 25V(1)
- 4V(1)
- 50V(1)
+ 50V(1)
- 50V(1)
+ 50V(1)
- 5V(1)
- 75V(1)
+ 75V(1)
- 100V(1)
+ 75V(1)
- 6V(1)
- 100V(1)
+ 100V(1)
- 150V(1)
+ 100V(1)
- 7V(1)
2ms, 10Ω
0.2ms, 10Ω
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
3a
3b
4
5
+ 26.5V(1)
+ 46.5V(2)
+ 66.5V(2)
+ 86.5V(2)
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.
Figure 9.
Waveforms (1)
OUTA shorted to VCC and undervoltage shutdown
IN
IN
A
B
OUT
A
OUT
B
GATE
A
B
GATE
DIAG /EN
B
B
DIAG /EN
A
A
normal operation
OUT shorted to V
normal operation
undervoltage shutdown
A
CC
Load disconnection test (INA=1, PWM=-2V)
IN
A
IN
B
PWM
(test mode)
OUT
A
OUT
B
GATE
A
GATE
B
DIAG /EN
A
A
DIAG /EN
B
B
load connected
load connected back
load disconnected
14/20
VND670SP
Application information
Figure 10. Waveforms (2)
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
DIAG /EN
A
A
B
DIAG /EN
B
IN
IN
A
B
PWM
OUT
A
OUT
B
GATE
GATE
A
B
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
DIAG /EN
A
A
DIAG /EN
B
B
IN
IN
A
B
PWM
OUT
A
OUT
B
GATE
A
B
GATE
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
IN
IN
A
B
I
LIM
I
OUTA
T
TSD
T
j
DIAG /EN
A
A
DIAG /EN
B
B
GATE
A
B
GATE
normal operation
normal operation
OUT shorted to ground
A
15/20
Package and packing information
VND670SP
4
Package and packing information
4.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
4.2
PowerSO-10 mechanical data
Figure 11. PowerSO-10 package dimensions
B
0.10
E
A B
10
H
E
E2
E4
1
SEATING
PLANE
DETAIL "A"
e
B
A
C
0.25
D
=
=
=
=
h
D1
SEATING
PLANE
A
F
A1
L
A1
DETAIL "A"
α
16/20
VND670SP
Package and packing information
Table 14. PowerSO-10 mechanical data
mm
Dim.
Min.
Typ.
Max.
3.65
3.6
A
A(1)
A1
B
3.35
3.4
0
0.10
0.60
0.53
0.55
0.32
9.60
7.60
9.50
7.60
7.50
6.10
6.30
0.40
0.37
0.35
0.23
9.40
7.40
9.30
7.20
7.30
5.90
5.90
B(1)
C
C(1)
D
D1
E
E2
E2(1)
E4
E4(1)
e
1.27
F
1.25
1.20
1.35
1.40
F(1)
H
13.80
13.85
14.40
14.35
H(1)
h
0.50
L
1.20
0.80
0°
1.80
1.10
8°
L(1)
α
(1)
α
2°
8°
1. Muar only POA P013P.
17/20
Package and packing information
VND670SP
4.3
PowerSO-10 packing information
Figure 12. PowerSO-10 suggested Figure 13. PowerSO-10 tube shipment
pad layout
(no suffix)
14.6- 14.9
CASABLANCA
MUAR
C
B
10.8 - 11
6.30
C
A
A
0.67 - 0.73
0.54 - 0.6
B
1
2
3
10
9
All dimensions are in mm.
Base Q.ty Bulk Q.ty
8
9.5
Tube length (
0.5)
C (
B
7
4
5
1.27
A
0.1)
6
Casablanca
Muar
50
50
1000
1000
532
532
10.4 16.4
4.9 17.2
0.8
0.8
Figure 14. PowerSO-10 tape and reel shipment (suffix “TR”)
Reel dimensions
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
600
600
330
1.5
13
20.2
24.4
60
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
P0 ( 0.1)
P
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
24
D ( 0.1/-0) 1.5
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
D1 (min)
F ( 0.05)
K (max)
1.5
11.5
6.5
2
P1 ( 0.1)
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
18/20
VND670SP
Revision history
5
Revision history
Table 15. Document revision history
Date
Revision
Changes
03-May-2006
1
Initial release.
Document reformatted and restructured.
Added contents, list of tables and figures.
Added ECOPACK® packages information.
11-Dec-2008
2
19/20
VND670SP
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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20/20
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