VND7004AY_技术文档

VND7004AY

Double channel high-side driver with MultiSense analog

feedback for automotive applications

Datasheet - production data



Configurable latch-off on

overtemperature or power limitation

with dedicated fault reset pin

Loss of ground and loss of V_CC

Reverse battery with self switch of the

PowerMOS



Electrostatic discharge protection

Applications

Features

Specially intended for Automotive smart power

distribution, glow plugs, heating systems, DC

motors, relay replacement and high power

resistive and inductive actuators.

Max transient supply voltage

Operating voltage range

Typ. on-state resistance (per Ch)

Current limitation (typ)

V_CC

40 V

4 to 28 V

4 mΩ

R_ON

I_LIMH

I_STBY

100 A

Description

Standby current (max)

0.5 µA

The device is a double channel high-side driver

manufactured using ST proprietary VIPower^®

M0-7 technology and housed in PowerSSO-36

package. The device is designed to drive 12 V

automotive grounded loads through a 3 V and

5 V CMOS-compatible interface, providing

protection and diagnostics.



AEC-Q100 qualified

General



Double channel smart high-side driver

with MultiSense analog feedback

Very low standby current

Compatible with 3 V and 5 V CMOS

outputs



The device integrates advanced protective

functions such as load current limitation, overload

active management by power limitation and

overtemperature shutdown with configurable

latch-off.



MultiSense diagnostic functions



Multiplexed analog feedback of: load

current with high precision proportional

current mirror, V_CCsupply voltage and

T_CHIPdevice temperature

A FaultRST pin unlatches the output in case of

fault or disables the latch-off functionality.



Overload and short to ground (power

limitation) indication

A dedicated multifunction multiplexed analog

output pin delivers sophisticated diagnostic

functions including high precision proportional

load current sense, supply voltage feedback and

chip temperature sense, in addition to the

detection of overload and short circuit to ground,

short to V_CCand OFF-state open-load.



Thermal shutdown indication

OFF-state open-load detection

Output short to V_CCdetection

Sense enable/disable



Protections



Undervoltage shutdown

Overvoltage clamp

Load current limitation

Self limiting of fast thermal transients

A sense enable pin allows OFF-state diagnosis to

be disabled during the module low-power mode

as well as external sense resistor sharing among

similar devices.

November 2016

DocID027772 Rev 9

1/47

www.st.com

This is information on a product in full production.

Contents

VND7004AY

Contents

1

2

Block diagram and pin description................................................5

Electrical specification....................................................................7

2.1

2.2

2.3

2.4

2.5

Absolute maximum ratings................................................................7

Thermal data.....................................................................................8

Main electrical characteristics ...........................................................8

Waveforms......................................................................................20

Electrical characteristics curves ......................................................22

3

4

Protections.....................................................................................26

3.1

3.2

3.3

3.4

Power limitation...............................................................................26

Thermal shutdown...........................................................................26

Current limitation.............................................................................26

Negative voltage clamp...................................................................26

Application information ................................................................27

4.1

4.2

4.3

4.4

GND protection network against reverse battery.............................27

Immunity against transient electrical disturbances..........................28

MCU I/Os protection........................................................................28

Multisense - analog current sense ..................................................29

4.4.1

4.4.2

4.4.3

Principle of Multisense signal generation......................................... 30

TCASE and VCC monitor................................................................. 32

Short to VCC and OFF-state open-load detection ........................... 33

5

Package and PCB thermal data....................................................34

5.1

PowerSSO-36 thermal data ............................................................34

6

7

Maximum demagnetization energy (VCC = 16 V)........................38

Package information .....................................................................39

7.1

7.2

7.3

PowerSSO-36 package information................................................39

PowerSSO-36 packing information .................................................41

PowerSSO-36 marking information.................................................43

8

9

Order codes ...................................................................................44

Revision history ............................................................................45

2/47

DocID027772 Rev 9

VND7004AY

List of tables

Table 1: Pin functions .................................................................................................................................5

Table 2: Suggested connections for unused and not connected pins........................................................6

Table 3: Absolute maximum ratings ...........................................................................................................7

Table 4: Thermal data.................................................................................................................................8

Table 5: Power section ...............................................................................................................................8

Table 6: Switching.....................................................................................................................................10

Table 7: Logic inputs.................................................................................................................................10

Table 8: Protections..................................................................................................................................11

Table 9: MultiSense ..................................................................................................................................12

Table 10: Truth table.................................................................................................................................19

Table 11: MultiSense multiplexer addressing...........................................................................................19

Table 12: ISO 7637-2 - electrical transient conduction along supply line.................................................28

Table 13: MultiSense pin levels in off-state ..............................................................................................32

Table 14: PCB properties .........................................................................................................................35

Table 15: Thermal parameters .................................................................................................................37

Table 16: PowerSSO-36 mechanical data................................................................................................39

Table 17: Reel dimensions .......................................................................................................................41

Table 18: PowerSSO-36 carrier tape dimensions ....................................................................................42

Table 19: Device summary.......................................................................................................................44

Table 20: Document revision history ........................................................................................................45

DocID027772 Rev 9

3/47

List of figures

VND7004AY

List of figures

Figure 1: Block diagram..............................................................................................................................5

Figure 2: Configuration diagram (top view).................................................................................................6

Figure 3: Current and voltage conventions.................................................................................................7

Figure 4: Switching time and Pulse skew .................................................................................................17

Figure 5: MultiSense timings (current sense mode).................................................................................17

Figure 6: Multisense timings (chip temperature and VCC sense mode) ..................................................18

Figure 7: TDSTKON..................................................................................................................................18

Figure 8: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ........................20

Figure 9: Latch functionality - behavior in hard short circuit condition......................................................20

Figure 10: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off)....21

Figure 11: Standby mode activation .........................................................................................................21

Figure 12: Standby state diagram.............................................................................................................22

Figure 13: OFF-state output current .........................................................................................................22

Figure 14: Standby current .......................................................................................................................22

Figure 15: IGND(ON) vs. Iout ...................................................................................................................22

Figure 16: Logic Input high level voltage ..................................................................................................22

Figure 17: Logic Input low level voltage....................................................................................................23

Figure 18: High level logic input current ...................................................................................................23

Figure 19: Low level logic input current ....................................................................................................23

Figure 20: Logic Input hysteresis voltage .................................................................................................23

Figure 21: FaultRST Input clamp voltage .................................................................................................23

Figure 22: Undervoltage shutdown...........................................................................................................23

Figure 23: On-state resistance vs. Tcase.................................................................................................24

Figure 24: On-state resistance vs. VCC ...................................................................................................24

Figure 25: Turn-on voltage slope..............................................................................................................24

Figure 26: Turn-off voltage slope..............................................................................................................24

Figure 27: Won vs. Tcase.........................................................................................................................24

Figure 28: Woff vs. Tcase.........................................................................................................................24

Figure 29: OFF-state open-load voltage detection threshold ...................................................................25

Figure 30: Vsense clamp vs. Tcase..........................................................................................................25

Figure 31: Vsenseh vs. Tcase ..................................................................................................................25

Figure 32: Application diagram.................................................................................................................27

Figure 33: Simplified internal structure .....................................................................................................27

Figure 34: MultiSense and diagnostic – block diagram............................................................................29

Figure 35: MultiSense block diagram .......................................................................................................30

Figure 36: Analogue HSD – open-load detection in off-state ...................................................................31

Figure 37: Open-load / short to VCC condition.........................................................................................32

Figure 38: GND voltage shift ....................................................................................................................33

Figure 39: PowerSSO-36 PC board .........................................................................................................34

Figure 40: Rthj-amb vs PCB copper area in open box free air conditions ...............................................35

Figure 41: PowerSSO-36 thermal impedance junction ambient single pulse ..........................................36

Figure 42: Thermal fitting model for PowerSSO-36..................................................................................36

Figure 43: Maximum turn off current versus inductance ..........................................................................38

Figure 44: PowerSSO-36 package outline ...............................................................................................39

Figure 45: PowerSSO-36 reel 13" ............................................................................................................41

Figure 46: PowerSSO-36 carrier tape ......................................................................................................42

Figure 47: PowerSSO-36 schematic drawing of leader and trailer tape ..................................................43

Figure 48: PowerSSO-36 marking information.........................................................................................43

4/47

DocID027772 Rev 9

VND7004AY

Block diagram and pin description

1

Block diagram and pin description

Figure 1: Block diagram

V_CC

Internal supply

V_CC– GND

Clamp

Undervoltage

shut-down

CH1

Channe l 1

Control & Diagno stic

V_CC– OUT

Clamp

Channe l 0

CH0

FaultRST

INPUT

1

Gate Driver

INPUT₀

OUTPUT

1

SEL

1

T

V

CC

SEL

0

Current

Limitation

SEn

Power Limitation

Overtemperature

T

Multisense

Short to V_CC

Open-Loadin OFF

Current

Sense

0

Fault

V_SENSEH

GND

OUTPUT

0

Table 1: Pin functions

Function

Name

V_CC

Battery connection.

OUTPUT_0,1Power output.

GND

Ground connection.

Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS

outputs. They control output switch state.

INPUT_0,1

Multiplexed analog sense output pin; it delivers a current proportional to the selected

diagnostic: load current, supply voltage or chip temperature.

MultiSense

SEn

Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense

diagnostic pin.

Active high compatible with 3 V and 5 V CMOS outputs pin; they address the

MultiSense multiplexer.

SEL_0,1

Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in

case of fault; If kept low, sets the outputs in auto-restart mode

FaultRST

DocID027772 Rev 9

5/47

Block diagram and pin description

VND7004AY

Figure 2: Configuration diagram (top view)

OUTPUT0

N.C.

OUTPUT1

1

2

3

4

5

6

7

36

35

34

33

32

31

30

OUTPUT1

N.C.

TAB/Vcc

8

9

10

11

12

29

28

27

26

25

N.C.

13

14

15

16

24

23

22

21

N.C.

SEn

N.C.

SEL1

N.C.

INPUT1

INPUT0

MultiSense

GND

SEL0 17

18

20

19

N.C.

FaultRST

PowerSSO-36

Table 2: Suggested connections for unused and not connected pins

SEn, SELx,

FaultRST

Connection /

MultiSense

N.C.

Output

Input

Floating

Not allowed

X ⁽¹⁾

X

Through 1 kΩ

Not

allowed

Through 10 kΩ

To ground

resistor

Notes:

⁽¹⁾X: do not care.

6/47

DocID027772 Rev 9

VND7004AY

Electrical specification

2

Electrical specification

Figure 3: Current and voltage conventions

I_S

V_CC

V_Fn

I_FR

I_OUT

FaultRST

SE_n

OUTPUT_0,1

MultiSense

I_SEn

V_OUT

I_SENSE

I_SEL

SEL_0,1

V_SENSE

I_IN

INPUT_0,1

I_GND

GAPGCFT00315

V_F= V_OUT- V_CCwhen V_OUT> V_CCand INPUT = LOW.

2.1

Absolute maximum ratings

Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to the conditions in table below for extended

periods may affect device reliability.

Table 3: Absolute maximum ratings

Symbol

V_CC

Parameter

Value

38

Unit

DC supply voltage

V

-V_CC

Reverse DC supply voltage

16

Maximum transient supply voltage (ISO 7637-2:2004 Pulse 5b

level IV clamped to 40 V; R_L= 4 Ω)

V_CCPK

40

V

V_CCJS

-I_GND

Maximum jump start voltage for single pulse short circuit protection

DC reverse ground pin current

28

V

200

mA

Internally

limited

I_OUT

OUTPUT_0,1DC output current

A

-I_OUT

I_IN

Reverse DC output current

INPUT_0,1DC input current

SEn DC input current

65

-1 to 10

7.5

I_SEn

I_SEL

I_FR

mA

SEL_0,1DC input current

FaultRST DC input current

FaultRST DC input voltage

V_FR

V

DocID027772 Rev 9

7/47

Electrical specification

VND7004AY

Symbol

Parameter

Value

Unit

MultiSense pin DC output current (V_GND= V_CCand V_SENSE< 0 V)

MultiSense pin DC output current in reverse (V_CC< 0 V)

10

I_SENSE

mA

-20

Maximum switching energy (single pulse) (T_DEMAG= 0.4 ms;

T_jstart= 150 °C)

E_MAX

103

mJ

Electrostatic discharge (JEDEC 22A-114F)

4000

2000

4000

V



INPUT_0,1



MultiSense

SEn, SEL_0,1, FaultRST

OUTPUT_0,1

V_CC

V_ESD

T_j

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

750

V

-40 to 150

-55 to 150

°C

T_stg

2.2

Thermal data

Table 4: Thermal data

Parameter

Symbol

Typ. value

3.4

Unit

R_thj-board

R_thj-amb

Thermal resistance junction-board ⁽¹⁾

Thermal resistance junction-ambient (JEDEC JESD 51-5)⁽¹⁾⁽²⁾

Thermal resistance junction-ambient (JEDEC JESD 51-7)⁽¹⁾⁽³⁾

50.6

°C/W

15.8

Notes:

⁽¹⁾One channel ON.

⁽²⁾Device mounted on two-layers 2s0p PCB with 2 cm²heatsink copper trace

⁽³⁾Device mounted on four-layers 2s2p PCB

2.3

Main electrical characteristics

7 V < V_CC< 28 V; -40°C < T_j< 150°C, unless otherwise specified.

All typical values refer to V_CC= 13 V; T_j= 25°C, unless otherwise specified.

Table 5: Power section

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

Operating supply

voltage

V_CC

4

13

28

4

V

Undervoltage

shutdown

V_USD

Undervoltage

shutdown reset

V_USDReset

V_USDhyst

5

Undervoltage

shutdown hysteresis

0.3

4

I_OUT= 15 A; T_j= 25°C

R_ON

On-state resistance⁽¹⁾

I_OUT= 15 A; T_j= 150°C

8

6

mΩ

I_OUT= 15 A; V_CC= 4 V; T_j= 25°C

8/47

DocID027772 Rev 9

VND7004AY

Electrical specification

Symbol

R_{ON_REV}

V_clamp

Parameter

Test conditions

Min. Typ. Max. Unit

On-state resistance in

reverse battery

I_OUT= -15 A; V_CC= -13 V;

T_j= 25°C

mΩ

4

Clamp voltage

I_S= 20 mA; 25°C < T_j< 150°C

41

46

52

V

V_CC= 13 V;

V_IN= V_OUT= V_FR= V_SEn= 0 V;

V_SEL0,1= 0 V; T_j= 25°C

0.5

Supply current in

standby at

V_CC= 13 V⁽²⁾

V_CC= 13 V;

V_IN= V_OUT= V_FR= V_SEn= 0 V;

V_SEL0,1= 0 V; T_j= 85°C

I_STBY

1.9

15

µA

(3)

V_CC= 13 V;

V_IN= V_OUT= V_FR= V_SEn= 0 V;

V_SEL0,1= 0 V; T_j= 125°C

V_CC= 13 V;

V_IN= V_OUT= V_FR= V_SEL0,1= 0 V;

V_SEn= 5 V to 0 V

Standby mode

blanking time

t_{D_STBY}

60

300

6

550

µs

V_CC= 13 V;

V_SEn= V_FR= V_SEL0,1= 0 V;

V_IN0= 5 V; V_IN1= 5 V;

I_S(ON)

Supply current

12

mA

I_OUT0= 0 A; I_OUT1= 0 A

Control stage current

consumption in ON

state. All channels

active.

V_CC= 13 V; V_SEn= 5 V;

V_FR= V_SEL0,1= 0 V; V_IN0= 5 V;

V_IN1= 5 V; I_OUT0,1= 15 A

I_GND(ON)

mA

V_IN= V_OUT= 0 V; V_CC= 13 V;

T_j= 25°C

0

0.01

0.5

7.5

0.7

Off-state output

current ⁽²⁾

I_L(off)

µA

V

V_IN= V_OUT= 0 V; V_CC= 13 V;

T_j= 125°C

Output - V_CCdiode

voltage

V_F

I_OUT= -15 A; T_j= 150°C

Notes:

⁽¹⁾For each channel

⁽²⁾PowerMOS leakage included.

⁽³⁾Parameter specified by design; not subjected to production test.

DocID027772 Rev 9

9/47

Electrical specification

VND7004AY

Table 6: Switching

V_CC= 13 V; -40°C < T_j< 150°C, unless otherwise specified

Test

conditions

Symbol

Parameter

Turn-on delay time

Min. Typ. Max. Unit

(1)

t_d(on)

60

50

110

100

195

160

R_L= 0.87 Ω

µs

(1)

t_d(off)

Turn-off delay time

(1)

(dV_OUT/dt)_on

(dV_OUT/dt)_off

Turn-on voltage slope

0.05 0.21 0.35

R_L= 0.87 Ω

V/µs

mJ

Turn-off voltage slope

Switching energy losses at turn-on

W_ON

—

2.3

3.7⁽²⁾

(t_won

Switching energy losses at turn-off

(t_woff

Differential pulse skew (t_PHL- t_PLH

)

W_OFF

R_L= 0.87 Ω

—

2.5

-45

4.5⁽²⁾

20

mJ

µs

)

(1)

t_SKEW

)

-110

Notes:

⁽¹⁾See Figure 4: "Switching time and Pulse skew".

⁽²⁾Parameter guaranteed by design and characterization; not subjected to production test.

Table 7: Logic inputs

7 V < V_CC< 28 V; -40°C < T_j< 150°C

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

INPUT_0,1characteristics

V_IL

I_IL

Input low level voltage

0.9

V

µA

V

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V_IN= 0.9 V

V_IN= 2.1 V

1

V_IH

2.1

I_IH

10

µA

V

V_I(hyst)

0.2

5.3

I_IN= 1 mA

I_IN= -1 mA

7.2

V_ICL

Input clamp voltage

V

-0.7

FaultRST characteristics

V_FRL

I_FRL

V_FRH

I_FRH

Input low level voltage

0.9

V

µA

V

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V_IN= 0.9 V

V_IN= 2.1 V

1

2.1

10

µA

V

V_FR(hyst)

0.2

5.3

I_IN= 1 mA

I_IN= -1 mA

7.5

V_FRCL

Input clamp voltage

V

-0.7

SEL_0,1characteristics (7 V < V_CC< 18 V)

V_SELL

I_SELL

V_SELH

I_SELH

Input low level voltage

Low level input current

Input high level voltage

High level input current

0.9

10

V

µA

V

V_IN= 0.9 V

V_IN= 2.1 V

1

2.1

µA

10/47

DocID027772 Rev 9

VND7004AY

7 V < V_CC< 28 V; -40°C < T_j< 150°C

Electrical specification

Symbol

Parameter

Test conditions

Min.

0.2

Typ.

Max.

Unit

V_SEL(hyst)

Input hysteresis voltage

V

I_IN= 1 mA

I_IN= -1 mA

5.3

7.2

V_SELCL

Input clamp voltage

V

-0.7

SEn characteristics (7 V < V_CC< 18 V)

V_SEnL

I_SEnL

V_SEnH

I_SEnH

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

0.9

V

µA

V

V_IN= 0.9 V

V_IN= 2.1 V

1

2.1

10

µA

V

V_SEn(hyst)

0.2

5.3

I_IN= 1 mA

I_IN= -1 mA

7.2

V_SEnCL

Input clamp voltage

V

-0.7

Table 8: Protections

Test conditions

7 V < V_CC< 18 V; -40°C < T_j< 150°C

Symbol

Parameter

Min.

Typ.

Max. Unit

V_CC= 13 V

70

100

DC short circuit

current

I_LIMH

140

A

4 V < V_CC< 18 V⁽¹⁾

V_CC= 13 V;

Short circuit current

during thermal cycling

I_LIML

33

T_R< T_j< T_TSD

Shutdown

temperature

T_TSD

T_R

150

175

200

Reset temperature⁽¹⁾

T_RS+ 1 T_RS+ 7

135

°C

Thermal reset of fault

diagnostic indication

T_RS

V_FR= 0 V; V_SEn= 5 V

Thermal hysteresis

(T_TSD- T_R)⁽¹⁾

T_HYST

7

ΔT_{J_SD}

Dynamic temperature T_j= -40°C; V_CC= 13 V

60

K

V_FR= 5 V to 0 V;

Fault reset time for

t_{LATCH_RST}

V_SEn= 5 V; V_IN= 5 V;

output unlatch

3

10

20

µs

V_SEL0,1= 0 V

I_OUT= 2 A; L = 6 mH; T_j= -

40°C

V_CC

38

-

V

Turn-off output

voltage clamp

V_DEMAG

I_OUT= 2 A; L = 6 mH;

T_j= 25°C to 150°C

V_CC

41

V_CC

46

-

V_CC

52

-

Notes:

⁽¹⁾Parameter guaranteed by design and characterization; not subjected to production test.

DocID027772 Rev 9

11/47

Electrical specification

7 V < V_CC< 18 V; -40°C < T_j< 150°C

VND7004AY

Table 9: MultiSense

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

V_SEn= 0 V; I_SENSE= 1 mA

-17

-12

MultiSense clamp

voltage

V_{SENSE_CL}

V

V_SEn= 0 V; I_SENSE= -1 mA

7

Current sense characteristics

I_OUT= 3.5 A; V_SENSE= 4 V;

V_SEn= 5 V

K₁

I_OUT/I_SENSE

1500 14200 31500

I_OUT= 3.5 A; V_SENSE= 4 V;

V_SEn= 5 V

Current sense

ratio drift

(1)(2)

dK₁/K₁

-30

30

%

I_OUT= 10 A; V_SENSE= 4 V;

V_SEn= 5 V

K_GP

dK_GP/K_GP

K₂

I_OUT/I_SENSE

7990 13900 21050

I_OUT= 10 A; V_SENSE= 4 V;

V_SEn= 5 V

Current sense

ratio drift

(1)(2)

-10

10

I_OUT= 15 A; V_SENSE= 4 V;

V_SEn= 5 V

I_OUT/I_SENSE

9580 13850 19020

I_OUT= 15 A; V_SENSE= 4 V;

V_SEn= 5 V

Current sense

ratio drift

(1)(2)

dK₂/K₂

K₃

-7

7

I_OUT= 45 A; V_SENSE= 4 V;

V_SEn= 5 V

I_OUT/I_SENSE

11470 13800 15840

Current sense

ratio drift

I_OUT= 45 A; V_SENSE= 4 V;

V_SEn= 5 V

(1)(2)

dK₃/K₃

-5

0

5

MultiSense disabled:

V_SEn= 0 V

0.5

MultiSense disabled:

-1 V < V_SENSE< 5 V⁽¹⁾

-0.5

MultiSense enabled:

V_SEn= 5 V; All channels

ON; I_OUTX= 0 A; Ch_X

diagnostic selected;



E.g. Ch₀:

0

120

V_IN0= 5 V;

V_IN1= 5 V;

V_SEL0= 0 V;

V_SEL1= 0 V;

I_OUT0= 0 A;

I_OUT1= 15 A

MultiSense

leakage current

I_SENSE0

µA

MultiSense enabled:

V_SEn= 5 V; Ch_XOFF; Ch_X

diagnostic selected:



E.g. Ch₀:

0

2

V_IN0= 0 V;

V_IN1= 5 V;

V_SEL0= 0 V;

V_SEL1= 0 V;

I_OUT1= 15 A

12/47

DocID027772 Rev 9

VND7004AY

7 V < V_CC< 18 V; -40°C < T_j< 150°C

Electrical specification

Symbol

Parameter

Test conditions

V_SEn= 5 V;

Min.

Typ.

Max.

Unit

R_SENSE= 2.7 kΩ;

Output Voltage for

MultiSense

shutdown



E.g. Ch₀:

(1)

V_{OUT_MSD}

5

V

V_IN0= 5 V;

V_SEL0= 0 V;

V_SEL1= 0 V;

I_OUT0= 15 A

V_CC= 7 V;

R_SENSE= 2.7 kΩ;

Multisense

saturation voltage

V_{SENSE_SAT}

V_SEn= 5 V; V_IN0= 5 V;

V_SEL0= 0 V; V_SEL1= 0 V;

I_OUT0= 45 A; T_j= 150°C

5

V

V_CC= 7 V; V_SENSE= 4 V;

V_IN0= 5 V; V_SEn= 5 V;

V_SEL0= 0 V; V_SEL1= 0 V;

CS saturation

current

(1)

I_{SENSE_SAT}

4

mA

A

T_j= 150°C

V_CC= 7 V; V_SENSE= 4 V;

V_IN0= 5 V; V_SEn= 5 V;

V_SEL0= 0 V; V_SEL1= 0 V;

Output saturation

current

(1)

I_{OUT_SAT}

65

T_j= 150°C

OFF-state diagnostic

V_SEn= 5 V; Ch_XOFF;

OFF-state open-

Ch_Xdiagnostic selected

load voltage

detection

threshold



E.g: Ch₀

V_OL

2

3

4

V

V_IN0= 0 V;

V_SEL0= 0 V;

V_SEL1= 0 V

V_IN= 0 V; V_OUT= V_OL

;

OFF-state output

sink current

I_L(off2)

-100

-15

µA

T_j= -40°C to 125°C

V_SEn= 5 V; Ch_XON to

OFF transition;

OFF-state

Ch_Xdiagnostic selected

diagnostic delay

time from falling

edge of INPUT

(see Figure 7:

"TDSTKON")



E.g: Ch₀

t_DSTKON

100

350

700

µs

V_IN0= 5 V to 0 V;

V_SEL0= 0 V;

V_SEL1= 0 V;

I_OUT0= 0 A;

V_OUT= 4 V

Settling time for

valid OFF-state

open load

diagnostic

indication from

rising edge of SEn

V_IN0= 0 V; V_IN1= 0 V;

V_FR= 0 V; V_SEL0= 0 V;

V_SEL1= 0 V; V_OUT0= 4 V;

V_SEn= 0 V to 5 V

t_{D_OL_V}

60

DocID027772 Rev 9

13/47

Electrical specification

7 V < V_CC< 18 V; -40°C < T_j< 150°C

VND7004AY

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

V_SEn= 5 V; Ch_XOFF;

Ch_Xdiagnostic selected

OFF-state



E.g: Ch₀

diagnostic delay

time from rising

edge of V_OUT

t_{D_VOL}

5

30

µs

V_IN0= 0 V;

V_SEL0= 0 V;

V_SEL1= 0 V;

V_OUT= 0 V to 4 V

Chip temperature analog feedback

V_SEn= 5 V; V_SEL0= 0 V;

V_SEL1= 5 V; V_IN0,1= 0 V;

R_SENSE= 1 kΩ; T_j= -40°C

2.325

1.985

1.435

2.41

2.07

2.495

2.155

1.605

V

MultiSense output

V_SEn= 5 V; V_SEL0= 0 V;

V_SEL1= 5 V; V_IN0,1= 0 V;

R_SENSE= 1 kΩ; T_j= 25°C

voltage

proportional to

V_{SENSE_TC}

chip temperature

V_SEn= 5 V; V_SEL0= 0 V;

V_SEL1= 5 V; V_IN0,1= 0 V;

R_SENSE= 1 kΩ; T_j= 125°C

1.52

-5.5

V

Temperature

dV_{SENSE_TC}/dT⁽¹⁾

T_j= -40°C to 150°C

mV/K

coefficient

Transfer function

V_{SENSE_TC}(T) = V_{SENSE_TC}(T₀) + dV_{SENSE_TC}/ dT * (T - T₀)

V_CCsupply voltage analog feedback

MultiSense output

V_CC= 13 V; V_SEn= 5 V;

V_SEL0= 5 V; V_SEL1= 5 V;

voltage

V_{SENSE_VCC}

3.16

3.23

3.3

V

proportional to V_CCV_IN0,1= 0 V;

supply voltage

R_SENSE= 1 kΩ

Transfer function ⁽³⁾

V_{SENSE_VCC}= V_CC/ 4

Fault diagnostic feedback (see Table 10: "Truth table")

V_CC= 13 V;

R_SENSE= 1 kΩ;



E.g: Ch₀in open

load V_IN0= 0 V;

V_SEn= 5 V;

V_SEL0= 0 V;

V_SEL1= 0 V;

I_OUT0= 0 A;

MultiSense output

voltage in fault

condition

V_SENSEH

5

7

6.6

30

V

V_OUT= 4 V

MultiSense output

current in fault

condition

I_SENSEH

V_CC= 13 V; V_SENSE= 5 V

20

mA

MultiSense timings (current sense mode - see Figure 5: "MultiSense timings (current sense

mode)")⁽⁴⁾

Current sense

V_IN= 5 V; V_SEn= 0 V to

t_DSENSE1H

settling time from

5 V; R_SENSE= 1 kΩ;

60

µs

rising edge of SEn R_L= 0.87 Ω

14/47

DocID027772 Rev 9

VND7004AY

7 V < V_CC< 18 V; -40°C < T_j< 150°C

Electrical specification

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Current sense

disable delay time

from falling edge

of SEn

V_IN= 5 V; V_SEn= 5 V to

0 V; R_SENSE= 1 kΩ;

R_L= 0.87 Ω

t_DSENSE1L

5

20

µs

Current sense

settling time from

rising edge of

INPUT

V_IN= 0 V to 5 V;

V_SEn= 5 V;

R_SENSE= 1 kΩ;

R_L= 0.87 Ω

t_DSENSE2H

Δt_DSENSE2H

t_DSENSE2L

170

400

200

250

µs

Current sense

settling time from

rising edge of I_OUT

(dynamic

V_IN= 5 V; V_SEn= 5 V;

R_SENSE= 1 kΩ; I_SENSE

= 90 % of I_SENSEMAX

;

response to a step R_L= 0.87 Ω

change of I_OUT

)

Current sense

V_IN= 5 V to 0 V;

V_SEn= 5 V;

R_SENSE= 1 kΩ;

R_L= 0.87 Ω

turn-off delay time

from falling edge

of INPUT

50

MultiSense timings (chip temperature sense mode - see Figure 6: "Multisense timings (chip

temperature and VCC sense mode)")⁽⁴⁾

V_{SENSE_TC}settling

time from rising

edge of SEn

V_SEn= 0 V to 5 V;

V_SEL0= 0 V; V_SEL1= 5 V;

R_SENSE= 1 kΩ

t_DSENSE3H

60

20

µs

V_{SENSE_TC}disable

delay time from

falling edge of

SEn

V_SEn= 5 V to 0 V;

V_SEL0= 0 V; V_SEL1= 5 V;

R_SENSE= 1 kΩ

t_DSENSE3L

MultiSense timings (V_CCvoltage sense mode - see Figure 6: "Multisense timings (chip

temperature and VCC sense mode)")⁽⁴⁾

V_{SENSE_VCC}settling V_SEn= 0 V to 5 V;

t_DSENSE4H

time from rising

edge of SEn

V_SEL0= 5 V; V_SEL1= 5 V;

R_SENSE= 1 kΩ

60

20

µs

V_{SENSE_VCC}disable

delay time from

falling edge of

SEn

V_SEn= 5 V to 0 V;

V_SEL0= 5 V; V_SEL1= 5 V;

R_SENSE= 1 kΩ

t_DSENSE4L

MultiSense timings (Multiplexer transition times)⁽⁴⁾

V_IN0= 5 V; V_IN1= 5 V;

MultiSense

transition delay

from Ch_Xto Ch_Y

V_SEn= 5 V; V_SEL1= 0 V;

V_SEL0= 0 V to 5 V;

I_OUT0= 0 A; I_OUT1= 15 A;

R_SENSE= 1 kΩ

t_{D_XtoY}

20

60

µs

MultiSense

transition delay

from current

V_IN0= 5 V; V_SEn= 5 V;

V_SEL0= 0 V; V_SEL1= 0 V to

5 V; I_OUT0= 1.5 A;

t_{D_CStoTC}

sense to T_Csense R_SENSE= 1 kΩ

DocID027772 Rev 9

15/47

Electrical specification

7 V < V_CC< 18 V; -40°C < T_j< 150°C

VND7004AY

Symbol

Parameter

MultiSense

transition delay

from T_Csense to

current sense

Test conditions

Min.

Typ.

Max.

Unit

V_IN0= 5 V; V_SEn= 5 V;

V_SEL0= 0 V; V_SEL1= 5 V to

0 V; I_OUT0= 1.5 A;

t_{D_TCtoCS}

20

µs

R_SENSE= 1 kΩ

MultiSense

transition delay

from current

sense to V_CC

sense

V_IN1= 5 V; V_SEn= 5 V;

V_SEL0= 5 V; V_SEL1= 0 V to

5 V; I_OUT1= 15A;

t_{D_CStoVCC}

60

µs

R_SENSE= 1 kΩ

MultiSense

V_IN1= 5 V; V_SEn= 5 V;

V_SEL0= 5 V; V_SEL1= 5 V to

0 V; I_OUT1= 15 A;

transition delay

from V_CCsense to

current sense

t_{D_VCCtoCS}

t_{D_TCtoVCC}

t_{D_VCCtoTC}

20

µs

R_SENSE= 1 kΩ

MultiSense

V_CC= 13 V; T_j= 125°C;

V_SEn= 5 V; V_SEL0= 0 V to

5 V; V_SEL1= 5 V;

transition delay

from T_Csense to

V_CCsense

R_SENSE= 1 kΩ

MultiSense

V_CC= 13 V; T_j= 125°C;

V_SEn= 5 V; V_SEL0= 5 V to

0 V; V_SEL1= 5 V;

transition delay

from V_CCsense to

T_Csense

R_SENSE= 1 kΩ

MultiSense

transition delay

from stable

current sense on

Ch_Xto V_SENSEHon

Ch_Y

V_IN0= 5 V; V_IN1= 0 V;

V_SEn= 5 V; V_SEL1= 0 V;

V_SEL0= 0 V to 5 V;

I_OUT0= 3 A; V_OUT1= 15 V;

R_SENSE= 1 kΩ

t_{D_CStoVSENSEH}

20

µs

Notes:

⁽¹⁾Parameter guaranteed by design and characterization; not subjected to production test.

⁽²⁾All values refer to V_CC= 13 V; T_j= 25 °C, unless otherwise specified.

(3)

V

sensing and T_Csensing are referred to GND potential.

CC

⁽⁴⁾Transition delay are measured up to +/- 10% of final conditions.

16/47

DocID027772 Rev 9

VND7004AY

Electrical specification

Figure 4: Switching time and Pulse skew

Figure 5: MultiSense timings (current sense mode)

DocID027772 Rev 9

17/47

Electrical specification

VND7004AY

Figure 6: Multisense timings (chip temperature and VCC sense mode)

Figure 7: TDSTKON

18/47

DocID027772 Rev 9

VND7004AY

Electrical specification

Table 10: Truth table

IN_XFR SEn SEL_XOUT_XMultiSense

Mode

Standby

Conditions

Comments

Low quiescent

current

consumption

All logic inputs

low

L

X

L

Hi-Z

See ⁽¹⁾

Outputs

configured for

auto-restart

Nominal load

connected;

H

Normal

See ⁽¹⁾

T_j< 150 °C

Outputs

configured for

Latch-off

H

L

H

X

H

L

See ⁽¹⁾

Overload or

short to GND

causing:

Output cycles

with

temperature

hysteresis

H

L

H

L

See ⁽¹⁾

Overload

See ⁽¹⁾

T_j> T_TSDor

ΔT_j> ΔT_{j_SD}

Output latches-

off

H

X

H

X

Re-start when

L

Hi-Z

V_CC< V_USD

(falling)

V_CC> V_USD

+

Undervoltage

X

V_USDhyst(rising)

Short to V_CC

Open-load

Inductive

L

X

H

See ⁽¹⁾

OFF-state

diagnostics

See ⁽¹⁾

External pull-up

Negative

L

X

< 0 V

See ⁽¹⁾

output voltage loads turn-off

Notes:

⁽¹⁾Refer to Table 11: "MultiSense multiplexer addressing"

Table 11: MultiSense multiplexer addressing

MultiSense output

SEn SEL₁SEL₀MUX channel

Normal

mode

OFF-state

diag. ⁽¹⁾

Negative

output

Overload

L

X

L

X

L

Hi-Z

Channel 0

diagnostic

I_SENSE

1/K * I_OUT0

=

V_SENSE

V_SENSEH

=

V_SENSE

V_SENSEH

=

H

Hi-Z

Channel 1

diagnostic

I_SENSE

1/K * I_OUT1

=

V_SENSE

V_SENSEH

=

V_SENSE

V_SENSEH

=

L

H

L

T_CHIPSense

V_CCSense

V_SENSE= V_{SENSE_TC}

V_SENSE= V_{SENSE_VCC}

H

Notes:

⁽¹⁾In case the output channel corresponding to the selected MUX channel is latched off while the

relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic.

Example 1: FR = 1; IN₀= 0; OUT₀= L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0.

Example 2: FR = 1; IN₀= 0; OUT₀= latched, V_OUT0> V_OL; MUX channel = channel 0 diagnostic;

Mutisense = V_SENSEH

DocID027772 Rev 9

19/47

Electrical specification

VND7004AY

2.4

Waveforms

Figure 8: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)

Figure 9: Latch functionality - behavior in hard short circuit condition

20/47

DocID027772 Rev 9

VND7004AY

Electrical specification

Figure 10: Latch functionality - behavior in hard short circuit condition (autorestart mode +

latch off)

Figure 11: Standby mode activation

DocID027772 Rev 9

21/47

Electrical specification

VND7004AY

Figure 12: Standby state diagram

2.5

Electrical characteristics curves

Figure 13: OFF-state output current

Figure 14: Standby current

Figure 15: IGND(ON) vs. Iout

Figure 16: Logic Input high level voltage

22/47

DocID027772 Rev 9

VND7004AY

Electrical specification

Figure 17: Logic Input low level voltage

Figure 19: Low level logic input current

Figure 21: FaultRST Input clamp voltage

Figure 18: High level logic input current

Figure 20: Logic Input hysteresis voltage

Figure 22: Undervoltage shutdown

DocID027772 Rev 9

23/47

Electrical specification

Figure 23: On-state resistance vs. Tcase

VND7004AY

Figure 24: On-state resistance vs. VCC

Figure 25: Turn-on voltage slope

Figure 26: Turn-off voltage slope

Figure 27: Won vs. Tcase

Figure 28: Woff vs. Tcase

24/47

DocID027772 Rev 9

VND7004AY

Electrical specification

Figure 29: OFF-state open-load voltage

detection threshold

Figure 30: Vsense clamp vs. Tcase

Figure 31: Vsenseh vs. Tcase

DocID027772 Rev 9

25/47

Protections

VND7004AY

3

Protections

3.1

Power limitation

The basic working principle of this protection consists of an indirect measurement of the

junction temperature swing ΔT_jthrough the direct measurement of the spatial temperature

gradient on the device surface in order to automatically shut off the output MOSFET as

soon as ΔT_jexceeds the safety level of 60 K. According to the voltage level on the

FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis

according to the maximum instantaneous power which can be handled (FaultRST = Low)

or remains off (FaultRST = High). The protection prevents fast thermal transient effects

and, consequently, reduces thermo-mechanical fatigue.

3.2

3.3

3.4

Thermal shutdown

In case the junction temperature of the device exceeds the maximum allowed threshold

(typically 175°C), it automatically switches off and the diagnostic indication is triggered.

According to the voltage level on the FaultRST pin, the device switches on again as soon

as its junction temperature drops to T_RS(FaultRST = Low) or remains off

(FaultRST = High).

Current limitation

The device is equipped with an output current limiter in order to protect the silicon as well

as the other components of the system (e.g. bonding wires, wiring harness, connectors,

loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or

during load power-up, the output current is clamped to a safety level, I_LIMH, by operating the

output power MOSFET in the active region.

Negative voltage clamp

In case the device drives inductive load, the output voltage reaches a negative value during

turn off. A negative voltage clamp structure limits the maximum negative voltage to a

certain value, V_DEMAG, allowing the inductor energy to be dissipated without damaging the

device.

26/47

DocID027772 Rev 9

VND7004AY

Application information

4

Application information

Figure 32: Application diagram

4.1

GND protection network against reverse battery

Figure 33: Simplified internal structure

Vcc

5V

Rprot

INPUT

Rprot

SEn

MCU

Dld

Rprot

FaultRST

OUTPUT

Multisense

GND

Rsense

GND

The device does not need any external components to protect the internal logic in case of a

reverse battery condition. The protection is provided by internal structures.

DocID027772 Rev 9

27/47

Application information

VND7004AY

In addition, due to the fact that the output MOSFET turns on even in reverse battery mode,

thus providing the same low ohmic path as in regular operating conditions, no additional

power dissipation has to be considered.

4.2

Immunity against transient electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the

supply lines and injected into the V_CCpin, is tested in accordance with ISO7637-2:2011 (E)

and ISO 16750-2:2010.

The related function performance status classification is shown in Table 12: "ISO 7637-2 -

electrical transient conduction along supply line".

Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and

in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present

device only, without components and accessed through V_CCand GND terminals.

Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as

follows: “The function does not perform as designed during the test but returns

automatically to normal operation after the test”.

Table 12: ISO 7637-2 - electrical transient conduction along supply line

Test pulse severity

Test

Pulse

2011(E)

Burst cycle /

pulse

Minimum

number of

pulses or test

time

level with Status II

functional performance

status

Pulse duration and

pulse generator

internal impedance

repetition time

(1)

Level

III

U_S

min

0.5 s

0.2 s

max

1

-112 V

+55 V

500 pulses

2 ms, 10 Ω

50 µs, 2 Ω

2a

III

5 s

100

ms

3a

IV

-220 V

1h

90 ms

0.1 µs, 50 Ω

100

ms

3b

IV

+150 V

-7 V

1h

0.1 µs, 50 Ω

4 ⁽²⁾

1 pulse

100 ms, 0.01 Ω

Load dump according to ISO 16750-2:2010

Test B ⁽³⁾

40 V

5 pulse

1 min

400 ms, 2 Ω

Notes:

⁽¹⁾U_Sis the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.

⁽²⁾Test pulse from ISO 7637-2:2004(E).

⁽³⁾With 40 V external suppressor referred to ground (-40°C < T_j< 150 °C).

4.3

MCU I/Os protection

If a ground protection network is used and negative transients are present on the V_CCline,

the control pins will be pulled negative. ST suggests to insert a resistor (R_prot) in line both to

prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.

The value of these resistors is a compromise between the leakage current of

microcontroller and the current required by the HSD I/Os (Input levels compatibility) with

the latch-up limit of microcontroller I/Os.

28/47

DocID027772 Rev 9

VND7004AY

Application information

Equation

V_CCpeak/I_latchup≤ R_prot≤ (V_OHµC- V_IH- V_GND) / I_IHmax

Calculation example:

For V_CCpeak= -150 V; I_latchup≥ 20 mA; V_OHµC≥ 4.5 V

7.5 kΩ ≤ R_prot≤ 140 kΩ.

Recommended values: R_prot= 15 kΩ

4.4

Multisense - analog current sense

Diagnostic information on device and load status are provided by an analog output pin

(MultiSense) delivering the following signals:



Current monitor: current mirror of channel output current

V_CCmonitor: voltage propotional to V_CC



T_CASE: voltage propotional to chip temperature

Those signals are routed through an analog multiplexer which is configured and controlled

by means of SELx and SEn pins, according to the address map in MultiSense multiplexer

addressing Table.

Figure 34: MultiSense and diagnostic – block diagram

DocID027772 Rev 9

29/47

Application information

VND7004AY

4.4.1

Principle of Multisense signal generation

Figure 35: MultiSense block diagram

Current monitor

When current mode is selected via MultiSense, this output is capable of providing:



Current mirror proportional to the load current in normal operation, delivering current

proportional to the load according to a known ratio named K



Diagnostics flag in fault conditions delivering fixed voltage V_SENSEH

The current delivered by the current sense circuit, I_SENSE, can be easily converted to a

voltage V_SENSEby using an external sense resistor, R_SENSE, allowing continuous load

monitoring and abnormal condition detection.

Normal operation (channel ON, no fault, SEn active)

While device is operating in normal conditions (no fault intervention), V_SENSEcalculation can

be done using simple equations

Current provided by MultiSense output: I_SENSE= I_OUT/K

Voltage on R_SENSE: V_SENSE= R_SENSE· I_SENSE= R_SENSE· I_OUT/K

30/47

DocID027772 Rev 9

VND7004AY

Where:

V_SENSEis the voltage measurable on R_SENSEresistor

I_SENSEis the current provided from MultiSense pin in current output mode

Application information



I_OUTis the current flowing through output

K factor represents the ratio between PowerMOS cells and SenseMOS cells; its

spread includes geometric factor spread, current sense amplifier offset and process

parameters spread of overall circuitry specifying the ratio between I_OUTand I_SENSE

.

Failure flag indication

In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin

which is switched to a “current limited” voltage source, V_SENSEH

.

In any case, the current sourced by the MultiSense in this condition is limited to I_SENSEH

.

The typical behavior in case of overload or hard short circuit is shown in Waveforms

section.

Figure 36: Analogue HSD – open-load detection in off-state

DocID027772 Rev 9

31/47

Application information

VND7004AY

Figure 37: Open-load / short to VCC condition

Table 13: MultiSense pin levels in off-state

Condition

Output

MultiSense

SEn

L

Hi-Z

V_SENSEH

Hi-Z

0

V_OUT> V_OL

H

L

Open-load

V_OUT< V_OL

V_OUT> V_OL

V_OUT< V_OL

H

L

Hi-Z

V_SENSEH

Hi-Z

0

Short to V_CC

Nominal

H

L

H

4.4.2

TCASE and VCC monitor

In this case, MultiSense output operates in voltage mode and output level is referred to

device GND. Care must be taken in case a GND network protection is used, because a

voltage shift is generated between the device GND and the microcontroller input GND

reference.

Figure 38: "GND voltage shift" shows the link between V_MEASUREDand the real V_SENSE

signal.

32/47

DocID027772 Rev 9

VND7004AY

Application information

Figure 38: GND voltage shift

V_CCmonitor

Battery monitoring channel provides V_SENSE= V_CC/ 8.

Case temperature monitor

Case temperature monitor is capable of providing information about the actual device

temperature. Since a diode is used for temperature sensing, the following equation

describes the link between temperature and output V_SENSElevel:

V_{SENSE_TC}(T) = V_{SENSE_TC}(T₀) + dV_{SENSE_TC}/ dT * (T - T₀)

where dV_{SENSE_TC}/ dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C)).

4.4.3

Short to VCC and OFF-state open-load detection

Short to V_CC

A short circuit between V_CCand output is indicated by the relevant current sense pin set to

V_SENSEHduring the device off-state. Small or no current is delivered by the current sense

during the on-state depending on the nature of the short circuit.

OFF-state open-load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor R_PUconnecting

the output to a positive supply voltage V_PU.

It is preferable that V_PUis switched off during the module standby mode in order to avoid

the overall standby current consumption to increase in normal conditions, i.e. when load is

connected.

R_PUmust be selected in order to ensure V_OUT> V_OLmaxin accordance with the following

equation:

Equation

DocID027772 Rev 9

33/47

Package and PCB thermal data

VND7004AY

5

Package and PCB thermal data

5.1

PowerSSO-36 thermal data

Figure 39: PowerSSO-36 PC board

34/47

DocID027772 Rev 9

VND7004AY

Package and PCB thermal data

Table 14: PCB properties

Dimension

Value

1.6 mm +/- 10%

129 mm x 60 mm

FR4

Board finish thickness

Board dimension

Board Material

Copper thickness (top and bottom layers)

Copper thickness (inner layers)

Thermal vias separation

0.070 mm

0.035 mm

1.2 mm

Thermal via diameter

0.3 mm +/- 0.08 mm

0.025 mm

Copper thickness on vias

Footprint dimension (top layer)

Heatsink copper area dimension (bottom layer)

4.1 mm x 6.5 mm

Footprint, 2 cm²or 8 cm²

Figure 40: Rthj-amb vs PCB copper area in open box free air conditions

RTHjamb

65

60

55

50

45

40

35

30

RTHjamb

0

2

4

6

8

10

DocID027772 Rev 9

35/47

Package and PCB thermal data

VND7004AY

Figure 41: PowerSSO-36 thermal impedance junction ambient single pulse

ZTH (°C/W)

100

Cu=8 cm2

Cu=2 cm2

Cu=foot print

4Layer

10

1

0.1

0.0001

0.001

0.01

0.1

1

10

100

1000

Time (s)

Equation: pulse calculation formula

Z_THδ= R_TH· δ + Z_THtp(1 - δ)

where δ = t_P/T

Figure 42: Thermal fitting model for PowerSSO-36

The fitting model is a simplified thermal tool and is valid for transient evolutions

where the embedded protections (power limitation or thermal cycling during

thermal shutdown) are not triggered.

36/47

DocID027772 Rev 9

VND7004AY

Package and PCB thermal data

Table 15: Thermal parameters

Area/island (cm2)

R1 = R7 (°C/W)

FP

2

8

4L

0.01

1.2

3.4

6

R2 = R8 (°C/W)

R3 (°C/W)

3.4

6

3.4

6

2.6

3

R4 (°C/W)

R5 (°C/W)

18

14

26

10

15

2

R6 (°C/W)

30

7

C1 = C7 (W·s/°C)

C2 = C8 (W·s/°C)

C3 (W·s/°C)

C4 (W·s/°C)

C5 (W·s/°C)

C6 (W·s/°C)

0.0005

0.001

0.1

0.5

1

0.8

2

0.8

3

1

10

18

3

5

9

DocID027772 Rev 9

37/47

Maximum demagnetization energy (VCC = 16 V)

VND7004AY

6

Maximum demagnetization energy (VCC = 16 V)

Figure 43: Maximum turn off current versus inductance

100

10

1

VND7004AY - Single Pulse

Repetitive pulse Tjstart=100°C

Repetitive pulse Tjstart=125°C

0.1

1

10

L (mH)

100

1000

Values are generated with R_L= 0 Ω.

In case of repetitive pulses, T_jstart(at the beginning of each demagnetization) of

every pulse must not exceed the temperature specified above for curves A and B.

38/47

DocID027772 Rev 9

VND7004AY

Package information

7

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK^®packages, depending on their level of environmental compliance. ECOPACK^®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK^®is an ST trademark.

7.1

PowerSSO-36 package information

Figure 44: PowerSSO-36 package outline

BOTTOM VIEW

TOP VIEW

SECTION A-A

SECTION B-B

GAPG2508150825CFT

Table 16: PowerSSO-36 mechanical data

Dimensions

Ref.

Millimeters

Min.

0°

Typ.

Max.

8°

Θ

Θ1

Θ2

A

5°

10°

0°

2.15

0.00

2.45

0.10

A1

DocID027772 Rev 9

39/47

Package information

VND7004AY

Dimensions

Millimeters

Typ.

Ref.

Min.

2.15

0.18

0.13

0.23

0.20

Max.

2.35

0.32

0.30

0.32

0.30

A2

b

b1

c

0.25

c1

D

0.20

10.30 BSC

D1

D2

D3

e

6.90

7.50

3.65

4.30

0.50 BSC

10.30 BSC

7.50 BSC

E

E1

E2

E3

E4

G1

G2

G3

h

4.30

5.20

2.30

2.90

1.20

1.00

0.80

0.30

0.55

0.40

0.85

L

0.70

1.40 REF

0.25 BSC

36

L1

L2

N

R

0.30

0.20

0.25

R1

S

Tolerance of form and position

aaa

bbb

ccc

ddd

eee

fff

0.20

0.10

0.20

0.10

0.20

0.15

ggg

40/47

DocID027772 Rev 9

VND7004AY

Package information

7.2

PowerSSO-36 packing information

Figure 45: PowerSSO-36 reel 13"

Table 17: Reel dimensions

Description

Base quantity

Bulk quantity

A (max)

Value⁽¹⁾

1000

330

B (min)

1.5

C (± 0.2)

F

13

20.2

24.4

100

G (+2 / -0)

N (min)

T (max)

30.4

Notes:

⁽¹⁾All dimensions are in mm.

DocID027772 Rev 9

41/47

Package information

VND7004AY

Figure 46: PowerSSO-36 carrier tape

Table 18: PowerSSO-36 carrier tape dimensions

Description

Value⁽¹⁾

10.90 ± 0.10

10.80 ± 0.10

2.75 ± 0.10

2.45 ± 0.10

1.50 (+0.10 / -0)

1.60 ± 0.10

4.00 ± 0.10

12.00 ± 0.10

2.00 ± 0.10

40.00 ± 0.20

1.75 ± 0.10

11.50 ± 0.10

24.00 ± 0.30

0.30 ± 0.05

A₀

B₀

K₀

K₁

D₀

D₁

P₀

P₁

P₂

P₁₀

E

F

W

T

Notes:

⁽¹⁾All dimensions are in mm.

42/47

DocID027772 Rev 9

VND7004AY

Package information

Figure 47: PowerSSO-36 schematic drawing of leader and trailer tape

7.3

PowerSSO-36 marking information

Figure 48: PowerSSO-36 marking information

Engineering Samples: Parts marked as & are not yet qualified and therefore not

approved for use in production. ST is not responsible for any consequences

resulting from such use. In no event will ST be liable for the customer using any of

these engineering samples in production. ST’s Quality department must be

contacted to run a qualification activity prior to any decision to use these

engineering samples.

Commercial Samples: fully qualified parts from ST standard production with no

usage restrictions.

DocID027772 Rev 9

43/47

Order codes

VND7004AY

8

Order codes

Table 19: Device summary

Order codes

Tape and reel

VND7004AYTR

Package

PowerSSO-36

44/47

DocID027772 Rev 9

VND7004AY

Revision history

9

Revision history

Table 20: Document revision history

Changes

Date

Revision

23-Apr-2015

1

Initial release.

Table 3: "Absolute maximum ratings":



-I_OUT: updated value

Updated Table 4: "Thermal data" and Table 6: "Switching"

Table 8: "Protections":



T_R, T_HYST: added note

20-Jul-2015

2

Table 9: "MultiSense":



K₀, dK₀/K₀: removed rows

K_x, dK_x/K_x, I_{OUT_SAT}: updated values

Added Section 5: "Package and PCB thermal data"

Updated Figure 1: "Block diagram"

Updated Table 1: "Pin functions"

Table 3: "Absolute maximum ratings":



I_SENSE: updated parameter and value

E_MAX: updated parameter

Table 5: "Power section":

R_{ON_REV}: updated value

Table 9: "MultiSense":

V_{SENSE_CL}, V_{SENSE_TC}, V_{SENSE_VCC}: updated test conditions

Removed following tables:



30-Jul-2015

3



Table: Electrical transient requirements (part 1)

Table: Electrical transient requirements (part 2)

Table: Electrical transient requirements (part 3)

Added Section 4: "Application information"

Table 5: "Power section":



I_STBY, I_L(off): updated values

Updated Table 6: "Switching"

Table 9: "MultiSense":

02-Dec-2015

27-Jan-2016

4

5



K_x, t_DSENSE2H: updated values

Added Section 2.5: "Electrical characteristics curves"

Table 9: "MultiSense":



I_SENSE0: updated value

DocID027772 Rev 9

45/47

Revision history

VND7004AY

Date

Revision

Changes

Updated Features list

Table 3: "Absolute maximum ratings":

E_MAX: updated value

Table 9: "MultiSense":

dK_x/K_x, I_{SENSE_SAT}, I_{OUT_SAT}: added note



20-Apr-2016

6



Added Section 6: "Maximum demagnetization energy (VCC = 16 V)"

Updated Figure 1: "Block diagram" and Figure 34: "MultiSense and

diagnostic – block diagram"

26-Apr-2016

7

Updated Figure 45: "PowerSSO-36 reel 13""and Table 17: "Reel

dimensions"

8

9

15-Jul-2016

02-Nov-2016

Updated Applications section

46/47

DocID027772 Rev 9

VND7004AY

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST

products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the

design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DocID027772 Rev 9

47/47


型号：	VND7004AY
厂家：	ST
描述：	Double channel high-side driver with MultiSense analog feedback for automotive applications
文件：	总47页 (文件大小：2999K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VND7004AY [STMICROELECTRONICS]

相关型号：

VND7004AYTR

VND7020AJ

VND7020AJTR

VND7030AJ

VND7030AJ-E

VND7030AJTR

VND7030AJTR-E

VND7040AJTR-E

VND7050AJ

VND7050AJ12

VND7050AJ12TR

VND7050AJTR