VND7050AJ12TR [STMICROELECTRONICS]
Double channel high-side driver with CurrentSense analog feedback;
| 型号： | VND7050AJ12TR |
| 厂家： | 
ST |
| 描述： | Double channel high-side driver with CurrentSense analog feedback |
| 文件： | 总43页 (文件大小：1497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND7050AJ12
Double channel high-side driver with CurrentSense analog
feedback for automotive applications
Datasheet - production data
−
Sense enable/ disable
•
Protections
−
−
−
−
−
−
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Loss of ground and loss of VCC
Reverse battery with external
components
PowerSSO-12
GAPG040515 1112CFT
Features
−
Electrostatic discharge protection
Max transient supply voltage
VCC
VCC
40 V
Applications
Operating voltage range
4 V to 28 V
2.85 V
•
All types of Automotive resistive, inductive
and capacitive loads
Minimum cranking supply
voltage (VCC decreasing)
VUSD_Cranking
RON
•
Specially intended for Automotive Signal
Lamps (up to P27W or SAE1156 or LED
Rear Combinations)
Typ. on-state resistance
(per Ch)
50 mΩ
Current limitation (typ)
Standby current (max)
ILIMH
ISTBY
30 A
Description
0.5 µA
The device is a double channel high-side driver
manufactured using ST proprietary VIPower®
technology and housed in PowerSSO-12
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS compatible interface, providing
protection and diagnostics.
•
•
Automotive qualified
Extreme low voltage operation for deep cold
cranking applications (compliant with LV124,
revision 2013)
•
General
−
Double channel smart high-side driver
with CurrentSense analog feedback
Very low standby current
Compatible with 3 V and 5 V CMOS
outputs
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown.
−
−
•
CurrentSense diagnostic functions
A current sense delivers high precision
proportional load current sense in addition to the
detection of overload and short circuit to ground,
short to VCC and off-state open-load.
−
Multiplexed analog feedback of: load
current with high precision proportional
current mirror
−
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
Off-state open-load detection
Output short to VCC detection
A sense enable pin allows off-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
−
−
−
September 2015
DocID027585 Rev 3
1/43
www.st.com
This is information on a product in full production.
Contents
VND7050AJ12
Contents
1
2
Block diagram and pin description................................................5
Electrical specification....................................................................7
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings................................................................7
Thermal data.....................................................................................8
Main electrical characteristics ...........................................................8
Waveforms......................................................................................18
Electrical characteristics curves ......................................................19
3
4
Protections.....................................................................................23
3.1
3.2
3.3
3.4
Power limitation...............................................................................23
Thermal shutdown...........................................................................23
Current limitation.............................................................................23
Negative voltage clamp...................................................................23
Application information ................................................................24
4.1
GND protection network against reverse battery.............................24
4.1.1
Diode (DGND) in the ground line ..................................................... 25
4.2
4.3
4.4
4.5
Immunity against transient electrical disturbances..........................25
MCU I/Os protection........................................................................26
Behaviour during engine start transients.........................................26
CurrentSense - analog current sense .............................................28
4.5.1
4.5.2
Principle of CurrenSense signal generation..................................... 29
Short to VCC and OFF-state open-load detection ........................... 31
5
6
Maximum demagnetization energy (VCC = 16 V)........................33
Package and PCB thermal data....................................................34
6.1
PowerSSO-12 thermal data ............................................................34
7
Package information .....................................................................37
7.1
7.2
7.3
PowerSSO-12 package information................................................37
PowerSSO-12 packing information .................................................38
PowerSSO-12 marking information.................................................40
8
9
Order codes ...................................................................................41
Revision history ............................................................................42
2/43
DocID027585 Rev 3
VND7050AJ12
List of tables
List of tables
Table 1: Pin functions .................................................................................................................................5
Table 2: Suggested connections for unused and not connected pins........................................................6
Table 3: Absolute maximum ratings ...........................................................................................................7
Table 4: Thermal data.................................................................................................................................8
Table 5: Electrical characteristics during cranking .....................................................................................8
Table 6: Power section ...............................................................................................................................9
Table 7: Switching.......................................................................................................................................9
Table 8: Logic inputs.................................................................................................................................10
Table 9: Protections..................................................................................................................................11
Table 10: CurrentSense............................................................................................................................11
Table 11: Truth table.................................................................................................................................17
Table 12: CurrentSense multiplexer addressing ......................................................................................17
Table 13: ISO 7637-2 - electrical transient conduction along supply line.................................................26
Table 14: Test parameters, E-11 Start pulses..........................................................................................27
Table 15: Cranking operating mode .........................................................................................................28
Table 16: CurrentSense pin levels in off-state..........................................................................................31
Table 17: PCB properties .........................................................................................................................34
Table 18: Thermal parameters .................................................................................................................36
Table 19: PowerSSO-12 mechanical data................................................................................................38
Table 20: Reel dimensions .......................................................................................................................38
Table 21: PowerSSO-12 carrier tape dimensions ....................................................................................39
Table 22: Device summary.......................................................................................................................41
Table 23: Document revision history ........................................................................................................42
DocID027585 Rev 3
3/43
List of figures
VND7050AJ12
List of figures
Figure 1: Block diagram..............................................................................................................................5
Figure 2: Configuration diagram (top view).................................................................................................6
Figure 3: Current and voltage conventions.................................................................................................7
Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................14
Figure 5: Current sense accuracy versus IOUT .......................................................................................15
Figure 6: Switching times and Pulse skew ...............................................................................................15
Figure 7: CurrentSense timings................................................................................................................16
Figure 8: TDSTKON..................................................................................................................................16
Figure 9: Standby mode activation ...........................................................................................................18
Figure 10: Standby state diagram.............................................................................................................18
Figure 11: OFF-state output current .........................................................................................................19
Figure 12: Standby current .......................................................................................................................19
Figure 13: IGND(ON) vs. Tcase ...............................................................................................................19
Figure 14: Logic Input high level voltage ..................................................................................................19
Figure 15: Logic Input low level voltage....................................................................................................19
Figure 16: High level logic input current ...................................................................................................19
Figure 17: Low level logic input current ....................................................................................................20
Figure 18: Logic Input hysteresis voltage .................................................................................................20
Figure 19: Undervoltage shutdown...........................................................................................................20
Figure 20: On-state resistance vs. Tcase.................................................................................................20
Figure 21: On-state resistance vs. Vcc.....................................................................................................20
Figure 22: Turn-on voltage slope..............................................................................................................20
Figure 23: Turn-off voltage slope..............................................................................................................21
Figure 24: Won vs Tcase..........................................................................................................................21
Figure 25: Woff vs Tcase..........................................................................................................................21
Figure 26: ILIMH vs. Tcase.......................................................................................................................21
Figure 27: OFF-state open-load voltage detection threshold ...................................................................21
Figure 28: Vsense clamp vs Tcase...........................................................................................................21
Figure 29: Vsenseh vs Tcase ...................................................................................................................22
Figure 30: Application diagram.................................................................................................................24
Figure 31: Simplified internal structure - GND network protection with Schottly diode............................24
Figure 32: Simplified internal structure - GND network protection with MOSFET....................................25
Figure 33: Cranking profile .......................................................................................................................27
Figure 34: CurrentSense and diagnostic – block diagram........................................................................28
Figure 35: CurrentSense block diagram...................................................................................................29
Figure 36: Analogue HSD – open-load detection in off-state ...................................................................30
Figure 37: Open-load / short to VCC condition.........................................................................................31
Figure 38: Maximum turn off current versus inductance ..........................................................................33
Figure 39: PowerSSO-12 on two-layers PCB (2s0p to JEDEC JESD 51-5)............................................34
Figure 40: PowerSSO-12 on four-layers PCB (2s2p to JEDEC JESD 51-7) ...........................................34
Figure 41: Rthj-amb vs PCB copper area in open box free air condition (one channel on).....................35
Figure 42: PowerSSO-12 thermal impedance junction ambient single pulse (one channel on) ..............35
Figure 43: Thermal fitting model of a double-channel HSD in PowerSSO-12..........................................36
Figure 44: PowerSSO-12 package dimensions........................................................................................37
Figure 45: PowerSSO-12 reel 13" ............................................................................................................38
Figure 46: PowerSSO-12 carrier tape ......................................................................................................39
Figure 47: PowerSSO-12 schematic drawing of leader and trailer tape ..................................................40
Figure 48: PowerSSO-12 marking information.........................................................................................40
4/43
DocID027585 Rev 3
VND7050AJ12
Block diagram and pin description
1
Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Function
Name
VCC
Battery connection.
OUTPUT0,1 Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor
network.
GND
INPUT0,1
CurrentSense
SEn
Voltage controlled input pins with hysteresis, compatible with 3 V and 5 V CMOS
outputs. They control output switch state.
Multiplexed analog sense output pin; it delivers a current proportional to the load
current.
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the
CurrentSense diagnostic pin.
Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the
CurrentSense multiplexer.
SEL
DocID027585 Rev 3
5/43
Block diagram and pin description
VND7050AJ12
Figure 2: Configuration diagram (top view)
Table 2: Suggested connections for unused and not connected pins
Connection/pin
CurrentSense
N.C. Output
Input
SEn, SEL
Floating
Not allowed
X (1)
X
X
X
Through 1 kΩ
Not
allowed
Through 15 kΩ
Through 15 kΩ
To ground
X
resistor
resistor
resistor
Notes:
(1)X: do not care.
6/43
DocID027585 Rev 3
VND7050AJ12
Electrical specification
2
Electrical specification
Figure 3: Current and voltage conventions
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
VCC DC supply voltage
-VCC Reverse DC supply voltage
Parameter
Value
38
Unit
V
0.3
V
Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40 V; RL = 4 Ω)
VCCPK
40
V
VCCJS Maximum jump start voltage for single pulse short circuit protection
-IGND DC reverse ground pin current
28
V
200
Internally limited
11
mA
IOUT OUTPUT0,1 DC output current
A
mA
-IOUT Reverse DC output current
IIN
INPUT0,1 DC input current
ISEn
ISEL
SEn DC input current
-1 to 10
SEL DC input current
CurrentSense pin DC output current (VGND = VCC and VSENSE < 0 V)
CurrentSense pin DC output current in reverse (VCC < 0V)
10
ISENSE
mA
-20
DocID027585 Rev 3
7/43
Electrical specification
VND7050AJ12
Symbol
Parameter
Value
Unit
Maximum switching energy (single pulse)
(TDEMAG = 0.4 ms; Tjstart = 150 °C)
EMAX
30
mJ
Electrostatic discharge (JEDEC 22A-114F)
•
•
•
•
•
INPUT0,1
CurrentSense
SEn, SEL
OUTPUT0,1
VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
VESD Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Junction operating temperature
Storage temperature
-40 to 150
-55 to 150
°C
Tstg
2.2
Thermal data
Table 4: Thermal data
Parameter
Symbol
Typ. value Unit
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) (1)(2)
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(3)
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(2)
6.4
59
25
°C/W
Notes:
(1)One channel ON.
(2)Device mounted on four-layers 2s2p PCB.
(3)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.
2.3
Main electrical characteristics
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5: Electrical characteristics during cranking
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Minimum cranking supply voltage
(VCC decreasing)
VUSD_Cranking
2.85
V
IOUT = 0.5 A; VCC = 2.85 V;
VCC decreasing
RON
On-state resistance (1)
500 mΩ
Shutdown temperature (VCC
decreasing)
(2)
TTSD
VCC = 2.85 V
140
°C
Notes:
(1)For each channel.
(2)Parameter guaranteed by design and characterization; not subject to production test.
8/43
DocID027585 Rev 3
VND7050AJ12
Electrical specification
Table 6: Power section
Test conditions
Symbol
VCC
Parameter
Min. Typ. Max. Unit
Operating supply voltage
4
13 28
2.85
VUSD Undervoltage shutdown
Undervoltage shutdown
V
VUSDReset
reset
5
Undervoltage shutdown
hysteresis
VUSDhyst
0.3
50
I
OUT = 2 A; Tj = 25 °C
RON
On-state resistance (1)
IOUT = 2 A; Tj = 150 °C
100 mΩ
IOUT = 2 A; VCC = 4 V; Tj = 25 °C
IS = 20 mA; Tj = -40 °C
75
38
Vclamp Clamp voltage
V
IS = 20 mA; 25°C < Tj < 150°C
41 46 52
V
V
CC = 13 V; VIN = VOUT = VSEn = 0 V;
SEL = 0 V; Tj = 25 °C
0.5 µA
0.5 µA
µA
60 300 550 µA
Supply current in standby at VCC = 13 V; VIN = VOUT = VSEn = 0 V;
ISTBY
(2)
(3)
VCC = 13 V
VSEL = 0 V; Tj = 85 °C
VCC = 13 V; VIN = VOUT = VSEn = 0 V;
3
VSEL = 0 V; Tj = 125 °C
V
CC = 13 V; VIN = VOUT = VSEL = 0 V;
Standby mode blanking
time
tD_STBY
VSEn = 5 V to 0 V
V
CC = 13 V; VSEn = VSEL = 0 V;
IS(ON) Supply current
Control stage current
V
IN0 = 5 V; VIN1 = 5 V; IOUT0 = 0 A;
5
8
mA
IOUT1 = 0 A
VCC = 13 V; VSEn = 5 V; VSEL = 0 V;
IGND(ON) consumption in ON state.
All channels active.
V
IN0 = 5 V; VIN1 = 5 V; IOUT0 = 2 A;
12 mA
IOUT1 = 2 A
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
0
0
0.01 0.5
Off-state output current at
IL(off)
µA
V
VCC = 13 V(1)
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
3
Output - VCC diode
VF
I
OUT = -2 A; Tj = 150 °C
0.7
voltage(1)
Notes:
(1)For each channel.
(2)PowerMOS leakage included.
(3)Parameter specified by design; not subject to production test.
Table 7: Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol
Parameter
Test conditions Min. Typ. Max. Unit
(1)
td(on)
Turn-on delay time at Tj = 25°C
Turn-off delay time at Tj = 25°C
10
10
60
40
120
100
0.7
RL = 6.5 Ω
RL = 6.5 Ω
µs
(1)
td(off)
(1)
(dVOUT/dt)on Turn-on voltage slope at Tj = 25°C
0.1 0.3
V/µs
(1)
(dVOUT/dt)off Turn-off voltage slope at Tj = 25°C
0.1 0.32 0.7
DocID027585 Rev 3
9/43
Electrical specification
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
VND7050AJ12
Symbol
WON
Parameter
Test conditions Min. Typ. Max. Unit
Switching energy losses at turn-on (twon
Switching energy losses at turn-off (twoff
)
)
RL = 6.5 Ω
RL = 6.5 Ω
RL = 6.5 Ω
—
—
0.25 0.33 (2) mJ
0.23 0.31(2) mJ
WOFF
(1)
tSKEW
Differential pulse skew (tPHL - tPLH
)
-80 -30
20
µs
Notes:
(1)See Figure 6: "Switching times and Pulse skew"
(2)Parameter guaranteed by design and characterization; not subject to production test.
Table 8: Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
INPUT0,1 characteristics
VIL
IIL
Input low level voltage
0.9
V
µA
V
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VIN = 0.9 V
1
VIH
2.1
IIH
VIN = 2.1 V
10
µA
V
VI(hyst)
0.2
5.3
I
IN = 1 mA
7.2
VICL
Input clamp voltage
V
IIN = -1 mA
-0.7
-0.7
-0.7
SEL characteristics (7 V < VCC < 18 V)
VSELL
ISELL
VSELH
ISELH
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VSEL(hyst) Input hysteresis voltage
VSELCL Input clamp voltage
SEn characteristics (7 V < VCC < 18 V)
0.2
5.3
I
IN = 1 mA
7.2
V
IIN = -1 mA
VSEnL
ISEnL
VSEnH
ISEnH
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VSEn(hyst) Input hysteresis voltage
0.2
5.3
I
IN = 1 mA
7.2
VSEnCL Input clamp voltage
V
IIN = -1 mA
10/43
DocID027585 Rev 3
VND7050AJ12
Electrical specification
Table 9: Protections
Test conditions
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter
Min.
Typ.
Max. Unit
V
CC = 13 V
21
30
42
ILIMH DC short circuit current
4 V < VCC < 18 V (1)
42
A
Short circuit current during
thermal cycling
ILIML
VCC = 13 V; TR < Tj < TTSD
10
TTSD Shutdown temperature
150
175
200
TR
Reset temperature(1)
TRS + 1 TRS + 7
Thermal reset of fault
diagnostic indication
°C
TRS
VSEn = 5 V
135
Thermal hysteresis (TTSD
TR)(1)
-
THYST
7
ΔTJ_SD Dynamic temperature
Tj = -40 °C; VCC = 13 V
60
K
V
IOUT = 2 A; L = 6 mH;
Tj = -40 °C
V
CC - 38
VCC - 41 VCC - 46 VCC - 52
20
Turn-off output voltage
VDEMAG
clamp
IOUT = 2 A; L = 6 mH;
Tj = 25 °C to +150 °C
Output voltage drop
limitation
VON
IOUT = 0.2 A
mV
Notes:
(1)Parameter guaranteed by design and characterization; not subject to production test.
Table 10: CurrentSense
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VSEn = 0 V; ISENSE = 1 mA
VSEn = 0 V; ISENSE = -1 mA
-17
-12
V
V
VSENSE_CL
CurrentSense clamp voltage
7
CurrentSense characteristics
IOUT = 0.01 A;
KOL
dKcal/Kcal
KLED
IOUT/ISENSE
440
-30
VSENSE = 0.5 V; VSEn = 5 V
I
I
OUT = 0.01 A to 0.05 A;
cal = 30 mA;
Current sense ratio drift at
calibration point
(1)(2)
30
%
VSENSE = 0.5 V; VSEn = 5 V
IOUT = 0.05 A;
VSENSE = 0.5 V; VSEn = 5 V
IOUT/ISENSE
530 1450 2200
-25 25
830 1400 1935
-20 20
915 1300 1700
IOUT = 0.05 A;
(1)(2)
dKLED/KLED
K0
Current sense ratio drift
IOUT/ISENSE
%
%
V
SENSE = 0.5 V; VSEn = 5 V
IOUT = 0.2 A;
SENSE = 0.5 V; VSEn = 5 V
IOUT = 0.2 A;
SENSE = 0.5 V; VSEn = 5 V
IOUT = 0.4 A; VSENSE = 4 V;
SEn = 5 V
V
(1)(2)
dK0/K0
K1
Current sense ratio drift
IOUT/ISENSE
V
V
DocID027585 Rev 3
11/43
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
VND7050AJ12
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
IOUT = 0.4 A; VSENSE = 4 V;
VSEn = 5 V
(1)(2)
dK1/K1
K2
Current sense ratio drift
-15
980 1230 1470
-10 10
1095 1215 1335
15
%
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V
IOUT/ISENSE
IOUT = 1.5 A; VSENSE = 4 V;
(1)(2)
(1)(2)
dK2/K2
K3
Current sense ratio drift
IOUT/ISENSE
%
V
SEn = 5 V
IOUT = 4.5 A; VSENSE = 4 V;
SEn = 5 V
OUT = 4.5 A; VSENSE = 4 V;
SEn = 5 V
CurrentSense disabled:
SEn = 0 V;
V
I
V
dK3/K3
Current sense ratio drift
-5
0
5
%
0.5
0.5
µA
µA
V
CurrentSense disabled:
-1 V < VSENSE < 5 V(1)
-0.5
CurrentSense enabled:
V
SEn = 5 V;
All channel ON;
OUTX = 0 A;
ChX diagnostic selected;
I
0
2
µA
•
E.g. Ch0:
VIN0 = 5 V; VIN1 = 5 V;
VSEL = 0 V;
ISENSE0
CurrentSense leakage current
IOUT0 = 0 A;
IOUT1 = 2 A
CurrentSense enabled:
SEn = 5 V;
V
ChX channel OFF;
ChX diagnostic selected;
0
2
µA
•
E.g. Ch0:
VIN0 = 0 V; VIN1 = 5 V;
VSEL = 0 V;
I
OUT1 = 2 A
VSEn = 5 V;
RSENSE = 2.7 kΩ
Output Voltage for
CurrentSense shutdown
•
E.g. Ch0:
(1)
VOUT_MSD
5
V
VIN0 = 5 V;
VSEL = 0 V;
IOUT0 = 2 A
VCC = 7 V;
SENSE = 2.7 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL = 0 V; IOUT0 = 4.5 A;
Tj = 150°C
R
CurrentSense saturation
voltage
VSENSE_SAT
5
4
V
V
V
CC = 7 V; VSENSE = 4 V;
IN0 = 5 V; VSEn = 5 V;
(1)
ISENSE_SAT
CS saturation current
mA
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
12/43
DocID027585 Rev 3
VND7050AJ12
7 V < VCC < 18 V; -40°C < Tj < 150°C
Electrical specification
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
V
CC = 7 V; VSENSE = 4 V;
(1)
IOUT_SAT
Output saturation current
VIN0 = 5 V; VSEn = 5 V;
SEL = 0 V; Tj = 150°C
6
A
V
Off-state diagnostic
VSEn = 5 V; ChX OFF;
Off-state open-load voltage
detection threshold
ChX diagnostic selected
VOL
2
3
4
V
•
E.g: Ch0
VIN0 = 0 V; VSEL = 0 V
IL(off2)
Off-state output sink current
VIN = 0 V; VOUT = VOL
-100
-15
µA
VSEn = 5 V; ChX ON to OFF
transition
ChX diagnostic selected
Off-state diagnostic delay time
from falling edge of INPUT
(see Figure 8: "TDSTKON")
•
E.g: Ch0
tDSTKON
100 350 700
µs
VIN0 = 5 V to 0 V;
VSEL = 0 V;
I
OUT0 = 0 A;
VOUT = 4 V
Settling time for valid OFF-
state open load diagnostic
indication from rising edge of
SEn
V
IN0 = 0 V; VIN1 = 0 V;
tD_OL_V
VSEL = 0 V; VOUT0 = 4 V;
V
60
µs
µs
SEn = 0 V to 5 V
V
SEn = 5 V; ChX OFF
ChX diagnostic selected
Off-state diagnostic delay time
from rising edge of VOUT
•
E.g: Ch0
VIN0 = 0 V;
tD_VOL
5
30
VSEL = 0 V;
VOUT = 0 V to 4 V
Fault diagnostic feedback (see Table 11: "Truth table")
VCC = 13 V; RSENSE = 1 kΩ
•
E.g: Ch0 in open load
VIN0 = 0 V;
CurrentSense output voltage
in fault condition
VSENSEH
5
7
6.6
30
V
VSEn = 5 V;
VSEL = 0 V;
IOUT0 = 0 A;
VOUT = 4 V
CurrentSense output current in
fault condition
ISENSEH
VCC = 13 V; VSENSE = 5 V
20
mA
CurrentSense timings (current sense mode - see Figure 7: "CurrentSense timings")(3)
V
IN = 5 V; VSEn = 0 V to
Current sense settling time
from rising edge of SEn
tDSENSE1H
tDSENSE1L
tDSENSE2H
5 V; RSENSE = 1 kΩ;
RL = 6.5 Ω
60
20
µs
µs
µs
VIN = 5 V; VSEn = 5 V to
0 V; RSENSE = 1 kΩ;
RL = 6.5 Ω
Current sense disable delay
time from falling edge of SEn
5
VIN = 0 V to 5 V;
Current sense settling time
from rising edge of INPUT
VSEn = 5 V; RSENSE = 1 kΩ;
100 250
RL = 6.5 Ω
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Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
VND7050AJ12
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ;
Current sense settling time
from rising edge of IOUT
ΔtDSENSE2H
100
250
µs
µs
(dynamic response to a step
ISENSE = 90 % of ISENSEMAX
RL = 6.5 Ω
;
change of IOUT
)
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V;
VSEn = 5 V; RSENSE = 1 kΩ;
RL = 6.5 Ω
tDSENSE2L
50
CurrentSense timings (Multiplexer transition times) (3)
VIN0 = 5 V; VIN1 = 5 V;
V
SEn = 5 V;
CurrentSense transition delay
from ChX to ChY
tD_XtoY
20
20
µs
µs
VSEL = 0 V to 5 V;
IOUT0 = 0A; IOUT1 = 3 A;
RSENSE = 1 kΩ
VIN0 = 5 V; VIN1 = 0 V;
VSEn = 5 V;
CurrentSense transition delay
tD_CStoVSENSEH from stable current sense on
ChX to VSENSEH on ChY
VSEL = 0 V to 5 V;
I
OUT0 = 3 A; VOUT1 = 4 V;
RSENSE = 1 kΩ
Notes:
(1)Parameter guaranteed by design and characterization; not subject to production test.
(2)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(3)Transition delay are measured up to +/- 10% of final conditions.
Figure 4: IOUT/ISENSE versus IOUT
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VND7050AJ12
Electrical specification
Figure 5: Current sense accuracy versus IOUT
Figure 6: Switching times and Pulse skew
twon
twoff
VOUT
Vcc
80% Vcc
20% Vcc
ON
OFF
dVOUT/dt
dVOUT/dt
t
INPUT
td(off)
td(on)
tpLH
tpHL
t
GAPGCFT00797
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Electrical specification
VND7050AJ12
Figure 7: CurrentSense timings
Figure 8: TDSTKON
VINPUT
VOUT
VOUT > VOL
CurrentSense
TDSTKON
GAPG0912131101CFT
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Electrical specification
Table 11: Truth table
Mode
Standby
Conditions
INX SEn SEL OUTX CurrentSense
Comments
Low quiescent current
consumption
All logic inputs low
L
L
L
L
L
L
Hi-Z
See (1)
See (1)
Nominal load
connected;
Outputs configured for
auto-restart
H
H
See (1)
Normal
Tj < 150°C
Outputs configured for
latch off
See (1)
See (1)
See (1)
See (1)
H
L
H
L
Overload or short to
GND causing:
Output cycles with
temperature hysteresis
See (1)
Overload
H
H
H
L
Tj > TTSD or
ΔTj > ΔTj_SD
Output latches off
Re-start when
L
L
Hi-Z
Hi-Z
VCC > VUSD
+
Under-voltage VCC < VUSD (falling)
X
X
X
VUSDhyst (rising)
See (1)
See (1)
Short to VCC
Off-state
L
L
H
H
See (1)
See (1)
diagnostics
Open-load
External pull up
Negative output Inductive loads turn-
See (1)
L
< 0 V
voltage
off
Notes:
(1)Refer to Table 12: "CurrentSense multiplexer addressing"
Table 12: CurrentSense multiplexer addressing
CurrentSense output
MUX
SEn SEL
Negative
output
channel
Normal mode
Overload
Off-state diag.
Hi-Z
L
X
L
Channel 0
diagnostic
ISENSE
=
VSENSE
=
VSENSE
=
H
Hi-Z
Hi-Z
1/K * IOUT0
VSENSEH
VSENSEH
Channel 1
diagnostic
ISENSE
=
VSENSE
=
VSENSE
=
H
H
1/K * IOUT1
VSENSEH
VSENSEH
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Electrical specification
VND7050AJ12
2.4
Waveforms
Figure 9: Standby mode activation
Figure 10: Standby state diagram
Normal Operation
INx = High
INx = Low
AN
OR
D
SEn = High
OR
SEL = High
SEn = Low
AND
SEL = Low
t > tD_STBY
Stand-by Mode
GAPG2911131147CFT
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Electrical specification
2.5
Electrical characteristics curves
Figure 12: Standby current
Figure 11: OFF-state output current
Figure 13: IGND(ON) vs. Tcase
Figure 14: Logic Input high level voltage
Figure 15: Logic Input low level voltage
Figure 16: High level logic input current
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Electrical specification
Figure 17: Low level logic input current
VND7050AJ12
Figure 18: Logic Input hysteresis voltage
Figure 19: Undervoltage shutdown
Figure 20: On-state resistance vs. Tcase
Figure 21: On-state resistance vs. Vcc
Figure 22: Turn-on voltage slope
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Electrical specification
Figure 24: Won vs Tcase
Figure 23: Turn-off voltage slope
Figure 25: Woff vs Tcase
Figure 26: ILIMH vs. Tcase
Figure 27: OFF-state open-load voltage
detection threshold
Figure 28: Vsense clamp vs Tcase
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Electrical specification
VND7050AJ12
Figure 29: Vsenseh vs Tcase
VSENSEH [V]
10
9
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
175
T [°C]
GAPG2110131629CFT
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Protections
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔTj_SD. The output MOSFET switches on and
cycles with a thermal hysteresis according to the maximum instantaneous power which can
be handled. The protection prevents fast thermal transient effects and, consequently,
reduces thermo-mechanical fatigue.
3.2
3.3
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered. The
device switches on again as soon as its junction temperature drops to TR.
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
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Application information
VND7050AJ12
4
Application information
Figure 30: Application diagram
4.1
GND protection network against reverse battery
Figure 31: Simplified internal structure - GND network protection with Schottly diode
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VND7050AJ12
Application information
Figure 32: Simplified internal structure - GND network protection with MOSFET
4.1.1
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (»600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
To comply with LV124, E-11 "severe" start pulse, a Schottky diode (see Figure 31:
"Simplified internal structure - GND network protection with Schottly diode") or N-channel
MOSFET (see Figure 32: "Simplified internal structure - GND network protection with
MOSFET") is recommended in order to ensure a lower ground network shift (≤ 350 mV).
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 13: "ISO 7637-2 -
electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
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Application information
VND7050AJ12
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 13: ISO 7637-2 - electrical transient conduction along supply line
Test pulse severity
Test
Pulse
Minimum
number of
pulses or test
time
level with Status II
functional performance
status
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator
internal impedance
2011(E)
(1)
Level
III
US
min
0,5 s
max
1
-112V
+55V
-220V
+150V
-7V
500 pulses
500 pulses
1h
2ms, 10Ω
50µs, 2Ω
2a
3a
3b
4 (2)
III
0,2 s
5 s
IV
90 ms
90 ms
100 ms
100 ms
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
IV
1h
IV
1 pulse
Load dump according to ISO 16750-2:2010
Test B (3)
40V
5 pulse
1 min
400ms, 2Ω
Notes:
(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test pulse from ISO 7637-2:2004(E).
(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
4.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Behaviour during engine start transients
The battery voltage drops every time an engine start occurs as well as in start&stop
automotive systems.
The device is designed to operate during engine start pulses without external components.
In particular, the device achieves functional status A, for both E-11 start pulses, “normal”
and “severe” as defined in Table 14: "Test parameters, E-11 Start pulses".
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Application information
Functional status A is defined as follows: the DUT (device under test) must fulfill all
functions during and after exposure to the test parameters.
Table 14: Test parameters, E-11 Start pulses
Parameter
Test pulse “normal”
Test pulse “severe”
VB
11,0 V
4,5 V (0%, -4%)
4,5 V (0%, -4%)
6,5 V (0%, -4%)
2 V
11,0 V
VT
3,2 V +0,2V
5,0 V (0%, -4%)
6,0 V (0%, -4%)
2 V
VS
VA
VR
tf
≤1 ms
≤1 ms
t4
0 ms
19 ms
t5
0 ms
≤1 ms
t6
19 ms
329 ms
50 ms
t7
50 ms
t8
10 s
10 s
tr
100 ms
2 Hz
100 ms
2 Hz
f
Break between two cycles
Test cycles
2 s
2 s
10
10
For more details see standard norm “LV124 - Electric and Electronic Components
in Motor Vehicles up to 3.5 t”.
Figure 33: Cranking profile
The extremely low VUSD_Cranking, minimum cranking supply voltage (VCC decreasing),
specification of 2.85 V, much lower than the standard requirement, allows the device
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Application information
VND7050AJ12
operating in all the applications where a ground network protection is required (see Section
4.1: "GND protection network against reverse battery").
Table 15: Cranking operating mode
Operating range
Voltage range
Operating mode
All functions are performed as specified. Some
deviations of the electrical characteristics.
18 V - 28 V
All functions are performed as specified. All
parameters in range.
Normal mode 4 V to 28 V
7 V - 18 V
4 V - 7 V
All functions are performed as specified. Some
deviations of the electrical characteristics.
Device is operating (VCC decreasing). Device is
protected. No diagnostic. Electrical parameters
deviations.
Cranking mode 2.85 V to 4 V
2.85 V - 4 V
4.5
CurrentSense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(CurrentSense) delivering a current mirror of channel output current
Figure 34: CurrentSense and diagnostic – block diagram
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VND7050AJ12
Application information
4.5.1
Principle of CurrenSense signal generation
Figure 35: CurrentSense block diagram
Current monitor
This output is capable of providing:
•
Current mirror proportional to the load current in normal operation, delivering
current proportional to the load according to known ratio named K
•
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by CurrentSense output: ISENSE = IOUT/K
Voltage on RSENSE : VSENSE = RSENSE . ISENSE = RSENSE . IOUT/K
Where :
•
VSENSE is voltage measurable on RSENSE resistor
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Application information
VND7050AJ12
ISENSE is current provided from CurrentSense pin in current output mode
IOUT is current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
•
•
•
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE
.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CurrentSense pin
which is switched to a “current limited” voltage source, VSENSEH
.
In any case, the current sourced by the CurrentSense in this condition is limited to ISENSEH
.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 36: Analogue HSD – open-load detection in off-state
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Application information
Figure 37: Open-load / short to VCC condition
Table 16: CurrentSense pin levels in off-state
Condition
Output
CurrentSense
SEn
L
Hi-Z
VSENSEH
Hi-Z
0
V
OUT > VOL
H
L
Open-load
VOUT < VOL
VOUT > VOL
VOUT < VOL
H
L
Hi-Z
VSENSEH
Hi-Z
0
Short to VCC
Nominal
H
L
H
4.5.2
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
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Application information
VND7050AJ12
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
VPU - 4
IL(off2)min @ 4V
RPU
<
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Maximum demagnetization energy (VCC = 16 V)
5
Maximum demagnetization energy (VCC = 16 V)
Figure 38: Maximum turn off current versus inductance
Maximum turn off current versus inductance
100
10
1
Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
0.1
0.1
1
10
100
1000
L (mH)
GAPG0912131502CFT
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of
every pulse must not exceed the temperature specified above for curves A and B.
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Package and PCB thermal data
VND7050AJ12
6
Package and PCB thermal data
6.1
PowerSSO-12 thermal data
Figure 39: PowerSSO-12 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 40: PowerSSO-12 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 17: PCB properties
Dimension
Value
1.6 mm +/- 10%
77 mm x 86 mm
FR4
Board finish thickness
Board dimension
Board material
Copper thickness (top and bottom layers)
Copper thickness (inner layers)
Thermal via separation
0.070 mm
0.035 mm
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
0.025 mm
Copper thickness on via
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
2.2 mm x 3.9 mm
Footprint, 2 cm2 or 8 cm2
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Package and PCB thermal data
Figure 41: Rthj-amb vs PCB copper area in open box free air condition (one channel on)
Figure 42: PowerSSO-12 thermal impedance junction ambient single pulse (one channel on)
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
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Package and PCB thermal data
VND7050AJ12
Figure 43: Thermal fitting model of a double-channel HSD in PowerSSO-12
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 18: Thermal parameters
Area/island (cm2)
R1 = R7 (°C/W)
R2 = R8 (°C/W)
R3 (°C/W)
Footprint
1.8
2
8
4L
3.2
8
8
6
8
6
6
4
3
7
R4 (°C/W)
14
R5 (°C/W)
30
20
20
10
18
R6 (°C/W)
26
C1 = C7 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
0.00035
0.005
0.05
0.2
C4 (W.s/°C)
0.3
1
0.3
1
0.4
4
C5 (W.s/°C)
0.4
C6 (W.s/°C)
3
5
7
18
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Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
PowerSSO-12 package information
Figure 44: PowerSSO-12 package dimensions
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Package information
VND7050AJ12
Table 19: PowerSSO-12 mechanical data
Millimeters
Symbol
Min.
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Typ.
Max.
1.700
0.100
1.600
0.410
0.250
5.000
4.000
A
A1
A2
B
C
D
E
e
0.800
H
5.800
0.250
0.400
0°
6.200
0.500
1.270
8°
h
L
k
X
2.200
2.900
2.800
3.500
0.100
Y
ddd
7.2
PowerSSO-12 packing information
Figure 45: PowerSSO-12 reel 13"
Table 20: Reel dimensions
Value(1)
Description
Base quantity
Bulk quantity
A (max)
2500
2500
330
B (min)
1.5
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Description
Package information
Value(1)
13
C (+0.5, -0.2)
D (min)
20.2
100
N
W1 (+2 /-0)
W2 (max)
12.4
18.4
Notes:
(1)All dimensions are in mm.
Figure 46: PowerSSO-12 carrier tape
P2
P0
2.0 0.1
4.0 0.1
X
1.55 0.05
1.6 0.1
1.75 0.1
0.30 0.05
Y
Y
R 0.5
Typical
K1
K0
X
P1
A0
SECTION X - X
REF 4.18
REF 0.5
SECTION Y - Y
GAPG2204151242CFT
Table 21: PowerSSO-12 carrier tape dimensions
Value(1)
Description
A0
B0
K0
K1
F
6.50 ± 0.1
5.25 ± 0.1
2.10 ± 0.1
1.80 ± 0.1
5.50 ± 0.1
8.00 ± 0.1
12.00 ± 0.3
P1
W
Notes:
(1)All dimensions are in mm.
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Package information
VND7050AJ12
Figure 47: PowerSSO-12 schematic drawing of leader and trailer tape
7.3
PowerSSO-12 marking information
Figure 48: PowerSSO-12 marking information
Marking area
1
2
3
4
5
6
7
8
Special function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-12 TOP VIEW
(not in scale)
GAPG1203151332CFT
Engineering Samples: these samples can be clearly identified by a dedicated
special symbol in the marking of each unit. These samples are intended to be
used for electrical compatibility evaluation only; usage for any other purpose may
be agreed only upon written authorization by ST. ST is not liable for any customer
usage in production and/or in reliability qualification trials.
Commercial Samples: Fully qualified parts from ST standard production with no
usage restrictions
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Order codes
8
Order codes
Table 22: Device summary
Order codes
Tape and reel
Package
PowerSSO-12
VND7050AJ12TR
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Revision history
VND7050AJ12
9
Revision history
Table 23: Document revision history
Changes
Date
Revision
09-Jun-2015
1
Initial release.
Table 5: "Electrical characteristics during cranking":
•
TTSD: updated value
18-Jun-2015
14-Sep-2015
2
3
Updated Table 7: "Switching"
Table 10: "CurrentSense":
•
KOL, KLED, K0, K1, K2: updated values
Updated Table 1: "Pin functions"
Table 5: "Electrical characteristics during cranking":
•
RON: updated test conditions
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
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