VNH5180A-E [STMICROELECTRONICS]
Automotive fully integrated H-bridge motor driver; 汽车完全集成H桥电机驱动器
| 型号： | VNH5180A-E |
| 厂家： | 
ST |
| 描述： | Automotive fully integrated H-bridge motor driver |
| 文件： | 总31页 (文件大小：533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VNH5180A-E
Automotive fully integrated H-bridge motor driver
Features
Type
RDS(on)
Iout VCCmax
8 A 41 V
180 mΩ max
(per leg)
VNH5180A-E
PowerSSO-36 TP
■ Output current: 8 A
proprietary VIPower® M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent
signal/protection circuitry. The three dies are
assembled in PowerSSO-36 TP package on
electrically isolated leadframes. This package,
specifically designed for the harsh automotive
environment offers improved thermal
■ 3 V CMOS compatible inputs
■ Undervoltage shutdown
■ Overvoltage clamp
■ Thermal shutdown
■ Cross-conduction protection
■ Current and power limitation
performance thanks to exposed die pads.
Moreover, its fully symmetrical mechanical design
allows superior manufacturability at board level.
The input signals INA and INB can directly
interface to the microcontroller to select the motor
direction and the brake condition. The DIAGA/ENA
or DIAGB/ENB, when connected to an external
pull-up resistor, enables one leg of the bridge.
Each DIAGA/ENA provides a feedback digital
diagnostic signal as well. The normal operating
condition is explained in the truth table. The CS
pin allows to monitor the motor current by
delivering a current proportional to its value when
CS_DIS pin is driven low or left open. When
CS_DIS is driven high, CS pin is in high
■ Very low standby power consumption
■ PWM operation up to 20 KHz
■ Protection against loss of ground and loss of
VCC
■ Current sense output proportional to motor
current
■ Output protected against short to ground and
short to VCC
■ Package: ECOPACK®
Description
The VNH5180A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side driver and two low-side
switches. Both switches are designed using
STMicroelectronics’ well known and proven
impedance condition. The PWM, up to 20 KHz,
allows to control the speed of the motor in all
possible conditions. In all cases, a low level state
on the PWM pin turns off both the LSA and LSB
switches.
Table 1.
Device summary
Package
Order codes
Tape and reel
Tube
PowerSSO-36 TP
VNH5180A-E
VNH5180ATR-E
December 2011
Doc ID 17074 Rev 5
1/31
www.st.com
1
Contents
VNH5180A-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.2
Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
6
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
®
5.1
5.2
5.3
ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-36 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-36 TP packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
Doc ID 17074 Rev 5
VNH5180A-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin functions description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching (VCC = 13 V, RLOAD = 5 W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current sense (9 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 23
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-36 TP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 17074 Rev 5
3/31
List of figures
VNH5180A-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 14
Definition of delay response time of sense current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Waveforms in full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Waveforms in full-bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 19
Figure 12. Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. PowerSSO-36™ PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 23
Figure 18. Detailed chipset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 25
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 25
Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22. PowerSSO-36 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 23. PowerSSO-36 TP tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/31
Doc ID 17074 Rev 5
VNH5180A-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
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Table 2.
Block description
Name
Description
Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the truth table.
Logic control
Undervoltage
Shuts down the device for battery voltage lower than 5V.
Protect the high-side and the low-side switches from the
high voltage on the battery line.
High-side and low-side clamp voltage
Drive the gate of the concerned switch to allow a proper
High-side and low-side driver
Current limitation
RDS(on) for the leg of the bridge.
Limits the motor current in case of short circuit.
In case of short-circuit with the increase of the junction
temperature, it shuts down the concerned driver to prevent
degradation and to protect the die.
High-side and low-side overtemperature
protection
Detects when low side current exceeds shutdown current
and latches off the concerned Low side.
Low-side overload detector
Fault detection
Signalizes the abnormal behaviour of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.
Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
Power limitation
Doc ID 17074 Rev 5
5/31
Block diagram and pin description
Figure 2. Configuration diagram (top view)
VNH5180A-E
1
NC
NC
36
DRAIN LS
A
GND_A
GND_A
NC
DRAIN LS
GND_B
GND_B
NC
B
Slug2
Slug3
GND_B
GND_B
GND_A
GND_A
DRAIN LS
NC
SOURCE HS
SOURCE HS
A
DRAIN LS
NC
B
A
SOURCE HS
SOURCE HS
B
B
A
SOURCE HS
A
SOURCE HSB
V
V
CC
CC
NC
NC
Slug1
IN_A
IN_B
EN/DIAG_A
EN/DIAG
CS_DIS
CS
_B
IN_PWM
NC
18
19
Table 3.
Suggested connections for unused and not connected pins
INPUTx, PWM
DIAGx/ENx
CS_DIS
Connection / pin
Current sense
N.C. SOURCE_HSx DRAIN_LSx
Floating
Not allowed
X
X
X
X
X
X
Through 1 kΩ
Through 10 kΩ
To ground
Not allowed
resistor
resistor
Table 4.
Pin N°
Pin definitions and functions
Symbol
Function
13, 24
VCC, Heat Slug1
NC
Drain of high-side switches and power supply voltage.
Not connected.
1, 5, 9, 14, 18, 23,
28, 32, 36
15
16
INA
Clockwise input
Status of high-side and low-side switches A;
open drain output.
ENA/DIAGA
17
19
IN_PWM
CS
PWM input.
Output of current sense.
6/31
Doc ID 17074 Rev 5
VNH5180A-E
Block diagram and pin description
Pin definitions and functions (continued)
Table 4.
Pin N°
Symbol
Function
Active high CMOS compatible pin to disable current sense
pin.
20
CS_DIS
Status of high-side and low-side switches b;
open drain output.
21
22
ENB/DIAGB
INB
Counter clockwise input.
25, 26, 27, 29, 35 OUTB Heat Slug3 Source of high-side switch B / drain of low-side switch B.
,
30, 31, 33, 34
2, 8, 10, 11, 12
3, 4, 6, 7
GNDB
OUTA, Heat Slug2 Source of high-side switch A / drain of low-side switch A.
GNDA Source of low-side switch A.
Source of low-side switch B.
Table 5.
Name
Pin functions description
Description
VCC
Battery connection.
Power ground.
GND
OUTA
OUTB
Power connections to the motor.
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins
control the state of the bridge in normal operation according to the truth table (brake
to VCC, Brake to GND, clockwise and counterclockwise).
INA
INB
Voltage controlled input pin with hysteresis, CMOS compatible. Gates of low-side
FETS get modulated by the PWM signal during their ON phase allowing speed control
of the motor.
PWM
Open drain bidirectional logic pins.These pins must be connected to an external pull
up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault
detection (thermal shutdown of a high-side FET or excessive ON-state voltage drop
across a low-side FET), these pins are pulled low by the device (see Table 14: Truth
table in fault conditions (detected on OUTA)).
ENA/DIAGA
ENB/DIAGB
Analog current sense output. This output delivers a current proportional to the motor
current if CS_DIS is low or left open. The information can be read back as an analog
voltage across an external resistor.
CS
CS_DIS
Active high CMOS compatible pin to disable the current sense pin.
Doc ID 17074 Rev 5
7/31
Electrical specifications
VNH5180A-E
2
Electrical specifications
Figure 3.
Current and voltage conventions
I
S
V
CC
I
INA
V
CC
I
OUTA
IN
A
OUT
A
I
INB
I
OUTB
I
SENSE
IN
B
OUT
B
V
I
OUTA
ENA
CS
DIAG /EN
A
A
I
CSD
V
I
OUTB
ENB
CS_DIS
V
SENSE
DIAG /EN
B
B
PWM
GND
I
pw
V
CSD
I
GND
V
V
V
V
V
ENB
INA
INB
pw
ENA
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the Table 6: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
Imax
IR
Supply voltage
+ 41
Internally limited
-15
V
A
Maximum output current (continuous)
Reverse output current (continuous)
Input current (INA and INB pins)
Enable input current (DIAGA/ENA and DIAGB/ENB pins)
PWM Input current
A
IIN
+/- 10
mA
mA
mA
mA
V
IEN
Ipw
+/- 10
+/- 10
ICS_DIS CS_DIS input current
+/- 10
VCS
Current sense maximum voltage
VCC-41/+VCC
Electrostatic discharge
(Human body model: R=1.5 kΩ, C=100 pF)
VESD
2
kV
Tc
Junction operating temperature
Storage temperature
-40 to 150
-55 to 150
200
°C
°C
TSTG
IGND
DC reverse ground pin current
mA
8/31
Doc ID 17074 Rev 5
VNH5180A-E
Electrical specifications
2.2
Thermal data
Table 7.
Symbol
Thermal data
Parameter
Max. value
Unit
HSD
LSD
4.8
4.6
°C/W
Rthj-case
Rthj-amb
Thermal resistance junction-case (per leg)
Thermal resistance junction-ambient
See Figure 17
°C/W
2.3
Electrical characteristics
Values specified in this section are for VCC = 9 V up to 18 V; -40 °C < TJ < 150 °C, unless
otherwise specified.
Table 8.
Symbol
Power section
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
5.5
18
V
Off-state with all fault cleared and
ENx = 0 (standby)
INA = INB = PWM = 0; Tj = 25 °C;
VCC = 13 V
3
6
µA
Off-state with all fault cleared and
ENx = 0 (standby)
INA = INB = PWM = 0;
10
5
µA
VCC = 13 V; Tj = - 40 to 150 °C
IS
Supply current
Off-state (no standby)
INA = INB = PWM = 0; ENx = 5 V;
Tj = - 40 to 150 °C
mA
On-state:
3
6
6
mA
mA
INA or INB = 5 V; no PWM
On-state:
INA or INB = 5 V; PWM = 20 kHz
IOUT = 2.5 A; Tj = -40 °C
75
mΩ
mΩ
mΩ
I
I
OUT = 2.5 A; Tj = 25 °C
OUT = 2.5 A; Tj = 150 °C
115
230
RONHS Static high-side resistance
RONLS Static low-side resistance
IOUT = 2.5 A; Tj = - 40 to 150 °C
250 mΩ
mΩ
I
I
OUT = 2.5 A; Tj = 25 °C
53.5
0.7
OUT = 2.5 A; Tj = - 40 to 150 °C
110 mΩ
High-side free-wheeling
Vf
IOUT = -2.5 A; Tj = 150 °C
0.9
V
diode forward voltage
Doc ID 17074 Rev 5
9/31
Electrical specifications
VNH5180A-E
Table 8.
Symbol
Power section (continued)
Parameter
Test conditions
Min. Typ. Max. Unit
Tj = 25 °C; VOUTX = ENX = 0 V;
VCC = 13 V
0
0
3
5
µA
µA
A
High-side off-state output
current (per channel)
IL(off)
Tj = 125 °C; VOUTX = ENX = 0 V;
VCC = 13 V
Dynamic cross-
conduction current
IRM
IOUT= 2.5A (see Figure 6)
0.6
Table 9.
Symbol
Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS)
Parameter
Test conditions
Min. Typ. Max. Unit
Normal operation
VIL
Input low level voltage
(DIAGX/ENX pin acts as an
input pin)
0.9
V
V
V
Normal operation
(DIAGX/ENX pin acts as an
input pin)
VIH
Input high level voltage
2.1
Normal operation
(DIAGX/ENX pin acts as an 0.15
input pin)
VIHYST
Input hysteresis voltage
Input clamp voltage
I
IN = 1 mA
IN = -1 mA
5.5
-1.0
1
6.3
7.5
V
V
VICL
I
-0.7
-0.3
IINL
IINH
Input current
Input current
VIN = 0.9 V
VIN = 2.1 V
µA
µA
10
Fault operation
(DIAGX/ENX pin acts as an
output pin); IEN = 1 mA
Enable output low
level voltage
VDIAG
0.4
V
Table 10. Switching (VCC = 13 V, RLOAD = 5 Ω)
Symbol
Parameter
PWM frequency
Test conditions
Min. Typ. Max. Unit
f
0
20
kHz
µs
Input rise time < 1µs
(see Figure 6)
td(on)
td(off)
Turn-on delay time
Turn-off delay time
250
Input rise time < 1µs
(see Figure 6)
250
µs
tr
tf
Rise time
Fall time
See Figure 5
See Figure 5
1
1
2
2
µs
µs
Delay time during change
of operating mode
tDEL
See Figure 4
See Figure 7
200
400 1600
400
µs
ns
High-side free wheeling
diode reverse recovery
time
trr
10/31
Doc ID 17074 Rev 5
VNH5180A-E
Electrical specifications
Min. Typ. Max. Unit
Table 11. Protections and diagnostics
Symbol
Parameter
Test conditions
VUSD
Undervoltage shutdown
3
5
V
V
Undervoltage shutdown
hysteresis
VUSDhyst
0.5
ILIM_H
ISD_LS
High-side current limitation
Shutdown LS current
8
12
30
16
52
A
A
16
High-side clamp voltage (VCC to
OUTA = 0 or OUTB = 0)
VCLPH
IOUT = 2.5 A
41
41
46
52
V
V
Low-side clamp voltage
(OUTA = VCC or
VCLPLS
I
OUT = 2.5 A
46
52
OUTB = VCC to GND)
(1)
TTSD
Thermal shutdown temperature
Thermal reset temperature
Thermal hysteresis (TSD - TR)
VIN = 2.1 V
150
135
175
200
°C
°C
°C
(2)
TTR
(2)
THYST
7
Low-side thermal shutdown
temperature
TTSD_LS
VIN = 2.1 V
150
41
175
200
52
°C
VCLP
Total clamp voltage (VCC to GND) IOUT = 2.5 A
Time to shutdown for the low-side
46
10
V
tSD_LS
µs
1.
T
is the minimum threshold temperature between HS and LS
TSD
2. Valid for both HSD and LSD.
Table 12. Current sense (9 V < VCC < 18 V)
Symbol
Parameter
IOUT/ISENSE
IOUT/ISENSE
IOUT/ISENSE
IOUT/ISENSE
Test conditions
Min. Typ. Max. Unit
IOUT = 0.35 A; VSENSE = 0.32 V;
VCSD = 0 V; Tj = - 40 to 150 °C
K0
645 840 1140
IOUT = 1 A; VSENSE = 0.98 V;
CSD = 0 V; Tj = - 40 to 150 °C
K1
K2
K3
700 820 955
710 810 900
690 790 900
V
IOUT = 2.5 A; VSENSE = 2.4 V;
VCSD = 0 V; Tj = - 40 to 150 °C
IOUT = 4 A; VSENSE = 4 V; VCSD = 0 V;
Tj = - 40 to 150 °C
Analog sense
current drift
IOUT = 0.35A; VSENSE = 0.32V;
(1)
dK0/K0
-18
-13
-13
-13
5
18
13
13
13
%
%
%
%
V
VCSD = 0 V; Tj = - 40 to 150 °C
Analog sense
current drift
IOUT = 1 A; VSENSE = 0.98 V;
VCSD = 0 V; Tj = - 40 to 150 °C
(1)
dK1/K1
Analog sense
current drift
IOUT = 2.5A; VSENSE = 2.4V;
VCSD = 0 V; Tj = - 40 to 150 °C
(1)
dK2/K2
Analog sense
current drift
IOUT = 4A; VSENSE = 4V; VCSD = 0 V;
Tj = - 40 to 150 °C
(1)
dK3/K3
Max analog sense
output voltage
IOUT = 2.5A; VCSD = 0 V;
RSENSE = 2 KΩ
VSENSE
Doc ID 17074 Rev 5
11/31
Electrical specifications
Table 12. Current sense (9 V < VCC < 18 V) (continued)
VNH5180A-E
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
IOUT = 0 A; VSENSE = 0 V; VCSD = 5 V;
VIN = 0 V; Tj = - 40 to 150 °C
0
0
0
5
180
5
µA
µA
µA
Analog sense
leakage current
VCSD = 0 V; VIN = 5 V;
Tj = - 40 to.150 °C
ISENSE0
VCSD = 5 V; VIN = 5 V; IOUT = 2.5 A;
Tj = - 40 to.150 °C
Delay response time VIN = 5 V; VSENSE < 4 V, IOUT = 2.5 A,
tDSENSEH from falling edge of ISENSE = 90 % of ISENSEmax
50
20
µs
µs
CS_DIS pin
(see Figure 8)
VIN = 5 V; VSENSE < 4 V; IOUT = 2.5 A;
Delay response time
tDSENSEL from rising edge of
CS_DIS pin
ISENSE = 10 % of ISENSEmax
(see Figure 8)
1. Analog sense current drift is deviation of factor K for a given device over (-40 °C to 150 °C and
9 V < V < 18 V) with respect to its value measured at T = 25 °C, V = 13 V.
CC
J
CC
Figure 4.
Definition of the delay times measurement
V
INA
t
V
INB
t
PWM
t
I
LOAD
t
DEL
t
DEL
t
12/31
Doc ID 17074 Rev 5
VNH5180A-E
Figure 5.
Electrical specifications
Definition of the low-side switching times
PWM
t
V
OUTA, B
90%
80%
t
f
t
t
10%
20%
r
Figure 6.
Definition of the high-side switching times
V
INA
t
t
D(off)
D(on)
t
V
OUTA
90%
10%
t
Doc ID 17074 Rev 5
13/31
Electrical specifications
Figure 7.
VNH5180A-E
Definition of dynamic cross conduction current during a PWM operation
INA = 1, INB = 0
PWM
t
I
MOTOR
t
V
OUTB
t
I
CC
I
RM
t
t
rr
Figure 8.
Definition of delay response time of sense current
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
t
t
DSENSEH
DSENSEL
14/31
Doc ID 17074 Rev 5
VNH5180A-E
Electrical specifications
Operating mode
Table 13. Truth table in normal operating conditions
INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB
CS
1
0
1
0
H
L
High Imp.
Brake to VCC
1
0
H
L
Clockwise (CW)
Counterclockwise (CCW)
Brake to GND
1
1
ISENSE = IOUT/K
High Imp.
H
L
Table 14. Truth table in fault conditions (detected on OUTA)
INA
INB
DIAGA/ENA
DIAGB/ENB
OUTA
OUTB
CS (VCSD=0V)
1
0
1
0
X
H
1
High Imp.
IOUTB/K
L
H
1
0
0
OPEN
0
L
High Imp.
X
OPEN
Fault Information
Protection Action
Note:
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
Doc ID 17074 Rev 5
15/31
Electrical specifications
VNH5180A-E
Table 15. Electrical transient requirements (part 1)
Burst cycle/pulse
repetition time
Test levels(1)
ISO 7637-2:
2004(E)
Test pulse
Number of
pulses or
test times
Delays and
Impedance
III
IV
Min.
Max.
1
2a
3a
3b
4
-75V
+37V
-100V
+75V
-6V
-100V
+50V
-150V
+100V
-7V
5000 pulses
5000 pulses
1h
0.5s
0.2s
5s
2 ms, 10Ω
50µs, 2Ω
5s
90ms
90ms
100ms
100ms
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
1h
1 pulse
1 pulse
5b(2)
+65V
+87V
1. The above test levels must be considered referred to V = 13.5 V except for pulse 5b.
CC
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 16. Electrical transient requirements (part 2)
ISO 7637-2:
2004(E)
Test level results(1)
III
IV
Test pulse
1
2a
3a
3b
4
C
C
C
C
C
C
C
C
C
C
C
C
5b(2)
1. The above test levels must be considered referred to V = 13.5 V except for pulse 5b.
CC
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 17. Electrical transient requirements (part 3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
16/31
Doc ID 17074 Rev 5
VNH5180A-E
Electrical specifications
2.4
Waveforms
Figure 9.
Waveforms in full-bridge operation
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS (*)
tDEL
tDEL
CS_DIS
(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS
CS_DIS
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
INA
INB
ILIM
IOUTA->OUTB
TTSD_HSA
TTR_HSA
Tj =TTSD
Tj < TTSD
Tj > TTR
TjHSA
DIAGA/ENA
DIAGB/ENB
CS
CS_DIS
power limitation
current
limitation
normal operation
normal operation
OUTA shorted to ground
Doc ID 17074 Rev 5
17/31
Electrical specifications
Figure 10. Waveforms in full-bridge operation (continued)
VNH5180A-E
OUTA shorted to VCC (resistive short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
I
SD_LS
ILSA
T
TSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA softly shorted to VCC
normal operation
undervoltage shutdown
OUTA shorted to VCC (pure short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
I
SD_LS
ILSA
T
TSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA hardly shorted to VCC
normal operation
undervoltage shutdown
18/31
Doc ID 17074 Rev 5
VNH5180A-E
Application information
3
Application information
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
PWM pin usage: In all cases, a “0” on the PWM pin turns off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turn on again depending on the input pin state.
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit
protection
VCC
Reg 5V
+ 5V
+5V
VCC
3.3K
3.3K
1K
DIAGA/ENA
1K
DIAGA/ENA
1K
DIAGB/ENB
HSA
HSB
PWM
1k
μC
OUTA
CS_DIS
OUTB
INA
1K
1K
LSA
LSB
INB
CS
10K
M
Vcc
33nF
1.5K
GND
GND
S
100K
G
b) N MOSFET
D
Note:
The value of the blocking capacitor (C) depends on the application conditions and defines
voltage and current ripple on supply line at PWM operation. Stored energy of the motor
inductance may fly back into the blocking capacitor, if the bridge driver goes into 3-state.
This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation,
500 µF per 10 A load current is recommended.
In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.
The fault conditions are:
–
–
Overtemperature on one or both high-sides
Short to battery condition on the output (overcurrent detection on the low-side
Power MOSFET)
Possible origins of fault conditions may be:
OUTA is shorted to ground → overtemperature detection on high-side A
OUTA is shorted to VCC → low-side Power MOSFET overcurrent detection
When a fault condition is detected, the user can identify which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
Doc ID 17074 Rev 5
19/31
Application information
VNH5180A-E
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUTX) again, the input signal must rise from low to high level.
Figure 12. Behavior in fault condition (how a fault can be cleared)
Note:
In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: INA if ENA = 0 or INB if ENB = 0)
- Pull low all inputs, PWM and Diag/EN pins within tDEL
.
If the Diag/En pins are already low, PWM = 0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.
3.1
Reverse battery protection
Three possible solutions can be considered:
–
–
A Schottky diode D connected to VCC pin
An N-channel MOSFET connected to the GND pin (see Figure 11: Typical
application circuit for DC to 20 kHz PWM operation short circuit protection)
–
A P-channel MOSFET connected to the VCC pin
The device sustains no more than -15 A in reverse battery conditions because of the two
Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5180A-E is pulled down to the VCC line (approximately -1.5 V).
20/31
Doc ID 17074 Rev 5
VNH5180A-E
Application information
Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If
Rmax is the maximum target reverse current through microcontroller I/Os, series resistor is:
I
V
– V
IOs
I
CC
R = ---------------------------------
Rmax
Figure 13. Half-bridge configuration
V
CC
IN
IN
IN
A
A
B
IN
B
DIAG /EN
DIAG /EN
A
A
A
A
B
DIAG /EN
DIAG /EN
B
B
B
PWM
PWM
OUT
A
OUT
OUT
OUT
B
M
B
A
GND
GND
Note:
The VNH5180A-E can be used as a high power half-bridge driver achieving an On
resistance per leg of 90 mΩ.
Figure 14. Multi-motors configuration
V
CC
IN
IN
IN
IN
A
B
A
B
DIAG /EN
DIAG /EN
A
A
A
A
B
DIAG /EN
DIAG /EN
B
PWM
B
B
PWM
OUT
A
OUT
OUT
OUT
B
M
2
B
A
GND
GND
M
M
1
3
Note:
The VNH5180A-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high impedance.
Doc ID 17074 Rev 5
21/31
Package and PCB thermal data
VNH5180A-E
4
Package and PCB thermal data
4.1
PowerSSO-36 thermal data
Figure 15. PowerSSO-36™ PC board
Double layers: footprint
2
Double layers: 2cm of Cu
2
Double layers: 8cm of Cu
Note:
Board finish thickness 1.6 mm +/- 10 %, Board double layers, Board dimension 129 mm x 60 mm, Board Material FR4, Cu
thickness 0.070 mm (front and back side), Thermal vias spaced on a 1.2 mm x 1.2 mm grid, Vias pad clearance thickness
0.2 mm, Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm.
22/31
Doc ID 17074 Rev 5
VNH5180A-E
Figure 16. Chipset configuration
Package and PCB thermal data
CHIP 1
RthA
RthAB
RthAC
CHIP 2
CHIP 3
RthC
RthB
RthBC
Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition
80
RthA
RthB = RthC
RthAB = RthAC
RthBC
70
60
50
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
cm2 of Cu Area (refer to PCB layout)
4.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
Table 18. Thermal calculation in clockwise and anti-clockwise operation in steady-
state mode
HSA HSB LSA LSB
TjHSAB
TjLSA
TjLSB
PdHSA x RthHS + PdLSB PdHSA x RthHSLS
+
PdHSA x RthHSLS + PdLSB
ON OFF OFF ON
x RthHSLS + Tamb
PdLSB x RthLSLS + Tamb x RthLS + Tamb
PdHSB x RthHS + PdLSA PdHSB x RthHSLS
+
PdHSB x RthHSLS + PdLSA
x RthLSLS + Tamb
OFF ON ON OFF
x RthHSLS + Tamb
PdLSA x RthLS + Tamb
Doc ID 17074 Rev 5
23/31
Package and PCB thermal data
VNH5180A-E
4.1.2
Thermal calculation in transient mode
Ths = Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb
TlsA = PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zhsls + Tamb
TlsB = PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zhsls + Tamb
Figure 18. Detailed chipset configuration
CHIP 1
Zts
Zhsls
Zhsls
CHIP 2
CHIP 3
Zls
Zls
Zlsls
Equation 1: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THtp
THδ
TH
where
δ = t ⁄ T
p
24/31
Doc ID 17074 Rev 5
VNH5180A-E
Package and PCB thermal data
Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse
ZTH -HSD @ cu area
100
HSD-8 cm^2 Cu
HSD-2 cm^2 Cu
HSD-footprint
HsLsD-8 cm^2 Cu
HsLsD-2 cm^2 Cu
HsLsD-footprint
10
1
0.1
0.001
0.01
0.1
time (sec)
1
10
100
1000
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse
ZTH -LSD @ cu area
100
LSD-8 cm^2 Cu
LSD-2 cm^2 Cu
LSD-footprint
LsLsD-8 cm^2 Cu
LsLsD-2 cm^2 Cu
LsLsD-footprint
10
Z ls
Z lsls
1
0.1
0.001
0.01
0.1
time (sec)
1
10
100
1000
Doc ID 17074 Rev 5
25/31
Package and PCB thermal data
VNH5180A-E
Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36
Table 19. Thermal parameters(1)
Area/island (cm2)
Footprint
2
8
R1 = R7 (°C/W)
0.4
3.5
8
R2 = R8 (°C/W)
R3 (°C/W)
R4 (°C/W)
30
16
30
34
11
14
21
R5 (°C/W)
40
R6 (°C/W)
36
R9 = R15 (°C/W)
R10 = R16 (°C/W)
R11 = R17 (°C/W)
R12 = R18 (°C/W)
R13 = R19 (°C/W)
R14 = R20 (°C/W)
R21 = R22 = R23 (°C/W)
C1 = C7 = C9 = C15 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
0.1
5.2
32
14
21
36
40
77
14
21
24
33
75
49
52
50
80
0.0005
0.008
0.09
0.5
0.8
7
C4 (W.s/°C)
0.8
1.4
8
0.8
2
C5 (W.s/°C)
C6 (W.s/°C)
10
C10 = C16 (W.s/°C)
C11 = C17 (W.s/°C)
C12 = C18 (W.s/°C)
C13 = C19 (W.s/°C)
C14 = C20 (W.s/°C)
C21 = C22 = C23 (W.s/°C)
0.009
0.09
0.45
0.8
4
0.07
0.45
1.2
0.07
0.45
1.4
5
8
0.005
0.003
0.003
1. The blank space means that the value is the same as the previous one.
26/31
Doc ID 17074 Rev 5
VNH5180A-E
Package and packing information
5
Package and packing information
®
5.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-36 TP package information
Figure 22. PowerSSO-36 TP package dimensions
Doc ID 17074 Rev 5
27/31
Package and packing information
VNH5180A-E
Table 20. PowerSSO-36 TP mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
A
A2
a1
b
2.15
2.15
0
-
2.47
2.40
0.1
-
-
0.18
0.23
10.10
7.4
-
-
0.36
0.32
10.50
7.6
c
-
D
-
-
E
e
0.5
8.5
2.3
-
-
e3
F
-
-
G
-
10.1
-
0.1
10.5
0.4
H
-
h
-
k
0 deg
0.6
8 deg
1
L
-
M
N
4.3
-
-
10 deg
O
1.2
0.8
2.9
3.65
1.0
Q
S
T
U
X1
Y1
X2
Y2
X3
Y3
Z1
Z2
1.85
3
2.35
3.5
1.85
3
2.35
3.5
4.7
3
-
5.2
-
3.5
0.4
0.4
28/31
Doc ID 17074 Rev 5
VNH5180A-E
Package and packing information
5.3
PowerSSO-36 TP packing information
Figure 23. PowerSSO-36 TP tube shipment (no suffix)
Base Qty
49
1225
532
3.5
Bulk Qty
Tube length ( 0.5)
A
C
B
B
13.8
0.6
C ( 0.1)
All dimensions are in mm.
A
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”)
Reel dimensions
Base Qty
Bulk Qty
A (max)
B (min)
C ( 0.2)
F
1000
1000
330
1.5
13
20.2
24.4
100
30.4
G (+2 / -0)
N (min)
T (max)
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 ( 0.1)
P
12
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.55
1.5
11.5
2.85
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
No components
500mm min
Top
cover
tape
No components Components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Doc ID 17074 Rev 5
29/31
Revision history
VNH5180A-E
6
Revision history
Table 21. Document revision history
Date
Revision
Changes
11-Feb-2010
1
Initial release.
Updated following tables:
– Table 7: Thermal data
– Table 8: Power section
28-Sep-2010
2
– Table 12: Current sense (9 V < VCC < 18 V)
Updated Chapter 3: Application information
Updated following tables:
13-Oct-2010
20-Oct-2010
3
4
– Table 18: Thermal calculation in clockwise and anti-clockwise
operation in steady-state mode
– Table 19: Thermal parameters
Changed document status from target specification to definitive
datasheet
Updated Figure 1: Block diagram
Added Table 3: Suggested connections for unused and not
connected pins
22-Dec-2011
5
Table 11: Protections and diagnostics:
– TTSD, TTR, THYST: added note
Updated Figure 9: Waveforms in full-bridge operation and
Figure 10: Waveforms in full-bridge operation (continued)
30/31
Doc ID 17074 Rev 5
VNH5180A-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
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相关型号：
VNI8200XP
Octal high-side smart power solid state relay with serial/parallel selectable interface on chip
STMICROELECTR
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