AT9933 [SUPERTEX]
Hysteretic Boost-Buck (cuk) LED Driver IC; 迟滞升压 - 降压（ CUK ） LED驱动IC
| 型号： | AT9933 |
| 厂家： | 
Supertex, Inc |
| 描述： | Hysteretic Boost-Buck (cuk) LED Driver IC |
| 文件： | 总9页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT9933
Hysteretic Boost-Buck (Ćuk) LED Driver IC
Features
General Description
The AT9933 is a variable frequency PWM controller IC,
designed to control an LED lamp driver using a low-noise
boost-buck (Ćuk) topology. The AT9933 uses patent-pending
hysteretic current-mode control to regulate both the input and
theoutputcurrents.Thisenablessuperiorinputsurgeimmunity
without the necessity for complex loop compensation. Input
current control enables current limiting during startup, input
under-voltage and output overload conditions. The AT9933
provides a low-frequency PWM dimming input that can accept
an external control signal with a duty cycle of 0 - 100% and a
high dimming ratio.
► Constant current LED Driver
► Steps input voltage Up or Down
► Low EMI
► Variable frequency operation
► Internal 8 to 100V linear regulator
► Input and output current sensing
► Input current limit
► Enable & PWM dimming
► Ambient temperature rating up to 125°C
► Meets AEC-Q100 requirements
The AT9933 based LED driver is ideal for automotive LED
lamps. The part is rated for up to 125°C ambient temperatures
and is AEC-Q100-Compliant.
Applications
► Automotive LED Lighting
Reference Documents
► AEC-Q100 Rev. F, 7/18/2003
► SAE J1752-3
Typical Application Circuit
C1
D2 (optional)
-
L2
L1
RD
CD
D3
VDC
VO
+
D1
Q1
RCS1
RCS2
RS2
RS1
C2
RREF1
RREF2
VIN
VDD
GATE
PWMD
CS2
CS1
GND
REF
C3
AT9933
AT9933
Pin Configuration
Ordering Information
Package Option
1
2
3
4
8
7
6
5
VIN
REF
DEVICE
8-Lead SOIC
AT9933
AT9933LG-G
CS2
CS1
-G indicates package is RoHS compliant (‘Green’)
GND
VDD
PWMD
Absolute Maximum Ratings
Parameter
Value
-0.5V to +100V
GATE
VIN to GND
8-Lead SOIC
CS1, CS2
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
12V
(top view)
PWMD to GND
GATE to GND
VDDMAX
Continuous Power Dissipation (TA = +25°C)
8-Pin SOIC
700mW
Junction to ambient thermal impedance
(typical); using standard footprint
128OC/W
Junction temperature
+150°C
Storage temperature range
-65°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(The * denotes the specifications which apply over the full operating ambient temperature range of -40°C < TA < +125°C, otherwise the specifications are
at TA = 25°C. VIN = 12V, unless otherwise noted)
Symbol Parameter
Input
Min
Typ
Max
Units Conditions
(2)
VINDC
Input DC supply voltage range1
*
-
-
100
1.0
V
DC input voltage
PWMD connected to GND,
VIN = 12V
IINSD
Shut-down mode supply current1
-
0.5
mA
Internal Regulator
VIN = 8 – 100V, I
= 0,
VDD
Internally regulated voltage
*
7.0
7.5
9.0
V
500pF capacitorDaD(texGt) ATE,
PWMD = GND
VDD undervoltage lockout
threshold
UVLO
*
-
6.45
-
6.70
500
6.95
-
V
VIN rising
VDD undervoltage lockout
hysteresis
∆UVLO
mV
---
2
AT9933
Symbol Description
Min
Typ
Max
Units Conditions
Reference
REF pin voltage
-
-
1.212 1.25 1.288
1.187 1.25 1.312
REF bypassed with a 0.1µF
capacitor to GND, IREF= 0,
PWMD = 5.0V
-40°C < TA < +85°C
VREF
V
REF pin voltage
-40°C < TA < +125°C
REF bypassed with a 0.1µF
capacitor to GND, IREF = 0,
VDD = 7.0 – 9.0V, PWMD = 5.0V
Line regulation of reference
VREFLINE
-
-
-
0
-0.01
0
-
20
500
10
mV
µA
voltage
REF bypassed with a 0.1µF
capacitor to GND, IREF = 0;
VDD = 7.0 – 9.0V, PWMD = 5.0V
IREF
Reference output current range
REF bypassed with a 0.1µF
capacitor to GND, IREF = 0 - 5 0 0 µ A ,
PWMD = 5.0V
Load regulation of reference
voltage
VREFLOAD
-
mV
PWM Dimming
PWMD input low voltage
*
*
-
-
-
2.0
50
-
-
0.8
-
V
V
VDD = 7.0V – 9.0V
VDD = 7.0V – 9.0V
VPWMD = 5.0V
---
VPWMD(hi)
RPWMD
IPWMD
PWMD input high voltage
-
100
-
PWMD pull-down resistance
Maximum current into PWMD pin
150
5
kΩ
mA
GATE
ISOURCE
ISINK
GATE short circuit current
GATE sinking current
GATE output rise time
GATE output fall time
-
-
-
-
0.165
-
A
A
VGATE = 0V
-
0.165
-
-
VGATE = VDD
TRISE
-
-
30
30
50
50
ns
ns
CGATE = 500pF
CGATE = 500pF
TFALL
Input Current Sense Comparator
CS2 = 200mV; CS1 increasing;
GATE goes LOW to HIGH
VTURNON1 Voltage required to turn GATE on
*
*
-
-
85
-15
-
100
0
115
15
mV
mV
ns
CS2 = 200mV; CS1 decreasing;
GATE goes HIGH to LOW
VTURNOFF1 Voltage required to turn GATE off
CS2 = 200mV;
CS1 = 50mV to +200mV step
TD1,ON
Delay to output (turn on)
Delay to output (turn off)
150
150
250
250
CS2 = 200mV;
CS1 = 50mV to -100mV step
TD1,OFF
-
ns
Output Current Sense Comparator
CS1 = 200mV; CS2 increasing;
GATE goes LOW to HIGH
VTURNON2 Voltage required to turn GATE on
*
*
-
-
85
-15
-
100
0
115
15
mV
mV
ns
CS1 = 200mV; CS2 decreasing;
GATE goes HIGH to LOW
VTURNOFF2 Voltage required to turn GATE off
CS1 = 200mV;
CS2 = 50mV to +200mV step
TD2,ON
Delay to output (turn on)
150
150
250
250
CS1 = 200mV;
CS2 = 50mV to -100mV step
TD2,OFF
Delay to output (turn off)
-
ns
1 Also limited by package power dissipation limit, whichever is lower.
2 Depends on the current drawn by the part - see application section.
3
AT9933
Pin Description
Pin Number
Pin
Description
1
2
7
VIN
CS1
CS2
This pin is the input of a 8 - 100V voltage regulator.
These pins are used to sense the input and output currents of the boost-buck converter.
They are the non-inverting inputs of the internal comparators.
Ground return for all the internal circuitry. This pin must be electrically connected to the
ground of the power train.
3
4
5
GND
GATE
PWMD
This pin is the output gate driver for an external N-channel power MOSFET.
When this pin is left open or pulled to GND, the gate driver is disabled. Pulling the pin to
a voltage greater than 2V will enable the gate drive output.
This is a power supply pin for all internal circuits. It must be bypassed to GND with a low
ESR capacitor greater than 0.1µF.
This pin provides accurate reference voltage. It must be bypassed with a 0.01 - 0.1µF
capacitor to GND.
6
8
VDD
REF
Block Diagram
VIN
Regulator
VDD
7.5V
Input Comparator
CS1
100mV
GATE
REF
0mV
CS2
Output Comparator
1.25V
PWMD
GND
AT9933
4
AT9933
Functional Description
Power Topology
voltages at the VIN pin can be determined using the maxi-
mum voltage drop across the linear regulator as a function
of the current drawn. This data is shown in Fig. 1 for ambient
temperatures of 25ºC and 125ºC.
The AT9933 is optimized to drive a continuous conduction
mode (CCM) boost-buck DC/DC converter topology com-
monly referred to as “Ćuk converter” (see Circuit Diagram
on page 1). This power converter topology offers numerous
advantages useful for driving high-brightness light emitting
diodes (HB LED). These advantages include step-up or
step-down voltage conversion ratio and low input and output
current ripple. The output load is decoupled from the input
voltage with a capacitor making the driver inherently failure-
safe for the output load.
Voltage Drop vs. IIN
3.5
3
2.5
2
O
125 C
1.5
O
25 C
1
The AT9933 offers a simple and effective control technique
for use with a boost-buck LED driver. It uses two hysteretic
mode controllers – one for the input and one for the output.
The outputs of these two hysteretic comparators are AND-
ED and used to drive the external FET. This control scheme
gives accurate current control and constant output current in
the presence of input voltage transients without the need for
complicated loop design.
0.5
0
0
1
2
3
4
5
6
7
IIN (mA)
Fig. 1. Maximum Voltage Drop vs. Input Current
Assume an ambient temperature of 125°C. Assuming the IC
is driving a 15nC gate charge FET at 300kHz, the total input
current is estimated to be 5.5mA (using Eqn. 1). At this input
current, the maximum voltage drop from Fig. 1 can be ap-
proximately estimated to be VDROP = 2.7V. However, before
the IC starts switching the current drawn will be 1mA. At this
current level, the voltage drop is approximately VDROP1 = 0.5V.
Thus, the start/stop VIN voltages can be computed to be:
Input Voltage Regulator
The AT9933 can be powered directly from its VIN pin that
takes a voltage from 8V to 100V. When a voltage is applied
at the VIN pin, the AT9933 seeks to regulate a constant 7.5V
(typ) at the VDD pin. The regulator also has a built in under-
voltage lockout which shuts off the IC if the voltage at the
VDD pin falls below the UVLO threshold.
VINSTART = UVLOMAX + VDROP1
= 6.95V + 0.5V
The VDD pin must be bypassed by a low ESR capacitor
(≥0.1μF) to provide a low impedance path for the high fre-
quency current of the output gate driver.
= 7.45V
VINSTOP = UVLOMAX - ΔUVLO + VDROP
= 6.95 - 0.5V + 2.7V
= 9.15V
The input current drawn from the VIN pin is a sum of the 1mA
current drawn by the internal circuit and the current drawn by
the gate driver (which in turn depends on the switching fre-
quency and the gate charge of the external FET).
Note that in this case, since the gate drive draws too much
current, VINSTART is less than VINSTOP. In such cases, the con-
trol IC will oscillate between ON and OFF if the input voltage
is between the start and stop voltages. In these circumstanc-
es, it is recommended that the input voltage be kept higher
IIN = 1mA + QG•fS
(1)
In the above equation, fS is the switching frequency and Q
is the gate charge of the external FET (which can be obG-
tained from the datasheet of the FET).
than VIN
(in this case the IC will operate normally if the
input voltSaTgOeP is kept higher than 9.2V).
In case of input transients that reduce the input voltage be-
low 8V (like cold crank condition in an automotive system),
the VIN pin of the AT9933 can be connected to the drain of
the MOSFET through a switching diode with a small (1nF)
capacitor between VIN and GND (as long as the drain volt-
age does not exceed 100V). Since the drain of the FET is at
a voltage equal to the sum of the input and output voltages,
the IC will still be operational when the input goes below 8V.
In these cases, a larger capacitor is needed to the VDD pin
to supply power to the IC when the MOSFET is ON.
Minimum Input Voltage at VIN pin
The minimum input voltage at which the converter will start
and stop depends on the minimum voltage drop required for
the linear regulator. The internal linear regulator will regu-
late the voltage at the VDD pin when VIN is between 8 and
100V. However, when VIN is less than 8V, the converter will
still function as long as VDD is greater than the under voltage
lockout. Thus, under certain conditions, the converter will be
able to start at VIN voltages of less than 8V. The start/stop
5
AT9933
In this case VDD UVLO cannot be relied upon to turn off the IC PWM Dimming frequency range is from 100Hz to a few kilo
at low input voltages when input current levels can get too hertz.
large. The input current limit must then be designed to limit
the input current to safe levels during input undervoltage The flying capacitor in the Ćuk converter (C1) is initially
conditions.
charged to the input Voltage VDC (through diodes D1 and
D2). When the circuit is turned on and reaches steady state,
the voltage across C1 will be VDC+VO. In the absence of
diode D2, when the circuit is turned off, capacitor C1 will
discharge through the LEDs and the input voltage source
VDC. Thus, during PWM dimming, if capacitor C1 has to be
charged and discharged each cycle, the transient response
of the circuit will be limited. By adding diode D2, the volt-
age across capacitor C1 is held at VDC+VO even when the
circuit is turned off enabling the circuit to return quickly to its
steady state (and bypassing the start-up stage) upon being
enabled.
Reference
An internally trimmed voltage reference of 1.25V is provided
at the REF pin. The reference can supply a maximum output
current of 500μA to drive external resistor dividers.
This reference can be used to set the current thresholds of
the two comparators as shown in the Typical Application Cir-
cuit.
Current Comparators
The AT9933 features two identical comparators with a built-
in 100mV hysteresis. When the GATE is low, the inverting
terminal is connected to 100mV and when the GATE is high,
it is connected to GND. One comparator is used for the input
current control and the other for the output current control.
Application Information
Over-voltage Protection
Over-voltage protection can be added by splitting the output
side resistor R into two components and adding a zener
diode D3 (see Sth2 e Design Example Circuit on the following
page). When there is an open LED condition, the diode D3
will clamp the output voltage and the zener diode current will
The input side hysteretic controller is in operation during
start-up, overload and input undervoltage conditions. This
ensures that the input current never exceeds the designed
value. During normal operation, the input current will be less
than the programmed current and hence, the output of the
input side comparator will be HIGH. The output of the AND
gate will then be dictated by the output current controller.
be regulated by the sum of RS2A and RCS2
.
Damping Circuit
The Ćuk converter is inherently unstable when the output
current is being controlled. An uncontrolled input current will
lead to an un-damped oscillation between L1 and C1 caus-
ing excessively high voltages across C1. To prevent these
oscillations, a damping circuit consisting of RD and CD is
applied across the capacitor C1. This damping circuit will
stabilize the circuit and help in the proper operation of the
AT9933 based Ćuk converter.
The output side hysteretic comparator will be in operation
during the steady state operation of the circuit. This com-
parator turns the MOSFET on and off based on the LED
current.
PWM Dimming
PWM Dimming can be achieved by applying a TTL-compat-
ible square wave signal at the PWM pin. When the PWMD
pin is pulled high, the gate driver is enabled and the circuit
Design and Operation of the Boost-Buck Con-
operates normally. When the PWMD pin is left open or con- verter
nected to GND, the gate driver is disabled and the external For details on the design for a Boost-Buck converter using
MOSFET turns off. The IC is designed so that the signal at the AT9933 and the calculation of the damping components,
the PWMD pin inhibits the driver only and the IC need not go please refer to Application Note AN-H51.
through the entire start-up cycle each time ensuring a quick
response time for the output current. The recommended
6
AT9933
Design Example Circuit
C1
D2 (optional)
L2
L1
-
RD
CD
CO
VDC
VO
+
D1
Q1
RCS2
RCS1
RS2A
D3
C2
VIN
VDD
RS1
RS2B
GATE
PWMD
CS2
CS1
RREF2
C3
GND
REF
RREF1
AT9933
Design Example
Current Limits
The choice of the resistor dividers to set the input and output The current sense resistor (RCS2), combined with the other
current levels is illustrated by means of the design example resistors (RS2 & RREF2), determines the output current limits.
given below.
The current sense resistor (RCS1), combined with the other
resistors (RS1 & RREF1), determines the input current limits.
The parameters of the power circuit are:
VIN MIN = 9V
VIN MAX = 16V
VO = 28V
IO = 0.35A
fS MIN = 300kHz
The resistors can be chosen using the following equations:
(2)
RS
I X RCS = 1.2V X
+ 0.05V
RREF
RS
RREF
(3)
∆I X RCS = 0.1V X
+ 0.1V
Using these parameters, the values of the power stage in-
ductors and capacitor can be computed as (see Application
Note AN-H51 for details):
Where I is the current (either IO or IIN) and ΔI is the peak-to-
peak ripple in the current (either ΔIO or ΔIIN).
L1 = 82µH
L2 = 150µH
C1 = 0.22µF
For the input side, the current level used in the equations
should be larger than the maximum input current so that it
does not interfere with the normal operation of the circuit.
The peak input current can be computed as:
The input and output currents for this design are:
(4)
∆I
2
in
IIN,PK = IIN,MAX
+
IIN MAX = 1.6A
ΔIIN = 0.21A
= 1.706A
IO = 350mA
ΔIO = 87.5mA
7
AT9933
Assuming a 30% peak-to-peak ripple when the converter is RCS2 + RS2A = 120Ω
in input current limit mode, the minimum value of the input
(8)
current will be:
LIM,MIN = 0.85 • IIN,LIM
Choose the following values for the resistors:
CS2 = 1.65Ω, 1/4W, 1%
I
(5)
R
RREF2 = 10kΩ, 1/8W, 1%
RS2A = 100Ω, 1/8W, 1%
RS2B = 5.23kΩ, 1/8W, 1%
Setting
ILIM,MIN = 1.05 • IIN,PK
(6)
The current level to limit the converter can then be com- The current sense resistor needs to be at least a 1/4W, 1%
puted.
resistor.
1.05
0.85
(7)
Similarly, using IIN = 2.1A and ΔIIN = 0.3xIIN = 0.63 in (1) and
(2):
• IIN PK
IIN LIM
=
= 2.1A
Using IO = 350mA and ΔIO = 87.5mA in (1) and (2),
RS1
= 0.442
RREF1
RCS2 = 1.78Ω
RCS1 = 0.228Ω
PRCS1 = I2IN,LIM • RCS1 = 1W
RS2
= 0.5625
RREF2
Choose the following values for the resistors:
Before the design of the output side is complete, over voltage
protection has to be included in the design. For this applica-
tion, choose a 33V zener diode. This is the voltage at which
the output will clamp in case of an open LED condition. For
a 350mW diode, the maximum current rating at 33V works
out to about 10mA. Using a 2.5mA current level during open
LED conditions, and assuming the same RS2/RREF2 ratio,
RCS1 = parallel combination of three
0.68Ω, 1/2W, 5%
RREF1 = 10kΩ, 1/8W, 1%
RS1 = 4.42kΩ, 1/8W, 1%
8
AT9933
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90 0.10
8
6.00 0.20
Note 2
3.90 0.10
1
5° - 15°
(4 PLCS)
0.25 - 0.50
Note 2
Top View
45°
0.17 - 0.25
1.25 MIN
1.75 MAX
0.10 - 0.25
0° - 8°
0.40 - 1.27
0.31 - 0.51
1.27BSC
End View
Side View
Notes:
1. All dimensions in millimeters. Angles in degrees.
2. If the corner is not chamfered, then a Pin 1 identifier
must be located within the area indicated.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-AT9933
NR112806
9
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