HV7350K6-GM937 [SUPERTEX]
Eight-Channel, High Speed, ±60V, ±1.0A, Ultrasound RTZ Pulser;
| 型号： | HV7350K6-GM937 |
| 厂家： | 
Supertex, Inc |
| 描述： | Eight-Channel, High Speed, ±60V, ±1.0A, Ultrasound RTZ Pulser |
| 文件： | 总8页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
HV7350
Eight-Channel, High Speed, ±60V, ±1.0A,
Ultrasound RTZ Pulser
Features
General Description
► HVCMOS technology for high performance
► High density integrated ultrasound transmitter
► 0 to ±60V output voltage
The Supertex HV7350 is an eight channel monolithic high voltage high-
speed pulse generator with built-in fast return to zero damping FETs.
This high voltage and high-speed integrated circuit is designed for
portable medical ultrasound image devices.
► ±1.0A source and sink current in pulse mode
► ±1.0A source and sink current in RTZ mode
► Up to 20MHz operating frequency
► Matched delay times
HV7350 consists of a controller logic interface circuit, level translators,
MOSFET gate drives, and high current power P-channel and N-channel
MOSFETs as the output stage for each channel.
► Optional clock re-alignment
► 3.3V CMOS logic interface and reference
► +3.3V low voltage supply for VDD
► Built-in linear regulators for floating gate driver
► Built-in output drain diodes & bleed resistors
The output peak currents of each channel are guaranteed to be over
±1.0A with up to ±60V pulse swings as well as return-to-zero (RTZ)
mode. The gate drivers for the output MOSFETs are powered by built-in
linear 5.0V regulators referenced to VPP and VNN. This direct coupling
topology of the gate drivers not only saves four floating voltage supplies
or AC coupling capacitors per channel, but also makes the PCB layout
smaller and easier.
Application
► Portable medical ultrasound imaging
► Piezoelectric transducer drivers
► Pulse waveform generator
An input clock pin is available to realign all the logic input control lines to
a master clock. Precise logic timing is always essential in any ultrasound
systems.
Typical Application Circuit
+3.3V
+3.3V
+10 to +60V
0.1µF
1.0µF
1.0µF
1.0µF
CPF VPP
LRP
1.0µF
VLL
VDD
CPOS
1 of 8 Channels
LRP
REN
OEN
PIN1
NIN1
GND
GND
VPF
RGND
+5.0V
P-Driver
+5.0V
DMP
-5.0V
3.3V Logic
VPF
VNF
TX1
HVOUT
1
Logic
&
Level
Translator
PIN8
NIN8
CLK
X1
Rb
N-Driver
RGND
-5.0V
VNF
GND
GND
RGND
1.0µF
LRN
LRN
GND
SUB
DAP
GND
CNEG
CNF
VNN
1.0µF
1.0µF
-10 to -60V
Doc.# DSFP-HV7350
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Supertex inc.
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HV7350
Ordering Information
Part Number
Package
Packing
250/ Tray
2000/Reel
HV7350K6-G
56-Lead (8x8) QFN
56-Lead (8x8) QFN
HV7350K6-G M937
ESD Sensitive Device
-G denotes a lead (Pb)-free / RoHS compliant package
Pin Configuration
Absolute Maximum Ratings
Parameter
56
Value
1
VSUB, substrate voltage is GND
0V
-0.5V to +5.5V
-0.5V to +5.5V
-0.5V to +5.5V
+0.5V to -5.5V
-0.5V to +5.5V
-0.5V to +5.5V
+130V
VLL, Positive logic supply
VDD, Positive logic and level translator supply
CPOS to GND, Positive level translator circuit
CNEG to GND, Negative level translator circuit
(VPP - CPF), Positive gate driver circuit
(CNF - VNN), Negative gate driver circuit
(VPP - VNN) Differential high voltage supply
VPP, High voltage positive supply
56-Lead QFN
(top view)
-0.5V to +65V
+0.5V to -65V
-0.5V to +5.5V
-40°C to 125°C
-65°C to 150°C
Package Marking
VNN, High voltage negative supply
All logic input PINX, NINX, OEN and REN voltages
Operating temperature
L = Lot Number
HV7350K6
LLLLLLLLL
YYWW
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
AAA CCC
Storage temperature
Package may or may not include the following marks: Si or
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
56-Lead QFN
Typical Thermal Resistance
Package
θja
56-Lead (8x8) QFN
21OC/W
Output Current & Ron
ISC
RonP
RonN
IDMP
1.5A
RonDP
RonDN
1.5A
13Ω
6.5Ω
13Ω
8.0Ω
Notes:
1.VPP/VNN = +/-60V, VDD = +3.3V; REN = 1
3. IDMP is current from +/-30V connected to TX pin.
2. ISC is current into 1.0Ω to GND;
4. Max pulse width for current measurement on TX pin is 100ns.
Power-Up Sequence
Power-Down Sequence
Step
Description
Step
Description
1
2
3
4
5
VLL with logic signal low
VDD
1
2
3
4
5
All logic signals go to low
VPP and VNN
REN = 1 (external supplies on)
VPP and VNN
REN = 0 (external supplies off)
VDD
VLL
Logic control signals active
Note:
Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in
order to minimize possible inrush current.
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2
HV7350
Operating Supply Voltages and Current (Eight Active Channels)
(Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C)
Sym
Parameter
Min
Typ
3.30
2.60
3.30
1.55
-
Max
5.20
2.80
5.00
1.70
+60
-10
-
Units Conditions
VDD
VDD voltage supply
2.97
V
V
V
V
V
V
---
---
---
---
---
---
UVLODD VDD UVLO
2.30
VLL
Logic voltage reference
2.50
UVLOLL VLL UVLO
1.30
VPP
VNN
Positive high voltage supply
+10
Negative high voltage supply
VLL current
-60
-
ILLQ
-
-
-
-
-
-
-
-
-
-
-
-
8.0
1.0
5.0
5.0
13
IDDQ
VDD current
-
μA OEN = REN = 0
IPPQ
VPP current
10
10
20
700
350
400
-
INNQ
VNN current
ILLEN
IDDEN
IPPEN
INNEN
IDDCW
IPPCW
INNCW
ILL,CLK
VLL current
VDD current
480
220
300
2.3
80
OEN = REN = 1
μA
5.0ms after f = 0MHz
VPP current
VNN current
VDD current
f = 5.0MHz, Continuous, no loads,
mA for calculation reference only.
VPP current
-
VNN current
80
-
VLL current
33
-
μA fCLK = 10MHz, PIN = NIN = 0
Electrical Characteristics
(Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C)
Pulser P-Channel MOSFET
Sym
Parameter
Min
1.0
-
Typ
1.5
Max
Units Conditions
IOUT
Output saturation current
Channel resistance
-
-
A
---
RON
13.2
Ω
ISD = 100mA
Pulser N-Channel MOSFET
Sym
Parameter
Min
1.0
-
Typ
1.5
8.0
Max
Units Conditions
IOUT
Output saturation current
Channel resistance
-
-
A
---
RON
Ω
ISD = 100mA
Damping P-Channel MOSFET
Sym
Parameter
Min
1.0
-
Typ
1.5
13
Max
Units Conditions
IOUT
Output saturation current
Channel resistance
-
-
A
---
RON
Ω
ISD = 100mA
Damping N-Channel MOSFET
Sym
Parameter
Min
1.0
-
Typ
1.5
9.0
Max
Units Conditions
IOUT
Output saturation current
Channel resistance
-
-
A
---
RON
Ω
ISD = 100mA
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HV7350
Logic Inputs
Sym
VIH
VIL
VIH
VIL
IIH
Parameter
Min
Typ
Max
VLL
Units Conditions
Input logic high voltage
Input logic low voltage
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
Input logic capacitance
0.7 • VLL
-
-
-
-
-
-
-
V
VLL = 2.5 to 3.3V
0
0.3 • VLL
VLL
V
V
V
0.8 • VLL
VLL = 5.0V
0
-
0.2 • VLL
10
μA ---
μA ---
IIL
-10
-
-
CIN
5.0
pF
---
MOSFET Drain Bleed Resistor
Sym
Parameter
Min
12
-
Typ
17
-
Max
25
Units Conditions
kΩ ---
mW ---
RB1~8
Output Bleed Resistance
PRB1~8 Bleed Resistors Power Limit
50
AC Electrical Characteristics
(Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C)
Sym
tr
Parameter
Min
Typ
30
Max
Units Conditions
Output rise time
-
-
-
-
-
-
-
-
-
-
-
ns
ns
μs
μs
330pF//2.5kΩ load
10 - 90%
tf
Output fall time
30
-
tEN
tDIS
td1
td2
td3
td4
tdc
Enable time
300
2.8
12
500
Cap value see page 1 diagram.
OEN = REN
Disable time
10
-
Delay time on PINX rise
Delay time on NINX rise
Delay time on damping rise
Delay time on damping fall
Delay time on CLK rise
1.0Ω resistor load, D%<1%
(See timing diagram)
50% inputs to 50% TX current
12
-
12
-
ns
12
-
9.0
±3.0
-
ΔtDELAY Delay time matching
-
ns
ps
ns
P to N, channel to channel
VPP/VNN = +/-25V, input tr50% to HVOUT
tr or tf 50%, with 330pF//2.5kΩ load
TBD
tj
Delay jitter on rise or fall
-
-
trr
RTZ FETs drain diode trr
Re-timing clock frequency
-
10
-
25
220
0.5
-
-
IF = 1.0A, IR = 1.0A, RL = 10Ω
fCLK
-
5.0
-
MHz ---
tRC, tFC Re-timing clock rise & fall times
ns
ns
---
---
---
tsu
tH
Set-up time, PIN/NIN to CLK
Hold time, CLK to PIN/NIN
2.0
1.0
2.0
2.0
-
-
-
ns
tCLK_LO Clock time low
-
100
100
-
ns
CLK input must have at least one
pulse before PIN and NIN inputs are
not zero. Be sure to return inputs to
zero before stopping clock.
tCLK_HI Clock time high
-
ns
tCLK_REC Clock recognition time
tCLK_RLS Clock release time
2.0
300
-
ns
150
-
800
20
-
ns
fOUT
HD2
COSS
Output frequency range
Second harmonic distortion
Output capacitance
MHz
dB
pF
100Ω resistor load
-
-40
50
-
-
VDS = 25V, f = 1.0MHz , of TX pin total
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HV7350
Truth Table
Logic Inputs
TXn Output
OEN
CLK
PINX
NINX
0
VPP
OFF
ON
VNN
OFF
OFF
ON
RGND
Note
1
1
1
1
1
1
1
1
0
VLL
VLL
VLL
VLL
0
ON
OFF
OFF
OFF
ON
1
0
Asynchronous Mode
Output change on PIN/NIN
0
1
OFF
OFF
OFF
ON
1
1
OFF
OFF
OFF
ON
0
0
Synchronous Mode
Output change at retiming
clock(CLK) rising edge,
registered by PIN/NIN
1
0
OFF
OFF
OFF
OFF
0
1
OFF
OFF
OFF
1
1
OFF
OFF
X
X
X
Disabled
Switching Time Diagram
CLK
CLK
PINn
(NINn = 0)
NINn
(PINn = 0)
50%
50%
td1
td4
td3
IOUT
td2
50%
TXn
0A
0A
TXn
50%
Asynchronous Mode
IOUT
CLK
CLK
PINn
(NINn = 0)
NINn
(PINn = 0)
tdc
tdc
tdc
tdc
IOUT
50%
TXn
0A
TXn
0A
50%
Synchronous Mode
IOUT
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HV7350
Pin Description
Pin
Name
PIN2
NIN2
PIN3
NIN3
PIN4
NIN4
OEN
Description
1
Input logic control of high voltage output P-FET for channel 2, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output N-FET for channel 2, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output P-FET for channel 3, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output N-FET for channel 3, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output P-FET for channel 4, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output N-FET for channel 4, Hi = on, Low = off. (see logic table)
Output enable Hi = on, Low = off. See logic truth table
2
3
4
5
6
7
Built-in positive and negative 5V voltage regulators enable. Hi = on, Low = off. If REN = 0, exter-
nal floating 5V power supplies may be supplied across CPF, CNF CPOS and CNEG capacitors
8
REN
9
PIN5
NIN5
PIN6
NIN6
PIN7
NIN7
PIN8
NIN8
VLL
Input logic control of high voltage output P-FET for channel 5, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output N-FET for channel 5, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output P-FET for channel 6, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output N-FET for channel 6, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output P-FET for channel 7, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output N-FET for channel 7, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output P-FET for channel 8, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output N-FET for channel 8, Hi = on, Low = off. (see logic table)
Logic supply voltage and reference input (+3.3V)
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
VDD
VPP
VPP
VPP
Logic and circuit return ground (0V)
Positive voltage power supply (+3.3V)
Positive high voltage power supply (+10 to +60V)
Built-in linear voltage VPF regulator output decoupling capacitor pin, 1uF from VPP to CPF per
each
23
24
CPF
CNF
Built-in linear voltage VNF regulator output decoupling capacitor pin, 1uF from CNF to VNN per
each
25
26
27
28
29
30
31
32
VNN
VNN
VNN
TX8
Negative high voltage power supply (-10 to -60V)
TX pulser channel 8 output
RGND
TX7
Damping ground and bleed resistors common return ground
TX pulser channel 7 output
RGND
TX6
Damping ground and bleed resistors common return ground
TX pulser channel 6 output
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HV7350
Pin Description (cont.)
Pin
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Name
RGND
TX5
Description
Damping ground and bleed resistors common return ground
TX pulser channel 5 output
CNEG
CPOS
TX4
Built-in linear voltage -5V regulator output decoupling capacitor pin, 1.0uF from CNEG to GND
Built-in linear voltage +5V regulator output decoupling capacitor pin, 1.0uF from CPOS to GND
TX pulser channel 4 output
RGND
TX3
Damping ground and bleed resistors common return ground
TX pulser channel 3 output
RGND
TX2
Damping ground and bleed resistors common return ground
TX pulser channel 2 output
RGND
TX1
Damping ground and bleed resistors common return ground
TX pulser channel 1 output
VNN
VNN
Negative high voltage power supply (-10 to -60V)
VNN
Built-in linear voltage VNF regulator output decoupling capacitor pin, 1uF from CNF to VNN per
each
47
48
CNF
CPF
Built-in linear voltage VPF regulator output decoupling capacitor pin, 1uF from VPP to CPF per
each
49
50
51
52
53
54
55
56
VPP
VPP
VPP
VDD
GND
CLK
PIN1
NIN1
Positive high voltage power supply (+10 to +60V)
Positive voltage power supply (+3.3V)
Logic and circuit return ground (0V)
Re-timing register clock input. Connect to VLL to disable the re-timing function
Input logic control of high voltage output P-FET for channel 1, Hi = on, Low = off. (see logic table)
Input logic control of high voltage output N-FET for channel 1, Hi = on, Low = off. (see logic table)
Substrate bottom is internally connected to the central thermal pad on the bottom of package. It
must be connected to GND (0V) externally
VSUB (Thermal Pad)
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HV7350
56-Lead QFN Package Outline (K6)
8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch
D2
D
56
56
1
1
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
b
E
E2
View B
Bottom View
Top View
Note 3
θ
L
A3
A
Seating
Plane
L1
Note 2
A1
Side View
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
A
A1
A3
b
D
D2
E
E2
e
L
L1
0.00
-
θ
0O
-
MIN
NOM
MAX
0.80
0.90
1.00
0.00
0.02
0.05
0.18
0.25
0.30
7.85*
2.75
7.85*
2.75
0.30
0.40
0.50
Dimension
(mm)
0.20
REF
0.50
BSC
8.00
5.70
8.00
5.70
8.15* 6.70† 8.15* 6.70†
0.15
14O
JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings are not to scale.
Supertex Doc.#: DSPD-56QFNK68X8P050, Version A031010.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2014 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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