TC6320K6-G [SUPERTEX]
N- and P-Channel Enhancement-Mode MOSFET Pair;
| 型号： | TC6320K6-G |
| 厂家： | 
Supertex, Inc |
| 描述： | N- and P-Channel Enhancement-Mode MOSFET Pair |
| 文件： | 总6页 (文件大小：695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
TC6320
N- and P-Channel
Enhancement-Mode MOSFET Pair
Features
General Description
► Integrated GATE-to-SOURCE resistor
► Integrated GATE-to-SOURCE Zener diode
► Low threshold
The Supertex TC6320 consists of high voltage, low threshold
N-channel and P-channel MOSFETs in 8-Lead SOIC and DFN
packages. Both MOSFETs have integrated GATE-to-SOURCE
resistors and GATE-to-SOURCE Zener diode clamps which are
desired for high voltage pulser applications. It is a complimentary,
high-speed, high voltage, GATE-clamped N- and P-channel
MOSFET pair, which utilizes an advanced vertical DMOS
structure and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces a device with the power
handling capabilities of bipolar transistors and with the high
input impedance and positive temperature coefficient inherent in
MOS devices. Characteristic of all MOS structures, this device
is free from thermal runaway and thermally induced secondary
breakdown.
► Low on-resistance
► Low input capacitance
► Fast switching speeds
► Free from secondary breakdown
► Low input and output leakage
► Independent, electrically isolated N- and
P-channels
Applications
► High voltage pulsers
► Amplifiers
► Buffers
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low
input capacitance, and fast switching speeds are desired.
► Piezoelectric transducer drivers
► General purpose line drivers
► Logic level interfaces
Typical Application Circuit
+100V
VH
VDD
OE
10nF
10nF
INA
INB
-100V
VL
VSS
Supertex
MD12xx, MD17xx, or MD18xx
Supertex
TC6320
Doc.# DSFP-TC6320
D012913
Supertex inc.
www.supertex.com
TC6320
Ordering Information
Product Summary
Part Number
TC6320K6-G
TC6320TG-G
Package Option
Packing
BVDSS/BVDGS
RDS(ON)
(max) (Ω)
(V)
8-Lead DFN (4x4)
8-Lead SOIC
3000/Reel
2000/Reel
N-Channel
P-Channel
N-Channel
P-Channel
-G indicates package is RoHS compliant (‘Green’)
200
-200
7.0
8.0
Pin Configurations
1
2
3
4
8
7
6
5
SN
GN
GP
SP
DN
DN
DP
DP
DN
DP
Absolute Maximum Ratings
Parameter
Value
BVDSS
BVDGS
DRAIN-to-SOURCE voltage
DRAIN-to-GATE voltage
Operating and storage temperature
-55°C to +150°C
8-Lead DFN
(top view)
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
S1
G1
S2
G2
1
2
3
4
8 D1
Typical Thermal Resistance
7 D1
6 D2
5 D2
Package
θja
N-Channel
P-Channel
8-Lead DFN
8-Lead SOIC
44OC/W
101OC/W
Note:
1.0oz, 4-layer, 3”x4” PCB
8-Lead SOIC
(top view)
Package Marking
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
6320
YWLL
= “Green” Packaging
Package may or may not include the following marks: Si or
8-Lead DFN
YY = Year Sealed
YYWW
WW = Week Sealed
C6320
L = Lot Number
LLLL
= “Green” Packaging
Package may or may not include the following marks: Si or
8-Lead SOIC
Doc.# DSFP-TC6320
D012913
Supertex inc.
2
www.supertex.com
TC6320
N-Channel Electrical Characteristics (TC = 25°C unless otherwise specified)
Sym
BVDSS
VGS(th)
Parameter
Min
200
1.0
-
Typ
Max
Units Conditions
DRAIN-to-SOURCE breakdown voltage
GATE threshold voltage
-
-
-
-
-
-
-
V
V
VGS = 0V, ID = 2.0mA
VGS = VDS, ID = 1.0mA
2.0
-4.5
50
ΔVGS(th) Change in VGS(th) with temperature
mV/OC VGS = VDS, ID = 1.0mA
RGS
GATE-to-SOURCE shunt resistor
GATE-to-SOURCE Zener voltage
10
kΩ
V
IGS = 100µA
VZGS
13.2
-
25
IGS = 2.0mA
10.0
µA
VDS = Max rating, VGS = 0V
IDSS
Zero GATE voltage DRAIN current
On-state DRAIN current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
-
-
1.0
mA
A
1.0
-
-
-
VGS = 4.5V, VDS = 25V
VGS = 10V, VDS = 25V
VGS = 4.5V, ID = 150mA
VGS = 10V, ID = 1.0A
VGS = 4.5V, ID =150mA
ID(ON)
2.0
-
-
-
8.0
7.0
1.0
-
Static DRAIN-to-SOURCE on-state
resistance
RDS(ON)
Ω
-
-
ΔRDS(ON) Change in RDS(ON) with temperature
-
-
%/OC
GFS
CISS
COSS
CRSS
td(ON)
tr
Forward transconductance
Input capacitance
400
-
mmho VDS = 25V, ID = 500mA
-
-
-
-
-
-
-
-
-
-
110
60
23
10
15
20
15
1.8
-
VGS = 0V,
VDS = 25V,
f = 1.0MHz
Common SOURCE output capacitance
Reverse transfer capacitance
Turn-on delay time
-
pF
ns
-
-
VDD =25V,
ID = 1.0A,
RGEN = 25Ω
Rise time
-
td(OFF)
tf
Turn-off delay time
-
Fall time
-
-
VSD
Diode forward voltage drop
Reverse recovery time
V
VGS = 0V, ISD = 500mA
VGS = 0V, ISD = 500mA
trr
300
ns
Notes:
1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
N-Channel Switching Waveforms and Test Circuit
10V
90%
VDD
RL
Input
10%
Pulse
0V
OUTPUT
Generator
t(ON)
td(ON)
t(OFF)
td(OFF)
RGEN
tr
tf
D.U.T
VDD
10%
90%
10%
90%
Input
Output
0V
Doc.# DSFP-TC6320
D012913
Supertex inc.
3
www.supertex.com
TC6320
P-Channel Electrical Characteristics (TC = 25°C unless otherwise specified)
Sym
BVDSS
VGS(th)
Parameter
Min
-200
-1.0
-
Typ
Max
Units Conditions
DRAIN-to-SOURCE breakdown voltage
GATE threshold voltage
-
-
-
-
-
-
-
V
V
VGS = 0V, ID = -2.0mA
VGS = VDS, ID = -1.0mA
-2.4
4.5
50
ΔVGS(th) Change in VGS(th) with temperature
mV/OC VGS = VDS, ID = -1.0mA
RGS
GATE-to-SOURCE shunt resistor
GATE-to-SOURCE Zener voltage
10
kΩ
V
IGS = 100µA
VZGS
13.2
-
25
IGS = -2mA
-10
µA
VDS = Max rating, VGS = 0V
IDSS
Zero GATE voltage DRAIN current
On-state DRAIN current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
-
-
-1.0
mA
A
-1.0
-
-
-
VGS = -4.5V, VDS = -25V
VGS = -10V, VDS = -25V
VGS = -4.5V, ID = -150mA
VGS = -10V, ID = -1.0A
VGS = -10V, ID =-200mA
ID(ON)
-2.0
-
-
-
10
8.0
1.0
-
Static DRAIN-to-SOURCE on-state resis-
tance
RDS(ON)
Ω
-
-
ΔRDS(ON) Change in RDS(ON) with temperature
-
-
%/OC
GFS
CISS
COSS
CRSS
td(ON)
tr
Forward transconductance
Input capacitance
400
-
mmho VDS = -25V, ID = -500mA
-
-
-
-
-
-
-
-
-
-
200
55
30
10
15
20
15
-1.8
-
VGS = 0V,
VDS = -25V,
f = 1.0MHz
Common SOURCE output capacitance
Reverse transfer capacitance
Turn-on delay time
-
pF
ns
-
-
VDD = -25V,
ID = -1.0A,
RGEN = 25Ω
Rise time
-
td(OFF)
tf
Turn-off delay time
-
Fall time
-
-
VSD
Diode forward voltage drop
Reverse recovery time
V
VGS = 0V, ISD = -500mA
VGS = 0V, ISD = -500mA
trr
300
ns
Notes:
1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
P-Channel Switching Waveforms and Test Circuit
0V
10%
Pulse
Generator
Input
90%
RGEN
-10V
D.U.T
t(ON)
td(ON)
t(OFF)
Input
tr
tf
td(OFF)
90%
10%
OUTPUT
RL
0V
90%
10%
Output
VDD
VDD
Doc.# DSFP-TC6320
D012913
Supertex inc.
4
www.supertex.com
TC6320
8-Lead DFN Package Outline (K6)
4.00x4.00mm body, 1.00mm height (max), 1.00mm pitch (dual pad)
K1
K1/2
D
D2
D2
8
8
E2
E
E2
Note 1
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
1
View B
1
Top View
Bottom View
Note 3
θ
A3
L
A
Seating
Plane
L1
e
b
Note 2
A1
Side View
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
A
A1
0.00
-
A3
b
D
D2
E
E2
e
K1
L
L1
0.00
-
θ
0O
-
MIN
0.80
0.25
0.30
0.35
3.90
4.00
4.10
1.35
1.45
1.55
3.90
4.00
4.10
1.35
1.45
1.55
0.40
0.50
0.60
Dimension
(mm)
0.20
REF
1.00
BSC REF
0.50
NOM 0.90
MAX 1.00
0.05
0.15
14O
Drawings not to scale
Supertex Doc. #: DSPD-8DFNK64x4P100, Version C010813
Doc.# DSFP-TC6320
D012913
Supertex inc.
5
www.supertex.com
TC6320
8-Lead SOIC (Narrow Body) Package Outline (TG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
θ1
D
8
Note 1
(Index Area
D/2 x E1/2)
E1
E
Gauge
Plane
L2
Seating
Plane
L
θ
1
L1
Top View
View B
View B
Note 1
h
A
h
A2
A
Seating
Plane
A1
e
b
A
Side View
View A-A
Note:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
Symbol
A
A1
A2
b
D
E
E1
e
h
L
L1
L2
θ
0O
-
θ1
5O
-
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
NOM 4.90 6.00 3.90
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00*
0.25 0.40
Dimension
(mm)
1.27
BSC
1.04 0.25
REF BSC
-
-
-
-
-
-
0.50 1.27
8O
15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-TC6320
D012913
6
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