MAS3529FFH [TDK]
Consumer Circuit, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-64;型号: | MAS3529FFH |
厂家: | TDK ELECTRONICS |
描述: | Consumer Circuit, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-64 商用集成电路 |
文件: | 总92页 (文件大小:1189K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MAS 35x9F
MPEG Layer 2/3,
AAC Audio Decoder,
G.729 Annex A Codec
June 30, 2004
6251-505-1DS
MICRONAS
MAS 35x9F
DATA SHEET
Contents
Page
Section
Title
5
6
6
7
1.
Introduction
1.1.
1.2.
1.3.
Features
Features of the MAS 35x9F Family
Application Overview
8
2.
Functional Description
Overview
8
2.1.
8
2.2.
Architecture of the MAS 35x9F
DSP Core
8
2.3.
9
2.3.1.
2.3.2.
2.3.2.1.
2.3.2.2.
2.4.
RAM and Registers
9
Firmware and Software
Internal Program ROM and Firmware, MPEG-Decoding
Program Download Feature
Audio Codec
9
9
10
10
10
10
10
10
10
11
11
11
11
11
12
12
12
13
15
15
15
15
15
15
15
15
16
17
17
18
18
18
18
18
18
19
2.4.1.
2.4.2.
2.4.2.1.
2.4.2.2.
2.4.2.3.
2.4.2.4.
2.4.3.
2.4.4.
2.5.
A/D Converter and Microphone Amplifier
Baseband Processing
Bass, Treble, and Loudness
Micronas Bass (MB)
Automatic Volume Control (AVC)
Balance and Volume
D/A Converters
Output Amplifiers
Clock Management
2.5.1.
2.5.2.
2.6.
DSP Clock
Clock Output At CLKO
Power Supply Concept
Power Supply Regions
DC/DC Converters
2.6.1.
2.6.2.
2.6.3.
2.7.
Power Supply Configurations
Battery Voltage Supervision
Interfaces
2.8.
2.8.1.
2.8.2.
2.8.3.
2.8.4.
2.8.5.
2.8.6.
2.9.
I2C Control Interface
S/PDIF Input Interface
S/PDIF Output
Multiline Serial Audio Input (SDI, SDIB)
Multiline Serial Output (SDO)
Parallel Input/Output Interface (PIO)
MPEG Synchronization Output
MP3 Block Input Mode
Functional Description of the MP3 Block Input Mode
Setup
2.10.
2.10.1.
2.10.2.
2.10.2.1.
2.10.2.2.
2.11.
Resync Timeout
Detailed Setup
Default Operation
2.11.1.
2.11.2.
2.11.2.1.
Stand-by Functions
Power-Up of the DC/DC Converters and Reset
Important Advice for Turn-on and Operating Voltage
2
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Micronas
DATA SHEET
MAS 35x9F
Contents, continued
Page
Section
Title
20
21
21
21
2.11.3.
2.11.4.
2.11.5.
2.11.6.
Reset Signal Specification
Control of the Signal Processing
Start-up of the Audio Codec
Power-Down
22
22
22
22
22
22
23
23
27
27
28
28
28
28
29
29
29
29
29
30
30
30
31
31
31
32
32
43
43
44
44
45
45
45
46
52
3.
Controlling
2
3.1.
I C Interface
3.1.1.
3.1.2.
3.1.3.
3.2.
Device Address
2
I C Registers and Subaddresses
Naming Convention
Direct Configuration Registers
Write Direct Configuration Registers
Read Direct Configuration Register
DSP Core
3.2.1.
3.2.2.
3.3.
3.3.1.
3.3.2.
3.3.2.1.
3.3.2.2.
3.3.2.3.
3.3.2.4.
3.3.2.5.
3.3.2.6.
3.3.2.7.
3.3.2.8.
3.3.2.9.
3.3.2.10.
3.3.2.11.
3.3.2.12.
3.3.3.
3.3.4.
3.3.4.1.
3.3.4.2.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.4.
Access Protocol
Data Formats
Run and Freeze (Codes 0hex to 3hex)
Read Register (Code A
Write Register (Code B
)
hex
)
hex
Read Memory (Codes C
and D
)
hex
hex
Short Read Memory (Codes C4
and D4
)
hex
hex
Write Memory (Codes Ehex and Fhex)
Short Write Memory (Codes E4 and F4
)
hex
hex
Clear SYNC Signal (Code 5hex)
Default Read
Fast Program Download (Code 6
Serial Program Download
)
hex
Read IC Version (Code 7
List of DSP Registers
)
hex
List of DSP Memory Cells
Application Selection and Application Running
Application Specific Control
Ancillary Data
Reading of the Memory Cells “Number of Bits in Ancillary Data” and “Ancillary Data”
DSP Volume Control
Explanation of the G.729A Data Format
Audio Codec Access Protocol
Write Codec Register
3.4.1.
3.4.2.
3.4.3.
3.4.4.
Read Codec Register
Codec Registers
Basic MB Configuration
Micronas
June 30, 2004; 6251-505-1DS
3
MAS 35x9F
DATA SHEET
Contents, continued
Page
Section
Title
54
54
57
60
60
60
60
60
60
60
61
61
61
61
61
61
61
61
62
62
63
64
65
65
67
71
72
73
74
76
77
77
79
4.
Specifications
4.1.
Outline Dimensions
4.2.
Pin Connections and Short Descriptions
Pin Descriptions
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
4.3.6.1.
4.3.7.
4.3.8.
4.3.9.
4.3.10.
4.3.11.
4.3.12.
4.3.13.
4.3.14.
4.4.
Power Supply Pins
Analog Reference Pins
DC/DC Converters and Battery Voltage Supervision
Oscillator Pins and Clocking
Control Lines
Parallel Interface Lines
PIO Handshake Lines
Serial Input Interface (SDI)
Serial Input Interface B (SDIB)
Serial Output Interface (SDO)
S/PDIF Input Interface
S/PDIF Output Interface
Analog Input Interfaces
Analog Output Interfaces
Miscellaneous
Pin Configuration
4.5.
Internal Pin Circuits
4.5.1.
4.6.
Reset Pin Configuration for MAS 3529F and MAS 3539F
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Digital Characteristics
4.6.1.
4.6.1.1.
4.6.2.
4.6.2.1.
4.6.2.2.
4.6.2.3.
4.6.2.4.
4.6.2.5.
4.6.2.6.
4.6.2.7.
2
I C Characteristics
2
Serial (I S) Input Interface Characteristics (SDI, SDIB)
Serial Output Interface Characteristics (SDO)
S/PDIF Input Characteristics
S/PDIF Output Characteristics
PIO as Parallel Input Interface: DMA Mode
PIO as Parallel Input Interface:
Program Download Mode
80
81
84
86
4.6.2.8.
4.6.3.
4.6.4.
4.6.5.
PIO as Parallel Output Interface
Analog Characteristics
DC/DC Converter Characteristics
Typical Performance Characteristics
89
89
90
5.
Application
5.1.
5.2.
Typical Application in a Portable Player
Recommended DC/DC Converter Application Circuit
92
6.
Data Sheet History
4
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
MPEG Layer 2/3, AAC Audio Decoder,
G.729 Annex A Codec
In MPEG 1 (ISO 11172-3), three hierarchical layers of
compression have been standardized. The most
sophisticated and complex, layer 3, allows compres-
sion rates of approximately 12:1 for mono and stereo
signals while still maintaining CD audio quality. Layer 2
(widely used, e.g., in DVD) achieves a compression of
8:1 without significant losses in audio quality.
Release Note: Revision bars indicate significant
changes to the previous edition. This data sheet
applies to the MAS 35x9F version B4.
1. Introduction
The MAS 35x9F supports the “Advanced Audio Cod-
ing” (AAC) that is defined as a part of MPEG 2. AAC
provides compression rates up to 16:1. It defines sev-
eral profiles for different applications. This IC decodes
the “low complexity profile” that is especially optimized
for portable applications.
The MAS 35x9F is a single-chip, low-power MPEG
layer 2/3 and MPEG2-AAC audio stereo decoder. It
also contains the G.729 Annex A speech compression
and decompression technology for use in memory-
based or broadcast applications. Additional functional-
ity is achievable via download software (e.g., CELP
voice decoder, Micronas SC4 (ADPCM) encoder/
decoder).
The MAS 35x9F also implements a voice encoder and
decoder that is compliant to the ITU Standard G.729
Annex A.
The MAS 35x9F decoding block accepts compressed
digital data streams as serial bit streams or in parallel
format, and provides serial PCM and S/PDIF output of
decompressed audio. In addition to the signal process-
ing function, the IC incorporates a high-performance
stereo D/A converter, headphone amplifiers, a stereo
A/D converter, a microphone amplifier, and two DC/DC
converters.
SC4 is a proprietary Micronas speech codec technol-
ogy that can be downloaded to the MAS 35x9F, to
allow recording and playing back speech at various
sampling rates.
Thus, the MAS 35x9F provides a true “all-in-one”
solution that is ideally suited for highly optimized mem-
ory-based portable music players with integrated
speech recording and playback function.
Micronas
June 30, 2004; 6251-505-1DS
5
MAS 35x9F
DATA SHEET
1.1. Features
Hardware Features
– Two independent embedded DC/DC converters,
(e.g., for DSP and flash RAM supply)
Firmware
– MPEG 1/2 layer 2 and layer 3 decoder
– Low DC/DC converter start-up voltage (0.9 V)
– DC converter efficiency up to 95%
– Battery voltage monitor
– Extension to MPEG 2 layer 3 for low sampling rates
(“MPEG 2.5”)
– Extraction of MPEG Ancillary Data
– Low supply voltage down to 2.2 V
– MPEG 2 AAC decoder (low-complexity profile)
– Low power dissipation, e.g., 87 mW
– Micronas G.729 Annex A speech compression and
decompression
(128kBit/s, 44.1 kHz, Headphone playback)
– High-performance RISC DSP core
– On-chip crystal oscillator
– Master or slave clock operation
– Adaptive bit rates (bit rate switching)
– Hardware power management and power-off func-
tions
– Intelligent power management (processor clock is
dependent on sampling frequencies)
– Microphone amplifier
– SDMI-compliant security technology
– Stereo channel mixer
– Stereo A/D converter for FM/AM-radio and speech
input
– Bass, treble, and loudness function
– Micronas Bass (MB)
– CD quality stereo D/A converter
– Headphone amplifier
– Automatic Volume Control (AVC)
– Noise and power-optimized volume
– External clock or crystal frequency of 13...28 MHz
– Standby current < 10 µA
Interfaces
– Two serial asynchronous interfaces for bit streams
and uncompressed digital audio
– Parallel handshake bit stream input
2
– Serial audio output via I S and related formats
– S/PDIF data input and output
2
– Controlling via I C interface
1.2. Features of the MAS 35x9F Family
Feature
3509
X
3519
X
3529
3539
3549 3559
Layer 3 Decoder
G.729 Encoder/Decoder
AAC Decoder
X
X
X
X
X
X
X
X
6
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
1.3. Application Overview
The following block diagram shows an example appli-
cation for the MAS 35x9F in a portable audio player
device. Besides a simple controller and the external
flash memories, all required components are inte-
grated in the MAS 35x9F. The MAS 35x9F supports
both speech and radio quality audio encoding, as well
as compressed-audio decoding tasks.
Fig. 1–1 depicts a portable power-optimized audio
application. The two embedded DC/DC converters of
the MAS 35x9F generate optimum power supply volt-
ages for the DSP core and also for state-of-the art
flash memories that typically require 2.7 to 3.3 V sup-
ply. The performance of the DC/DC converters
reaches efficiencies of up to 95%.
Portable Digital Music Player
MAS 35x9F
optional
line in
Audio
baseband
features
D/A
A/D
DSP Core
MP3
AAC
G.729
Microphone
amplifier
Headphone
Headphone
amplifier
Volume
Optional
SC4
optional
digital in
Downloads
digital out
S/PDIF and serial
S/PDIF
or
serial
Crystal
Osc./PLL
Battery
Voltage
Monitor
2
I C
DC/DC1
DC/DC2
System clock
e.g. 2.2 V e.g. 3.0 V
e.g. 1.0 V
2
I C
Display
µC
Keyboard
PC Connector
Fig. 1–1: Example of an application for the MAS 35x9F in a portable audio player device
Micronas
June 30, 2004; 6251-505-1DS
7
MAS 35x9F
DATA SHEET
2. Functional Description
2.1. Overview
2.2. Architecture of the MAS 35x9F
The hardware of the MAS 35x9F consists of a high-
performance RISC Digital Signal Processor (DSP),
and appropriate interfaces. A hardware overview of the
IC is shown in Fig. 2–1.
The MAS 35x9F is intended for use in portable con-
sumer audio applications. It receives parallel or serial
data streams and decodes MPEG Layer 2 and 3
(including the low sampling frequency extensions) and
MPEG 2 AAC. A low bit-rate speech codec, compliant
to the ITU Standard G.729 Annex A, is integrated.
Additional downloadable software modules (SDMI,
other audio/speech encoders/decoders) are available
on request.
2.3. DSP Core
The internal processor is a dedicated DSP for
advanced audio applications.
Mic. Input
(incl. Bias)
Audio Codec
1
2
2
Audio
2
Output
Audio
Proc.
Line Input
A/D
MIX
D/A
DSP Core
Serial
S/PDIF Input 1
S/PDIF Input 2
ALU
MAC
Audio
(I2S, SDO)
Accumulators
ROM
Serial Audio
(I2S, SDI)
S/PDIF
Output
Serial Audio
(stream, SDIB)
Control
V
BAT
Volt.
Mon.
2
I C
DCCF
DCFR
DSP
2
D0
D1
I C
control
Interface
Codec
Registers
V1
V2
Div.
Parallel
I/O Bus
(PIO)
Div.
CLKO
Xtal
18.432 MHz
PLL
Synth.
Osc.
Scaler
÷2
Synthesizer
Clock
Fig. 2–1: The MAS 35x9F architecture
8
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
2.3.1. RAM and Registers
selected, the Layer 2, Layer 3 or AAC bit stream is rec-
ognized and decoded automatically.
The DSP core has access to two RAM banks denoted
D0 and D1. All RAM addresses can be accessed in a
20-bit or a 16-bit mode via I C bus. For fast access of
To add/remove MPEG layers while running in MPEG
decoding mode (e.g. Layer 2, Layer 3 (0x0c) to
Layer 2, Layer 3, AAC (0x1c)), the application selec-
tion has to be reset before writing the new value.
2
internal DSP states the processor core has an address
space of 256 data registers which also can be
2
accessed via I C bus. For more details, please refer to
Section 3.3. on page 27.
For general control purposes, the operation system
provides a set of I C instructions that give access to
2
internal DSP registers and memory areas.
2.3.2. Firmware and Software
An auxiliary digital volume control and mixer matrix is
applied to the digital stereo audio data. This matrix is
capable of performing the balance control and a sim-
ple kind of stereo basewidth enhancement. All four
factors LL, LR, RL, and RR are adjustable, please
refer to Fig. 3–3 on page 44.
2.3.2.1. Internal Program ROM and Firmware,
MPEG-Decoding
The firmware implemented in the program ROM of the
MAS 35x9F provides MPEG 1/2 Layer 2, MPEG 1/2/
2.5 Layer 3 and MPEG 2 AAC-decoding as well as a
G.729 encoder and decoder.
2.3.2.2. Program Download Feature
The DSP operating system starts the firmware in the
“Application Selection Mode”. By setting the appropri-
ate bit in the Application Select memory cell (see
Table 3–8 on page 32), the MPEG audio decoder or
the G.729 Codec can be activated.
The standard functions of the MAS 35x9F can be
extended or substituted by downloading up to
4 kWords (1 Word = 20 bits) of program code and
additionally up to 4 kWords of coefficients into the
internal RAM.
The MPEG decoder provides an automatic standard
detection mode. If all MPEG audio decoders are
SDI
PIO
Encoder
Audio
Proc.
LINE IN
MIC IN
OUT
A/D
MIX
D/A
Fig. 2–2: Encoder signal flow
PIO
DSP
Volume
Matrix
S/PDIF
SDO
Decoder
SDIB
Audio
Proc.
LINE IN
MIC IN
OUT
A/D
MIX
D/A
Fig. 2–3: Decoder signal flow
Micronas
June 30, 2004; 6251-505-1DS
9
MAS 35x9F
DATA SHEET
2.4. Audio Codec
2.4.2.2. Micronas Bass (MB)
A sophisticated set of audio converters and sound fea-
tures has been implemented to comply with various
kinds of operating environments that range up to high-
end equipment (see Fig. 2–4).
The Micronas Bass system (MB) was developed to
extend the frequency range of loudspeakers or head-
phones below the cutoff frequency of the speakers.
Apart from dynamically amplifying the low-frequency
bass signals, the MB exploits the psycho-acoustic phe-
nomenon of the ‘missing fundamental’. Adding har-
monics of the frequency components below the cutoff
frequency gives the impression of actually hearing the
low frequency fundamental, while at the same time
retaining the loudness of the original signal. Due to the
parametric implementation of the MB, it can be cus-
tomized to create different bass effects and adapted to
Mic-In
Mic-Amplifier incl. Bias
Mono
A
D
D
Line-In
A
various
loudspeaker
characteristics
(see
Section 3.4.4. and Table 3–16).
Mixer
Q-peak
Mono/Stereo
AVC
2.4.2.3. Automatic Volume Control (AVC)
Q-peak
In a collection of tracks from different sources fairly
often the average volume level varies. Especially in a
noisy listening environment the user must adjust the
volume to comfortably enjoy listening. The Automatic
Volume Correction (AVC) solves this problem by
equalizing the volume level.
Bass/Treble
Audio
Codec
Loudness
MB
Right invert
D
D
A
Volume
Balance
To prevent clipping, the AVC's gain decreases quickly
in dynamic boost conditions. To suppress oscillation
effects, the gain increases rather slowly for low level
inputs. The decay time is programmable by means of
the AVC register (see Table 3–16 on page 46).
Output
A
Fig. 2–4: Signal flow block diagram of Audio Codec
For input levels of -18 dBr to 0 dBr, the AVC maintains
a fixed output level of -9 dBr. Fig. 2–5 shows the AVC
output level versus its input level. For volume and
baseband registers set to 0 dB, a level of 0 dBr corre-
sponds to full scale input/output.
2.4.1. A/D Converter and Microphone Amplifier
A pair of A/D converters is provided for recording or
loop-through purposes. In addition, a microphone
amplifier including voltage supply function for an elec-
tret type microphone has been integrated.
AVC
output level
dBr
off
AVC
on
2.4.2. Baseband Processing
−9
The several baseband functions are applied to the dig-
ital audio signal immediately before D/A conversion.
−15
−21
2.4.2.1. Bass, Treble, and Loudness
input level
dBr
−30
−24
−18
−12
−6
0
+6
Standard baseband functions such as bass, treble,
and loudness are provided (refer to Table 3–16 for
details).
Fig. 2–5: Simplified AVC characteristics
2.4.2.4. Balance and Volume
To minimize quantization noise, the main volume con-
trol is automatically split into a digital and an analog
part. The volume range is −114...+12 dB with an addi-
tional mute position. A balance function is provided.
10
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
2.4.3. D/A Converters
2.5.1. DSP Clock
One pair of Micronas’ unique multibit sigma-delta D/A
converters is used to convert the audio data with high
linearity and a superior S/N. In order to attenuate high-
frequency noise caused by noise-shaping, internal
low-pass filters are included. They require additional
external capacitors between pins FILTx and OUTx
(see Section 5.1. on page 89).
The DSP clock has a separate divider. In order to
reduce the power consumption, it is set to the lowest
acceptable rate of the synthesizer clock which is capa-
ble to allow the processor core to perform all tasks.
2.5.2. Clock Output At CLKO
If the DSP or audio codec functions are enabled
2
2.4.4. Output Amplifiers
(bits[11] or [10] in the Control Register at I C subad-
dress 6A ), the reference clock at pin CLKO is
hex
The integrated output amplifiers are capable of directly
driving stereo headphones or loudspeakers of 16 to
32 Ω impedance via 22 Ω series resistors. If more out-
put power is required, the right output signal can be
inverted and a single loudspeaker can be connected
as a bridge between pins OUTL and OUTR. In this
case, the source should be set to mono for optimized
power.
derived from the synthesizer clock.
Dependent on the sample rate of the decoded signal a
scaler is applied which automatically divides the clock-
out by 1, 2, or 4, as shown in Table 2–1. An additional
division by 2 may be selected by setting bit[17] of the
OutClkConfig memory cell (see Table 3–8 on
page 32). The scaler can be disabled by setting bit[8]
of this cell.
The controlling at OutClkConfig is only possible as
long as the DSP is operational (bit[10] of the Control
Register). Settings remain valid if the DSP is disabled
by clearing bit[10].
MASF
DAC
OUTL
DAC
OUTR
R ≥ 32 Ω
Table 2–1: Settings of bits[8] and [17] in OutClkConfig
and resulting CLKO output frequencies
Fig. 2–6: Bridge operation mode
Output Frequency at CLKO/MHz
2.5. Clock Management
Synth.
Clock bit[8]=0, bit[17]=0
fs/kHz bit[8]=1
Scaler On
Scaler Plus
Extra Division
bit[8]=0, bit[17]=1
The MAS 35x9F is driven by a single crystal-controlled
clock with a frequency of 18.432 MHz. It is possible to
drive the MAS 35x9F with other reference clocks. In
this case, the nominal crystal frequency must be writ-
ten into memory location D0:348. The crystal clock
acts as a reference for the embedded synthesizer that
generates the internal clock.
48
24.576
24.576
12.288
512⋅fs
256⋅fs
44.1
32
22.5792
22.5792
11.2896
768⋅fs
512⋅fs
24.576 384⋅fs
12.288
6.144
5.6448
6.144
3.072
2.8224
3.072
24.576
24
12.288
For compressed audio data reception, the MAS 35x9F
may act either as the clock master (Demand Mode) or
as a slave (Broadcast Mode) as defined by bit[1] in
IOControlMain memory cell (see Table 3–8 on
page 32). In both modes, the output of the clock syn-
thesizer depends on the sample rate of the decoded
data stream as shown in Table 2–1.
256⋅fs
22.05
16
22.5792
24.576
11.2896
768⋅fs
512⋅fs
12.288 384⋅fs
12
6.144
256⋅fs
11.025 22.5792
24.576 768⋅fs
5.6448
In the BROADCAST MODE (PLL on), the incoming
audio data controls the clock synthesizer via a PLL.
8
6.144
384⋅fs
In the DEMAND MODE (PLL off) the MAS 35x9F acts
as the system master clock. The data transfer is trig-
gered by a demand signal at pin EOD.
Micronas
June 30, 2004; 6251-505-1DS
11
MAS 35x9F
DATA SHEET
2.6. Power Supply Concept
When the audio codec is enabled, the switching fre-
quency of the converters is synchronised to the audio
codec clock to avoid interferences into the audio band.
The actual switching frequency can be selected via the
I C-interface between 300 kHz and 580 kHz (for
details see DCFR Register in Table 3–3 on page 24).
The MAS 35x9F was designed for minimal power dis-
sipation. In order to optimize the battery management
in portable players, two DC/DC converters were imple-
mented to supply the complete portable audio player
with regulated voltages.
2
In the PFM operation mode, the switching frequency is
controlled by the converters themselves. It will be just
high enough to service the output load, thus resulting
in the best possible efficiency at low current loads. The
PFM mode does not need a clock signal from the crys-
tal oscillator. If both converters do not use the PWM-
mode, the crystal clock will be shut down as long it is
not needed by other internal blocks.
2.6.1. Power Supply Regions
The MAS 35x9F has five power supply regions.
The VDD/VSS pin pair supplies all digital parts includ-
ing the DSP core, the XVDD/XVSS pin pair is con-
nected to the digital signal pin output buffers, the
AVDD0/AVSS0 supply is for the analog output amplifi-
ers, AVDD1/AVSS1 for all other analog circuits like
clock oscillator, PLL circuits, system clock synthesizer
and A/D and D/A converters. The I C interface has an
own supply region via pin I2CVDD. Connecting this to
the microcontroller supply assures that the I C bus
always works as long as the microcontroller is alive so
that the operating modes can be selected.
The synchronous rectifier bypasses the external
Schottky diode to reduce losses caused by the diode
forward voltage providing up to 5% efficiency improve-
ment. By default, the P-channel synchronous rectifier
switch is turned on when the voltage at pin(s) DCSOn
exceeds the converter’s output voltage at pin(s)
VSENSn, and is turned off when the inductor current
drops below a threshold. If one or both converters are
disabled, the corresponding P-channel switch will be
turned on, connecting the battery voltage to the DC/
DC converters output voltage at pin VSENSn. How-
ever, it is possible to individually disable both synchro-
nous rectifier switches by setting the corresponding
bits (bit[8] and [0] in DCCF-register).
2
2
Beside these regions, the DC/DC converters have
start-up circuits of their own which get their power via
pin VSENSx.
2.6.2. DC/DC Converters
If both DC/DC-converters are off, a high signal may be
applied at pin DCEN. This will start the converters in
their default mode (PWM with 3.0 V output voltage).
The PUP signal will change from low to high when
both converters have reached their nominal output
voltage and will return to low when both converters
output voltages have dropped 200 mV below their pro-
grammed output voltage. The signal at pin PUP can be
used to control the reset of an external microcontroller
(see Section 2.11.2. on page 18 for details on the start-
up procedure).
The MAS 35x9F has two embedded high-performance
step-up DC/DC converters with synchronous rectifiers
to supply both the DSP core itself and external circuitry
such as a controller or flash memory at two different
voltage levels. An overview is given in Fig. 2–7 on
page 13.
The DC/DC converters are designed to generate an
output voltage between 2.0 V and 3.5 V which can be
2
programmed separately for each converter via the I C
interface (see table 3.3). Both converters are of boot-
strapped type allowing to start up from a voltage down
to 0.9 V for use with a single battery or NiCd/NiMH cell.
The default output voltages are 3.0 V. Both converters
are enabled with a high level at pin DCEN and
If only DC/DC-converter 1 is used, the output of the
unused converter 2 (VSENS2) must be connected to
the output of converter 1 (VSENS1) to make the PUP
signal work properly. Also, if a DC/DC-converter is not
used (no inductor connected), the pin DCSO must be
left vacant.
2
enabled/disabled by the I C interface.
The MAS 35x9F DC/DC converters feature a constant-
frequency, low noise pulse width modulation (PWM)
mode and a low quiescent current, pulse frequency
modulation (PFM) mode for improved efficiencies at
low current loads. Both modes – PWM or PFM – can
2
be selected independently for each converter via I C
interface. The default mode is PWM.
In PWM mode the switching frequency of the power-
MOSFET-switches is derived from the crystal oscilla-
tor. Switching harmonics generated by constant fre-
quency operation are consistent and predictable.
12
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DATA SHEET
MAS 35x9F
2.6.3. Power Supply Configurations
If DC/DC converter 1 is used, it must supply the analog
circuits (pins AVDD0, AVDD1) of the MAS 35x9F.
One of the following supply configurations may be
used:
If only one DC/DC converter is required, DC/DC1 must
be used. Pin DCSO2 must be left vacant, pin VSENS2
should be connected to pin VSENS1.
– Power-optimized solution (recommended opera-
tion). DC/DC 1 (e.g. 2.2 V) drives the MAS 35x9F
DSP and the audio circuitry, DC/DC 2 (e.g. 2.7 V)
supplies controller and flash (see Fig. 2–8 on
page 14)
If the DC/DC converters are not used, pin DCEN must
be connected to VSS, DCSOx must be left vacant.
– Volume-optimized solution. DC/DC 1 (e.g. 2.7 V)
supplies controller, flash and MAS 35x9F audio
parts, DC/DC 2 generates e.g. 2.2 V for the
MAS 35x9F DSP (see Fig. 2–9 on page 14).
– Minimized external components. DC/DC 1 operates
on, e.g., 2.7 V and feeds all components, DC/DC 2
remains off (see Fig. 2–10 on page 14).
– External power supply. All components are powered
by an external source, no DC/DC converter is used
(see Fig. 2–11 on page 14).
battery
voltage
monitor
VBAT
supply
I2CVDD
2
to I C interface
output 1
DCCF (76
)
L1
hex
DCSO2
DCSG2
15
8
22 µH
DC/DC
converter 2
D1
VSENS2
+
C1
330 µF
−
set voltage
voltage
monitor
PUP2
Start
DCEN
PUP
S
Vin
+
−
frequency
divider
R
+
system
or crystal
clock
−
factor
voltage
monitor
3
0
DCFR (77
)
hex
DC/DC
converter 1
DCCF (76
)
hex
7
0
VSS
Fig. 2–7: DC/DC converter overview. The DCEN input must be connected to pin I2CVDD via start-up push button.
Micronas
June 30, 2004; 6251-505-1DS
13
MAS 35x9F
DATA SHEET
VSENS1
VSENS1
Flash
DC/DC 1
Flash
DC/DC1
on
on
e.g. 2.7 V
I2CVDD
XVDD
I2CVDD
XVDD
2
2
µC
µC
I C
I C
DSP
DSP
VDD
VDD
VSENS2
VSENS2
DC/DC 2
DC/DC2
on
off
AVDD0/1
AVDD0/1
Analog
Parts
Analog
Parts
e.g. 2.7 V
e.g. 2.2 V
Fig. 2–8: Solution 1: Power-optimized
Fig. 2–10: Solution 3: Minimized components
VSENS1
VSENS1
Flash
DC/DC1
Flash
DC/DC1
on
off
I2CVDD
XVDD
I2CVDD
XVDD
2
2
I C
µC
µC
I C
DSP
DSP
VDD
VDD
VSENS2
VSENS2
DC/DC2
DC/DC2
on
off
External
Supply
AVDD0/1
AVDD0/1
Analog
Parts
Analog
Parts
e.g. 2.7 V
e.g. 2.7 V
e.g. 2.2 V
Fig. 2–9: Solution 2: Volume-optimized
Fig. 2–11: Solution 4: External power supply
14
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DATA SHEET
MAS 35x9F
2.7. Battery Voltage Supervision
2.8.4. Multiline Serial Audio Input (SDI, SDIB)
Independent of the DC/DC converters, a battery volt-
age supervision circuit (at pin VBAT) is provided. It can
be programmed to supervise one or two battery cells.
The voltage is measured by subsequently setting a
series of voltage thresholds and checking the respec-
There are two multiline serial audio input interfaces
(SDI, SDIB) each consisting of the three pins SI(B)C,
SI(B)I, and SI(B)D. The standard firmware only sup-
ports SDIB for bit-stream signals, while PCM-inputs
should be routed to SDI.
tive comparison result in register 77
.
hex
The interfaces can be configured as continuous bit-
stream or word-oriented inputs. For the MPEG bit
streams, the word strobe pin SIBI must always be con-
2.8. Interfaces
nected to V ; bits must be sent MSB first as created
by the encoder.
SS
2
The MAS 35x9F uses an I C control interface, a serial
input interface for MPEG bit streams, and digital audio
2
output interfaces for the decoded audio data (I S and
If the download software (refer to Download Software
Supplement I2SPDIF (6251-505-1PDS)) is used, the
S/PDIF). S/PDIF input is available after Software
download. A parallel I/O interface (PIO) may be used
for fast data exchange.
2
interface acts as an I S-type with SI(B)I as a word-
strobe for PCM data.
For the Demand Mode (see Section 2.5.), the signal
clock coming from the data source must be higher than
the nominal data transmission rate (e.g. 128 kbit/s).
Pin EOD is used to interrupt the data flow whenever
the input buffer of the MAS 35x9F is filled.
2
2.8.1. I C Control Interface
For controlling and program download purposes, a
standard I C slave interface is implemented. A
2
detailed description of all functions can be found in
Section 3.
For controlling details, please refer to Table 3–8 on
page 32.
2.8.2. S/PDIF Input Interface
2.8.5. Multiline Serial Output (SDO)
The S/PDIF interface receives a one-wire serial bus
signal. In addition to the signal input pin SPDI1/SPDI2,
a reference pin SPDIR is provided to support balanced
signal sources or twisted pair transmission lines.
The serial audio output interface of the MAS 35x9F is
a standard I S-like interface consisting of the data
2
lines SOD, the word strobe SOI and the clock signal
SOC. It is possible to choose between two standard
interface configurations (16-bit data words with word
strobe time offset or 32-bit data words with inverted
SOI signal).
The synchronization time on the input signal is
< 50 ms.
S/PDIF input is not supported for MPEG 1/2 Layer 2/3
and MPEG 2 AAC.
If the serial output generates 32 bits per audio sample,
only the first 20 bits will carry valid audio data. The
12 trailing bits are set to zero by default.
Micronas has developed a download software for flexi-
ble usage of the S/PDIF I/O and SDI/SDO interfaces. It
is described in Download Software Supplement
I2SPDIF (6251-505-1PDS).
2.8.6. Parallel Input/Output Interface (PIO)
The parallel interface of the MAS 35x9F consists of the
8 data lines PI12...PI19 (MSB) and the control lines
PCS, PR, PRTR, PRTW, and EOD. It can be used for
data exchange with an external memory, for fast pro-
gram download and for other special purposes as
defined by the DSP software.
2.8.3. S/PDIF Output
The S/PDIF output of the baseband audio signals is
implemented at pin SPDO since version B4.
The channel status bits can be set as described in
Table 3–8.
For MPEG data input, the PIO interface is activated by
setting bits[9] and [8] in D0:346 to 01. For the hand-
shake protocol, please refer to Section 4.6.2.8. on
page 80.
Micronas
June 30, 2004; 6251-505-1DS
15
MAS 35x9F
DATA SHEET
2.9. MPEG Synchronization Output
The signal at pin SYNC is set to ‘1’ after the internal
decoding for the MPEG header has been finished for
one frame. The rising edge of this signal can be used
as an interrupt input for the controller that triggers the
read out of the control information and ancillary data.
As soon as the MAS 35x9F has received the SYNC
reset command (see Section 4.6.2.6. on page 77), the
SYNC signal is cleared. If the controller does not issue
a reset command, the SYNC signal returns to ‘0’ as
soon as the decoding of the next MPEG frame is
started. MPEG status and ancillary data become
invalid until the frame is completely decoded and the
signal at pin SYNC rises again. The controller must
have finished reading all MPEG information before it
becomes invalid. The MPEG Layer 2/3 frame lengths
are given in Table 2–2. AAC has no fixed frame length.
t
= 24...72 ms
frame
Vh
Vl
t
read
Fig. 2–12: Schematic timing of the signal at pin SYNC.
The signal is cleared at t when the controller has
read
issued a Clear SYNC Signal command (see
Section 4.6.2.6. on page 77). If no command is
issued, the signal returns to ‘0’ just before the
decoding of the next MPEG frame.
Table 2–2: Frame length in MPEG Layer 2/3
f /kHz
Frame Length
Layer 2
Frame Length
Layer 3
s
48
24 ms
24 ms
44.1
32
26.12 ms
36 ms
26.12 ms
36 ms
24
24 ms
24 ms
22.05
16
26.12 ms
36 ms
26.12 ms
36 ms
12
not available
not available
not available
48 ms
11.025
8
52.24 ms
72 ms
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June 30, 2004; 6251-505-1DS
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DATA SHEET
MAS 35x9F
2.10.MP3 Block Input Mode
Table 2–3: MP3 bit rate vs. number of interrupts
A new so-called MP3 block input mode is now avail-
able which improves the input timing behavior of the
MAS 35x9F MPEG 1/2/2.5 Layer 3 decoder. The fol-
lowing sections provide a detailed description of this
new mode.
Bit Rate
[kbit/s]
Number of Interrupts
[1/s]
20
16
14
12
10
8
320
256
224
192
160
128
112
96
2.10.1.Functional Description of the MP3 Block
Input Mode
In MP3 block input, the MAS 35x9F generates a
demand for new input data each time one of its two
input buffers becomes available. The controller then
has to send one block of input data via the serial inter-
face SDIB. The block size is 2048 byte. The demand is
signalized via a pulse on the EOD pin.
7
Fig. 2–13 shows that the number of interrupts per sec-
ond does not depend on the data rate at the serial
interface. The maximum input data bit clock rate sup-
ported by the MAS 35x9F for all MPEG audio sampling
rates is 1.4 MHz.
6
80
5
64
4
Table 2–3 shows the average number of interrupts per
second for several typical MP3 bit rates.
The time period between two interrupts may vary
slightly even for fixed bit rate input streams due to the
MP3 specific bit reservoir.
Interrupt
Interrupt
a) SIC
b) SIC
Data blocks in a) and b) contain the same number of bytes.
t
Data block a) is sent with a lower data rate than data block b).
Fig. 2–13: Data Block Timing Diagram
Micronas
June 30, 2004; 6251-505-1DS
17
MAS 35x9F
DATA SHEET
2.10.2.Setup
2.11.Default Operation
Table 3–10 on page 39 lists the new bits, UIC cells,
and registers to setup the MP3 block input mode.
This sections refers to the standard operation mode
“power-optimized solution” (see Section 2.6.3.).
2.10.2.1.Resync Timeout
2.11.1. Stand-by Functions
In case the MP3 decoder loses the synchronization
(e.g. due to corrupted input data), the output is softly
muted and a resync loop is entered where the
MAS 35x9F can be accessed via I C. The loop is left
and the re-synchronization procedure continues in any
of the following cases:
After applying the battery voltage, the system will
remain stand-by, as long as the DCEN pin level is kept
low. Due to the low stand-by current of CMOS circuits,
the battery may remain connected to DCSOn/VSENSn
at all times.
2
– the last input data block is fully sent,
2.11.2.Power-Up of the DC/DC Converters
and Reset
– the Validate bit of IOControlMain is set
(D0:346, bit[0]),
The battery voltage must be applied to pin DCSOn via
the 22 µH inductor and, furthermore, to the sense pin
VSENSn via a Schottky diode (see Fig. 2–7 on
page 13).
– the timeout is reached (ResyncTimeout in
Table 3–10), the end bit is set (this bit will be reset
by the MAS 35x9F).
For start-up, the pin DCEN must be connected via an
external “start” push button to the I2CVDD supply,
which is equivalent to the battery supply voltage
(> 0.9 V) at start-up.
2.10.2.2.Detailed Setup
After the MPEG audio decoder application has been
selected, the following settings enable the MP3 block
decoding process.
The supply at DCEN must be applied until the DC/DC
converters have started up (signal at pin PUP) and
then removed for normal operation.
Play MP3
1. Write 0x318 into SerialInConfig.
2. Write IOControlMain with bit[2] and bit[0] equal one.
As soon as the output voltage at VSENSn reaches the
default voltage monitor reset level of 3.0 V, the respec-
tive internal PUPn bit will be set. When both PUPn bits
are set, the signal at pin PUP will go high and can be
used to start and reset the microcontroller.
3. Write IOControlMain with bit[2] equals zero and
bit[0] equals one.
4. Write 0x0 into ResyncTimeout.
2
Before transmitting any I C commands, the controller
5. Write 0x0 into SoftMute.
must issue a power-on reset to pin POR. The separate
supply pin I2CVDD ensures that the I C interface
works independently from the DSP or the audio codec.
Now the desired supply voltage can be programmed at
2
6. Enable EODQ interrupt for sending data in controller.
7. Set StartBit in MP3BlockConfig.
2
8. Send data block of 2048 byte when EODQ goes
high.
I C subaddress 76
.
hex
Stop/Pause MP3
1. Write 0x1 into SoftMute.
2. Clear start bit in MP3BlockConfig.
18
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Micronas
DATA SHEET
MAS 35x9F
2.11.2.1.Important Advice for Turn-on and Operat-
ing Voltage
Before the 2.2 V are programmed at the DCDC con-
verter, DSP+Codec must be enabled.
Operating and Turn-Off is possible down to 2.2 V.
The sequence should be similar to the following:
1. Start DCDC
2. Set DCDC to 2.5 V
Turn on DSP+Codec
Write App-Select memory cell
Read App-Running Mem cell
If okay: Set DCDC to 2.2 V
Set other mem cells
Set other codec registers
.....
3. Demute...send data
4. Mute...stop data.....loop "3)" "4)"...
5. Turn off DSP+Codec
goto "2)"
etc.....
The signal at pin PUP will return to low only when both
2
PUPn flags (I C subaddress 76 ) have returned to
hex
zero. Care must be taken when changing both DC/DC
output voltages to higher values. In this case, both out-
put voltages are momentarily insufficient to keep the
PUPn flags up; the resulting dip in the signal at the
PUP pin may, in turn, reset the microcontroller. To
avoid this condition, only one DC/DC output voltage
should be changed at a time. Before modifying the
second voltage, the microcontroller must wait for the
PUPn flag of the first voltage to be set again.
If only DC/DC converter 1 is used, the reference volt-
age of the second, unused converter should be set to
a lower value than that of converter 1, and its pin
VSENS2 should be connected to VDD.
The operating mode pulse width modulation, or pulse
2
frequency modulation, are controlled at I C subad-
2
dress 76 , the operating frequency at I C subad-
hex
dress 77
.
hex
Micronas
June 30, 2004; 6251-505-1DS
19
MAS 35x9F
DATA SHEET
2.11.3. Reset Signal Specification
After power-up, a reset signal should be applied to the pin POR by the microcontroller as follows:
V
2.2 V min.
DD
V
DD
POR 2.2 V min.
POR
see Note 1
2
I C access works without
0.5 µs min. delay
additional delay from this point
time
Fig. 2–14: Reset signal at pin POR
Note: The slew rate of POR should be as high as pos-
sible, but must be glitch-free in any case.
Slew rate typ.: 1 µs for 10% to 90% level transition,
Slew rate max.: 20 µs for 10% to 90% level transition.
20
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DATA SHEET
MAS 35x9F
2.11.4.Control of the Signal Processing
2.11.5.Start-up of the Audio Codec
Before starting the DSP, the controller should check
Before enabling the audio codec, the controller should
for a sufficient voltage supply (respective flag PUPn at
check for a sufficient voltage supply (respective flag
2
2
I C subaddress 76 ). The DSP is enabled by setting
PUPn at I C subaddress 76 ).
hex
hex
2
the appropriate bit in the Control register (I C subad-
dress 6A ). The nominal frequency of the crystal
The audio codec is enabled by setting the appropriate
hex
2
oscillator must be written into D0:348. After an initial-
ization phase of 5 ms, the DSP data registers can be
bit at the Control register (I C subaddress 6A ). After
hex
an initialization phase of 5 ms, the DSP data registers
2
2
accessed via I C.
can be accessed via I C. The A/D and the D/A con-
verters must be switched on explicitly (register
2
Input and output control is performed via memory loca-
tion D0:346 and D0:347. The serial input interface
SDIB is the default. The decoded audio can be routed
to either the S/PDIF, the SDO and the analog outputs.
The output clock signal at pin CLKO is defined in
D0:349.
00 00
at I C subaddress 6C ). The D/A convert-
hex
hex
ers may either accept data from the A/D converters or
the output of the DSP, or a mix of both (register
1)
2
00 06
and 00 07
at I C subaddress 6C ).
hex
hex
hex
Finally, an appropriate output volume (register
2
00 10
at I C subaddress 6C ) must be selected.
hex
hex
All changes in the D0 memory cells become effective
synchronously upon setting the LSB of Main I/O Con-
trol (see Table 3–8 on page 32). Therefore, this cell
should always be written last.
2.11.6.Power-Down
All analog outputs should be muted and the A/D and
the D/A converters must be switched off (register
2
The digital volume control (see Table 3–8 on page 32)
is applied to the output signal of the DSP. The
decoded audio data will be available at the SPDO out-
put interface in the next version.
00 10
and 00 00
at I C subaddress 6C ). The
hex
hex
hex
DSP and the audio codec must be disabled (clear
DSP_EN and CODEC_EN bits in the Control register,
I C subaddress 6A ). By clearing both DC/DC
enable flags in the Control register (I C subaddress
2
hex
2
The DSP does not have to be started if its functions
are not required, e.g., for routing audio through the
codec part of the IC via the A/D and the D/A convert-
ers.
6A ), the microcontroller can power down the com-
plete system.
hex
1) mixer available in version A2 and later; in version
A1, please use selector 00 0F
.
hex
Micronas
June 30, 2004; 6251-505-1DS
21
MAS 35x9F
DATA SHEET
3. Controlling
nibble.
– Data values in nibbles are always shown in hexa-
decimal notation.
2
3.1. I C Interface
Controlling between the MAS 35x9F and the external
controller is done via an I C slave interface.
– A hexadecimal 20-bit number d is written, e.g. as
2
d = 17C63 , its five nibbles are
hex
d0 = 3 , d1 = 6 , d2 = C , d3 = 7 , and
hex
hex
hex
hex
hex
3.1.1. Device Address
d4 = 1
.
– Variables used in the following descriptions:
The device addresses are 3C/3E
(device write
hex
I²C address:
“DW”) and 3D/3F
(device read, “DR”) as shown in
hex
2
DW3C/3E I C device write
hex
Table 3–1. The device address pair 3C/3D
the DVS pin is connected to VSS, the device address
applies if
hex
2
DR3D/3F I C device read
hex
DSP core:
pair 3E/3F
I2CVDD.
applies if the DVS pin is connected to
hex
data_write68 DSP data write
hex
data_read69 DSP data read
hex
Codec:
2
Table 3–1: I C device address
codec_write6C codec write
hex
codec_read6D codec read
hex
A7
A6
A5
A4
A3
A2
A1
W/R
– Bus signals
S
P
A
N
Start
Stop
0
0
1
1
1
1
DVS
0/1
ACK = Acknowledge
NAK = Not acknowledge
2
I C clock synchronization is used to slow down the
interface if required.
2
W Wait = I C clock line is held low
while the MAS 35x9F is processing
the current I C command
2
2
3.1.2. I C Registers and Subaddresses
– Symbols in the telegram examples
The interface uses one level of subaddresses. The
MAS 35x9F interface has 7 subaddresses allocated
for the corresponding I C registers. The registers can
be divided into three categories as shown in Table 3–
2.
<
>
Start Condition
Stop
2
dd
xx
data bytes
ignore
All telegram numbers are hexadecimal, data origi-
nating from the MAS 35x9F are represented as gray
letters.
Example:
The address 6A
and task select. The other addresses are used for data
transfer from/to the MAS 35x9F.
is used for basic control, i.e. reset
hex
<DW 68 dd dd >
write data to DSP
<DW 69 <DR dd dd > read data from DSP
2
The I C registers of the MAS 35x9F are 16 bits wide,
2
the MSB is denoted as bit[15]. Transmissions via I C
bus have to take place in 16-bit words (two byte trans-
fers, MSB sent first); thus, for each register access,
2
Fig. 3–1 shows I C bus protocols for write and read
operations of the interface; the read operations require
an extra start condition and repetition of the chip
address with the device read command (DR). Fields
with signals/data originating from the MAS 35x9F are
marked by a gray background.
2
two 8-bit data words must be sent/received via I C
bus.
3.1.3. Naming Convention
The description of the various controller commands
uses the following formalism:
Note: In some cases the data reading process must
be concluded by a NAK condition.
– Abbreviations used in the following descriptions:
a
d
n
o
r
address
data value
count value
offset value
register number
don’t care
3.2. Direct Configuration Registers
x
The task selection of the DSP and the DC/DC convert-
ers are controlled in the direct configuration registers
CONTROL, DCCF, and DCFR.
– Memory addresses, like D1:89f, are always in hexa-
decimal notation.
– A data value is split into 4-bit nibbles which are
numbered beginning with 0 for the least significant
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DATA SHEET
MAS 35x9F
2
Table 3–2: I C subaddresses
3.2.1. Write Direct Configuration Registers
2
S
DW
W
A
subaddr.
A
d3,d2
A
d1,d0
A
P
Sub-
I C-
Function
address Register
(hex) Name
The write protocol for the direct configuration registers
only consists of device address, subaddress and one
16-bit data word.
Direct Configuration
6A
76
77
CONTROL
DCCF
Controller writes to
MAS 35x9F CONTROL
register
3.2.2. Read Direct Configuration Register
S
DW
W
A
subaddr.
A
S
DR
W
A
Controller writes to first
DC/DC configuration reg-
ister
d3,d2
A
d1,d0
N
P
To check the PUP1 and PUP2 power-up flags, it is
necessary to read back the content of the direct config-
uration registers.
DCFR
Controller writes to
second DC/DC configura-
tion register
DSP Core Access
68
data_write
Controller writes to
MAS 35x9F DSP
69
data_read
Controller reads from
MAS 35x9F DSP
Codec Access
6C
codec_write Controller writes to
MAS 35x9F codec regis-
ter
6D
codec_read Controller reads from
MAS 35x9F codec regis-
ter
Example: I2C write access
DW
S
W
A
A
subaddress
subaddress
A
A
high byte data
A
low byte data
W
N
A
P
P
2
Example: I C read access
S
DW
W
S
DR
W
A
high byte data
A
low byte data
W
W = Wait
A = Acknowledge (Ack)
N = Not Acknowledge (NAK)
S = Start
SDA
SCL
1
0
P
S
P = Stop
2
Fig. 3–1: Example of an I C bus protocol for the MAS 35x9F (MSB first; data must be stable while clock is high)
Micronas
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MAS 35x9F
DATA SHEET
Table 3–3: Direct configuration registers
2
I C Sub-
address
(hex)
Function
Name
6A
Control Register (reset value = 3000
)
CONTROL
hex
bit[15:14]
Analog supply voltage range
Code
00
01
AGNDC
1.1 V
1.3 V
recommended for voltage range of AVDD
2.0 ... 2.4 V (reset)
2.4 ... 3.0 V
10
1.6 V
3.0 ... 3.6 V
11
reserved
reserved
Higher voltage ranges permit higher output levels and thus a better signal-to-
noise ratio.
bit[13]
bit[12]
Enable DC/DC 2 (reset=1)
Enable DC/DC 1 (reset=1)
Both DC/DC converters are switched on by default with DCEN = high (1).
2)
bit[11]
bit[10]
Enable and reset audio codec
Enable and reset DSP core
2)
For normal operation (MPEG-decoding and D/A conversion), both, the DSP
core and the audio codec have to be enabled after the power-up procedure.
The DSP can be left off if an audio signal is routed from the analog inputs to
the analog outputs (set bit[15] in codec register 00 0F ). The audio codec
hex
can be left off if the DSP uses digital inputs and outputs only.
bit[9]
bit[8]
Reset codec
Reset DSP core
bit[7]
Enable crystal input clock divider of 1.5
(extended range up to 28 MHz)
1)
bit[6:0]
Reserved, must be set to zero
1)
refer to Section 4.6.3. on page 81
refer to Section 2.11.2.1.
2)
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DATA SHEET
MAS 35x9F
Table 3–3: Direct configuration registers, continued
2
I C Sub-
address
(hex)
Function
Name
76
DCCF Register (reset = 5050
)
DCCF
hex
DC/DC Converter 2
bit[15]
PUP2: Voltage monitor 2 flag (readback)
2)
bit[14:11]
Converter 2 output voltage with respect to VREF
Code
Nominal
set level
reset level
output volt. of PUP2
of PUP2
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V (reset)
2.7 V
2.6 V
2.5 V
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
3.5 V
3.4 V
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
3.4 V
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2.4 V
2.3 V
2.2 V
2.1 V
1)
0100
0011
0010
1)
1)
2.0 V
bit[10]
Mode
1
0
pulse frequency modulation (PFM)
pulse width modulation (PWM) (reset)
bit[9:8]
Reserved, must be set to zero
The DC/DC converters are up-converters only. Thus, if the battery voltage is
higher than the selected nominal voltage, the output voltage will exceed the
nominal voltage.
DC/DC Converter 1
bit[7]
PUP1: Voltage monitor 1 flag (readback)
bit[6:3]
Converter 1 output voltage at VSENS1 with respect to VREF
(see bits 14 to 11)
2)
bit[2]
Mode
1
0
pulse frequency modulation (PFM)
pulse width modulation (PWM) (reset)
bit[1:0]
Reserved, must be set to zero
Note, that the reference voltage for DC/DC converter 1 is derived from the
main reference source supplied via pin AVDD1. Therefore, if this DC/DC con-
verter is used, its output must be connected to the analog supply.
The DC/DC converters are up-converters only. Thus, if the battery voltage is
higher than the selected nominal voltage, the output voltage will exceed the
nominal voltage.
1)
refer to Section 4.3.3. on page 60
refer to Section 2.11.2.1.
2)
Micronas
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MAS 35x9F
DATA SHEET
Table 3–3: Direct configuration registers, continued
2
I C Sub-
address
(hex)
Function
Name
77
DCFR Register (reset = 00
)
DCFR
hex
Battery Voltage Monitor
bit[15]
Comparison result (readback)
1
0
input voltage at pin VBAT above defined threshold
input voltage at pin VBAT below defined threshold
bit[14]
Number of battery cells
0
1
1 cell (range 0.8...1.5 V) (reset)
2 cells (range 1.6...3.0 V)
bit[13:10]
Voltage threshold level
1 cell
2 cells
3.0 V
2.9 V
1111
1110
...
1.5
1.45
0010
0001
0000
0.85
0.8
1.7 V
1.6 V
battery voltage supervision off (reset)
bit[9:8]
Reserved, must be set to 0
The result is stable 1 ms after enabling. The setup time for switching between
two thresholds is negligibly small.
For power management reasons, the battery voltage monitor should be
switched off by setting bit[13:10] to zero when the measurement is completed.
DC/DC Converter Frequency Control (PWM)
bit[7:4]
bit[3:0]
Reserved, must be set to 0
Frequency of DC/DC converter
Reference: 24.576
22.5792
18.432 MHz
297.3 kHz
307.2 kHz
317.8 kHz
329.1 kHz
341.3 kHz
354.5 kHz
368.6 kHz
384.0 kHz (reset)
400.7 kHz
418.9 kHz
438.9 kHz
460.8 kHz
485.1 kHz
512.0 kHz
542.1 kHz
576.0 kHz
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
315.1
323.4
332.1
341.3
351.1
361.4
372.4
384.0
396.4
409.6
423.7
438.9
455.1
472.6
491.5
512.0
289.5
297.1
305.1
313.6
322.6
332.0
342.1
352.8
364.2
376.3
389.3
403.2
418.1
434.2
451.6
470.4
2
If the audio codec is not enabled (bit[11] of the CONTROL register at I C-sub-
address 6A is zero), the clock for the DC/DC converters is directly derived
hex
from the crystal frequency (nominal 18.432 MHz). Otherwise, the synthesizer
clock is used as the reference (please refer to the respective column in
Table 2–1 on page 11).
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DATA SHEET
MAS 35x9F
3.3. DSP Core
S
DW
W
A
data_write
A
Code,...
A
...,...
A
...
3.3.1. Access Protocol
Fig. 3–2: General core access protocol
2
The I C data register is used to communicate with the
internal firmware of the MAS 35x9F. It is readable
(subaddress “data_read”) and writable (subaddress
“data_write”) and also has a length of 16 bits. The data
transfer is done with the most significant bit (m) first.
Table 3–5 gives an overview over the different com-
mands which the DSP Core receives via the I C data
register. The “Code” is always the first data nibble
transmitted after the “data_write” subaddress byte. A
second auxiliary code nibble is used for the short
memory (16-bit) access commands.
2
Table 3–4: Data register bit assignment
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
2
The MAS 35x9F firmware scans the I C interface peri-
m
l
odically and checks for pending or new commands.
The commands are then executed by the DSP during
its normal operation without any loss or interruption of
the incoming data or outgoing audio data stream.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected at the locations marked with a “W” (= wait).
The theoretical worst case response time does not
exceed 4 ms. However, the typical response time is
less than 0.5 ms.
A special command language is used that allows the
controller to access the DSP registers and RAM cells
and thus monitor internal states, set the parameters for
the DSP firmware, control the hardware, and even pro-
vide a download of alternative software modules. The
DSP commands consist of a “Code” which is sent to
2
the I C data register together with additional parame-
ters.
2
Due to the 16-bit width of the I C data register, all
actions transmit telegrams with multiples of 16 data
bits.
Table 3–5: Basic controller command codes
Code Command
(hex)
Function
0...3
Run
Start execution of an internal program. Run with start address 0 means
freeze the operating system.
5
6
7
a
b
c
d
e
f
Read Ancillary Data
Fast Program Download
Read IC Version
The controller reads a block of MPEG Ancillary Data from the MAS 35x9F
The controller downloads custom software via the PIO interface
The controller reads the version information of the IC
The controller reads an internal register of the MAS 35x9F
The controller writes an internal register of the MAS 35x9F
The controller reads a block of the DSP memory
Read from Register
Write to Register
Read D0 Memory
Read D1 Memory
Write D0 Memory
Write D1 Memory
The controller reads a block of the DSP memory
The controller writes a block of the DSP memory
The controller writes a block of the DSP memory
Micronas
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MAS 35x9F
DATA SHEET
3.3.2. Data Formats
The entry point of the default software will be accessed
automatically after a reset, thus issuing a Run or
Freeze command is only necessary for starting down-
loaded software or special program modules which are
not part of the standard set.
The internal data word size is 20 bits. All RAM-
addresses can be accessed in a 20-bit mode via I C
bus. Because of the 16-bit width of the I C data regis-
ter the full transfer of all 20 bits requires two 16-bit I C
2
2
2
words. Some commands only access the lower 16 bits
of a cell. For fast access of internal DSP states the
processor core also has an address space of 256 data
registers.
3.3.2.2. Read Register (Code A
)
hex
1) send command
S
DW
W
A
data_write
A
a,r1
A
r0,0
W
W
A
N
P
P
The internal data format is a 20 bit two’s complement
denoted “r”. If in some cases a fixed point notation “v”
is necessary. The conversion between the two forms
of notation is done as follows:
2) get register value
S
DW
x,x
W
A
A
data_read
A
A
S
DR
W
A
x,d4
W
d3,d2
A
d1,d0
r = v*524288.0+0.5; (−1.0 ≤ v < 1.0)
v = r/524288.0; (−524288 < r < 524287)
The MAS 35x9F has an address space of 256 DSP-
registers. Some of the registers (r = r1,r0 in the figure
above) are direct control inputs for various hardware
blocks, others control the internal program flow. In
Table 3–7, the registers of interest are described in
detail. In contrast to memory cells, registers cannot be
accessed as a block but must always be addressed
individually.
3.3.2.1. Run and Freeze (Codes 0
to 3
)
hex
hex
S
DW
W
A
data_write
A
a3,a2
A
a1,a0
W
A
P
The Run command causes the start of a program part
at address a = (a3,a2,a1,a0). Since nibble a3 is also
the command code (see Table 3–5), it is restricted to
values between 0 and 3. This command is used to
start alternate code or downloaded code from a RAM-
area that has been configured as program RAM.
Example:
Read the content of register C8
:
hex
<DW 68 ac 80>
<DW 69 <DR xx xd dd dd >
define register
and read
If the start address is 1000
≤ a < 3FFF
and the
hex
hex
3.3.2.3. Write Register (Code B
)
hex
respective RAM area has been configured as program
RAM (see Table 3–7 on page 31), the MAS 35x9F
continues execution with a custom program already
downloaded to this area.
S
DW
W
A
data_write
A
b,r1
A
A
r0,d4
d1,d0
W
W
A
A
d3,d2
P
Example 1: Start program execution at address
The controller writes the 20-bit value (d = d4,d3,d2,
d1,d0) into the MAS 35x9F register (r = r1,r0). A list of
registers needed for control purposes is given in Table
3–7.
345
:
hex
<DW 68 03 45>
Example 2: Start execution of a downloaded code at
Example: Writing the value 81234
into the register
hex
address 1000
:
hex
with the number AA
:
hex
<DW 68 10 00>
<DW 68 ba a8 12 34>
Freeze is a special run command with start address 0.
It suspends all normal program execution. The operat-
ing system will enter an idle loop so that all registers
and memory cells can be watched. This state is useful
for operations like downloading code or contents of
memory cells because the internal program cannot
overwrite these values. This freezing will be required if
alternative software is downloaded into the internal
RAM of the MAS 35x9F.
2
Freeze has the following I C protocol:
<DW 68 00 00>
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DATA SHEET
MAS 35x9F
3.3.2.4. Read Memory (Codes C
and D
)
hex
3.3.2.6. Write Memory
(Codes E and F
hex
)
hex
hex
The MAS 35x9F has 2 memory areas of 2048 words
denoted D0 and D1. The memory areas D0 and D1
The memory areas D0 and D1 can be written by using
the codes E and F , respectively.
can be written by using the codes C
respectively.
and D
,
hex
hex
hex
hex
S
DW
W
A
data_write
A
e,0
A
A
A
A
0,0
W
W
W
W
A
A
A
A
1) send command (Read D0)
n3,n2
a3,a2
d3,d2
n1,n0
a1,a0
d1,d0
S
DW
W
A
data_write
A
c,0
A
A
A
0,0
W
W
W
A
A
n3,n2
a3,a2
n1,n0
a1,a0
x,x
x,x
A
A
x,d4
W
A
A
P
....repeat for n data values....
2) get register value
x,d4
W
A
d3,d2
A
d1,d0
W
A
P
S
DW
x,x
W
A
A
data_read
A
A
S
DR
W
A
x,d4
W
d3,d2
A
d1,d0
W
W
A
N
With the Write D0/D1 Memory command n 20-bit
memory cells in D0 can be initialized with new data.
....repeat for n data values....
x,x
A
x,d4
W
A
d3,d2
A
d1,d0
P
Example: Write 80234
I C protocol:
to D1:456 has the following
hex
2
The Read D0 Memory command gives the controller
access to all 20 bits of the D0/D1 memory cells. The
telegram to read 3 words starting at location D1:100 is
<3a 68 f0 00
00 01
write D1 memory
1 word to write
start address
04 56
<DW 68 d0 00 00 03 01 00>
<DW 69 <DR xx xd dd dd
xx xd dd dd xx xd dd dd >
00 08
value = 80234
hex
02 34>
3.3.2.7. Short Write Memory
(Codes E4 and F4
3.3.2.5. Short Read Memory
)
hex
hex
(Codes C4
and D4
)
hex
hex
S
DW
W
A
data_write
A
A
A
A
e,4
A
A
A
A
0,0
W
W
W
W
A
A
A
A
Because most cells in the user interface are only 16
bits wide, it is faster and more convenient to access
the memory locations with a special 16-bit mode for
reading:
n3,n2
a3,a2
d3,d2
n1,n0
a1,a0
d1,d0
....repeat for n data values....
1) send command (e.g. Short Read D0)
A
d3,d2
A
d1,d0
W
A
P
S
DW
W
A
data_write
A
c,4
A
A
A
0,0
W
W
W
A
A
A
n3,n2
a3,a2
n1,n0
a1,a0
For faster access only the lower 16 bits of each mem-
ory cell are written. The 4 MSBs of the cell are cleared.
P
The command uses the same codes E
and F
for
2) get register value
hex
hex
D0/D1 as for the 20-bit command but followed by a 4
rather than a 0.
S
DW
W
A
data_read
A
S
DR
W
A
d3,d2
A
d1,d0
W
W
A
N
....repeat for n data values....
3.3.2.8. Clear SYNC Signal
d3,d2
A
d1,d0
P
(Code 5
)
hex
This command is similar to the normal 20 bit read com-
S
DW
W
A
data_write
A
5,0
A
0,0
W
A
P
mand and uses the same command code C
and
hex
D
for D0 and D1 memory, respectively, however it is
hex
followed by a 4
rather than a 0
.
After a successful decoding of an MPEG frame the sig-
nal at pin SYNC rises and thus generates an interrupt
event for the microcontroller. Issuing this command
lets the signal at pin SYNC return to ‘0’.
hex
hex
2
Example: Read 16 bits of D1:123 has the following I C
protocol:
<DW 68 d4 00
00 01
read 16 bits from D1
1 word to be read
start address
01 23
<DW 69 DR
dd dd >
start reading
and read
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MAS 35x9F
DATA SHEET
3.3.2.9. Default Read
– Issue a Run command to start program execution at
entry point of downloaded code
The Default Read command is the fastest way to get
information from the MAS 35x9F. Executing the
Default Read in a polling loop can be used to detect a
special state during decoding.
Example for Fast Program Download command:
Download 5 words starting at D0:800,
then download 4 words starting at D1:200:
<DW 68 00 00>
Freeze
S
DW
W
A
data_read
A
S
DR
W
A
A
d3,d2
d1,d0
W
N
P
<DW 68 b3 b0 03 18>Stop all internal transfers
<DW 68 b4 30 03 00>
The Default Read command immediately returns the
lower 16 bit content of a specific RAM location as
defined by the pointer D0:ffb. The pointer must be
loaded before the first Default Read action occurs. If
the MSB of the pointer is set, it points to a memory
location in D1 rather than to one in D0.
<DW 68 b4 b0 00 00>
<DW 68 b5 30 03 18>
<DW 68 b6 b0 00 00>
<DW 68 bb b0 03 18>
<DW 68 bc 30 03 00>
<DW 68 b0 60 00 00>
<DW 68 60 05
08 00>
initiate download of 5 words
start at address D0:800
Example: For watching D1:123 the pointer D0:ffb must
be loaded with 8123
:
hex
Now transfer 5 20-bit words via the parallel PIO-port:
<DW 68 e0 00
00 01
write to D0 memory
1 word to write
start address ffb
value = 8...
d4,d3 d2,d1 d0,d4 d3,d2 d1,d0
d4,d3 d2,d1 d0,d4 d3,d2 d1,d0
d4,d3 d2,d1 d0,x
0f fb
00 08
01 23>
...0123
hex
<DW 68 60 05
82 00>
initiate download of 4 words
start at address D1:200
Now the Default Read commands can be issued as
often as desired:
Now transfer 4 20-bit words via the parallel PIO-port:
<DW 69 <DR
Default Read command
16 bit content of the
address as defined by the
pointer
dd dd >
d4,d3 d2,d1 d0,d4 d3,d2 d1,d0
d4,d3 d2,d1 d0,d4 d3,d2 d1,d0
<DW 69 <DR dd dd > ... and do it again
<DW 68 b6 bc 00 00>switch the memory area
D0:800 ... D0:fff from
3.3.2.10.Fast Program Download (Code 6
)
hex
data to program usage
<DW 68 10 0a>
start program execution at
address D0:100a
S
DW
W
A
data_write
A
6,n2
A
A
n1,n0
a1,a0
W
A
a3,a2
W
A
P
The Fast Program Download command introduces a
data transfer via the parallel port. n = n2,n1,n0
denotes the number of 20-bit data words to be trans-
ferred, a = a3,a2,a1,a0 gives the start address. The
data must be organized in two times five nibbles to get
two words of 20-bit length. If the number n of 20-bit
data words is odd, the very last word has to be padded
with one additional nibble.
3.3.2.11.Serial Program Download
Program downloads may also be performed via the
2
I C-interface by using the Write D0/D1 Memory com-
mands. A similar command sequence as in the Fast
Program Download (Freeze, stop transfers...) applies.
The download must be initiated in the following order:
– Issue Freeze command
– Stop all DMA-transfers
– Issue Fast Program Download command
– Download code via PIO-interface
– Switch appropriate memory area to act as program
RAM (register ED
)
hex
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DATA SHEET
MAS 35x9F
3.3.2.12.Read IC Version (Code 7
)
hex
0 1
0
0 2
(hex)
Derivate (0..F)
1) send command
1
Version character (0 = “A”,.., F = “P”)
Version number (01..FF)
S
DW
W
A
data_write
A
A
7,0
A
0,0
W
A
P
P
2) get version information
0 2
S
DW
W
A
data_read
S
DR
W
A
n3,n2
d3,d2
A
A
n1,n0
d1,d0
W
W
A
N
3.3.3. List of DSP Registers
The PSelect_Shadow register in Table 3–7 is used to
switch four RAM areas from data to program usage
and thus enabling the DSP’s program counter to
access downloaded program code stored at these
locations. For normal operation (firmware in ROM),
this register must be kept to zero.
With this command the version of the IC is read in two
16 bit words. The first word n = n3,n2,n1,n0 contains
the IC’s major number (one nibble for each digit). The
second word (d = d3,d2,d1,d0) returns the version as
shown in Table 3–6.
Table 3–6: Second word of version information
Note: DSP registers not given in Table 3–7 must not
be written.
Bit
Nibble
d3
Content
15:12
11:8
IC family derivate
Coded character of order
3.3.4. List of DSP Memory Cells
d2
version (add 41
content of d2 to get ASCII)
to the
hex
Among the user interface control memory cells there
are some which have a global meaning and some
which control application specific parts of the DSP
core. In Table 3–8 and Table 3–9, this is reflected by
the key words All, MPEG, and G.729.
7:0
d1,d0
Digit of order version
Example:
Read the version information for MAS 35x9F, derivate
0, order version B2:
<DW 68 70 00
<DW 69 <DR
35 09
send version command
and read
MAS 3509F
derivate 0, version B2
(see Section 2.2. on page 8)
01 02 >
Table 3–7: Program Download registers
Address
(hex)
R/W Function
Mode
Default
(hex)
Name
6B
R/W Configuration of Variable RAM Areas
Download 0000
PSelect_Shadow
Affected RAM area
bit[19]
bit[18]
bit[17]
bit[16]
D0:800 ... D0:BFF
D0:C00 ... D0:FFF
D1:800 ... D1:BFF
D1:C00 ... D1:FFF
For details of program code download please refer to
Section 3.3.2.10. on page 30.
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DATA SHEET
3.3.4.1. Application Selection and
Application Running
3.3.4.2. Application Specific Control
The configuration of the MPEG Layer 2/3, AAC decod-
ing and the G.729 codec firmware is done via the con-
trol memory cells described in Table 3–9. The changes
applied to any of the control memory cells have to be
validated by setting bit[0] of memory cell Main I/O Con-
trol. This bit will be reset automatically after the
changes have been taken over by the DSP.
The AppSelect cell is a global user interface configura-
tion cell, which has to be written in order to start a spe-
cific application.
The AppRunning cell is a global user interface status
cell, which indicates, which application loop is actually
running.
The status memory cells in Table 3–11 are used to
read the decoder status and to get additional MPEG
bitstream information.
1. Write “0” to AppSelect
2. Check AppRunning for “0”
3. Write value to AppSelect according to Table 3–8
(determines start time of Application program)
Note: DSP memory cells not given in Table 3–8 or
Table 3–9 must not be written.
4. Apply necessary/wanted control settings
(D0:346..357)
Table 3–8: D0 control memory cells: mode selection
Memory
Address
(hex)
Function
Name
D0:34b
Application Selection
All AppSelect
AppSelect is used for selecting an application. This is done by setting the
appropriate bit to one. It is principally allowed to set more than one bit to one,
e.g. setting AppSelect to 1C
will select all MPEG audio decoders. The
hex
auto-detection feature will automatically detect the Layer 2, Layer 3, or AAC
data. Setting bit[0] or bit[1] will make the DSP loop in the OS loop or the Top
Level loop respectively.
To add/remove MPEG layers while running in MPEG decoding mode (e.g.
change from Layer 2, Layer 3 (0C ) to Layer 2, Layer 3, AAC (1C )), the
hex
hex
application selection has to be reset to 00
before writing the new value.
hex
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
G.729 Codec
MPEG AAC Decoder
MPEG Layer 3 Decoder
MPEG Layer 2 Decoder
Top Level
Operating System
D0:34c
Application Running
All AppRunning
The AppRunning cell is a global user interface status cell, that indicates which
application loop is actually running. Prior to writing any of the configuration
registers or memory cells (except AppSelect), it has to be checked whether
the appropriate bit(s) in the AppRunning cell is set.
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
G.729 Codec
MPEG AAC Decoder
MPEG Layer 3 Decoder
MPEG Layer 2 Decoder
Top Level
Operating System
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MAS 35x9F
Table 3–9: D0 control memory cells
Memory
Address
(hex)
Function
Name
D0:346
Main I/O Control (reset = 8025
)
MPEG
IOControlMain
hex
IOControlMain is used for selecting/deselecting the appropriate data input
interface and for setting up the serial data output interface. In serial input
mode the coded audio data (Layer 2, Layer 3, AAC) is expected at the serial
input interface SDIB (default). In the 8-bit-parallel input mode the PIO pins
PI[19:12] are used.
bit[15]
MP3 block input selection
0: MP3 block input mode OFF
1: MP3 block input mode ON
bit[14]
Invert serial output clock (SOC)
0 (reset)
1
do not invert SOC
invert SOC
bit[13:12]
bit[11]
Reserved, must be set to zero
Serial data output delay
0 (reset)
1
no additional delay (reset)
additional delay of data related to word strobe
bit[10]
Reserved, must be set to zero
bit[9:8]
Input Select Main
00 (reset) serial input at interface B
01
10
11
parallel input at PIO pins PI[19...12]
reserved for future use
reserved for future use
bit[7:6]
bit[5]
Reserved, must be set to zero
SDO Word Strobe Invert
0
do not invert
1 (reset)
invert outgoing word strobe signal
bit[4]
Bits per Sample at SDO
0 (reset)
1
32 bits/sample
16 bits/sample
bit[3]
bit[2]
Reserved, must be set to zero
Serial data input interface B clock invert (pin SIBC)
0
not inverted (data latched at rising clock edge)
incoming clock signal is inverted (data latched at
falling clock edge)
1 (reset)
bit[1]
bit[0]
0 (reset)
1
DEMAND MODE (PLL off, MAS 35x9F is clock
master)
BROADCAST MODE (PLL on, clock of MAS 35x9F
locks on data stream)
Validate
0 (reset)
1
no forced evaluation of control memory cells
changes in control memory will become effective
Bit[0] is reset after the DSP has recognized the changes. The controller
should set this bit after the other D0 control memory cells have been initialized
with the desired values.
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DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:347
Interface Status Control (reset = 05
)
MPEG
InterfaceControl
hex
This control cell allows to enable/disable the data I/O interfaces. In addition,
the clock of the output data interface interfaces, S/PDIF and SDO, can be set
to a low-impedance mode.
bit[6]
S/PDIF input selection (used for download modules)
0 (reset)
1
select S/PDIF input 1
select S/PDIF input 2
bit[5]
Enable/disable S/PDIF output
0 (reset)
1
enable S/PDIF output
S/PDIF output (invalid)
bit[4]
bit[3]
Reserved, must be set to zero
Enable/disable serial data output SDO
0 (reset)
1
SDO valid data
SDO invalid data
bit[2]
Output clock characteristic (SDO and S/PDIF outputs)
0
low impedance
high impedance
1 (reset)
bit[1]
bit[0]
reserved, must be set to zero
1)
Enable/Disable SDI
0
enable
disable
1 (reset)
2
Both digital outputs, S/PDIF and I S, and the D/A converters may use the
decoded audio independent of each other.
Changes at this memory address must be validated by setting bit[0] of
D0:346
.
hex
D0:348
Oscillator Frequency (reset = 18432
)
All
OfreqControl
dec
bit[19:0]
oscillator frequency in kHz
In order to achieve a correct internal operating frequency of the DSP, the nom-
inal crystal frequency has to be deposited into this memory cell.
Changes at this memory address must be validated by setting bit[0] of
D0:346
.
hex
1)
Note: The pins SIC, SII, SID are switched to output mode, if bit [0] = 1 (Reset value).
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MAS 35x9F
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:349
Output Clock Configuration (affects pin CLKO) (reset = 80000
)
All
OutClkConfig
hex
bit[19]
CLKO configuration
0
output clock signal at CLKO
CLKO is tristate
1 (reset)
The CLKO output pin of the MAS 35x9F can be disabled via bit[19].
bit[18]
bit[17]
Reserved, must be set to zero
Additional division by 2 if scaler is on (bit[8] cleared)
0 (reset)
1
oversampling factor 512/768
oversampling factor 256/384
bit[16:9]
bit[8]
Reserved, must be set to zero
Output clock scaler
0 (reset)
1
set output clock according to audio sample rate
(see Table 2–1)
output clock fixed at 24.576 or 22.5792 MHz
For a list of output frequencies at pin CLKO please refer to Table 2–1.
bit[7:0] reserved, must be set to zero
Changes at this memory address must be validated by setting bit[0] of
D0:346.
D0:350
D0:351
Soft Mute
MPEG
SoftMute
%0 (reset) mute off
%1
mute on
S/PDIF channel status bits category code setting (reset = 8200 ) All
SpdOutBits
hex
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DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:34d
Operation Mode Selection (reset = 0
)
G.729
UserControl
hex
The register is used to switch between basic G.729 operation modes.
bit[19:7]
bit[6]
Reserved, set to 0
Page headers
0
1
enable
disable
If the page headers bit is 0, a header frame is transfered before each page of
50 data frames. If the header bit is 1, all the frames are G.729 data frames.
Please (see Section 3.3.8. on page 44).
bit[5:4]
Decoding speed
00
01
10
11
8 kHz (normal)
6 kHz (slow)
12 kHz (fast)
not allowed
The recording (encoding) is always done with a sampling rate of 8 kHz. During
decoding this control can be used to speed up or slow down the playback.
bit[3]
bit[2]
Reserved, set to 0
Pause encoder/decoder
0
1
normal operation
pause
If the pause bit is set, the processing continues until the current page is fin-
ished and then en-/decoding is paused. The pause mode lasts until the pause
bit is cleared again or the mode is set to 0.
bit[1:0]
Mode
00
idle
01
10
11
decode
not allowed
encode
To switch to encoder operation mode, UserControl has to be set to 3 . Then
hex
50 frames are encoded and sent via the PIO interface. This is repeated until
the UserControl register is changed. If the transmission of headers is enabled,
each page of 50 frames is preceeded by a header frame as shown in Fig. 3–4
on page 44.
To switch to decoder operation mode, UserControl has to be set to 1 . For
hex
decoding with slow speed, UserControl must be 11 , for decoding with fast
hex
speed it must be 21 . Then the decoder is requesting several frames via the
hex
PIO interface to fill its internal buffer. If enough data is available, 50 frames are
decoded. This is repeated until the UserControl register is changed. If the
transmission of headers is enabled, a header frame has to be sent before
each page of 50 frames (see Fig. 3–4 on page 44).
To switch off the encoder or decoder, UserControl has to be set to 0 . Then
hex
the encoding/decoding and sending/receiving of frames continues until the
end of the current page and the operation mode is set to stop.
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Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
2
D0:34e
I S Audio Input/Output Interface (reset = 60
)
G.729
SDISDOConfig
hex
bit[19:15]
bit[14]
Reserved, set to 0
Output clock signal
0
1
standard signal
inverted signal
bit[13]
bit[12]
Reserved, set to 0
Additional delay of input data related to
word strobe
0
1
no delay
1 bit delay
bit[11]
Additional delay of output data related to
word strobe
0
1
no delay
1 bit delay
bit[10:7]
bit[6]
Reserveded, set to 0
Input word strobe signal
0
1
standard signal
inverted signal
bit[5]
bit[4]
Output word strobe signal
0
1
standard signal
inverted signal
Wordlength
0
1
32 bits/sample
16 bits/sample
This setting affects the wordlength on the SDI and SDO interfaces.
bit[3]
Input clock signal
0
1
standard signal
inverted signal
bit[2:0]
Reserved, set to 0
Changes become effective when the codec is started or the mode is changed
by writing to the UserControl memory cell.
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DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:34f
Interface Status Control (reset = 25
)
G.729
g729_InterfaceCont
rol
hex
This control cell is used to enable/disable interfaces in G.729 mode.
bit[6],[4]
bit [5]
reserved, must be set to zero
reserved, must be set to one
bit[3]
Enable/disable serial data output SDO
0 (reset)
1
SDO valid data
SDO invalid data
bit[2]
Output clock characteristic (SDO and S/PDIF outputs)
0
low impedance
high impedance
1 (reset)
bit[1]
bit[0]
reserved, must be set to zero
1)
Enable/Disable SDI
0
enable
disable
1 (reset)
D0:352
D0:353
D0:354
D0:355
D0:356
Volume input control: left gain
Volume input control: right gain
(reset=80000
)
G.729
G.729
All
in_L
hex
(reset=0
)
in_R
hex
Volume output control: left → left gain (reset=80000
)
out_LL
out_LR
out_RL
out_RR
hex
Volume output control: left → right gain (reset=0
)
All
hex
Volume output control: right → left gain(reset=0
)
All
hex
D0:357
Volume control: right → right gain (reset=80000
)
All
hex
1)
Note: The pins SIC, SII, SID are switched to output mode, if bit [0] = 1 (Reset value).
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MAS 35x9F
Table 3–10: MP3 block input mode user interface (all addresses in hex notation)
Addr.
Name
Description
bit[15] MP3 block input select
D0:346 IOControlMain
0: MP3 block input mode OFF
1: MP3 block input mode ON
works for input at serial input interface B
(bit[9:8] of IOControlMain = 00
)
bin
Reset value is 0x8024 (see Table 3–2).
R0:68
MP3BlockConfig
bit[17]
data end bit
Disables resync timeout. Should be set by the controller at the end of
an input file (file end, stop, or pause) when the last requested data
block has been fully sent.
0: resync timeout enabled
1: resync timeout disable ↔ no wait for end of block
bit[16]
bit[15]
reserved, set to “0”
start data request
0: MP3 decoder does not send data requests (wait loop)
1: MP3 decoder in operational mode, new input data will be requested
via pulses at the demand pin.
bit[14:0] input block size specific value, do not modify
Reset value is 0x6670. To set the start bit, the controller must write 0xe670.
R0:7e
PulseDelayCounter
bit[13:0] determines the variable fraction of the demand pulse length.
pulseLenVar[ns] = value * 88.58.
D0:34e ResyncTimeout
bit[19:0] timeout after resync: timeout[µs] = value * 3.32.
19
The default value is 2 -1, which results in a timeout of 1.74 seconds.
For an optimized resync behavior, it is recommended to set this value
to zero.
R0:5b
SerialInConfig
bit[14:0] configuration of the serial input interface
D0:350 SoftMute
bit[0]
MP3 soft mute
0: audio output on
1: audio output soft muted
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MAS 35x9F
DATA SHEET
Table 3–11: D0 status memory cells
Memory
Address
Function
Name
D0:FCF
D0:FD0
AAC bitrate in bit/s
AACbitrate
MPEG Frame Counter
MPEGFrameCount
bit[19:0]
number of MPEG frames after synchronization
The counter will be incremented with every new frame that is decoded. With
an invalid MPEG bit stream at its input (e.g. an invalid header is detected), the
MAS 35x9F resets the MPEGFrameCount to ‘0’.
D0:FD1
MPEG Header and Status Information
MPEGStatus1
bit[15]
reserved, must be set to zero
bit[14:13]
MPEG ID, Bits 12, 11 of the MPEG header
00
01
10
11
MPEG 2.5
reserved
MPEG 2
MPEG 1
not valid in case of AAC decoding (bit[12:11] = 00)
bit[12:11]
bit[10]
Bits 14 and 13 of the MPEG header
00
01
10
11
AAC
Layer 3
Layer 2
Layer 1
CRC Protection
0
1
bitstream protected by CRC
bitstream not protected by CRC
bit[9:2]
bit[1]
Reserved
CRC error
0
1
no CRC error
CRC error
bit[0]
Invalid frame
0
1
no invalid frame´
invalid frame
This location contains bits 15...11 of the original MPEG header and other sta-
tus bits. It will be set each frame directly after the header has been decoded
from the bit stream.
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DATA SHEET
MAS 35x9F
Table 3–11: D0 status memory cells, continued
Memory
Address
Function
Name
D0:FD2
MPEG Header Information
MPEGStatus2
bit[15:12]
MPEG Layer 2/3 Bitrate
MPEG1, L2
MPEG1, L3
MPEG2+2.5, L2/3
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
free
32
48
56
64
free
32
40
48
56
64
80
96
112
128
160
192
224
256
320
forbidden
free
8
16
24
32
40
48
56
64
80
96
112
128
160
192
224
256
320
384
forbidden
80
96
112
128
144
160
forbidden
bit[13:10]
Sampling frequency for MPEG2-AAC in Hz
0000..0010
0011
0100
0101
0110
0111
1000
1001
1010
reserved
48000
44100
32000
24000
22050
16000
12000
11025
8000
1011
1100..1111
reserved
...
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Table 3–11: D0 status memory cells, continued
Memory
Address
Function
Name
D0:FD2
MPEG Header Information, continued
MPEGStatus2
(continued)
bit[11:10]
Sampling frequencies in Hz
MPEG1
MPEG2
MPEG2.5
00
01
10
11
44100
48000
32000
reserved
22050
24000
16000
reserved
11025
12000
8000
reserved
bit[9]
Padding Bit
reserved
bit[8]
bit[7:6]
Mode
00
stereo
01
10
joint_stereo (intensity stereo / m/s stereo)
dual channel
11
single channel
bit[5:4]
Mode extension (applies to joint stereo only)
intensity stereo
m/s stereo
00
01
10
11
off
on
off
on
off
off
on
on
bit[3]
Copyright Protect Bit
0/1 not copyright protected/copyright protected
bit[2]
Copy/Original Bit
0/1
bitstream is a copy/bitstream is an original
bit[1:0]
Emphasis, indicates the type of emphasis
00
01
10
11
none
50/15 µs
reserved
CCITT J.17
This memory cell contains the 16 LSBs of the MPEG header. It will be set
directly after synchronizing to the bit stream.
Note that for AAC four bits are needed to define the sampling frequency while
for Layer2/Layer3 two bits are sufficient. This leads to an inconsistency in the
format of bits 13...10.
D0:FD3
D0:FD4
MPEG CRC Error Counter
CRCErrorCount
The counter will be increased by each CRC error detected in the MPEG bis-
stream. It will not be reset when losing the synchronization.
Number of Bits in Ancillary Data
NumberOfAncillary-
Bits
Number of valid ancillary bits in the current MPEG frame.
D0:FD5
...
D0:FF1
Ancillary Data
AncillaryData
(see Section 3.3.6. on page 43).
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MAS 35x9F
3.3.5. Ancillary Data
3.3.6. Reading of the Memory Cells “Number of
Bits in Ancillary Data” and “Ancillary Data”
The memory fields D0:FD5...D0:ff1 contain the ancil-
lary data. It is organized in 28 words of 16 bit each.
The last ancillary bit of a frame is placed at bit 0 in
D0:FD5. The position of the first ancillary data bit
received can be located via the content of
When in Broadcast Mode, reading of the cells “Num-
ber of Bits in Ancillary Data” and “Ancillary Data” will
lead to unpredictable results. These cells are
described in Table 3–11 on page 43.
NumberOfAncillaryBits because
The same applies to the “Number of Bits in Ancillary
Data” and “Ancillary Data” of the preliminary data
sheet MAS 3587F.
int[(NumberOfAncillaryBits-1)/16] + 1
of memory words are used.
Example:
First get the content of ‘NumberOfAncillaryBits’
<DW 68 c4 00 00 01 0f d4>
<DW 69 <DR dd dd>
Assume that the MAS 35x9F has received 19 ancillary
data bits. Therefore, it is necessary to read two 16-bit
words:
<DW 68 c4 00
Short Read from D0
00 02 0f d5> read 2 words starting at D0:fd5
<DW 69 <DR dd dd
dd dd>
receive the 2 16-bit words
The first bit received from the MPEG source is at posi-
tion 2 of D0:FD6; the last bit received is at the LSB of
D0:fd5.
Table 3–12: Content of D0:fd5 after reception of 19 ancillary bits.
D0:fd5
MSB 14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Ancillary
Data
4th
bit
5th
bit
6th
bit
...
...
...
...
...
...
...
...
...
...
17th
bit
18th
bit
last
bit
Table 3–13: Content of D0:fd6 after reception of 19 ancillary bits.
D0:fd6
MSB 14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Ancillary
Data
x
x
x
x
x
x
x
x
x
x
x
x
x
first
bit
2nd
bit
3rd
bit
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DATA SHEET
3.3.7. DSP Volume Control
Table 3–14: Settings for the digital volume matrix
The digital baseband volume matrix is used for control-
ling the digital gain as shown in Fig. 3–3. This volume
control is effective on both, the digital audio output and
the data stream to the D/A converters. The values are
in 20-bit 2’s complement notation.
Memory
Name
D0:354 D0:355 D0:356 D0:357
LL
LR
RL
RR
Stereo
−1.0
0
0
−1.0
(default)
Table 3–14 shows the proposed settings for the 4 vol-
ume matrix coefficients for stereo, left and right mono.
Mono left
−1.0
−1.0
0
0
The gain factors are given in fixed point notation
19
Mono right
0
0
−1.0
−1.0
(−1.0×2 = 80000 ).
hex
If channels are mixed, care must be taken to prevent
clipping at high amplitudes. Therefore, the sum of the
absolute values of coefficients for one output channel
must be less than 1.0.
3.3.8. Explanation of the G.729A Data Format
The codec is working on a page basis where the
encoding and decoding is performed in blocks of 50
G.729 frames, whereas each frame consists of
10 bytes in byte-swapped order (see Fig. 3–4). There-
fore most changes to the UserControl register become
effective when processing of the current page is fin-
ished. The pages are optionally preceeded by 10 byte
header frames (see Table 3–15).
For normal operating conditions it is recommended to
use the main volume control of the audio codec
instead (register 00 10
of the audio codec).
hex
left audio
+
−1
LL
Table 3–15: Content of page header
−1
−1
LR
RL
Byte
1
2
3
4
5
6
7
8
9
10
Value 64 6d 72 31 64 61 74 61 F4 01
(hex)
Switching directly from encoding to decoding mode (or
vice versa) is not allowed. Instead, the controller has to
send a stop request to the MAS 35x9F (writing 0
to
hex
+
UserControl) and must keep on sending data in decod-
ing mode or receive data in encoding mode until the
current page of 50 frames is finished. After this run-out
time, the encoding or decoding can be started again.
−1
RR
right audio
Fig. 3–3: Digital volume matrix
page frame frame frame
frame frame page frame frame
49 49 header 51 52
frame frame page frame frame
99 100 header 101 102
...
...
...
header
1
2
3
10 ms
10 ms
...
...
byte byte byte byte byte byte byte byte byte byte
10
64 6D 72 31 64 61 74 61 F4 01
2
1
4
3
6
5
8
7
9
Fig. 3–4: Schematic timing of the data transmission with preceeding header
44
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Micronas
DATA SHEET
MAS 35x9F
3.4. Audio Codec Access Protocol
The MAS 35x9F has 16-bit wide registers for the con-
trol of the audio codec. These registers are accessed
2
via the I C subaddresses codec_write (6C ) and
hex
codec_read (6D ).
hex
3.4.1. Write Codec Register
S
DW
W
A
codec_write
A
r3,r2
A
A
r1,r0
A
A
d3,d2
d1,d0
P
The controller writes the 16-bit value (d = d3,d2,d1,d0)
into the MAS 35x9F codec register (r = r3,r2,r1,r0). A
list of registers is given in Table 3–16.
Example: Writing the value 1234
into the codec reg-
hex
ister with the number 00 1B
:
hex
<DW 6c 00 1b 12 34>
3.4.2. Read Codec Register
1) send command
S
DW
W
A
codec_write
codec_read
A
r3,r2
A
r1,r0
A
P
P
2) get register value
S
DW
W
A
A
S
DR
W
A
N
d3,d2
A
d1,d0
Reading the codec registers also needs a set-up for
the register address and an additional start condition
during the actual read cycle. A list of status registers is
given in Table 3–17.
Micronas
June 30, 2004; 6251-505-1DS
45
MAS 35x9F
DATA SHEET
3.4.3. Codec Registers
2
Table 3–16: Codec control registers on I C subaddress 6C
hex
Register
Address
(hex)
Function
Name
CONVERTER CONFIGURATION
00 00
Audio Codec Configuration
CONV_CONF
0 dB is related to the D/A full-scale output voltage
Please refer to (see Section 4.6.3. on page 81).
bit[15:12]
bit[11:8]
A/D converter left amplifier gain = n*1.5−3 [dB]
A/D converter right amplifier gain = n*1.5−3 [dB]
1111
1110
...
+19.5 dB
+18.0 dB
...
0011
0010
0001
0000
+1.5 dB
0.0 dB
−1.5 dB
− 3.0 dB
bit[7:4]
bit[3]
Microphone amplifier gain = n*1.5+21 [dB]
1111
1110
...
+43.5 dB
+42.0 dB
...
0001
0000
+22.5 dB
+21.0 dB
Input selection for left A/D converter channel
0
1
line-in
microphone
1)
bit[2]
bit[1]
bit[0]
Enable left A/D converter
1)
Enable right A/D converter
1)
Enable D/A converter
1)
The generation of the internal DC reference voltage for the D/A converter is also controlled with this bit. In order
to avoid click noise, the reference voltage at pin AGNDC should have reached a near ground potential before
repowering the D/A converter after a short down phase.
Alternatively, at least one of the A/D converters (bits[2] or [1]) should remain set during short power-down phases
of the D/A. Then the DC reference voltage generation for the D/A converter will not be interrupted.
46
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DATA SHEET
MAS 35x9F
2
Table 3–16: Codec control registers on I C subaddress 6C , continued
hex
Register
Address
(hex)
Function
Name
INPUT MODE SELECT
00 08 Input Mode Setting
ADC_IN_MODE
bit[15]
Mono switch
0
1
stereo input mode
left channel is copied into the right channel
bit[14:2]
bit[1:0]
Reserved, must be set to 0
Deemphasis select
0
1
2
deemphasis off
deemphasis 50 µs
deemphasis 75 µs
OUTPUT MODE SELECT
D/A Converter Source Mixer
MIX ADC scale
MIX DSP scale
bit[15:8] Linear scaling factor (hex)
00 06
00 07
DAC_IN_ADC
DAC_IN_DSP
0
off
20
40
7f
50 % (−6 dB gain)
100 % (0 dB gain)
200 % (+6 dB gain)
In the sum of both mixing inputs exceeds 100 %, clipping may occur in the
successive audio processing.
00 0E
D/A Converter Output Mode
DAC_OUT_MODE
bit[15]
bit[14]
bit[1:0]
Mono switch
0
1
stereo through
mono matrix applied
Invert right channel
0
1
through
right channel is inverted
Reserved, must be set to 0
In order to achieve more output power a single loudspeaker can be connected
as a bridge between pins OUTL and OUTR. In this mode bit[15] and bit[14]
must be set.
Micronas
June 30, 2004; 6251-505-1DS
47
MAS 35x9F
DATA SHEET
2
Table 3–16: Codec control registers on I C subaddress 6C , continued
hex
Register
Address
(hex)
Function
Name
BASEBAND FEATURES
00 14
Bass
BASS
bit[15:8]
Bass range
60
58
...
+12 dB
+11 dB
hex
hex
08
00
F8
...
+1 dB
0 dB
−1 dB
hex
hex
hex
A8
A0
−11 dB
−12 dB
hex
hex
Higher resolution is possible, one LSB step results in a gain step of about
1/8 dB.
With positive bass settings clipping of the output signal may occur. Therefore,
it is not recommended to set bass to a value that, in conjunction with volume,
would result in an overall positive gain.
The settings require: max (bass, treble) + loudness + volume ≤ 0 dB
bit[7:0]
Not used, must be set to 0
00 15
Treble
TREBLE
bit[15:8]
Treble range
60
58
...
+12 dB
+11 dB
hex
hex
08
00
F8
...
+1 dB
0 dB
−1 dB
hex
hex
hex
A8
A0
−11 dB
−12 dB
hex
hex
Higher resolution is possible, one LSB step results in a gain step of about
1/8 dB.
With positive treble settings, clipping of the output signal may occur. There-
fore, it is not recommended to set treble to a value that, in conjunction with
loudness and volume, would result in an overall positive gain.
The settings require: max (bass, treble) + loudness + volume ≤ 0 dB
bit[7:0]
Not used, must be set to 0
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DATA SHEET
MAS 35x9F
2
Table 3–16: Codec control registers on I C subaddress 6C , continued
hex
Register
Address
(hex)
Function
Name
00 1E
Loudness
LDNESS
bit[15:8] Loudness Gain
44
40
...
+17 dB
+16 dB
hex
hex
04
00
+1 dB
0 dB
hex
hex
bit[7:0]
Loudness Mode
00
04
normal (constant volume at 1 kHz)
Super Bass (constant volume at 2 kHz)
hex
hex
Higher resolution of Loudness Gain is possible: An LSB step results in a gain
step of about 1/4 dB.
Loudness increases the volume of low- and high-frequency signals, while
keeping the amplitude of the 1-kHz reference frequency constant. The
intended loudness has to be set according to the actual volume setting.
Because loudness introduces gain, it is not recommended to set loudness to a
value that, in conjunction with volume, would result in an overall positive gain.
The settings should be: max (bass, treble) + loudness + volume ≤ 0 dB
The corner frequency for bass amplification can be set to two different values.
In Super Bass mode, the corner frequency is shifted up. The point of constant
volume is shifted from 1 kHz to 2 kHz.
Micronas
June 30, 2004; 6251-505-1DS
49
MAS 35x9F
DATA SHEET
2
Table 3–16: Codec control registers on I C subaddress 6C , continued
hex
Register
Address
(hex)
Function
Name
Micronas Bass (MB)
00 22
MB Effect Strength
MB_STR
MB_HAR
bit[15:8]
00
7F
MB off (default)
maximum MB
hex
hex
The MB effect strength can be adjusted in 1dB steps. A value of 40 will
yield a medium MB effect.
hex
00 23
MB Harmonics
bit[15:8]
00
64
7F
no harmonics are added (default)
50% fundamentals + 50% harmonics
100% harmonics
hex
hex
hex
The MB exploits the psychoacoustic phenomenon of the ‘missing fundamental
by creating harmonics of the frequencies below the center frequency of the
bandpass filter (MB_FC). This enables a loudspeaker to display frequencies
that are below its cutoff frequency. The Variable MB_HAR describes the ratio
of the harmonics towards the original signal.
00 24
MB Center Frequency
MB_FC
bit[15:8]
2
3
20 Hz
30 Hz
...
30
300 Hz
The MB Center Frequency defines the center frequency of the MB bandpass
filter (see Fig. 3–5 on page 52). The center frequency should approximately
match the cutoff frequency of the loudspeakers. For high end loudspeakers,
this frequency is around 50 Hz, for low end speakers around 90 Hz
00 21
MB Shape
MB_SHAPE
bit[15:8]
5...30
corner frequency in 10-Hz steps
(range: 50...300 Hz)
With a second lowpass filter the steepness of the falling edge of the MB band-
pass can be increased (see Fig. 3–5 on page 52). Choosing the corner fre-
quency of this filter close to the center frequency of the bandpass filter
(MB_FC) results in a narrow MB frequency range. The smaller this range, the
harder the bass sounds. The recommended value is around 1.5 × MB_FC
MB Switch
MB_SWITCH
bit[7:2]
bit[1]
reserved, must be set to zero
MB switch
MB off
MB on
0
1
bit [0]
reserved,must be set to zero
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DATA SHEET
MAS 35x9F
2
Table 3–16: Codec control registers on I C subaddress 6C , continued
hex
Register
Address
(hex)
Function
Name
VOLUME
00 12
Automatic Volume Correction (AVC) Loudspeaker Channel
AVC
bit[15:12] 0
8
AVC off (and reset internal variables)
AVC on
hex
hex
bit[11:8]
8
4
2
1
8 s decay time
4 s decay time
2 s decay time
20 ms decay time (intended for quick adaptation to the
average volume level after track or source change)
hex
hex
hex
hex
Note: To reset the internal variables, the AVC should be switched off and then
on again during any track or source change. For standard applications, the
recommended decay time is 4 s.
00 11
Balance
BALANCE
bit[15:8] Balance range
7F
7E
...
left −127 dB, right 0 dB
left −126 dB, right 0 dB
hex
hex
01
00
FF
left −1 dB, right 0 dB
left 0 dB, right 0 dB
left 0 dB, right −1 dB
hex
hex
hex
...
81
80
left 0 dB, right −127 dB
left 0 dB, right −128 dB
hex
hex
Positive balance settings reduce the left channel without affecting the right
channel; negative settings reduce the right channel leaving the left channel
unaffected.
00 10
Volume Control
VOLUME
bit[15:8] Volume table with 1 dB step size
7F
7E
...
+12 dB (maximum volume)
+11 dB
hex
hex
74
73
72
...
+1 dB
0 dB
−1 dB
hex
hex
hex
02
01
00
−113 dB
−114 dB
mute (reset)
hex
hex
hex
bit[7:0]
Not used, must be set to 0
This main volume control is applied to the analog outputs only. It is split
between a digital and an analog function. In order to avoid noise due to large
changes of the setting, the actual setting is internally low-pass filtered.
With large scale input signals, positive volume settings may lead to signal clip-
ping.
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51
MAS 35x9F
DATA SHEET
2
Table 3–17: Codec status registers on I C subaddress 6D
hex
Register
Address
(hex)
Function
Name
INPUT QUASI-PEAK
00 0A
A/D Converter Quasi-Peak Detector Readout Left
QPEAK_L
QPEAK_R
bit[14:0]
positive 15-bit value, linear scale
0%
25% (−12 dBFS)
50% (−6 dBFS)
100% (0 dBFS)
0000
2000
4000
7FFF
00 0B
A/D Converter Quasi-Peak Detector Readout Right
bit[14:0]
positive 15-bit value, linear scale
0%
25% (−12 dBFS)
50% (−6 dBFS)
100% (0 dBFS)
0000
2000
4000
7FFF
OUTPUT QUASI-PEAK
00 0C
Audio Processing Input Quasi-Peak Detector Readout Left
bit[14:0] positive 15-bit value, linear scale
Audio Processing Input Quasi-Peak Detector Readout Right
bit[14:0] positive 15-bit value, linear scale
DQPEAK_L
DQPEAK_R
00 0D
3.4.4. Basic MB Configuration
(which results in a softer/harder bass sound), turn
on/off the MB
With the parameters described in Table 3–16, the Mic-
ronas Bass system (MB) can be customized to create
different bass effects, as well as to fit the MB to various
loudspeaker characteristics. The easiest way to find a
good set of parameter is by selecting one of the set-
tings below, listening to music with strong bass content
and adjusting the MB parameters:
– MB_STR: Increase/decrease the strength of the MB
effect
– MB_HAR: Increase/decrease the content of low fre-
quency harmonics
Frequency
MB_SHAPE
MB_FC
– MB_FC: Shift the MB effect to lower/higher frequen-
cies
Fig. 3–5: Micronas Bass (MB): Bass boost in relation
to input signal level
– MB_SHAPE: Widen/narrow MB frequency range
Table 3–18: Suggested MB settings
Function
MB_STR
MB_HAR
MB_FC
MB_SHAPE
(22
)
(23
)
(24
)
(21
)
hex
hex
hex
hex
MB off
xxxx
xxxx
xxxx
xx00
hex
hex
hex
hex
Low end headphones, medium effect
5000
3000
0600
0902
hex
hex
hex
hex
52
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Micronas
DATA SHEET
MAS 35x9F
Micronas
June 30, 2004; 6251-505-1DS
53
MAS 35x9F
DATA SHEET
4. Specifications
4.1. Outline Dimensions
Fig. 4–1:
3
PLQFP64-1: Plastic Low Quad Flat Package, 64 leads, 10 × 10 × 1.4 mm
Ordering code: FH
Weight approximately 0.66 g
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Micronas
DATA SHEET
MAS 35x9F
Fig. 4–2:
3
PMQFP64-2: Plastic Metric Quad Flat Package, 64 leads, 10 × 10 × 2 mm
Ordering code: QI
Weight approximately 0.5 g
Micronas
June 30, 2004; 6251-505-1DS
55
MAS 35x9F
DATA SHEET
Fig. 4–3:
3
PQFN64-1: Plastic Quad Flat Non-leaded package, 64 pins, 9 × 9 × 0.85 mm , 0.5 mm pitch
Ordering code: XK
Weight approximately 0.23 g
56
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DATA SHEET
MAS 35x9F
4.2. Pin Connections and Short Descriptions
NC = not connected, leave vacant
LV = if not used, leave vacant
S.T.B. = shorted to BAGNDI if not used
DVSS = if not used, connect to DVSS
OBL = obligatory; connect as described in circuit diagram
AHVSS = connect to AHVSS
Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
PLQFP
64-1
PMQFP PQFN
64-2
64-1
1
2
1
1
AGNDC
MICIN
OBL
LV
Analog reference voltage
2
2
IN
Input for internal micro-
phone amplifier
3
4
5
6
7
3
4
5
6
7
3
4
5
6
7
MICBI
INL
IN
IN
IN
IN
IN
LV
Bias for internal microphone
Left A/D input
LV
INR
TE
LV
Right A/D input
OBL
OBL
Test enable
XTI
Crystal oscillator (ext. clock)
input
8
8
8
XTO
OUT
LV
Crystal oscillator output
Power on reset, active low
DSP supply ground
9
9
9
POR
IN
OBL
OBL
OBL
OBL
OBL
OBL
OBL
VDD
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
VSS
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
IN
XVSS
VDD
Digital output supply ground
DSP supply
XVDD
I2CVDD
DVS
Digital output supply
2
I C supply
2
I C device address selector
VSENS1
IN/OUT
Sense input and power out-
put
of DC/DC 1 converter
17
18
19
20
21
17
18
19
20
21
17
18
19
20
21
DCSO1
DCSG1
DCSG2
DCSO2
VSENS2
SUPPLY
SUPPLY
SUPPLY
SUPPLY
IN/OUT
LV
DC/DC 1 switch output
DC/DC 1 switch ground
DC/DC 2 switch ground
DC/DC 2 switch output
VSS
VSS
LV
VDD
Sense input and power out-
put
of DC/DC 2 converter
22
22
22
DCEN
IN
VSS
DC/DC enable (both con-
verters)
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June 30, 2004; 6251-505-1DS
57
MAS 35x9F
DATA SHEET
Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
PLQFP
64-1
PMQFP PQFN
64-2
64-1
23
24
25
26
27
23
23
CLKO
I2CC
I2CD
SYNC
VBAT
OUT
LV
Clock output
2
24
24
IN/OUT
IN/OUT
OUT
OBL
OBL
LV
I C clock
2
25
25
I C data
26
26
Sync output
27
27
IN
LV
Battery voltage monitor
input
28
28
28
PUP
OUT
LV
DC Converters Power-Up
Signal
29
30
29
30
29
30
EOD
OUT
OUT
LV
LV
PIO end of DMA, active low
PRTR
PIO ready to read, active
low
31
32
31
32
31
32
PRTW
PR
OUT
IN
LV
PIO ready to write, active
low
VDD
PIO DMA request, active
high
33
34
35
36
37
38
39
40
41
42
43
33
34
35
36
37
38
39
40
41
42
43
33
34
35
36
37
38
39
40
41
42
43
PCS
PI19
PI18
PI17
PI16
PI15
PI14
PI13
PI12
SOD
SOI
IN
VSS
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
PIO chip select, active low
PIO data bit[7] (MSB)
PIO data bit[6]
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
OUT
PIO data bit[5]
PIO data bit[4]
PIO data bit[3]
PIO data bit[2]
PIO data bit[1]
PIO data bit[0] (LSB)
Serial output data
OUT
Serial output word identifi-
cation
44
45
46
44
45
46
44
45
46
SOC
SID
SII
OUT
LV
Serial output clock
IN/OUT
IN/OUT
OBL
OBL
Serial input data, interface A
Serial input word identifica-
tion, interface A
47
47
47
SIC
IN/OUT
OBL
Serial input clock, interface
A
48
49
48
49
48
49
SPDO
SIBD
OUT
IN
LV
S/PDIF output interface
VSS
Serial input data, interface B
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Micronas
DATA SHEET
MAS 35x9F
Pin No.
PMQFP PQFN
Pin Name
Type
Connection
(If not used)
Short Description
PLQFP
64-1
64-2
64-1
50
51
52
53
54
55
56
50
50
SIBC
IN
VSS
VSS
LV
Serial input clock, interface
B
51
52
53
54
55
56
51
52
53
54
55
56
SIBI
IN
Serial input word identifica-
tion, interface B
SPDI2
SPDI1
SPDIR
FILTL
AVDD0
IN
Active differential S/PDIF
input 2
IN
LV
Active differential S/PDIF
input 1
IN
LV
Reference differential S/
PDIF input 1 and 2
IN
OBL
OBL
Feedback input for left
amplifier
SUPPLY
Analog supply for output
amplifiers
57
58
59
57
58
59
57
58
59
OUTL
OUTR
AVSS0
OUT
LV
Left analog output
Right analog output
OUT
LV
SUPPLY
OBL
Analog ground for output
amplifiers
60
60
60
FILTR
IN
OBL
Feedback for right output
amplifier
61
62
63
64
61
62
63
64
61
62
63
64
AVSS1
VREF
SUPPLY
OBL
OBL
OBL
OBL
Analog ground
Analog reference ground
Internal power supply
Analog Supply
PVDD
AVDD1
SUPPLY
SUPPLY
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June 30, 2004; 6251-505-1DS
59
MAS 35x9F
DATA SHEET
4.3. Pin Descriptions
VSENS1/VSENS2
IN
Sense input and power output of DC/DC converters. If
the respective DC/DC converter is not used, this pin
should be connected to a supply to enable proper
function of the PUP-signals.
4.3.1. Power Supply Pins
The use of all power supply pins is mandatory to
achieve correct function of the MAS 35x9F.
DCEN
IN
VDD, VSS
Digital supply pins.
SUPPLY
SUPPLY
SUPPLY
Enable signal for both DC/DC converters. If none of
the DC/DC converters is used, this pin must be con-
nected to VSS.
XVDD, XVSS
Supply for digital output pins.
PUP
OUT
Power-up. This signal is set when the required volt-
ages are available at both DC/DC converter output
pins VSENS1 and VSENS2. The signal is cleared
when both voltages have dropped below the reset
level in the DCCF Register.
I2CVDD
2
Supply for I C interface circuitry. This net uses VSS or
XVSS as the ground return line.
PVDD
SUPPLY
Auxiliary pin for analog circuitry. This pin has to be
connected via a 3 nF capacitor to AVDD1. Extra care
should be taken to achieve a low-inductance PCB line.
VBAT
IN
Analog input for battery voltage supervision.
AVDD0/AVSS0
SUPPLY
4.3.4. Oscillator Pins and Clocking
Supply for analog output amplifier.
XTI
IN
AVDD1/AVSS1
SUPPLY
XTO
OUT
Supply for internal analog circuits (A/D, D/A convert-
ers, clock, PLL, S/PDIF input).
The XTI pin is connected to the input of the internal
crystal oscillator, the XTO pin to its output. Each pin
should be directly connected to the crystal and to a
ground-connected capacitor (see application diagram,
Fig. 5–1 on page 89).
AVDD0/AVSS0 and AVDD1/AVSS1 should receive the
same supply voltages.
CLKO
OUT
4.3.2. Analog Reference Pins
The CLKO can drive an output clock line.
AGNDC
Internal analog reference voltage. This pin serves as
the internal ground connection for the analog circuitry.
4.3.5. Control Lines
I2CC
I2CD
SCL
SDA
IN/OUT
IN/OUT
VREF
2
Analog reference ground. All analog inputs and out-
puts should drive their return currents using separate
traces to a ground starpoint close to this pin. Connect
to AVSS1. This reference pin should be as noise-free
as possible.
Standard I C control lines.
DVS
IN
2
I C device address selector. Connect this pin either to
2
2
VDD (I C device address: 3E/3F ) or VSS (I C
device address: 3C/3D ) to select a proper I C
hex
2
hex
device address (see also Table 3–2 on page 23).
4.3.3. DC/DC Converters and
Battery Voltage Supervision
4.3.6. Parallel Interface Lines
DCSG1/DCSG2
SUPPLY
DC/DC converters switch ground. Connect using sep-
arate wide trace to negative pole of battery cell. Con-
nect also to AVSS0/1 and VSS/XVSS, VREF.
PI12..PI19
IN/OUT
The PIO input pins PI12..PI19 are used as 8-bit I/O
interface to a microcontroller in order to transfer com-
pressed and uncompressed data. PI12 is the LSB,
PI19 the MSB.
DCSO1/DCSO2
SUPPLY
DC/DC converter switch connection. If the respective
DC/DC converter is not used, this pin must be left
vacant.
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DATA SHEET
MAS 35x9F
4.3.6.1. PIO Handshake Lines
PCS
The PIO chip select PCS must be set to ‘0’ to activate
the PIO in operation mode.
specification are used in conjunction with download
software only. A switch at D0:ff6 selects one of these
pins at a time. The SPDIR pin is a common reference
for both input lines (see Fig. 5–1 on page 89).
IN
PR
IN
4.3.11. S/PDIF Output Interface
Pin PR must be set to ‘1’ to validate data output from
MAS 35x9F PIO pins.
SPDO
OUT
The SPDO pin provides an digital output with standard
CMOS level that is compliant to the IEC 958 consumer
specification.
PRTR
OUT
Ready to read. This signal indicates that the
MAS 35x9F is able to receive data in PIO input mode.
PRTW
OUT
4.3.12. Analog Input Interfaces
Ready to write. This pin indicates that MAS 35x9F has
data available for PIO output mode.
In the standard MPEG-decoding DSP firmware the
analog inputs are not used. However, they can be
selected as a source for the D/A converters
EOD
OUT
EOD indicates the end of an DMA cycle in the IC’s PIO
input mode. In ’serial’ input mode it is used as Demand
signal, that indicates that new input data are required.
(set MIX ADC scale of the D/A Converter Source
Mixer, Register 00 06
in Table 3–16).
hex
MICIN
MICBI
IN
IN
4.3.7. Serial Input Interface (SDI)
The MICIN input may be directly used as electret
microphone input, which should be connected as
described in application information (see Fig. 5–1 on
page 89). The MICBI signal provides the supply volt-
age for these microphones.
SID
SII
DATA
WORD STROBE
CLOCK
IN/OUT
IN/OUT
IN/OUT
SIC
2
I S compatible serial interface A for digital audio data.
In the standard firmware this interface is not used.
Note: Please refer to Bit [0] of Table 3–5
INL
INR
IN
IN
INL and INR are analog line-in input lines. They are
connected to the embedded stereo A/D converter of
the MAS 35x9F. The sources should be AC-coupled.
The reference ground for these analog input pins is the
VREF pin.
4.3.8. Serial Input Interface B (SDIB)
SIBD
SIBI
DATA
WORD STROBE
CLOCK
IN
IN
IN
SIBC
The serial interface B is primarily used as bitstream
input interface. The SIBI line must be connected to
VSS in the standard application.
4.3.13. Analog Output Interfaces
OUTL
OUTR
OUT
OUT
OUTL and OUTR are left and right analog outputs, that
may be directly connected to the headphones as
described in the application information (see Fig. 5–1
on page 89).
4.3.9. Serial Output Interface (SDO)
SOD
SOI
SOC
DATA
WORD STROBE
CLOCK
OUT
OUT
IN/OUT
FILTL
FILTR
IN
IN
Data, Frame Indication, and Clock line of the serial
output interface. The SOI is reconfigurable and can be
Connection to input terminal of output amplifier.Can be
used to connect a capacitance from OUTL respectively
OUTR to FILTL respectively FILTR in parallel to feed-
back resistor and thus implement a low pass filter to
reduce the out-of-band noise of the DAC.
2
adapted to several I S compliant modes.
4.3.10. S/PDIF Input Interface
SPDI1
SPDI2
SPDIR
IN
IN
IN
SPDIF1 and SPDIF2 are alternative input pins for
S/PDIF sources according to the IEC 958 consumer
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61
MAS 35x9F
DATA SHEET
4.3.14. Miscellaneous
SYNC
OUT
The SYNC signal indicates the detection of a frame
start in the input data of MAS 35x9F. Usually this sig-
nal generates an interrupt in the controller.
POR
IN
The Power-On Reset pin is used to reset the whole
MAS 35x9F. The POR is an active-low signal (see
Fig. 5–1 on page 89).
TE
IN
The TE pin is for production test only and must be con-
nected with VSS in all applications.
4.4. Pin Configuration
PI12
SOD
SOI
PI13
PI14
PI15
PI16
PI17
PI18
PI19
SOC
SID
SII
SIC
SPDO
PCS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SIBD 49
SIBC 50
32 PR
31 PRTW
30 PRTR
29 EOD
SIBI 51
SPDI2 52
SPDI1 53
SPDIR 54
FILTL 55
AVDD0 56
OUTL 57
OUTR 58
AVSS0 59
FILTR 60
AVSS1 61
VREF 62
PVDD 63
AVDD1 64
28 PUP
27 VBAT
26 SYNC
25 I2CD
MAS 35x9F
24 I2CC
23 CLKO
22 DCEN
21 VSENS2
20 DCSO2
19 DCSG2
18 DCSG1
17 DCSO1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
AGNDC
VSENS1
MICIN
MICBI
DVS
I2CVDD
XVDD
VDD
XVSS
VSS
POR
INL
INR
TE
XTI
XTO
Fig. 4–4: PLQFP64-1/PMQFP64-2 and PQFN64-1 package
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DATA SHEET
MAS 35x9F
4.5. Internal Pin Circuits
VDD
TTLIN
N
VSS
Fig. 4–5: Input pins PCS, PR
Fig. 4–10: Input/output pins I2CC, I2CD
VSENS
P
Fig. 4–6: Input pin TE, DVS, POR
DCSO
N
DCSG
Fig. 4–11: Input/output pins DCSO1/2, DCSG1/2,
VSENS1/2
Fig. 4–7: Input pin DCEN
XVDD
P
XVDD
P
N
N
XVSS
XVSS
Fig. 4–12: Output pins PRTW, EOD, PRTR, CLKO,
SYNC, PUP
Fig. 4–8: Input/output pins SOC, SOI, SOD,
PI12...PI19, SPDO
AVDD
XVDD
P
P
XTI
P
P
N
XTO
N
XVSS
N
Enable
N
Fig. 4–9: Input pins SIC, SII, SID
AVSS
Fig. 4–13: Clock oscillator XTI, XTO
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MAS 35x9F
DATA SHEET
MICIN
INL
INR
XVDD
A
−
+
SPDI1,
SPDI2
−
D
+
SPDIR
AGNDC
XVDD
Fig. 4–14: Analog input pins MICIN, INL, INR
Bias
Fig. 4–18: S/PDIF inputs
+
−
AGNDC
MICBI
VBAT
+
VREF
−
programmable
=
Fig. 4–15: Microphone bias pin (MICBI)
VSS
VSS
Fig. 4–19: Battery voltage monitor VBAT
FILTL(R)
4.5.1.Reset Pin Configuration for MAS 3529F and
MAS 3539F
D
I
−
+
A
OUTL(R)
The Power-On Reset pin POR is used to reset the
entire MAS 35x9F. The POR is an active-low signal.
AGNDC
Note: If a pull-up resistor is used for building a delay
time here (see Fig. 5–1 on page 89), referred to
the VDD pins, the maximum allowed value for
this resistor is 3.3 kOhm!
Fig. 4–16: Analog outputs OUTL(R) and connections
for filter capacitors FILTL(R)
+
AGNDC
−
1.25 V
VREF
Fig. 4–17: Analog ground generation with pin to
connect external capacitor
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DATA SHEET
MAS 35x9F
4.6. Electrical Characteristics
Abbreviations:
tbd = to be defined
vacant = not applicable
positive current values mean current flowing into the chip
4.6.1. Absolute Maximum Ratings
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute
maximum rating conditions for extended periods will affect device reliability.
This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso-
lute maximum-rated voltages to this high-impedance circuit.
All voltages listed are referenced to ground (V
V
V
= 0 V) except where noted.
SUP1, SUP2, SUP3
All GND pins must be connected to a low-resistive ground plane close to the IC.
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For
power up/down sequences, see the instructions in Section 2.6. of this document.
Table 4–1: Absolute Maximum Ratings
Symbol
Parameter
Pin Name
Limit Values
Unit
Min.
Max.
1)
2)
T
Ambient Temperature
°C
A
- operating conditions
- extended temperature range
−10
−40
85
85
1)
T
Case Temperature
PLQFP64-1
PMQFP64-2
PQFN64-1
°C
C
−10
−10
−10
115
120
120
T
Storage Temperature
−40
125
°C
S
3)
P
V
Maximum Power Dissipation
PLQFP64-1
PMQFP64-2
VDD, XVDD,
AVDD0/1,
I2CVDD
W
MAX
0.67
0.63
0.87
PQFN64-1
Supply Voltage 1
VDD, XVDD,
I2CVDD,
−0.3
6
V
SUP1
4)
AVDD0/1
1)
2)
Data sheet parameters are valid for “operating conditions” only. The functionality of the device in the “extended
temperature range” was checked by electrical characterization on sample base.
A power-optimized board layout is recommended. The Case Temperature mentioned in the “Absolute Maxi-
mum Ratings” must not be exceeded at worst case conditions of the application.
3)
4)
Package limits
Both AVDD0 and AVDD1 have to be connected together!
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June 30, 2004; 6251-505-1DS
65
MAS 35x9F
DATA SHEET
Table 4–1: Absolute Maximum Ratings, continued
Symbol
Parameter
Pin Name
Limit Values
Unit
Min.
Max.
V
V
Supply Voltage 2
VDD, XVDD,
I2CVDD,
AVDD0/1
−0.3
6
V
SUP2
SUP3
1)
Supply Voltage 3
VDD, XVDD,
I2CVDD,
−0.3
−0.3
6
6
V
V
1)
AVDD0/1
2
V
V
Input Voltage, I C pins
I2CC,
I2CD
II2C
ID
Input Voltage
all digital inputs
all digital inputs
−0.3
−20
V
+ 0.3
V
SUP
I
Input Current
+20
mA
V
ID
V
Input Voltage
all analog inputs −0.3
all analog inputs −5
V
+ 0.3
SUP
IA
I
I
I
I
I
Input Current
+5
mA
A
IA
2)
Output Current, audio output
OUTL/R
−0.2
−50
0.2
+50
1.5
1.5
Oaudio
Odig
3)
Output Current, all digital outputs
mA
A
Output Current DCDC converter 1
Output Current DCDC converter 2
DCSO1
DCSO2
Odcdc1
Odcdc2
A
1)
2)
3)
Both AVDD0 and AVDD1 have to be connected together!
These pins are not short-circuit-proof!
Total chip power dissipation must not exceed maximum rating.
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DATA SHEET
MAS 35x9F
4.6.1.1. Recommended Operating Conditions
Functional operation of the device beyond those indicated in the “Recommended Operating Conditions/Characteris-
tics” is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device.
All voltages listed are referenced to ground (V
V
V
= 0 V) except where noted.
SUP1, SUP2, SUP3
All GND pins must be connected to a low-resistive ground plane close to the IC.
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For
power up/down sequences, see the instructions in section Section 2.11.2. of this document.
Symbol
Parameter
Pin Name
Limit Values
Typ.
Unit
Min.
Max.
1)
T
Ambient Operating Temperature
PLQFP64-1
PMQFP64-2
°C
A
0
0
0
25
25
25
85
85
85
PQFN64-1
T
Case Operating Temperature
PLQFP64-1
PMQFP64-2
°C
C
15
20
15
95
100
95
100
105
100
PQFN64-1
P
P
P
P
V
MP3 Decoder (SC4 En-/Decoder)
AAC Decoder/G729 Encoder
G.729 Decoder
VDD
80
122
50
7
mW
mW
mW
mW
V
MAX_D1
MAX_D2
MAX_D3
MAX_A
VDD
VDD
DAC-Headphone Playback
AVDD0/1
VDD
1)
Digital supply voltage (MP3
decoder, G729 Decoder)
2.2
2.5
2.5
3.6
3.6
SUPD1
V
V
Digital supply voltage
(G.729 A encoder/MP3 Decoder
and SD Decryption/AAC Decoder)
2.7
SUPD2
SUPI2C
2
2)
I C bus supply voltage
I2CVDD
XVDD
V
3.9
V
SUPDn
at VDD
VSUPx
PIN supply voltage
2.2
2.5
2.7
3.6
V
V
PIN supply voltage in relation to
digital supply voltage
0.62 *
1.6 *
2)
2)
2)
2)
V
V
SUPDn
SUPDn
VSUPA
Analog audio supply voltage
AVDD0/1
2.2
3.6
V
V
Analog audio supply voltage in rela-
tion to the digital supply voltage
0.62 *
1.6 *
V
V
SUPDn
SUPDn
V
Voltage differences within supply
domains
V
SUPDX
1)
2)
A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the
“Recommended Operating Conditions” must not be exceeded at worst case conditions of the application.
For turn-on voltage of DSP and codec, please refer to Section 2.11.2.1.
n = 1 or 2
Micronas
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MAS 35x9F
DATA SHEET
Table 4–2: Reference Frequency Generation and Crystal Recommendation
Symbol
External Clock Input Recommendations
Clock frequency
Parameter
Pin Name
Min.
Typ.
Max.
Unit
f
XTI, XTO
13.00
0.7
18.432
20.00
1.05
MHz
CLK
V
Clockamplitude of external clock XTI
fed into XTI at V = 2.2 V
V
PP
CLKI
AVDD
Clockamplitude of external clock
fed into XTI at V = 2.7 V
0.55
0.45
1.25
0.75
0.55
45
1.5
1.75
2.2
2.7
3.3
55
AVDD
Clockamplitude of external clock
fed into XTI at V = 3.3 V
AVDD
Clockamplitude of external clock XTO
fed into XTO at V = 2.2 V
AVDD
Clockamplitude of external clock
fed into XTO at V = 2.7 V
AVDD
Clockamplitude of external clock
fed into XTO at V
= 3.3 V
AVDD
Duty cycle
XTI, XTO
XTI, XTO
50
%
Crystal Recommendations
Load resonance frequency at
f
18.432
MHz
ppm
ppm
P
C = 20 pF
I
∆f/f
∆f/f
Accuracy of frequency adjust-
ment
−50
−50
50
50
S
Frequency variation vs. temper-
ature
S
R
C
Equivalent series resistance
Shunt (parallel) capacitance
12
3
30
5
Ω
EQ
0
pF
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DATA SHEET
MAS 35x9F
Table 4–3: Input clock frequency
Symbol
Parameter
Pin Name
Limit Values
Typ.
Unit
Min.
Max.
1)
f
G.729 Decoder
G.729 Encoder
XTI, XTO
16.4
13.7
MHz
MHz
CLK
MPEG Decoder (SC4 En-
Decoder)
11.0
MHz
1)
Minimum F
for SD-card decryption is defined in a supplement.
CLK
Table 4–4: Input levels
Symbol Parameter
Pin Name
Limit Values
Typ.
Unit
Min.
1.4
0.9
V
Max.
V
V
V
V
V
V
Input low voltage
Input high voltage
Input low voltage
Input high voltage
Input low voltage
Input high voltage
I2CC,
I2CD
0.3
0.2
0.3
V
V
V
V
V
V
IL
IH
POR,
DCEN
IL
IH
PI<I>,
SI(B)I,
SI(B)C,
SI(B)D, PR,
PCS,
ILD
IHD
SUPx
−0.5
TE, DVS
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MAS 35x9F
DATA SHEET
Table 4–5: Analog input and output recommendations
Symbol
Parameter
Pin Name
Limit Values
Typ.
Unit
Min.
1.0
3
Max.
Analog Reference
C
C
C
Analog filter capacitor
AGNDC
PVDD
3.3
10
µF
nF
nF
AGNDC1
AGNDC2
PVDD
Ceramic capacitor in parallel
Capacitor for analog circuitry
Analog Audio Inputs
C
C
C
DC-decoupling capacitor at A/D- INL/R
converter inputs
390
390
nF
nF
nF
inAD
DC-decoupling capacitor at
microphone-input
MICIN
MICBI
inMI
Minimum-Capacitance at micro-
phone bias
3.3
LMICBI
Analog Audio Filter Outputs
C
Filter capacitor for headphone
amplifier
FILTL/R
OUTL/R
−20 %
470
+20 %
pF
FILT
high-Q type,
NP0 or C0G material
Analog Audio Output
Z
Analog output load with stereo
headphones
OUTL/R
16
Ω
AOL_HP
100
330
pF
DC/DC-Converter External Circuitry (please refer to application example)
C
VSENS blocking
(<100 mΩ ESR)
VSENS1/2
µF
V
1
V
L
Schottky diode threshold voltage DCSO1/2
VSENS1/2
0.39
TH
Ferrite core coil inductance
DCSO1/2
22
µH
S/PDIF Interface Analog Input
S/PDIF coupling capacitor
C
SPDI1/2
SPDIR
100
nF
SPI
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DATA SHEET
MAS 35x9F
4.6.2. Digital Characteristics
at T = T , V
, V
= 2.2 ... 3.6 V, f
= 18.432 MHz, Typ. values for T = 25 °C in P(L/M)QFP package
A
SUPD SUPA
Crystal A
Limit Values
Typ.
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Max.
Digital Supply Voltage
I
I
I
Current consumption
VDD,
XVDD,
I2CVDD
36
23
15
mA
mA
mA
2.2 V, sampling fre-
quency ≥ 32 kHz
SUPD
SUPD
SUPD
Current consumption
Current consumption
2.2 V, sampling fre-
quency ≤ 24 kHz
2.2 V, sampling fre-
quency
≤ 12 kHz
I
Total current at stand-by
10
µA
DSP off, Codec off,
DC/DC off, AD and
DAC off, no I C access
STANDBY
2
Digital Outputs and Inputs
O
O
Output low voltage
Output low voltage
PI<I>,
SOI,
SOC,
0.3
V
V
I
I
= 2 mA
DigL
DigH
load
load
V
−0.3
= −2 mA
SUPx
SOD,
EOD,
PRTR,
PRTW,
CLKO,
SYNC, PUP,
SPDO
Z
Input impedance
ALLDIGITAL
INPUTS
7
1
pF
µA
DigI
I
Digital input leakage cur-
rent
−1
0 V < V < V
pin SUPD
DLeak
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June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
2
4.6.2.1. I C Characteristics
at T = 25°C, V
= 2.2...3.6 V in P(L/M)QFP package
SUPI2C
Limit Values
Typ.
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Max.
I2C Input Specifications
fI2C
Upper limit I2C bus frequency I2CC
operation
400
300
300
kHz
ns
tI2C1
I2C START condition setup
time
I2CC, I2CD
I2CC, I2CD
tI2C2
I2C STOP condition setup
time
ns
tI2C3
tI2C4
tI2C5
I2C clock low pulse time
I2C clock high pulse time
I2CC
I2CC
I2CC
1250
1250
80
ns
ns
ns
I2C data setup time before
rising edge of clock
tI2C6
I2C data hold time after falling I2CC
edge of clock
80
ns
VI2COL
II2COH
I2C output low voltage
I2CC, I2CD
I2CC, I2CD
0.4
1
V
Iload = 3 mA
I2C output high leakage
current
µA
tI2COL1
I2C data output hold time after I2CC, I2CD
falling edge of clock
20
ns
ns
tI2COL2
I2C data output setup time
before rising edge of clock
I2CC, I2CD
250
fI2C = 400 kHz
VI2CIL
VI2CIH
tW
I2C input low voltage
I2C input high voltage
Wait time
I2CC, I2CD
I2CC, I2CD
I2CC, I2CD
0.3
4
VSUPI2C
VSUPI2C
ms
0.6
0
0.5
1/f
I2C
t
t
I2C3
I2C4
H
L
I2CC
t
t
t
t
I2C2
I2C1
I2C5
I2C6
H
L
I2CD as input
t
t
IC2OL1
I2COL2
H
L
I2CD as output
2
Fig. 4–20: I C timing diagram
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June 30, 2004; 6251-505-1DS
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DATA SHEET
MAS 35x9F
2
4.6.2.2. Serial (I S) Input Interface Characteristics (SDI, SDIB)
at T = T , V
, V
= 2.2 ... 3.6 V, f
= 18.432 MHz, Typ. values for T = 25 °C in P(L/M)QFP package
CRYSTAL A
A
SUPD SUPA
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
tSICLK
I2S clock input clock period
SI(B)C
325
ns
fS = 48 kHz Stereo,
32 bits per sample
(for demand mode see
Table 4–6)
tSIDS
I2S data setup time before
rising edge of clock (for
continuous data stream:
falling edge)
SI(B)C,
SI(B)D
50
ns
tSIDH
tSIIS
I2S data hold time
SI(B)D
50
50
ns
ns
I2S ident setup time before
rising edge of clock (for
continuous data stream:
falling edge)
SI(B)C,
SI(B)I
tSIIH
tbw
I2S ident hold time
Burst wait time
SI(B)I
50
ns
SI(B)C, SI(B)D 480
Table 4–6: Maximum allowed sample clock frequency in Demand Mode
f
(kHz)
f (MHz)
min. t
162
(ns)
SICLK
Sample
C
48, 32
44.1
6.144
5.6448
3.072
177
24, 16
22.05
12, 8
325
2.8224
1.536
354
651
11.025
1.4112
708
T
SICLK
H
SI(B)C
SI(B)I
L
H
L
H
L
SI(B)D
T
T
SIDH
SIDS
Fig. 4–21: Continuous data stream at serial input A or B. In this mode, the word strobe SI(B)I is not used and the
data are read at the falling edge of the clock (bit[2] in D0:346 is set).
Micronas
June 30, 2004; 6251-505-1DS
73
MAS 35x9F
DATA SHEET
Table 4–7: Allowed transmission delays of external data source MPEG1/2 Layer 2/3
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
tSTART48-320 Allowed delay time before
start of serial data
EOD
3.1
ms
ms
ms
ms
ms
ms
ms
ms
ms
48 kHz/s, 320 kbit/s
48 kHz/s, 64 kbit/s
24 kHz/s, 320 kbit/s
24 kHz/s, 32 kbit/s
12 kHz/s, 64 kbit/s
12 kHz/s, 16 kbit/s
8 kHz/s, 64 kbit/s
8 kHz/s, 8 kbit/s
tSTART48-64
tSTART24-320
tSTART24-32
tSTART12-64
tSTART12-16
tSTART8-64
tSTART8-8
5.7
transmission after assertion
of signal at EOD
4.2
9.2
23.1
25.6
34.8
38.4
1.3
tSTOP
Allowed delay time before
stop of serial data
Clock rate of input data
1 Mbit/s
EOD
transmission after
deassertion of signal at EOD
T
SICLK
H
SI(B)C
L
H
SI(B)I
L
T
T
T
SIIS
SIIH
H
SI(B)D
L
T
SIDH
SIDS
2
Fig. 4–22: Serial input of I S signal
4.6.2.3. Serial Output Interface Characteristics (SDO)
at T = T , V
, V
= 2.2 ... 3.6 V, f
= 18.432 MHz, Typ. values for T = 25 °C in P(L/M)QFP package
CRYSTAL A
A
SUPD SUPA
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
tSOCLK
tSOISS
tSOODC
I2S clock output frequency
SOC
325
ns
ns
ns
fS = 48 kHz Stereo
32 bits per sample
I2S word strobe delay time
after falling edge of clock
SOC,
SOI
0
0
I2S data delay time after
falling edge of clock
SOC,
SOD
74
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
T
SOCLK
H
SOC
L
H
SOI
L
T
T
SOISS
SOISS
H
SOD
L
T
SOODC
Fig. 4–23: Serial output interface timing
Vh
SOC
Vl
Vh
7
6 5 4 3 2 1 0
15 14 13 12 11 10
14
15
13 12 11 10
8
9
9
8
7 6 5 4 3 2 1 0
SOD
SOI
Vl
Vh
Vl
right 16-bit audio sample
left 16-bit audio sample
Fig. 4–24: Sample timing of the SDO interface in 16 bit/sample mode
D0:346 settings are
bit[14] = 0 (SOC not inverted)
bit[11] = 1 (SOI delay)
bit[5] = 0 (word strobe not inverted)
bit[4] = 1 (16 bits/sample)
Vh
...
...
SOC
Vl
Vh
SOD
SOI
...
31
30 29 28 27 26 25 ... 7
0
6 5 4 3 2 1 0
31 30 29 28 27 26 25
7
6
5
4
3
2
1
Vl
Vh
Vl
right 32-bit audio sample
left 32-bit audio sample
Fig. 4–25: Sample timing of the SDO interface in 32 bit/sample mode
D0:346 settings are
bit[14] = 0 (SOC not inverted)
bit[11] = 0 (no SOI delay)
bit[5] = 1 (word strobe inverted)
bit[4] = 0 (32 bits/sample)
Micronas
June 30, 2004; 6251-505-1DS
75
MAS 35x9F
DATA SHEET
4.6.2.4. S/PDIF Input Characteristics
at T = T , V
, V
= 2.2 ... 3.6 V, f
= 18.432 MHz, Typ. values for T = 25 °C in P(L/M)QFP package.
Crystal A
A
SUPD SUPA
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
VS
fs1
fs2
fs3
tP
Signal amplitude
Bi-phase frequency
Bi-phase frequency
Bi-phase frequency
Bi-phase period
Rise time
SPDI1, SPDI2, 200
SPDIR
500
1000
mVpp
MHz
MHz
MHz
ns
SPDI1, SPDI2,
SPDIR
2.048
2.822
3.072
326
±1000 ppm, fs = 48 kHz
SPDI1, SPDI2,
SPDIR
±1000 ppm,
fs = 44.1 kHz
SPDI1, SPDI2,
SPDIR
±1000 ppm, fs = 32 kHz
SPDI1, SPDI2,
SPDIR
at fs = 48 kHz, (highest
sampling rate)
tR
SPDI1, SPDI2,
SPDIR
0
65
ns
at fs = 48 kHz, (highest
sampling rate)
tF
Fall time
SPDI1, SPDI2,
SPDIR
0
65
ns
at fs = 48 kHz, (highest
sampling rate)
Duty cycle
SPDI
40
81
50
60
%
at bit value=1 and
fs = 48 kHz
tH1,L1
SPDI
163
ns
minimum/maximum pulse
duration with a level
above 90 % or below
10 % and at fs = 48 kHz
tH0,L0
SPDI
163
244
ns
minimum/maximum pulse
duration with a level
above 90 % or below
10 % and at fs = 48 kHz
t
t
R
F
t
t
H1
L1
Bit value = 1
Bit value = 0
t
t
L0
H0
t
P
Fig. 4–26: Timing of the S/PDIF input
76
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
4.6.2.5. S/PDIF Output Characteristics
at T = T , V
, V
= 2.2 ... 3.6 V, f
= 18.432 MHz, Typ. values for T = 25 °C in P(L/M)QFP package.
CRYSTAL A
A
SUPD SUPA
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
fs1
fs2
fs3
tP
Bi-phase frequency
Bi-phase frequency
Bi-phase frequency
Bi-phase period
SPDO
SPDO
SPDO
SPDO
3.072
2.822
2.048
326
MHz
MHz
MHz
ns
fs = 48 kHz
fs = 44.1 kHz
fs = 32 kHz
at fs = 48 kHz, (highest
sampling rate)
tR
tF
Rise time
Fall time
SPDO
SPDO
SPDO
SPDO
0
0
2
2
ns
ns
%
Cload = 10 pF
Cload = 10 pF
Duty cycle
50
tH1,L1
tH0,L0
VS
163
ns
minimum/maximum pulse
duration with a level
above 90% or below 10%
and at fs = 48 kHz
SPDO
SPDO
326
ns
minimum/maximum pulse
duration with a level
above 90% or below 10%
and at fs = 48 kHz
Signal amplitude
VSUPD
t
t
R
F
t
t
H1
L1
Bit value = 1
Bit value = 0
t
t
L0
H0
t
P
Fig. 4–27: Timing of the S/PDIF output
4.6.2.6. PIO as Parallel Input Interface: DMA Mode
the controller. Please refer to Figure for the exact tim-
ing.
In decoding mode, the data transfer can be started
after the EOD pin of the MAS 35x9F is set to “high”.
After verifying this, the controller signalizes the send-
ing of data by activating the PR line. The MAS 35x9F
responds by setting the RTR line to the “low” level. The
MAS 35x9F reads the data PI[19:12] and sets RTR to
low after rising edge of PR. After RTR is set to high,
the mC sets PR to low. The next data word write oper-
ation will be initialized again by setting the PR line via
The procedure above will be repeated until the
MAS 35x9F sets the EOD signal to “0” which indicates
that the transfer of one data block has been executed.
Subsequently, the controller should set PR to “0”, wait
until EOD rises again and then repeat the procedure to
send the next block of data. The DMA buffer for MPEG
decoding is 30 bytes long. The size for G.729 is 10
bytes.
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 4–8: PIO input DMA mode timing
Table 4–9: t_clm in MP3
Symbol
Pin Name Min.
Max.
Sample rate
[kHz]
t_clm [ns]
f_clm [MHz]
t
t
t
PR, EOD
PR, RTR
PI[19:12]
10 ns
2000 µs
t_clm
st
48 or 32
44.1
41
24.5760
22.5792
12.2880
11.2896
6.1440
r
44
2*t_clm-
33 ns
set1
24 or 16
22.05
81
t
t
t
PI[19:12]
PI[19:12]
RTR
dep. on
appl.
89
set2
h
12 or 8
11.025
163
177
5*t_
clm
5.6448
MP3:
60*t_clm
5*t_
clm
rtrq
AAC:
140*t_clm
Table 4–10: t_clm in AAC
Sample rate
[kHz]
t_clm [ns]
f_clm [MHz]
t
PR
5*t_
clm
pr
48 or 32
44.1
33
30.720
28.224
15.360
14.112
7.680
t
t
t
PR, RTR
PR, EOD
EOD
t_clm
rpr
35
t_clm
eod
eodq
150*t_clm1)
200 ms1)
24 or 16
22.05
65
1) See Parallel I/O Application Note,
Order no. 6251-590-2-1IC.
71
12 or 8
11.025
130
142
7.056
tst
teod
teodq
/EOD
/EOD
GPIO
tpr = Twr
tr
PR
/CS
/WR
PR
MAS3509F
/RTR
trtrq
trpr
Customer IC
GPIO
/RTR
tset1 = Tchl_dov
th
tset2
Twrh
_csh
PI(19:12)
PI(19:12)
D7-D0
Fig. 4–28: Handshake protocol for writing MPEG data to the PIO-DMA
78
June 30, 2004; 6251-505-1DS
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DATA SHEET
MAS 35x9F
4.6.2.7. PIO as Parallel Input Interface:
Program Download Mode
Table 4–11: PIO Program Download Mode timing
Symbol Pin
Min.
0
Max.
Unit
µs
Handshake for PIO input in Program Download
Mode is accomplished through the RTR, PCS, and
PI12..PI19 signal lines (see Fig. 4–29). The PR line
should be set to low level.
t
t
t
t
t
t
RTR, PCS
PCS
0
1
2
3
4
5
150
0
ns
PCS, RTR
RTR
30
5
ns
The MAS 35x9F will drive RTR low as soon as it is
ready to receive a byte and RTR will stay low until one
byte has been written. Writing of a byte is performed
with a PCS pulse, driven by the microcontroller. The
MAS 35x9F reads data after the falling edge of PCS
and will finish the cycle by setting RTR to high level
after the rising edge of PCS. The next data transfer is
initialized by the MAS 35x9F by driving the RTR line.
0.4
50
50
µs
PI
ns
PI
ns
t
t
t
t
0
1
2
3
RTW
PIxx
PCS
t
t
4
5
Fig. 4–29: PIO program download mode timing
Micronas
June 30, 2004; 6251-505-1DS
79
MAS 35x9F
DATA SHEET
4.6.2.8. PIO as Parallel Output Interface
Table 4–12: PIO output mode timing
Some downloadable software may use the PIO inter-
face (lines PI19...PI12) as output. The data transfer
rate and conditions are defines by the software func-
tion.
Symbol Pin
Min.
RTW, PCS 0.010
PCS 0.330
PCS, RTW 0.010
Max.
Unit
µs
t
t
t
t
t
t
1800
0
1
2
3
4
5
µs
Handshaking for PIO output mode is accomplished
through the RTW, PCS, and PI12..PI19 signal lines
(see Fig. 4–30). The PR line has to be set to high level.
µs
RTW
PI
0.330
0.330
0.081
10000
µs
RTW will go low as soon as a byte is available in the
output buffer and will stay low until a byte has been
read. Reading of a byte is performed with a PCS
pulse. Data is latched out from the MAS on the falling
edge of PCS and removed from the bus on the rising
edge of PCS.
µs
PI
µs
t
t
t
t
0
1
2
3
RTW
PIxx
PCS
t
t
4
5
Fig. 4–30: Output timing
80
June 30, 2004; 6251-505-1DS
Micronas
DATA SHEET
MAS 35x9F
4.6.3. Analog Characteristics
at T = T , V
, V
= 2.2 to 3.6 V, V
= 2.2 to 3.6 V, f
= 13 to 20 MHz,
A
SUPDn
SUPx
SUPA
CRYSTAL
typical values at T = 25 °C and f
= 18.432 MHz in P(L/M)QFP package
A
CRYSTAL
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
Analog Supply
IAVDD
Current consumption analog
audio
AVDD0/1
AVDD0/1
5
mA
VSUPA = 2.2 V, Mute
IQOSC
Current consumption crystal
oscillator
200
µA
Codec = off
DSP = off
DC/DC = on
ISTANDBY
10
Codec = off
DSP = off
DC/DC = off
Crystal Oscillator
VDCCLK
VACLK
DC voltage at oscillator pins
XTI, XTO
0.5
VSUPA
Clock amplitude
0.5
VSUPA VPP
if crystal is used
VSUPA = 2.2 V
−0.5
CIN
Input capacitance
Output resistance
3
pF
ROUT
XTO
220
125
94
Ω
V
V
SUPA = 2.7 V
SUPA = 3.3 V
Analog Reference
VAGNDC Analog Reference Voltage
AGNDC
V
RL >> 10 MΩ,
referred to VREF
VSUPA
bits[15], [14] in
register 6Ahex
1.1
1.3
1.6
>2.2 V
>2.4 V
>3.0 V
VSUPA
00
01
10
VMICBI
Bias voltage for microphone
MICBI
MICBI
bits[15], [14] in
register 6Ahex
1.8
>2.2 V
>2.4 V
>3.0 V
00
01
10
2.13
2.62
180
RMICBI
IMAX
Source resistance
Ω
Maximum current microphone MICBI
bias
µA
VSUPA
>2.2 V
bits[15], [14] in
register 6Ahex
300
00
Micronas
June 30, 2004; 6251-505-1DS
81
MAS 35x9F
DATA SHEET
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
Analog Audio Input
VAI
Analog line input clipping
level (at minimum analog
INL/R
Vpp
VSUPA
bits[15], [14] in
register 6Ahex
input gain, i.e. −3 dB)
2.2
2.6
3.2
>2.2 V
>2.4 V
>3.0 V
VSUPA
00
01
10
VMI
Microphone input clipping
level (at minimum analog
input gain, i.e. +21 dB)
MICIN
mVpp
bits[15], [14] in
register 6Ahex
141
167
282
97
>2.0 V
>2.4 V
>3.0 V
00
01
10
RinAI
Analog line input resistance
Microphone input resistance
INL/R
kΩ
kΩ
at minimum analog input
gain, i.e. −3 dB
20
at maximum analog input
gain, i.e. +19.5 dB
67
94
not selected
RinMI
MICIN
at minimum analog input
gain, i.e. −21 dB
8
at maximum analog input
gain, i.e. +43.5 dB
94
74
not selected
SNRAI
SNRMI
THDAI
Signal-to-noise ratio of line
input
INL/R
dB(A) BW = 20 Hz...20 kHz,
analog gain = 0 dB,
input 1 kHz at VAI−20 dB
Signal-to-noise ratio of
microphone input
MICIN
73
dB(A) BW = 20 Hz...20 kHz,
analog gain = +21 dB,
input 1 kHz at VMI−20 dB
Total harmonic distortion of
analog inputs
INL/R
MICIN
0.01
0.02
%
BW = 20 Hz...20 kHz,
analog gain = 0 dB,
resp. 24 dB,
input 1 kHz at
−3 dBFS = VAI−6 dB
resp. VMI−6 dB
XTALKAI
PSRRAI
Crosstalk attenuation
left/right channel
(analog inputs)
INL/R
MICIN
80
dB
f = 1 kHz, sine wave,
analog gain = 0 dB,
input = −3 dBFS
Power supply rejection ratio
for analog audio inputs
AVDD0/1,
INL/R
MICIN
45
20
dB
dB
1 kHz sine at 100 mVrms
≤100 kHz sine at
100 mVrms
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June 30, 2004; 6251-505-1DS
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DATA SHEET
MAS 35x9F
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
Audio Output
VAO1
Analog output voltage AC
OUTL/R
RL ≥1 kΩ
input = 0 dBFS digital
VSUPA
bits[15], [14] in
register 6Ahex
at 0 dB output gain
at +3 dB output gain
1.56
1.84
2.27
2.20
2.60
3.20
Vpp
Vpp
mV
>2.2 V
>2.4 V
>3.0 V
>2.2 V
>2.6 V
>3.2 V
00
01
10
00
01
10
dVAO1
Deviation of DC-level at
analog output for AGNDC-
Voltage
OUTL/R
−20
20
VAO2
Analog output voltage AC
OUTL/R
RLis 16 Ω headphone and
22 Ω series resistor
Input = 0 dBFS digital
(see Fig. 5–1 on page 89)
VSUPA
bits[15], [14] in
register 6Ahex
at 0 dB output gain
1.56
1.84
2.27
2.00
2.40
3.00
Vpp
Vpp
Ω
>2.2 V
>2.4 V
>3.0 V
>2.2 V
>2.6 V
>3.2 V
00
01
10
00
01
10
at +3 dB output gain
RoutAO
SNRAO
Analog output resistance
OUTL/R
6
analog gain = +3 dB,
input = 0 dBFS digital
Signal-to-noise ratio of analog OUTL/R
output
94
dB(A) RL≥16 Ω
BW = 20 Hz...20 kHz,
analog gain = 0 dB
input = −20 dBFS
THDAO
Total harmonic distortion
(headphone)
OUTL/R
OUTL/R
0.03
0.05
%
for RL≥16 Ω plus 22 Ω
series resistor
(see Fig. 5–1 on page 89)
for RL≥1 kΩ
0.003 0.01
LevMuteAO
Mute level
−113
dBV
A-weighted
BW = 20 Hz...22 kHz,
no digital input signal,
analog gain = mute
Micronas
June 30, 2004; 6251-505-1DS
83
MAS 35x9F
DATA SHEET
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
XTALKAO
Crosstalk attenuation left/right OUTLR
channel (headphone)
80
dB
f = 1 kHz, sine wave,
OUTL/R: RL≥16 Ω
(see Fig. 5–1 on page 89)
analog gain = 0 dB
input = −3 dBFS
PSRRAO
Power supply rejection ratio
for analog audio outputs
AVDD0/1
OUTL/R
70
35
dB
dB
1 kHz sine at 100 mVrms
≤100 kHz sine at
100 mVrms
4.6.4. DC/DC Converter Characteristics
at T = T , V = 1.2 V, V = 3.0 V, f = 18.432 MHz, f = 384 kHz, PWM mode, L = 22 µH, in P(L/M)QFP pack-
A
in
outn
clk
sw
age (unless otherwise noted) Typ. values for T = 25 °C
A
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
VIN
VIN
Minimum start-up input
voltage
0.9
V
ILOAD ≤ 1 mA,
DCCF = 5050hex (reset)
1)
Minimum operating input
voltage
DC1
DC2
0.7
0.8
V
V
V
ILOAD = 50 mA,
DCCF = 5050hex (reset)
DC1
DC2
1.1
1.2
ILOAD = 200 mA,
DCCF = 5050hex (reset)
VOUT
Programmable output voltage VSENSn
range
2.0
3.5
Voltage settings in DCCF
register (I2C subaddress
76hex
)
VOTOL
ILOAD1
ILOAD2
Output voltage tolerance
VSENSn
VSENSn
−4
4
%
ILOAD = 20 mA
TA = 25 °C
2)
Output current
1 battery cell
200
600
mA
mA
%/V
%
VIN = 0.9...1.5 V, 330 µF
VIN = 1.8...3.0 V, 330 µF
ILOAD = 20 mA
Output current
2 battery cells
dVOUT
/
Line regulation
VSENSn
VSENSn
0.7
dVIN/VOUT
dVOUT
/
Load regulation
−1.8
ILOAD = 20...200 mA,
VIN = 2.4 V, VOUT = 3.5 V
VOUT
hmax
Maximum efficiency
Switching frequency
95
%
fswitch
DCSOn
DCSOn
297
384
250
576
kHz
(see Section 2.6.2. on
page 12), (see Table 3–3)
fstartup
Switching frequency during
start-up
kHz
VSENSn < 1.9 V
1) Since the regulators are bootstrapped, once started they will operate down to 0.7 V input voltage
2) PFM mode regulates approx. 1% higher
84
June 30, 2004; 6251-505-1DS
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DATA SHEET
MAS 35x9F
Limit Values
Symbol
Parameter
Pin Name
Unit
µA
Test Conditions
Min.
Typ.
75
Max.
3)
IsupPFM1
IsupPFM2
IsupPWM1
IsupPWM2
Ilnmax
Supply current in PFM mode
VSENS1
VSENS2
135
265
325
1
Supply current in PWM mode VSENS1
VSENS2
µA
VSENSn
3)
4)
NMOS switch current limit
(low side switch)
DCSOn,
DCSGn
A
PWM-Mode
PFM-Mode
0.4
70
A
IIptoff
PMOS switch turnoff current
(rectifier switch)
DCSOn
VSENSn
mA
Ron
NMOS switch on Resistance
(low side switch)
DCSO1,
DCSG1
170
280
0.1
mΩ
mΩ
µA
DCSO2,
DCSG2
ILEAK
Leakage current
DCSOn,
DCSGn
Converter off, no load
3) Current into VSENSn Pin. VIN > VOUT + 0.4V; no DC/DC-Converter switching action present
4) Add. current of oscillator at PIN AVDD0/1, (see Section 4.6.3. on page 81)
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
4.6.5. Typical Performance Characteristics
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (V
= 3.5 V)
DCDC2 (V
= 3.5 V)
OUT
OUT
100
80
60
40
20
0
100
80
60
40
20
0
3.0 V
3.0 V
1.8 V
1.8 V
V :
3.0 V
2.4 V
1.8 V
V :
3.0 V
2.4 V
1.8 V
IN
IN
PFM
PWM
PFM
PWM
−4
−4
−3
−2
−1
−3
−2
−1
10
1
10
1
10
10
10
10
10
10
Load Current (A)
Load Current (A)
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (V
= 3.0 V)
DCDC2 (V
= 3.0 V)
OUT
OUT
100
80
60
40
20
0
100
80
60
40
20
0
2.4 V
2.4 V
0.9 V
0.9 V
V :
V :
IN
IN
2.4 V
1.5 V
1.2 V
0.9 V
2.4 V
1.5 V
1.2 V
0.9 V
PFM
PFM
PWM
PWM
−4
−4
−3
−2
−1
−3
−2
−1
10
1
10
1
10
10
10
10
10
10
Load Current (A)
Load Current (A)
Fig. 4–31: Efficiency vs. Load Current
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DATA SHEET
MAS 35x9F
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (V
= 2.2 V)
DCDC2 (V
= 2.2 V)
OUT
OUT
100
80
60
40
20
0
100
80
60
40
20
0
1.5 V
1.5 V
0.9 V
0.9 V
V :
1.5 V
1.2 V
0.9 V
V :
1.5 V
1.2 V
0.9 V
IN
IN
PFM
PFM
PWM
PWM
−4
−4
−3
−2
−1
−3
−2
−1
10
1
10
1
10
10
10
10
10
10
Load Current (A)
Load Current (A)
Maximum Load Current
vs. Input Voltage
Maximum Load Current
vs. Input Voltage
0.8
0.6
0.4
0.2
0.8
0.6
0.4
DCDC1
DCDC2
V
:
V
:
out
out
2.2 V
3.0 V
3.5 V
2.2 V
3.0 V
3.5 V
PFM
PFM
PWM
PWM
0.2
0
0
0.0
0.0
1.0
2.0
3.0
1.0
2.0
3.0
Input Voltage (V)
Fig. 4–32: Maximum Load Current vs. Input Voltag
Note: Efficiency is measured as V × I / (V × I ).
Input Voltage (V)
SENSn
LOAD
in
in
I
is not included (Oscillator current)
AVDD
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MAS 35x9F
DATA SHEET
Loadregulation
Loadregulation
at V
= 2.7 V, 2.5 V
at V
= 3.0 V, 3.5 V
OUT
OUT
2.75
2.7
3.55
3.5
1.5 V
1.5 V
2.65
3.45
0.9 V
0.9 V
V :
1.5 V
V :
1.5 V
IN
IN
2.6
3.4
1.2 V
0.9 V
1.2 V
0.9 V
2.55
3.05
2.5
3.0
2.45
2.4
2.95
2.9
DCDC1
50
DCDC1
50
0
100
150
200
0
100
150
200
Load Current (mA)
Load Current (mA)
No-Load Battery Current
V
= 3.0 V
OUT
10
8
Both DCDC running in PWM
One DCDC running in PFM
6
4
2
0
0.5
1.0
1.5
2.0
2.5
3.0
Input Voltage (V)
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DATA SHEET
MAS 35x9F
5. Application
5.1. Typical Application in a Portable Player
− MMC/SDI-Card or SMC/CF2+ used as storage media
− Dashed lines show optional (external) devices
PCSQ
PI19
PI18
PI17
PI16
PI15
PI14
PI13
PI12
SOD
SOI
VSENS1
DVS
I2CVDD
XVDD
VDD
XVSS
VSS
POR
XTO
XTI
TE
INR
SOC
SID
INL
SII
MICBI
SIC
MICIN
AGNDC
SPDO
Fig. 5–1: Application circuit of the MAS 35x9F. For connections of the DC/DC converters, please refer to Fig. 5–2.
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
5.2. Recommended DC/DC Converter Application Circuit
(Power optimized scenario, (see Fig. 2–7 on page 13)).
VBAT
L1 = 22 µH
DCSO1
D1, Schottky
+
AVDD0/1
VSENS1
C3 = 330 µF
Vin (Input Voltage)
(0.9..1.5 V)
VDC1
e.g. 2.2 V
C1 = 330 µF
(low ESR)
+
DCSG1
VSS, XVSS
D
DCEN
Power-On Push Button
L2 = 22 µH
DCSO2
D2, Schottky
VSENS2
VDC2
e.g. 3.0 V
for µC,
Storage Media
C2 = 330 µF
(low ESR)
+
Star Point
Ground Connection
very close to Pins
DCSG2
DCSG1 and DCSG2
VREF
D
AVSS0/1
A
A
Fig. 5–2: External circuitry for the DC/DC converters
For turn-on voltage of DSP and codec, please refer
to Section 2.11.2.1.
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DATA SHEET
MAS 35x9F
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June 30, 2004; 6251-505-1DS
91
MAS 35x9F
DATA SHEET
6. Data Sheet History
1. Preliminary data sheet: “MAS 35x9F, MPEG Layer
2/3, AAC Audio Decoder, G.729 Annex A Codec”,
Aug. 01, 2001, 6251-505-1PD. First release of the
preliminary data sheet.
2. Data Sheet: “MAS 35X9F MPEG Layer 2/3, AAC
Audio Decoder, G.729 Annex A Codec”, June 30,
2004, 6251-505-1DS. First release of the data
sheet.
Major changes:
– New package diagrams were included for
PLQFP64-1, PMQFP64-2, PQFN64-1
– Functional description of the MP3 Block Input Mode
now available for improved input timing behavior of
the MPEG 1/2/2.5 Layer3 decoder
– Important advice for turn-on and operating voltage
– Changes in configuration registers
– Tables were added: PIO input DMA mode timing;
Sample rate in MP3; Sample rate in AAC
– Handshake protocol for writing MPEG data to the
PIO-DMA was added.
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-505-1DS
92
June 30, 2004; 6251-505-1DS
Micronas
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