VPX3216BQG [TDK]
Consumer Circuit, PQFP44, PLASTIC, QFP-44;型号: | VPX3216BQG |
厂家: | TDK ELECTRONICS |
描述: | Consumer Circuit, PQFP44, PLASTIC, QFP-44 商用集成电路 |
文件: | 总80页 (文件大小:751K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
VPX 3220 A,
VPX 3216 B,
VPX 3214 C
Video Pixel Decoders
MICRONAS
Edition July 1, 1996
6251-368-2PD
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
5
5
5
5
1.
Introduction
1.1.
1.2.
1.3.
Difference between VPX 3220 A and VPX 3216 B
Difference between VPX 3216 B and VPX 3214 C
System Architecture
6
2.
Functional Description
Analog Front-End
6
2.1.
6
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.1.5.
2.2.
Input Selector
6
Clamping
6
Automatic Gain Control
Digitally Controlled Clock Oscillator
Analog-to-Digital Converters
Color Decoder
7
7
7
7
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.2.6.
2.2.7.
2.2.8.
2.2.9.
2.3.
IF-Compensation
7
Demodulator
8
Chrominance Filter
8
Frequency Demodulator
Burst Detection
8
9
Color Killer Operation
Delay Line/Comb Filter
Luminance Notch Filter
YCbCr Color Space
Component Processing
Horizontal Resizer
9
10
11
11
12
13
13
13
14
14
15
15
15
15
16
16
16
2.3.1.
2.3.2.
2.3.3.
2.3.4.
2.4.
Skew Correction
Contrast, Brightness, and Noise Shaping
C C Upsampler
b
r
Color Space Stage
2.4.1.
2.4.2.
2.4.3.
2.4.4.
2.4.4.1.
2.5.
Color Space Selection
Compression 24 → 8 Bits
Inverse Gamma Correction
Alpha Key
Alpha Key as Static Control Signal
Output Pixel Format
Output Ports
2.5.1.
2.5.2.
Output Port Formats
2
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
18
18
18
18
18
18
18
18
20
20
23
24
24
26
3.
Video Timing
3.1.
Video Reference Signals HREF and VREF
HREF
3.1.1.
3.1.2.
3.1.3.
3.2.
VREF
Odd/Even
Operational Modes
Open Mode
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.3.
Forced Mode
Scan Mode
Transition Behavior
Windowing the Video Field
Video Data Transfer
Synchronous Output
Asynchronous Output
3.4.
3.4.1.
3.4.2.
27
27
27
27
27
28
29
29
35
41
4.
Serial Interface A
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
Overview
2
I C-Bus Interface
Reset and IC Address Selection
Protocol Description
FP Control and Status Registers
2
I C Initialization
2
I C Control and Status Registers
FP Control and Status Registers
Initial Values on Reset
43
43
43
43
43
43
44
44
44
44
44
44
44
44
45
45
45
45
5.
JTAG Boundary-Scan, Test Access Port (TAP)
General Description
5.1.
5.2.
TAP Architecture
5.2.1.
5.2.2.
5.2.3.
5.2.4.
5.2.5.
5.2.6.
5.3.
TAP Controller
Instruction Register
Boundary Scan Register
Bypass Register
Device Identification Register
Master Mode Data Register
Exception to IEEE 1149.1
IEEE 1149.1–1990 Spec Adherence
Instruction Register
5.4.
5.4.1.
5.4.2.
5.4.3.
5.4.4.
5.4.5.
5.4.6.
5.4.7.
Public Instructions
Self-test Operation
Test Data Registers
Boundary-Scan Register
Device Identification Register
Performance
MICRONAS INTERMETALL
3
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
49
49
50
53
54
55
57
57
59
59
60
60
60
60
61
62
63
64
65
66
68
69
70
71
73
74
74
75
6.
Specifications
6.1.
Outline Dimensions
6.2.
Pin Connections and Short Descriptions
Pin Descriptions
6.3.
6.4.
Pin Configuration
6.5.
Pin Circuits
6.6.
Electrical Characteristics
6.6.1.
6.6.2.
6.6.3.
6.6.4.
6.6.5.
6.6.6.
6.6.7.
6.6.8.
6.6.9.
6.6.10.
6.6.10.1.
6.6.11.
6.6.12.
6.6.12.1.
6.6.12.2.
6.6.12.3.
6.6.12.4.
6.6.13.
6.6.13.1.
6.6.13.2.
6.6.14.
Absolute Maximum Ratings
Recommended Operating Conditions
Power Consumption
Characteristics, Reset
Input Characteristics of RES and OE
Recommended Crystal Characteristics
XTAL Input Characteristics
Characteristics, Analog Video Inputs
Characteristics, Analog Front-End and ADCs
Characteristics of the JTAG Interface
Timing of the Test Access Port TAP
2
Characteristics, I C-Bus Interface
Digital Video Interface
Characteristics, Synchronous Mode, 13.5 MHz Data Rate, “Single Clock”
Characteristics, Synchronous Mode, 20.25 MHz Data Rate, “Single Clock”
Characteristics, Synchronous Mode, 13.5 MHz Data Rate, “Double Clock”
Characteristics, Asynchronous Mode
Characteristics, TTL Output Driver
TTL Output Driver Type A
TTL Output Driver Type B
Characteristics, Enable/Disable of Output Signals
77
77
79
80
1.
2.
3.
4.
Introduction for Addendum
New Output Timing – NewVACT
Low Power Mode
Data Sheet History
4
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Video Pixel Decoder Family
– VBI bypass mode for Teletext, Closed Caption, and
Intercast
Release Notes: Revision bars indicate significant
changes to the previous edition.
– 44-pin plastic package (PLCC, TQFP)
– total power consumption under 1 W
2
– I C serial control, selectable power-up default state
1. Introduction
– on-chip clock generation
TheVideoPixelDecoder(VPX)isafull-featurevideoac-
quisition IC for consumer video and multimedia applica-
tions. All of the processing necessary to convert an ana-
log video signal into a digital component stream has
been integrated onto a single 44-pin IC. Its notable fea-
tures include:
– IEEE 1149.1 (JTAG) boundary scan interface
VPX 3220 A, VPX 3216 B, and VPX 3214 C are pin and
software compatible, but differ slightly in the feature set.
1.1. Difference between VPX 3220 A and VPX 3216 B
– single chip multistandard color decoding NTSC/PAL/
SECAM/S-VHS, NTSC with chroma comb filter.
VPX 3220 A performs low-pass filtering before resam-
pling the data, whereas VPX 3216 B does not. For more
info, see Fig. 1–1 and refer to section 2.3.
– two 8-bit video A/D converters with clamping and au-
tomatic gain control (AGC)
– four analog inputs with integrated selector for
3 composite video sources (CVBS), or
2 YC sources (SVHS), or
1.2. Difference between VPX 3216 B and VPX 3214 C
2 composite video sources and one YC source.
The VPX 3214 C is based on the VPX 3216 B but without
color space conversion. VPX 3214 C supports only
– automatic standard detection
YC C 4:2:2.
b
r
– horizontalandverticalsyncdetectionforallstandards
– hue, brightness, contrast, and saturation control
– horizontal resizing between 32 and 1056 pixel/line
– vertical resizing by line dropping
1.3. System Architecture
The block diagram in Fig. 1–1 illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, andAGC. Thecolordecodersep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The component processing stage resizes
the YCbCr samples, adjusts the contrast and bright-
ness, and interpolates the chroma. The color space
– high quality anti-aliasing filter (VPX 3220 A only)
– ITU-R601 level compatible
– YC C (4:4:4, 4:2:2, or 4:1:1) or
b
r
γ-corrected RGB 4:4:4 (15, 16, or 24 bits)
compressed Video (DPCM 8 bit)
(VPX 3214 C supports only YCrCb 4:2:2)
–1
stage contains a dematrix, a γ correction, a DPCM-like
– alpha key generation
encoder, and an alpha key generator. The format stage
arranges the samples into the selected byte format and
(in the case of asynchronous output) buffers the data for
output.
(only VPX 3220 A, and VPX 3216 B)
– 8-bit or 16-bit synchronous output mode
– asynchronous output mode via FIFO with status flags
H/V
Sync
Sync
Skew
CVBS/Y
YCbCr/
A
Y
RGB
Luma
Filter
YCbCr
Chroma
Demod.
Alpha
Key
B
C C
b
r
Chroma
Line Store
Clock
Component
Processing
Output
MUX
Sampling
Color Decoder
Color Space
Fig. 1–1: Block diagram of the VPX
MICRONAS INTERMETALL
5
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
CVBS Luma Chroma
2. Functional Description
2.1. Analog Front-End
CVBS S-VHS
VIN1
VIN2
VIN3
CIN
n
n
n
n
n
n
n
This block provides the analog interfaces to all video in-
puts and mainly carries out analog-to digital conversion
for the following digital video processing. A block dia-
gram is given in Fig. 2–2.
3
2
0
0
1
2
n
Most of the functional blocks in the front-end are digitally
controlled (clamping, AGC, and clock-DCO). The con-
trol loops are closed by the Fast Processor (‘FP’) em-
bedded in the decoder.
Fig. 2–1: Combinations and types of input signals
2.1.2. Clamping
2.1.1. Input Selector
ThecompositevideoinputsignalsareAC-coupledtothe
IC. The clamping voltage is stored on the coupling ca-
pacitors and is generated by digitally controlled current
sources. The clamping level is the back porch of the vid-
eo signal. S-VHS chroma is also AC-coupled. The input
pin is internally biased to the center of the ADC input
range.
Uptofouranaloginputscanbeconnected. Theyallmust
be AC-coupled. Two of them (VIN2 and VIN3) are for in-
put of composite video or S-VHS luma signal. These in-
puts are clamped to the sync back porch and are ampli-
fied by a variable gain amplifier. One input (CIN) is for
connection of S-VHS carrier-chrominance signal. This
input is internally biased and has a fixed gain amplifier.
The fourth one (VIN1) can be used for both functions
(see Fig. 2–2). For possible combinations and types of
input signals, see Fig. 2–1.
2.1.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in
64 logarithmic steps to the optimal range of the ADC.
reference
generation
VIN3
CVBS/Y
AGC
+6/–4.5 dB
digital
CVBS
or Y
VIN2
VIN1
CIN
8
clamp
level
ADC
CVBS/Y
DAC
gain
to
color
decoder
CVBS/
Y/C
digital
chroma
8
bias/
C
ADC
clamp
select
level
system
clocks
frequ.
DVCO
±150
ppm
DAC
freq.
doubler
frequ.
divider
20.25 MHz
Fig. 2–2: Analog front-end
6
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2.1.4. Digitally Controlled Clock Oscillator
2.2.1. IF-Compensation
With off-air or mistuned reception, any attenuation at
The clock generation is also a part of the analog front-
end. The crystal oscillator is controlled digitally by the
control processor; the clock frequency can be adjusted
within ±150 ppm if the recommended crystal is used.
higher frequencies or asymmetry around the color sub-
carrier is compensated. Three different settings of the
IF-compensation are possible:
– flat (no compensation)
– 6 dB/octave
2.1.5. Analog-to-Digital Converters
– 12 dB/octave
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8-bit reso-
lution. An integrated bandgap circuit generates the re-
quired reference voltages for the converters. The two
ADCs are of a 2-stage subranging type.
2.2. Color Decoder
In this block, the entire luma/chroma separation and
multistandardcolordemodulationiscarriedout. Thecol-
or demodulation uses an asynchronous clock, thus al-
lowing a unified architecture for all color standards.
Fig. 2–3: Frequency response of chroma IF-com-
pensation
Both luma and chroma are processed to an orthogonal
sampling raster. Luma and chroma delays are matched.
The total delay of the decoder is adjustable by a FIFO
memory. Therefore, even when the display processing
delay is included, a processing delay of exactly 64 µsec
can be achieved.
2.2.2. Demodulator
The entire signal (which might still contain luma) is now
quadrature-mixed to the baseband. The mixing frequen-
cy is equal to the subcarrier for PAL and NTSC, thus
achieving the chroma demodulation. For SECAM, the
mixing frequency is 4.286 MHz giving the quadrature
baseband components of the FM modulated chroma.
After the mixer, a lowpass filter selects the chroma com-
ponents; a downsampling stage converts the color dif-
ference signals to a multiplexed half-rate data stream.
The color decoder output is YC C in a 4:2:2 format.
r
b
The subcarrier frequency in the demodulator is gener-
ated by direct digital synthesis; therefore, substandards
such as PAL 3.58 or NTSC 4.43 can also be demodu-
lated.
MICRONAS INTERMETALL
7
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2.2.3. Chrominance Filter
2.2.4. Frequency Demodulator
The demodulation is followed by a lowpass filter for the
color difference signals for PAL/NTSC. SECAM requires
a modified lowpass function with a bell-filter characteris-
tic. Attheoutputofthelowpassfilter, alllumainformation
is eliminated.
The frequency demodulator for demodulating the
SECAM signal is implemented as a CORDIC-structure.
It calculates the phase and magnitude of the quadrature
components by coordinate rotation.
The phase output of the CORDIC processor is differen-
tiated to obtain the demodulated frequency. After a pro-
grammable deemphasis filter, the Dr and Db signals are
The lowpass filters are calculated in time multiplex for
the two color signals. Three bandwidth settings (narrow,
normal, broad) are available for each standard. The filter
passband can be shaped with an extra peaking term at
1.25 MHz.
scaled to standard C C amplitudes and fed to the cross-
r
b
over-switch.
dB
0
dB
0
–1
–2
PAL/
NTSC
–10
–3
–4
–5
–20
broad
–6
normal
–7
–30
narrow
–8
–9
–40
–10
–11
MHz
0.01
0.1
1.0
–50
MHz
0
1
2
3
4
5
Fig. 2–5: Frequency response of SECAM
deemphasis
dB
0
–10
–20
SECAM
2.2.5. Burst Detection
–30
–40
–50
In the PAL/NTSC-system, the burst is the reference for-
the color signal. The phase and magnitude outputs of
the CORDIC are gated with the color key and used for
controlling the phase-lock-loop (APC) of the demodula-
tor and the automatic color control (ACC) in PAL/NTSC.
MHz
0
1
2
3
4
5
Fig. 2–4: Frequency response of chroma filters
The ACC has a control range of +30...–6 dB.
ForSECAMdecoding, thefrequencyoftheburstismea-
sured. Thus, the current chroma carrier frequency can
be identified and is used to control the SECAM proces-
sing. The burst measurements also control the color kill-
er operation.
8
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
CVBS
Luma
2.2.6. Color Killer Operation
Y
Notch
filter
Y
Chroma
Chroma
Process.
Chroma
Process.
The color killer uses the burst-phase, -frequency mea-
surement to identify a PAL/NTSC or SECAM color sig-
nal. For PAL/NTSC, the color is switched off (killed) as
long as the color subcarrier PLL is not locked. For
SECAM, the killer is controlled by the toggle of the burst
frequency. The burst amplitude measurement is used to
switch-off the color if the burst amplitude is below a pro-
grammable threshold. Thus, color will be killed for very
noisy signals. The color amplitude killer has a program-
mable hysteresis.
C C
r
C C
r
b
b
a) conventional
b) S-VHS
CVBS
Notch
filter
Y
1 H
Chroma
C C
Delay
Process.
r
b
c) compensated
2.2.7. Delay Line/Comb Filter
The color decoder uses one fully integrated delay line.
Only active video is stored.
Notch
filter
Y
CVBS
1 H
Delay
The delay line application depends on the color stan-
dard:
– NTSC:
– PAL:
combfilter or color compensation
Chroma
Process.
C C
r
b
color compensation
d) Comb Filter
– SECAM: crossover-switch
Fig. 2–6: NTSCcolor decoding options
In the NTSC compensated mode, Fig. 2–6 c), the color
signal is averaged for two adjacent lines. Therefore,
cross-color distortion and chroma noise is reduced. In
the NTSC combfilter mode, Fig. 2–6 d), the delay line is
in the composite signal path, thus allowing reduction of
cross-color components, as well as cross-luminance.
The loss of vertical resolution in the luminance channel
is compensated by adding the vertical detail signal with
removed color information.
CVBS
Y
Notch
filter
8
1 H
Chroma
Process.
C C
r
Delay
b
a) conventional
Luma
Y
Chroma
1 H
Chroma
Process.
C C
r
Delay
b
b) S-VHS
Fig. 2–7: PAL color decoding options
CVBS
Notch
filter
Y
MUX
1 H
Delay
Chroma
Process.
C C
r
b
Fig. 2–8: SECAM color decoding
MICRONAS INTERMETALL
9
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2.2.8. Luminance Notch Filter
subcarrier frequency for PAL/NTSC. For SECAM, the
notch is directly controlled by the chroma carrier fre-
quency. This considerably reduces the cross-lumi-
nance. The frequency responses and the delay charac-
teristics of all three systems are shown below.
If a composite video signal is applied, the color informa-
tion is suppressed by a programmable notch filter. The
position of the filter center frequency depends on the
dB
10
nsec
100
90
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
MHz
MHz
MHz
0
MHz
MHz
MHz
0
2
4
6
6
6
8
8
8
10
10
10
0
2
2
2
4
4
4
6
6
6
8
8
8
10
10
10
PAL notch filter
dB
10
nsec
100
90
0
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
0
2
4
0
SECAM notch filter
dB
10
nsec
100
90
0
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
0
2
4
0
NTSC notch filter
Fig. 2–9: Frequency responses and time delay characteristics for PAL, SECAM, and NTSC
10
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2.2.9. YCbCr Color Space
2.3. Component Processing
The color decoder outputs luminance and two chromi-
nance signals at a sample clock of 20.25 MHz. Active
video samples are flagged by a separate reference sig-
nal. The number of active samples is 1056 for all stan-
dards (525 lines and 625 lines). The representation of
the chroma signals is the ITUR-601 digital studio stan-
dard.
Recovery of the YCbCr components by the decoder is
followed by horizontal resizing and skew compensation.
Contrast enhancement with noise shaping can also be
applied to the luminance signal. The CbCr samples are
interpolated to create a 4:4:4 format.
Fig. 2–10 illustrates the signal flow through the compo-
nent processing stage. The YCbCr 4:2:2 samples are
separated into a luminance path and a chrominance
path. TheLuma Filtering andChromaFiltering blocks
apply FIR lowpass filters with selectable cutoff frequen-
cies. These filters are available only in VPX 3220 A. The
Resize and Skew blocks alter the effective sampling
rate and compensate for horizontal line skew. The
YCbCr samples are buffered in a FIFO for continuous
read out at a fixed clock rate. In the luminance path, the
contrastandbrightnesscanbevariedandnoiseshaping
applied. In the chrominance path, interpolation is used
to generate a 24-bit/pixel output stream (4:4:4 format).
In the following equations, the RGB signals are already
gamma-weighted.
– Y
=
0.299*R + 0.587*G + 0.114*B
– (R–Y) = 0.701*R – 0.587*G – 0.114*B
– (B–Y) = –0.299*R – 0.587*G + 0.886*B
In the color decoder, the weighting for both color differ-
ence signals is adjusted individually. The default format
will have the following specification:
– Y = 224*Y + 16 (pure binary),
– C = 224*(0.713*(R–Y)) + 128 (offset binary),
r
– C = 224*(0.564*(B–Y)) + 128 (offset binary).
b
VPX 3220 A only
Resize
Contrast &
Brightness
Y
in
Y
out
Skew
Luma Filter
Luma
Phase Shift
F
I
F
O
Active Video
Reference
Sequence
Control
Latch
Chroma
Phase Shift
Cb
Cr
out
16 bit
C C
Upsampler
b
r
Resize
CbCr
out
in
Skew
Chroma Filter
Fig. 2–10: Component processing stage
MICRONAS INTERMETALL
11
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2.3.1. Horizontal Resizer
The horizontal resizer alters the sampling raster of the
video signal, thereby varying the number of pixels in the
active portion of the video line. The number of pixels per
line is selectable within the range from 1056 to 32 in in-
crements of 2 pixels. In the digital domain, this is done
by lowpass filtering (VPX 3220 A only), followed by a
programmable phase shift with an allpass filter.
The VPX 3220 A is equipped with a battery of 32 FIR fil-
ters to cover the four octave operating range of the resiz-
er. Fig. 2–13 shows the magnitude response of the en-
tire filter set. All filters exhibit a minimum stop band
attenuation of at least 35 dB. Figures 2–11 and 2–12
illustrate the performance of the filters in detail.
Fig. 2–11: Resizer filters for the upper octave
Filter selection is performed by an internal processor
based on the selected resizing factor. This automated
selection is optimized for best visual performance but
can be fine tuned to satisfy different needs. It is also pos-
sible to override the internal selection completely. In that
2
case, filters are selected over I C bus.
The Resize and Skew block performs programmable
phase shifting with subpixel accuracy. In the luminance
path, a linear interpolation filter provides a phase shift
between 0 and 31/32 in steps of 1/32. This corresponds
to an accuracy of 1.6 ns. The chrominance signal can be
shifted between 0 and 3/4 in steps of 1/4. Figs. 2–14
through 2–17 show the the transfer function of the two
skew filters.
Fig. 2–12: Resizer filters for the lower three octaves
Fig. 2–13: Magnitude response of resizer filter bank (VPX 3220 A only)
12
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
dB
2
clocks
2.5
parameter: α, 32 steps
parameter: α, 32 steps
2.3
1
2.1
0
0, 1.0
1.0
–1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.9
0.1
0.8
0.2
0.1, 0.9
0.7
0.3
–2
–3
–4
0.6
0.4
0.5
0.2, 0.8
0.3, 0.7
0.5
0.4, 0.6
–5
–6
–7
–8
0
MHz
MHz
0
2
4
6
8
10
0
2
4
6
8
10
Fig. 2–14: Luminance skew filter magnitude
Fig. 2–15: Luminance skew filter group delay
frequency response
characteristics
clocks
dB
2
5.0
parameter: α, 4 steps
parameter: α, 4 steps
4.6
1
4.2
4.0
3.8
0
0, 1.0
1.0
–1
0.8
–2
–3
–4
–5
–6
–7
–8
3.4
3.0
2.6
0.5
0.2
2.2
2.0
1.8
0
0.25
0.5
1.4
1
MHz
MHz
0
1
2
3
4
5
0
1
2
3
4
5
Fig. 2–16: Chrominance skew filter magnitude
Fig. 2–17: Chrominance skew filter group delay
frequency response
characteristics
2.3.2. Skew Correction
niques: simple rounding, 1-bit error diffusion, or 2-bit er-
ror diffusion.
The VPX delivers orthogonal pixels with a fixed clock
even in the case of non-broadcast signals with substan-
tial horizontal jitter (VCRs, laser disks, certain portions
of the 6 o’clock news...).
Rounding
1 bit
ꢀ
ꢁ
This is achieved by highly accurate sync slicing com-
bined with post correction. Immediately after the analog
input is sampled, a horizontal sync slicer tracks the posi-
tion of sync. This slicer evaluates, to within 1.6 ns., the
skew between the sync edge and the edge of the pixel-
clock. This value is passed as a skew on to the phase
shift filter in the resizer. The skew is then treated as a
fixed initial offset during the resizing operation.
Err. Diff.
2 bit
Err. Diff.
2
Contrast
Select
Brightness
I C Registers
Fig. 2–18: Contrast and brightness adjustment
2.3.3. Contrast, Brightness, and Noise Shaping
I
= c * I + b
c = 0...63/32 in 64 steps
b = –127...128 in 256 steps
out
in
2.3.4. C C Upsampler
b r
A selectable gain and offset can be applied to the lumi-
nance samples. Both the gain and offset factors can be
set externally via I C serial control. Fig. 2–18 gives a
functional description of this circuit. First, a gain is ap-
plied, yielding a 10-bit luminance value. The conversion
back to 8-bit is done using one of three selectable tech-
Simple interpolation is used to convert the 4:2:2 video
samples up to the 4:4:4 format. The CbCr samples are
upsampled and then band limited with the linear phase
FIR kernel. The passband of this filter covers the entire
chroma spectrum present in analog composite and
S-VHS signals.
2
MICRONAS INTERMETALL
13
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2.4. Color Space Stage
2.4.1. Color Space Selection
Thecolorspacestage(Fig. 2–19)oftheVPX3220Aand
VPX 3216 B optionally performs a series of conversions
in the color space and component format. Generation of
an alpha key signal, compression using quantized differ-
ential coding, and inverse gamma correction are pro-
grammable options.
0
ȡ1
1.403ȣ
ȡY ȣ
ȡRȣ
G
+
B
Ȣ Ȥ
ȧ1 *0.344 *0.714ȧ ȧ ȧ ȧ ȧ
Cb
1
Ȣ
1.773
0
Cr
Ȣ Ȥ
Ȥ
An optional dematrix stage converts the YCbCr 4:4:4
dataintoRGBusingthematrixequationsspecifiedinthe
ITUR 601 recommendation (shown above). The satura-
tion control in the color decoder is first selected to pro-
Beginning with the 24-bit/pixel YCbCr input signal, two
other component formats (4:2:2 and 4:1:1) can be gen-
erated by simple downsampling of the chroma. Alterna-
tively, the 24-bit YCbCr can be dematrixed to produce
24-bit RGB. The RGB components can either be output
directly or further quantized to yield other quantization
formats such as 16-bit (R:5 G:6 B:5) or 15-bit (R:5 G:5
B:5) The table below summarizes the supported output
signal formats.
duce C and C , the ITUR studio chrominance norm. In
b
r
the dematrix computation, the full 8-bit resolution is
maintained.
Compo-
nents
Sampling
Format
Quantization
Format
Bits/
Pixel
YCbCr
4:4:4
4:2:2
4:1:1
4:4:4
8 8 8
8 8 8
8 8 8
8 8 8
24
16
12
8
(compressed)
RGB
4:4:4
4:4:4
4:4:4
8 8 8
5 6 5
5 5 5
24
16
15
YCbCr
24 bit / pixel
4:4:4 !4:2:2
YCbCr
16 bit / pixel
4:4:4 !4:1:1
YCbCr
12 bit / pixel
S
e
Downsampling
l
e
c
t
YCbCr
Compression
8 bit / pixel
RGB
Dematrix
24 bit / pixel
−1
γ
RGB
16 bit / pixel
888 !565
RGB
888 !555
15 bit / pixel
Quantization
Alpha Key
Fig. 2–19: The color space stage
14
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2.4.2. Compression 24 ! 8 bits
2.4.3. Inverse Gamma Correction
Today, most broadcast video sources anticipate the dis-
play on conventional CRTs by predistorting the RGB sig-
nals with a gamma function (shown below)
A variant of the time-honored DPCM coding technique
is available to compress the 24-bit YCbCr 4:4:4 signal to
an 8-bit per pixel signal. The technique combines differ-
ential coding, companding, and adaptive subsampling
of the chrominance. For the most natural image materi-
al, the resulting bandwidth savings are purchased at a
modest loss of amplitude resolution, which appears
mostly as high frequency noise. Signals encoded in this
form are readable by decoders, which are embedded in
commercially available ICs (RAMDACs, back-end ana-
log encoders, etc...).
I’ = cIγ + I0 γ ꢀ 2.2
c, I = constants
0
I Ů{R, G, B}...linear intensity
However, for video processing in a computer, linear
space (no gamma distortion) is often the representation
of choice. The VPX provides two options for gamma re-
moval. Both conform to the basic formula:
/γ)
(1
I = I’
Differenttechniquesareusedtocodetheluminanceand
the two chroma signals. For the luma, the difference be-
tween 8-bit luma value and a computed reference is
companded to a 5-bit value for transmission. The com-
puted reference is simply the 8-bit value of the nearest
horizontal neighbor as it appears at the decoder. Each
decoded luminance sample is therefore used as a pre-
diction for the next pixel. This, in turn, requires that the
encoder contains almost a complete decoder as a sub-
set.
These two γ–1 functions are realized as fixed entries in
ROM. The first table compensates for a γ = 1.4. The se-
cond table compensates for a γ = 2.2.
2.4.4. Alpha Key
A 1-bit threshold select signal can be generated for ev-
ery pixel in the YCbCr 4:4:4 signal. Using six registers,
an upper and a lower threshold is separately defined for
each of the Y, C , and C components. These six register
b
r
The chrominance samples are encoded in a similar
fashion. The samples of each chrominance component
are ordered into non-overlapping groups of four. For
each group, one of the four samples is selected as a rep-
resentative value. For each representative pixel, the rel-
ative position and companded differential amplitude are
computed for transmission. The position data is relative
to the beginning of the group and is encoded as a 2-bit
word. The difference between the 8-bit value of the sam-
ple and the decoded reference value of the previous
group is companded to a 5-bit word.
values define a cube in YC C space. Equality is always
b
r
included in comparison. For each pixel, an alpha bit is
generated, which signals whether the pixel lies inside or
outside this cube. A 3-point horizontal median filter is
available to mitigate the effects of impulse noise.The al-
pha signal is fed out through the alpha pin, which is in
turn multiplexed with JTAG TDO function (see chapter
5, sections 5.1. and 5.3.). When there is no JTAG activ-
ity, the TDO pin is used for the alpha signal. Polarity of
this signal (high active or low active) can be pro-
2
grammed using I C.
2.4.4.1. Alpha Key as Static Control Signal
The alpha pin can also be used as a static control signal.
When doing so, all comparators have to be set to their
respective maximal or minimal values.
YMIN = 00
YMAX = FF
UMIN = 80
UMAX = 7F
VMIN = 80
VMAX = 7F
In this case, the alpha signal will always be correct and
theoutputstate(highorlow)canbeselectedthroughthe
polarity bit (keyinv bit in FORMAT register).
MICRONAS INTERMETALL
15
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2.5. Output Pixel Format
2.5.1. Output Ports
The two 8-bit ports produce TTL level signals coded in
binary offset. The ports can be tristated either via the
output enable pin (OE) or via I C commands.
The output formatting stage (Fig. 2–20) receives the vid-
eo samples from the color component stage, performs
the necessary bit packing, buffers the data for transmis-
sion, and channels the output via one or both 8-bit ports.
Data transfer can be either synchronous to an internally
generated pixel clock or asynchronous with FIFO and
status signals.
2
2.5.2. Output Port Formats
The format of output data depends on three parameters:
the selected signal format, the number of active ports,
and the output clock rate. For a given clock rate and
number of active ports, a subset of these output formats
is supported. Figures 2–21 and 2–22 illustrate this de-
pendency. All single port transfers use port A only.
Format section controls:
– byte formats (bit order)
– number of ports (A only or both A and B)
– clock speed (single or double).
The video samples (and alpha key) arrive from the color
component stage at one of two pixel transport rates:
13.5 MHz or 20.25 MHz. This clock rate is selectable via
2
I C command. However, the use of the 13.5 MHz clock
assumes that the resizer is reducing the number of ac-
tive samples per line to a maximum of 768 pixels.
1
Alpha Key
1
1
Alpha
Key
8
8
8
8
Port 1
OE
24
24
24
Video
Samples
Port 2
Clock
Generation
2
PIXCLK
I C reg
Syncr / Asyncr
FE
HF
Fig. 2–20: Output formatting stage
16
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Single Clock
(Port A only)
Double Clock
(Port A only)
7
0
Y 7 ...... Y 0
T Φ
a
a
1
1
Y 4 ..... Y 0
a
a
0, U 1, U 0
a
a
T1
T2
T3
U 7 ...... U 0
Φ
a
a
YCbCr
4:2:2
(Mode 1)
2
Y 4 ..... Y 0
b
b
T
Φ
Φ
U 4, U 3, U 2
YCbCr 4:1:1
Compressed
2
1
2
a
a
a
Y 7 ...... Y 0
b b
V 7 ...... V 0
0, V 1 V 0
Y 4 ..... Y 0
a
a
a
a
c
c
Y 4 ..... Y 0
V 4, V 3, V 2
T4
d
d
a
a
a
T Φ
1
U 7 ...... U 0
a
a
1
Y 7 ...... Y 0
Φ
Φ
a
a
2
YCbCr
4:2:2
(Mode 2)
V 7 ...... V 0
T
2
a
a
1
Y 7 ...... Y 0
b
b
Φ
2
Note: All single port transfers
use Port A only
α
Φ
Φ
R ..... R
G , G
7 6
7
3
1
2
RGB
5 5 5 + α
G ... G
B .... B
7
5
3
3
Note: U, V ³ C , C
b
r
R ..... R
G ... G
Φ
Φ
7
3
7
5
1
2
RGB
5 6 5
G ... G
B .... B
7 3
4
2
Fig. 2–21: Byte formats for single port transfers
Port A
Port B
Y 7 ...... Y 0
U 7 U 6 V 7 V 6
0...0
a
a
a
a
a
a
1
2
T
T
T
T
Y 7 ...... Y 0
U 5 U 4 V 5 V 4
0...0
0...0
0...0
b
b
a
a
a
a
YCbCr 4:1:1
YCbCr 4:2:2
Y 7 ...... Y 0
U 3 U 2 V 3 V 2
c
c
a
a
a
a
3
4
Y 7 ...... Y 0
U 1 U 0 V 1 V 0
d
d
a
a
a
a
Y 7 ...... Y 0
U 7 ...... U 0
a a
a
a
1
2
T
T
Y 7 ...... Y 0
V 7 ...... V 0
b
b
a
a
α
R ....R
G , G
7
G ... G
B .... B
RGB 5 5 5 + α
7
3
6
5
3
7
3
Single Clock
R ....R
G ... G
G ... G
B .... B
7 3
RGB 5 6 5
7
3
7
5
4
2
Y 7 ...... Y 0
U 7 ...... U 0
a a
a
a
Φ1
Φ2
YCbCr 4:4:4
RGB 8 8 8
V 7 ...... V 0
U 7 ...... U 0
a
a
a
a
G
G
.....
.....
G
G
R
.....
.....
R
B
7
0
Φ1
Φ2
7
0
B
7
0
7
0
Double Clock
Fig. 2–22: Byte formats for double port transfers
MICRONAS INTERMETALL
17
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
3. Video Timing
3.1.3. Odd/Even
Information on whether the current field is odd or even,
is supplied through the relationship between the edge
(either leading or trailing) of VREF and level of HREF.
This relationship is fixed and shown in Figs. 3–2 and
3–3. The same information can be supplied to the
FIELD/PREF pin. The polarity of the signal is program-
mable.
3.1. Video Reference Signals HREF and VREF
The VPX generates two video reference signals; a hori-
zontal reference (HREF) and a vertical reference
(VREF). These two signals are generated by program-
mable hardware and can be either free running or syn-
chronous to the analog input video. The video line stan-
dard (625/50 or 525/60) can be either inferred from the
2
analog input video or forced via I C command from the
3.2. Operational Modes
external controller. The polarity of the two signals is indi-
vidually selectable.
The relationship between the video timing signals
(HREF and VREF) and the analog input video is deter-
mined by the selected operational mode. Three such
modes are available: the Open Mode, the Forced
Mode, and the Scan Mode. These modes are selected
The circuitry which produces the VREF and HREF sig-
nals has been designed to provide a stable, robust set
of timing signals, even in the presence of erratic behav-
ior at the analog video input. Depending on the selected
operating mode, the period of the HREF and VREF sig-
nals are guaranteed to remain within a fixed range.
These video reference signals can therefore be used to
synchronizetheexternalcomponentsofavideosubsys-
tem (for example the neighboring ICs of a PC add-in
card).
2
via I C commands from the external controller.
3.2.1. Open Mode
In the Open Mode, both the HREF and the VREF signal
track the analog video input. In the case of a change in
the line standard (i.e. switching between the video input
ports), HREF and VREF automatically synchronize to
thenewinput. Whennovideoispresent, bothHREFand
VREF float to the idling frequency of their respective
PLLs. During changes in the video input (drop-out,
switching between inputs), the performance of the
HREF and VREF signals is not guaranteed.
3.1.1. HREF
Fig. 3–1 illustrates the timing of the HREF signal relative
to the analog input. The active period of HREF is fixed
and is always equal to the length of the active portion of
a video signal. Therefore, regardless of the video line
standard, HREF is active for 1056 periods of the 20.25
MHz system clock. The total period of the HREF signal
3.2.2. Forced Mode
is expressed as Φ
and depends on the video line
nominal
standard.
In the Forced Mode, VREF and HREF follow the input
video signal within certain tolerances. Dedicated hard-
ware is used to monitor the frequency of the analog tim-
ing. At the moment when the video signal exceeds the
allowed timing tolerances, generation of the timing sig-
nals is taken over by free running hardware. If the input
video is still present, the VPX continually attempts to re-
synchronize to it.
Analog
Video
Input
VPX
Delay
For each of the two video line standards (625/50 and
525/60), there exist normative values for the period of
both the HREF and VREF signals. Many analog input
signalsdeviatesignificantlyfromthesenorms(example,
consumer VCRs in their shuttle modes). In the Forced
Mode, monitoring hardware is used to impose an upper
boundary on the deviation. The maximum allowed hori-
zontaldeviationis$24µs. Theupperboundaryforverti-
cal deviation is $11% of the number of lines in the se-
lected line standard (625/50: $35 lines, 525/60: $30
lines)
HREF
52 µs
Φ
nominal
Fig. 3–1: HREF relative to Input Video
3.1.2. VREF
During the free-running operation, video output data is
suppressed. If the VPX successfully resynchronizes,
video output resumes. The specific method used to sup-
press the output video depends on the transfer mode
(synchronous or asynchronous).
Figs. 3–2and3–3illustratethetimingoftheVREFsignal
relative to field boundaries of the two TV standards. The
length of the VREF pulse is programmable in the range
between 2 and 9 video lines.
18
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
625
1
2
3
4
5
8
6
7
Input CVBS
(50 Hz)
3
4
5
6
7
9
10
Input CVBS
(60 Hz)
HREF
VREF
541 t
CLK20
541 t
CLK20
2 .. 9 H
> 1 t
CLK20
ODD/EVEN
Fig. 3–2: VREF timing for ODD fields
312
265
313
266
314
315
316
269
317
270
318
319
272
320
Input CVBS
(50 Hz)
267
268
271
273
Input CVBS
(60 Hz)
HREF
VREF
69 t
CLK20
69 t
CLK20
2 .. 9 H
> 1 t
CLK20
ODD/EVEN
Fig. 3–3: VREF timing for EVEN fields
MICRONAS INTERMETALL
19
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
3.2.3. Scan Mode
free running sync generation. In such a case, it is likely
that the internal sync generators are out of phase with
the time base of the analog input. Maintaining a stable
sync signal requires that the transition between time
bases occur over several field periods.
In the Scan Mode, the HREF and VREF signals are al-
ways generated by free running hardware. They are
therefore completely decoupled from the analog input.
The output video data is always suppressed.
The purpose of the Scan Mode is to allow the external
controller to freely switch between the analog inputs
while searching for the presence of a video signal. In-
formation regarding the video (standard, source, etc...)
Fig. 3–5 illustrates the transition between an internal
free running vertical sync and a vertical sync of the ana-
log input. The top two lines in this figure show the vertical
time base of the analog input signal relative to that of the
VREF generated from the free running clock. Both the
analog input and free running syncs conform to the
same line standard, but the field polarities are out of
phase and the offset between field syncs (given by
2
can be queried via I C read.
In the Scan Mode, the video line standard of the VREF
2
and HREF signals can be changed via I C command.
The transition always occurs at the first frame boundary
Φ
) is greater than the allowed 20 lines.
2
error
after the I C command is received. Fig. 3–4, below,
demonstrates the behavior of the VREF signal during
the transition from the 525/60 system to the 625/50 sys-
tem (the width of the vertical reference pulse is exagger-
ated for illustration).
In the Forced Mode, vertical resynchronization takes
place on field boundaries (as opposed to frame bound-
aries) and begins immediately after the appearance of
the analog input. In the first field after the appearance of
this analog video, the period between VREF pulse is
3.2.4. Transition Behavior
shortened by 20 lines (Φ
and the field polarity of the
rec–)
VREF is repeated. For each subsequent field, the phase
During normal operation, the timing characteristics of
the input video can change in response to a number of
phenomena: power up/reset, unplugging of the video
jack, switching between selected video inputs, etc... The
effect of these changes on the video timing signals is de-
pendent on the current operational mode. Table 3–1
summarizes this dependency.
error is reduced by Φ
until the two signals are again
rec–
in phase.
Because the resynchronization occurs on field bound-
aries and because the internally generated sync can be
either lengthened or shortened, the maximum value of
Φ
is 313/2[157 lines. With a maximum correction
error
In the Forced Mode, it can often occur that the VPX must
resynchronize to an analog input signal after a period in
of 20 lines per field, field locking requires a maximum of
8 fields.
2
I C Command to
Selected timing standard
becomes active
switch video timing standard
time
VREF
f
f
f
f
f
odd
odd
even
odd
even
20.0 ms
16.683 ms
40.0 ms
33.367 ms
(525/60)
(625/50)
Fig. 3–4: Transition between timing standards
20
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Feven
Fodd
Input Signal :
Vertical Timing
Φfield
Fodd
Φerror
Feven
Fodd
Free running
vertical sync
Φfield
Fodd
Fodd 1
Feven 1 ...
First frame after
switch to tracking mode
Φrec–
2Φrec–
Φfield − Φrec–
Φerror – Φrec–
Feven 1
Fodd 2
Feven 2
Φerror – (3Φrec–
)
2Φrec–
Second frame after
switch to tracking mode
Φfield − Φrec–
Fig. 3–5: Synchronization to analog input
MICRONAS INTERMETALL
21
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Table 3–1: Transition Behavior as a Function of Operating Mode
Transition Behavior as a Function of Operating Mode
Transition
Mode
Forced
Behavior
Power up / Reset
VREF, HREF: comes up free running
(video timing standard read from internal initialization tables)
Output ports: suppressed
Open,
Scan
not applicable
video → no video
Open
Forced
Scan
VREF, HREF: floats to steady state frequency of internal PLL
Output ports: still enabled but with undefined data.
VREF, HREF: switches immediately to free running
Output ports: suppressed until video restored.
no visible effect on any data or control signals
– timing signals continue unchanged in free running mode,
– data ports remain suppressed
no video → video
Open
VREF, HREF: track the input signal
Forced
No change in timing standard:
VREF, HREF: slowly resynchronize. When resynchronization is complete,
the timing control switches back from free running to monitored tracking
Output ports: re-enabled.
Change in the timing standard:
– no visible effect on any data or control signals
Scan
VREF, HREF: no change, continues in free running mode
Output ports: remain suppressed.
video → video
(same timing standard)
Open
Forced
VREF, HREF: track the input video immediately
Output Ports: Data available immediately after color decoder locks to input.
VREF, HREF: brief period in free running mode while the timing is
resynchronized
Output Ports: suppressed during resynchronization.
Scan
no outwardly visible effect on any data or control signals.
– timing signals continue unchanged in free running mode,
– data ports remain disabled.
video → video
(different timing standard)
Open
Forced
Scan
same as above
VREF, HREF: switches immediately to free running
Output ports: suppressed
same as the case no video → video
22
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
3.3. Windowing the Video Field
from field #2. For example: On an interlace monitor, line
#23 from field #1 is displayed directly above line #23
For each input video field, two non-overlapping windows
can be defined. The dimensions of these two windows
are supplied via I C commands. The presence of two
windows allows separate processing parameters such
as filter responses and the number of pixels per line to
be selected.
from field #2. There are a few restrictions to the vertical
definition of the windows. Windows must not overlap
vertically, but can be adjacent. Windows must begin af-
ter line #6 (i.e. line #7 is the first one allowed) of their re-
spective fields. The number of lines out cannot be great-
er than the number of lines in (no vertical zooming). The
combined height of the two windows cannot exceed the
number of lines in the input field.
2
External control over the dimensions of the windows is
2
performed by I C writes to a window definition table
1
2
1
2
1
2
264
265
(WinDefTab). For each window, a corresponding Win-
2
DefTab is defined in a table of I C registers. Data written
D
D
D
D
D
D
to these tables does not become active until the the cor-
respondinglatchbitissetinacontrolregister. A2-bitflag
specifies the field polarity over which the window is ac-
tive.
5
6
5
6
5
6
268
269
7
8
7
8
7
8
270
271
D
D
D
D
D
D
Vertically, ascanbeseeninFig. 3–6, eachwindowisde-
fined by a beginning line, a number of lines to be read-in,
and a number of lines to be output. Each of these values
is specified in units of video lines.
15
16
17
15
16
17
15
16
17
278
279
280
18
18
18
281
D
D
D
The option, to separately specify the number of input
lines and the number of output lines, enables vertical
compression. In the VPX, vertical compression is per-
formed via simple line dropping. A nearest neighbor al-
gorithm selects the subset of the lines for output. The
presence of a valid line is signaled by a reference signal.
The specific signal which is used for the blanking de-
pends on the transfer mode (synchronous/asynchro-
nous).
D
D
D
257
257
257
520
521
522
258
259
260
258
259
260
258
259
260
523
524
525
261
262
261
262
261
262
263
263
The numbering of the lines in a field of interlace video is
dependent on the line standard. Figs. 3–7 and 3–8 illus-
trate the mapping of the window dimensions to the actu-
al video lines. The indices on the left are the line num-
bers relative to the beginning of the frame. The indices
on the right show the numbering used by the VPX. As
seen here, the vertical boundaries of windows are de-
fined relative to the field boundary. Spatially, the lines
from field #1 are displayed above identically numbered
Field 1
Field 2
Fig. 3–7: Mapping for 525/60 line systems
1
1
2
1
2
314
315
2
D
D
D
D
D
D
5
6
5
6
5
6
318
319
7
8
7
8
7
8
320
321
Line 1
D
D
D
D
D
D
begin
22
23
24
25
22
23
24
25
22
23
24
25
335
336
337
# lines in,
# lines out
Window 1
begin
338
D
D
D
D
D
D
308
309
308
308
309
310
311
621
622
623
624
625
309
310
311
310
311
312
# lines in,
# lines out
Window 2
312
313
312
313
Field 1
Field 2
Fig. 3–6: Vertical dimensions of windows
Fig. 3–8: Mapping for 625/50 line systems
MICRONAS INTERMETALL
23
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Horizontally, the windows are defined by a starting point
and a length. The starting point and the length are both
givenrelativetothenumberofpixelsintheactiveportion
of the line (Fig. 3–9).
In both modes, data arrives at the output FIFO in an
uninterruptedburstwithafixedtransportrate. Thetrans-
portrateisselectedbytheexternalcontrollertobeeither
13.5 MHz or 20.25 MHz. The duration of the burst is
measured in clock periods of the transport clock and is
equal to the number of pixels per output line.
There are some restrictions in the horizontal window
definition. The total number of active pixels (NPixel)
mustbeanevennumber. ThemaximumvalueforNPixel
depends on the selected transport clock. For a
20.25 MHz transport clock, the maximum value for
NPixelis1056. Fora13.5MHztransportclock, themaxi-
mumvalueis800. HLengthshouldalsobeanevennum-
ber. Obviously, the sum of HBegin and HLength may not
be greater than NPixel.
Thecontrolsignalsonthethreepins:PIXCLK, FE/VACT,
and HF/FSY, LLC regulate the data transfer. Their func-
tion is dependent on the transfer mode (sync., or
async.). For the synchronous mode, the signals at these
pins are PIXCLK (internal), VACT, and LLC (respective-
ly). For the asynchronous mode, the signals at these
pins are PIXCLK (external), FE, and HF.
Window boundaries are defined by writing the dimen-
sions into the associated WinDefTab and then setting
the corresponding latch bit in the control word. Window
definition data is latched at the beginning of the next vid-
eo frame. Once the WinDefTab data has been latched,
the latch bit in the control word is reset. By polling the
info-word, the external controller can know when the
window boundary data has been read. Multiple window
definitions within a single frame time are ignored and
can lead to error.
3.4.1. Synchronous Output
In the synchronous transfer mode, data is transferred
synchronous to an internally generated PIXCLK. The
frequency of the PIXCLK is equal to the selected trans-
port rate. In the single clock mode, data can be latched
onto the falling edge of PIXCLK. In double clock mode,
output data must be latched onto both clock edges. The
double clock mode is supported for the 13.5 MHz trans-
port rate only. The available transfer bandwidths at the
ports are therefore 13.5 MHz, 20.25 MHz (single clock),
and 27.0 MHz (double clock).
52.15 µsec
64 µsec
The video data is output in a continuous stream. The
PIXCLK is free running. The VACT signal flags the pres-
ence of valid output data. Fig. 3–10 illustrates the rela-
tionship between the video port data, VACT, and
PIXCLK. Whenever a line of video data should be sup-
pressed (line dropping, switching between analog in-
puts), it is done by suppression of the VACT signal.
Window
H Begin
H Length
N Pixel
Fig. 3–11 illustrates the temporal relationship between
the VACT and the HREF signals as a function of the
number of pixels per output line and the horizontal di-
mensions of the window. The duration of the active peri-
od of the HREF (Fig. 3–11, points B, D) is fixed. Table
3–2 lists the positions of the VACT edges (points A, C)
relative to those of HREF.
Fig. 3–9: Horizontal Dimensions of Sampling Window
3.4. Video Data Transfer
The LLC signal is provided as an additional support for
the 13.5 MHz single clock mode. The LLC provides a 2x
PIXCLKsignal (27 MHz) for interface to external compo-
nents which rely on the Philips transfer protocols. In the
single clock 13.5 MHz mode, the pixel data can be
latched onto alternate rising edges of the LLC.
The VPX supports two methods of transfer for the
sampled video data: a synchronous mode and an
asynchronous mode. Both modes support all the byte
formats shown in Figs. 2–21 and 2–22, as well as both
alternative transport rates.
24
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Table 3–2: Relationship of the HREF to the VACT in synchronous transfer mode
Resizing
Windowing
Timing of rising edges
Timing of falling edges
20.25 MHz Transport Rate
npix/line = 1056
npix/line < 1056
A = B
A > B
A > B
C = D
C = D
none
npix/line v 1056
Window begin > 0
Window end < 1055
C < D
13.5 MHz Transport Rate
npix/line = 704
A = B
A = B
A > B
A > B
C = D
C > D
C = D
704 < npix/line v768
npix/line < 704
none
npix/line v 704
Window begin > 0
Window end < 1055
C < D
Port
D
D
D
D
D
D
n
1
2
n–3
n–2
n–1
Data
VACT
3
2
1
0
3
2
1
0
PIXCLK
(single clock)
PIXCLK
(double clock)
Fig. 3–10: Timing for synchronous output
Port
D
D
D
D
D
D
n
1
2
n–3
n–2
n–1
Data
PIXCLK
(single edge.)
VACT
HREF
A
B
C
D
Fig. 3–11: Relation between HREF and VACT signals
MICRONAS INTERMETALL
25
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
3.4.2. Asynchronous Output
Intheasynchronousmode, dataisstrobedfromtheVPX
by an external clock supplied to the PIXCLK pin. A
32-pixel FIFO buffers the video samples for transfer.
Two FIFO status signals (HF and FE) arbitrate the trans-
fer. The ‘half full’ signal (HF) indicates that the number
of samples present in the FIFO has exceeded some pro-
grammable threshold (defined over the range of 0³31).
The FE signal indicates that the FIFO is empty.
Some implementations of the asynchronous mode re-
quire a more detailed understanding of the rates at
which the data is written to and read from the 32 pixel
output FIFO. On the input side of the FIFO, sampled vid-
eo data from the VPX-core arrives as a continuous burst
with a pixel rate equal to that of the transport clock
(20 MHz or 13 MHz burst rate).
On the output side, the rate at which the FIFO is emptied
is dependent on the speed of the PIXCLK and the se-
lected clocking mode. In the asynchronous mode, the
PIXCLK is always a single-edge clock.
FIFO
7
8
7
7
6
6
5
2
1
1
0
1
2
3
2
2
1
1
0
fullness level
PIXCLK=2*internal
transfer rate
HF
if full-level is 8
FE
Port Data
Fig. 3–12: Timing for Asynchronous Output
26
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
4. Serial Interface A
4.1. Overview
SCL and SDA float. External pull-up devices must be
adapted to fulfill the required rise time for the fast-mode.
For bus loads up to 200 pF, the pull-up device could be
a resistor; for bus loads between 200 pF and 400 pF, the
pull-up device can be a current source (3 mA max.) or
Communication between the VPX and the external con-
troller is performed serially via the I C-bus (pins SCL
a switched resistor circuit.
2
and SDA).
4.3. Reset and IC Address Selection
There are basically two classes of registers in the VPX.
The first class of registers are the directly addressable
I C registers. These are registers embedded directly in
the hardware. Data written to these registers is inter-
preted combinatorially directly by the hardware (as in
any register driven state machine). These registers are
all a maximum of 8 bits wide.
The VPX can respond to one of two possible chip ad-
dresses. The address selection is made at reset by an
externally supplied level on the PREF pin. This level is
latched onto the inactive going edge of RES.
2
4.4. Protocol Description
The second class of registers are the ‘FP RAM regis-
ters’: the RAM memory of the on-board microcontroller
(INTERMETALL’s Fast Processor). Data written into this
class of registers is read and interpreted by the FP’s mi-
cro-code. Internally, these registers are 12 bits wide.
Once the reset is complete, the IC is selected by assert-
ing a the device address in the address part of a I C
2
transmission. A device address pair is defined as a write
address (86 hex or 8e hex) and a read address (87 hex
or8fhex). Writingisdonebysendingthedevicewritead-
dress first, followed by the subaddress byte and one or
two data bytes. For reading, the read address has to be
transmitted first by sending the device write address (86
hex or 8e hex), followed by the subaddress, a second
start condition with the device read address (87 hex or
8f hex) and reading one or two bytes of data.
2
Communications with these registers requires I C pack-
ets with 16-bit data payloads.
2
Communication with both classes of registers (I C and
2
2
FP RAM) is performed via I C. But the format of the I C
telegram depends on which type of register is being ad-
dressed.
2
The I C-bus device addresses are
2
4.2. I C-Bus Interface
A6
1
A5
0
A4
0
A3
0
A2
0
A1
1
A0
1
R/W
1/0
hex
2
2
The VPX has an I C-bus slave interface and uses I C
clock synchronization to slow down the interface if re-
86/87
8e/8f
2
quired. The I C-bus interface uses one level of subad-
1
0
0
0
1
1
1
1/0
dressing. First, the bus address selects the IC, then a
subaddress selects one of the internal registers.
The registers of the VPX have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data bytes with the high byte first. The order of the
bits in a data/address/subaddress byte is always MSB
first.
2
2
The I C interface of the VPX conforms to the I C-bus
specification for the fast-mode. It incorporates slope
control for the falling edges of the SDA and SCL signals.
If the power supply of the VPX is switched off, both pins
Write to Hardware Control Registers
S
1 0 0 0 0 1 1 0
ACK
sub-addr
ACK
send data-byte
ACK
NAK
P
P
Read from Hardware Control Registers
S
1 0 0 0 0 1 1 0
ACK
sub-addr
ACK
S
1 0 0 0 0 1 1 1
ACK
receive data-byte
2
Note: S =
I C-Bus Start Condition
2
P =
I C-Bus Stop Condition
ACK = Acknowledge-Bit (active low on SDA from receiving device)
NAK = No Acknowledge-Bit (inactive high on SDA from receiving device)
Before accessing the address or data registers for the FP interface (FPRD, FPWR, FPDAT), make sure that the busy
bit of FP is cleared (FPSTA).
MICRONAS INTERMETALL
27
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2
Figure 4–1 shows I C bus protocols for read and write
operations of the interface. The read operation requires
an extra start condition after the subaddress and repeti-
tion of the read chip address, followed by the read data
bytes. The following protocol examples use device ad-
dress hex 86/87.
1
0
SDA
S
P
SCL
2
Fig. 4–1: I C bus protocol
(MSB first)
2
FP
I C
4.5. FP Control and Status Registers
subaddress
space
subaddress
space
2
In addition to the I C subaddress space, a second class
0
0
of address space is defined for direct communication
with the on-board µ−controller. These registers are ac-
2
cessed via indirect addressing through I C registers
(see Fig. 4–2).
Read Address
Write Address
FP
Data
Due to the internal architecture of the VPX 3220 A, the
IC cannot react immediately to all I C requests which in-
µ controller
2
Status
teract with the embedded processor (FP). The maxi-
mum response timing is approx. 20 ms (one TV field) for
the FP processor if TV standard switching is active. If the
addressed processor is not ready for further transmis-
2
sions on the I C bus, the clock line SCL is pulled low.
ff
ff
This puts the current transmission into a wait state. After
a certain period of time, the VPX releases the clock and
the interrupted transmission is carried on.
Fig. 4–2: FP register addressing
Write to FP
S
S
1 0 0 0 0 1 1 0
1 0 0 0 0 1 1 0
ACK
ACK
FPWR
FPDAT
ACK send FP-address- ACK send FP-address- ACK
P
P
byte high
byte low
ACK
send data-byte
high
ACK
send data-byte
low
ACK
Read from FP
S
S
1 0 0 0 0 1 1 0
ACK
ACK
FPRD
ACK send FP-address- ACK send FP-address- ACK
byte high byte low
P
1 0 0 0 0 1 1 0
FPDAT
ACK
S
1 0 0 0 0 1 1 1
ACK receive data-byte ACK receive data-byte NAK
high low
P
28
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2
2
4.6. I C Initialization
4.7. I C Control and Status Registers
The following tables give definitions for the VPX control
In order to completely specify the operational mode of
the VPX, appropriate values must be loaded into both
the I C and FP registers. For both the I C and FP regis-
ters, this data is loaded from internal ROM. The length
of this set-up procedure is approximately 200 µsec after
the leading edge of RES#.
and status registers. The number of bits indicated for
each register in the table is the number of bits imple-
mented in the hardware, i.e. a 9-bit register must always
be accessed using two data bytes, but the 7 MSB will be
don’t care on write operations and 0 on read operations.
Write registers that can be read back are indicated in the
following table.
2
2
Initialization is basically a two step procedure: first, the
2
I C registers are initialized, and afterwards, the FP runs
A hardware reset initializes all control registers to 0. The
automatic chip initialization loads a selected set of val-
ues from one of four internal ROM tables.
its own initialization routine. There are two different set-
ups for the I C initialization available. The selection is
made with the pin signal PIXCLK. On the active → inac-
tive edge of the RES# signal, the state of the PIXCLK pin
is latched and used as an index to the selected ROM
table.
2
The mnemonics used in the Intermetall VPX demo soft-
ware are given in the last column.
2
I C-Register Table
2
I C Reg.
Number
of Bits
Mode
Function
Name
Address
Chip Identification
00
8
r
r
Manufacture ID in accordance with
I2C_ID0
JEDEC Solid State Products Engineering Council, Washington DC
INTERMETALL Code EC
hex
01 / 02
8 / 8
16-bit Part number (01: LSBs, 02: MSBs)
I2C_ID1,
I2C_ID2
VPX 3220 A
VPX 3216 B
VPX 3214 C
4680
4260
4280
hex
hex
hex
Fast Processor (FP)
26
12 / 16
wd
wd
FP read address
FPRD
addr
bit [7:0] :
address
bit [15:8] :
reserved (must be set to zero)
27
12 / 16
FP write address
FPWR
addr
bit [7:0] :
address
reserved (must be set to zero)
bit [15:8] :
Registers 26
and 27
use the same hardware by subaddressing.
hex
hex
28
12 / 16
w
FP data
bit [11:0] :
bit [15:12] :
FP status
bit [0] :
FPDAT
data
data
reserved (must be set to zero)
29
3 / 8
r
FPSTA
write request
read request
busy
bit [1] :
bit [2] :
bit [7:3] :
reserved (return ones)
The control register modes are
– w: write/read register
– d: register is double latched
– r: read-only register
– v: register is latched with vsync
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
The mnemonics used in the Intermetall VPX demo software are given in the last column.
MICRONAS INTERMETALL
29
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2
I C-Register Table
2
I C Reg.
Address
Number
of Bits
Mode
Function
Name
Analog Front-end
33
8
w
Input Selector Luma ADC:
bit [1:0] 00 VIN3
01 VIN2
AFEND
vis
10 VIN1
11
reserved (no luma input selected)
Input Selector Chroma ADC:
cs
bit [2]
0/1 select VIN1/CIN
Clamping Modes:
dclc
bit [3]
0/1 clamp on/off for chroma ADC
bit [5:4] reserved (must be set to zero)
bit [6]
bit [7]
1
1
stand-by luma ADC
stand-by chroma ADC
Href, Vref
D8
8
w
HREF and VREF control
REFSIG
bit [0] : reserved (must be set to zero)
bit [1] : HREF Polarity
hpol
0
1
active high
active low
bit [2] : VREF Polarity
vpol
0
1
active high
active low
bit [5:3] : VREF Pulse width. binary value + 2
vlen
0 0 0
1 1 1
pulse width = 2
pulse width = 9
bit [6] : PREF select
prefsel
prefpol
0
1
Odd/Even flag
PIntr (programmable interrupt signal)
bit [7] : PREF polarity
0
1
polarity unchanged
invert polarity
Chroma Processing
20
2 / 8
w
IF compensation:
IFC
bit [1:0] 00 12 dB
01 reserved
10
11
6 dB/oct
0 dB/oct
bit [7:2]
reserved (must be set to zero)
The control register modes are
– w: write/read register
– d: register is double latched
– r: read-only register
– v: register is latched with vsync
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
The mnemonics used in the Intermetall VPX demo software are given in the last column.
30
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2
I C-Register Table
2
I C Reg.
Address
Number
of Bits
Mode
Function
Name
Color Space Converter
E0
E1
E2
E3
E4
E5
E6
E7
8
8
8
8
8
8
8
8
w
w
w
w
w
w
w
w
Alpha Keyer: Y
(VPX 3220 A and VPX 3216 B)
(VPX 3220 A and VPX 3216 B)
(VPX 3220 A and VPX 3216 B)
(VPX 3220 A and VPX 3216 B)
(VPX 3220 A and VPX 3216 B)
(VPX 3220 A and VPX 3216 B)
YMAX
ymax
max
bit [7:0] : Y
(Integer)
max
Alpha Keyer: Y
YMIN
min
bit [7:0] : Y
(Integer)
ymin
min
Alpha Keyer: C
UMAX
umax
b max
bit [7:0] : C
(2’s complement)
b max
Alpha Keyer: C
UMIN
b min
bit [7:0] : C
(2’s complement)
umin
b min
Alpha Keyer: C
VMAX
vmax
r max
bit [7:0] : C
(2’s complement)
r max
Alpha Keyer: C
VMIN
r min
bit [7:0] : C
(2’s complement)
vmin
r min
Contrast Brightness 1
CBM_BRI
brightness
CBM_CON
contrast
bit [7:0] : Brightness Level (binary offset)
Contrast Brightness 2
bit [5:0] : Contrast Level .... linear scale factor for luminance
[5]
[4:0]
integer part
fractional part
default = 1.0
bit [7:6] : Noise Shaping .... Control for 10 bit to 8 bit conversion
noise
0 0 :
0 1 :
1 0 :
1 1 :
9-bit to 8-bit via1-bit rounding
9-bit to 8-bit via truncation
9-bit to 8-bit via 1-bit error diffusion
10-bit to 8-bit via 2-bit error diffusion
The control register modes are
– w: write/read register
– d: register is double latched
– r: read-only register
– v: register is latched with vsync
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
The mnemonics used in the Intermetall VPX demo software are given in the last column.
MICRONAS INTERMETALL
31
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2
I C-Register Table
2
I C Reg.
Address
Number
of Bits
Mode
Function
Name
Color Space Converter
E8
8
w
Format Selection, Alpha Keyer and Contrast Brightness
bit [7, 5, 2:0] : unused in VPX 3214 C
FORMAT
format
bit [2:0] : Format Selector:
000 YUV 4:2:2, YUV 4:2:2 ITUR
001 YUV 4:4:4,
010 YUV 4:1:1
011 YUV 4:1:1 DPCM
100 RGB 888 – 24 bit
101 RGB 888 (Invers Gamma) – 24 bit
110 RGB 565 (Invers Gamma) – 16 bit
111 RGB 555 (Invers Gamma) + Alpha Key – 15+1 bit
bit [3] : Select data format of C C video output data stream
twosq
clamp
b,
r
0
1
2’s complement (–128 ... 127)
binary offset (0 ... 255)
bit [4] : Contrast Brightness: Clamping Level
0
1
clamping level = 32,
clamping level = 16
bit [5] : Gamma: Round Dither Enable (=1)
bit [6] : Alpha Key Polarity
dither
keyinv
0
1
active high
active low
bit [6] : Programmable output pin in VPX 3214 C, connected to TDO
bit [7] : Alpha Key Median Filter
median
0
1
Median Filter is disable
Median Filter is enable
EA
8
w
Diverse settings
bit [2:0] :
reserved (must be set to zero).
connect LLC2 to ALPHA/TDO pin
LLC2 polarity
bit [3] :
bit [4] :
bit [5] :
0
1
Output FIFO Pointer Reset with posedge of VACT
Output FIFO Pointer Reset with VRF=0.
FFRES
intern
bit [7:6] :
reserved (must be set to zero)
The control register modes are
– w: write/read register
– d: register is double latched
– r: read-only register
– v: register is latched with vsync
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
The mnemonics used in the Intermetall VPX demo software are given in the last column.
32
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2
I C-Register Table
2
I C Reg.
Address
Number
of Bits
Mode
Function
Name
Output Multiplexer
F0
8
w
Output FIFO
OFIFO
FIFO Control: (only available in Asynchronous Mode)
bit [4:0] : FIFO Flag – Half Full Level (interface signal HF)
hfull
shuf
bit [7:5] : Bus Shuffler
000 Out[23:0] = In[23:0]
001,
010 Out[23:0] = In[7:0, 23:8]
011 Out[23:0] = In[15:0, 23:16]
100 Out[23:0] = In[15:8, 23:16, 7:0]
101,
110 Out[23:0] = In[7:0, 15:8, 23:16]
111 Out[23:0] = In[23:16, 7:0, 15:8]
Meaning:
In[23:0] : Data from Color Space Stage
Out[23:0] : Data to Output FIFO
F1
8
w
Output Multiplexer
OMUX
mode
vact
bit [1:0]: Port Mode
00 parallel_out, ’single clock’ Port A = FifoOut[23:16]
Port B = FifoOut[15:8];
01 ’double clock’ (only available with a transport rate of 13.5 MHz)
Port A = FifoOut[23:16] / FifoOut[15:8],
Port B = FifoOut[7:0];
10,11 reserved
vact
bit [2] :
ASYNCHRONOUS MODE: Clock Slope (if Clock Source = external)
slope
1
0
negative edge triggered
positive edge triggered.
SYNCHRONOUS MODE: Data Reset
set output ports to 0 during VACT(/FE#) = 0.
1
vact
bit [3] :
Clock Source
clkio
1
0
Internal Source (Synchronous Mode) – PIXCLK is output
External Mode (Asynchronous Mode) – PIXCLK is input
direct
bit [5:4] : delay signal ’active video’ (signal FE) with respect to video output data.
Only available in Synchronous Mode.
00 no delay (default)
delay
01 one clock cycle
10 two clock cycles
11
three clock cycles
direct
bit [6] :
bit [7] :
1
disable FIFO-Empty FE low pass filter
Only available in Asynchronous Mode.
1
enable HLEN counter
hlen
The control register modes are
– w: write/read register
– d: register is double latched
– r: read-only register
– v: register is latched with vsync
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
The mnemonics used in the Intermetall VPX demo software are given in the last column.
MICRONAS INTERMETALL
33
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2
I C-Register Table
2
I C Reg.
Address
Number
of Bits
Mode
Function
Name
Output Multiplexer
F2
8
w
Output Enable
OENA
aen
direct
bit [0] :
bit [1] :
1
0
Enable Video Port A
Disable / High Impedance Mode
direct
1
0
Enable Video Port B
Disable / High Impedance Mode
ben
direct
direct
bit [2] : reserved (must be set to zero)
bit [3] :
bit [4] :
bit [5] :
1
0
Enable Controls (HREF, VREF, PREF, HF#, FE#, ALPHA)
Disable / High Impedance Mode
zen
direct
direct
1
1
Enable LLC-Clock to HF-Pad
(if transport rate is 13 MHz and internal clock source is used)
llcen
Enable FSY-Data to HF-Pad
(if transport rate is 20 MHz and internal clock source is used)
fsyen
hvsynbyq
direct
direct
w
bit [6] :
bit [7] :
1
1
Synchronize HREF, VREF with PIXCLK
disable OEQ pin function
F8
6 / 8
Pad Driver Strength – TTL Output Pads Typ A
DRIVER_A
stra1
bit [2:0] :
bit [5:3] :
bit [7:6] :
Driver strength of Port A[7:0]
Driver strength of PIXCLK, HF# and FE#
stra2
additional PIXCLK driver strength
strength = bit [5:3] | {bit [7:6], 0}
F9
6 / 8
w
Pad Driver Strength – TTL Output Pads Typ B
DRIVER_B
strb1
bit [2:0] :
bit [5:3] :
bit [7:6] :
Driver strength of Port B[7:0] and C[7:0]
Driver strength of HREF, VREF, PREF and ALPHA
reserved (must be set to zero)
strb2
The control register modes are
– w: write/read register
– d: register is double latched
– r: read-only register
– v: register is latched with vsync
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
The mnemonics used in the Intermetall VPX demo software are given in the last column.
34
MICRONAS INTERMETALL
VPX 3220 A, VPX 216 B, VPX 3214 C
PRELIMINARY DATA SHEET
4.8. FP Control and Status Registers
Warning: The FP subaddress space accesses the RAM
of the fast processor. It is therefore very sensitive to
unintended access. In particular, the user must be sure
not to overwrite reserved areas.
The tables below list the registers which are currently
defined. Electrically, all of the registers in the FP subad-
dress space are both readable and writeable. Function-
ally, they are intended for either read or write (as shown
in the ‘mode’ column)
FP-Register Table
FP Reg.
Address
Number
of Bits
Mode
Function
Name
WinLoadTab1
Load Table for Window #1
88
12
w
A
Vertical Begin
bit [8:0] :
Vertical Begin (field line number)
vbeg1
minimum line number ³ 7
maximum line number ³ determined by current TV line standard
bit [11:9]
sharpness control .... regulates the subjective sharpness
by selecting filters to admitting horizontal alias / blurring
1 1 1
1 1 0
1 0 1
0 0 0
0 0 1
0 1 0
0 1 1
maximum blurring
.....
more blurring
default filter setting
more aliasing
.....
maximum aliasing
1 0 0
set filters for pass-thru
89
12
w
Vertical Lines In
bit [8:0] :
Number of input lines
vlinei1
bit [9]
reserved (must be set to zero)
field flag
bit [11:10] :
1 1 Window disabled
1 0 Window enabled in ODD fields only
0 1 Window enabled in EVEN fields only
0 0 Window enabled in both fields
8A
8B
8C
8D
12
12
12
12
w
w
w
w
Vertical Lines Out
bit [8:0] :
Number of output lines
vlineo1
hbeg1
hlen1
bit [11:9]
reserved (must be set to zero)
Horizontal Begin
bit [10:0] :
bit [11]
Horizontal start of window
reserved (must be set to zero)
Horizontal Length
bit [10:0] :
bit [11]
Horizontal length of window
reserved (must be set to zero)
Number of Pixels
bit [10:0] :
bit [11]
Number of active pixels per line
reserved (must be set to zero)
npix1
The control register modes are
– w: write/read register
– r: read-only register
– A: register or register field has function only in VPX 3220 A
The mnemonics used in the Intermetall VPX demo software are given in the last column.
MICRONAS INTERMETALL
35
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
FP-Register Table
FP Reg.
Address
Number
of Bits
Mode
Function
Name
WinLoadTab2
Load Table for Window #2
8E
12
w
A
Vertical Begin
bit [8:0] :
Vertical Begin (field line number)
vbeg2
minimum line number ³ 7
maximum line number ³ determined by current TV line standard
bit [11:9]
sharpness control ...regulates the subjective sharpness
by selecting filters to admitting horizontal alias / blurring
1 1 1
1 1 0
1 0 1
0 0 0
0 0 1
0 1 0
0 1 1
maximum blurring
.....
more blurring
default filter setting
more aliasing
.....
maximum aliasing
1 0 0
set filters for pass-thru
8F
12
w
Vertical Lines In
bit [8:0] :
Number of input lines
vlinei2
bit [9]
reserved (must be set to zero)
field flag
bit [11:10] :
1 1 Window disabled
1 0 Window enabled in ODD fields only
0 1 Window enabled in EVEN fields only
0 0 Window enabled in both fields
90
91
92
93
12
12
12
12
w
w
w
w
Vertical Lines Out
bit [8:0] :
Number of output lines
vlineo2
hbeg2
hlen2
bit [11:9]
reserved (must be set to zero)
Horizontal Begin
bit [10:0] :
bit [11]
Horizontal start of window
reserved (must be set to zero)
Horizontal Length
bit [10:0] :
bit [11]
Horizontal length of window
reserved (must be set to zero)
Number of Pixels
bit [10:0] :
bit [11]
Number of active pixels per line
reserved (must be set to zero)
npix2
The control register modes are
– w: write/read register
– r: read-only register
– A: register or register field has function only in VPX 3220 A
The mnemonics used in the Intermetall VPX demo software are given in the last column.
36
MICRONAS INTERMETALL
VPX 3220 A, VPX 216 B, VPX 3214 C
PRELIMINARY DATA SHEET
FP-Register Table
FP Reg.
Address
Number
of Bits
Mode
Function
Name
Control Word
F0
12
w r
w
Register for control and latching
CMDWD
settr
bit [0] :
Transport Rate
0
1
20.25 MHz.
13.5 MHz.
w
w
bit [1] :
Latch Transport Rate
lattr
1
latch (reset automatically)
bit [3:2] :
Sync timing mode
settm
0 0
0 1
1 x
Open
Forced
Scan
w
w
bit [4] :
bit [5] :
bit [6] :
bit[8] :
Latch Timing Mode
lattm
1
latch (reset automatically)
Latch Window #1
latwin1
latwin2
disoef
1
latch (reset automatically)
w
Latch Window #2
1
latch (reset automatically)
wr
Odd/Even mode
0
1
toggles always
follows odd/even property of input video signal
bit [11:9]
reserved (must be set to zero)
InfoWord
Info Word
F1
12
r
Internal status register do not overwrite
bit [2:0] :
bit [5:3] :
reserved
Current active TV standard
acttv
actls
x x x
see table of 3-bit code of TV standards
bit [6] :
Line Standard of currently active TV standard
0
1
525 / 60
625 / 50
bit [11:7]
reserved
The control register modes are
– w: write/read register
– r: read-only register
– A: register or register field has function only in VPX 3220 A
The mnemonics used in the Intermetall VPX demo software are given in the last column.
MICRONAS INTERMETALL
37
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
The FP RAM locations which manage the TV coding
standard (selection/recognition) all use a 3-bit code for
the eight supported standards. This code (shown below)
is assumed in the register descriptions which follow.
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
PAL B,G,H,I
NTSC M
SECAM
NTSC 44
PAL M
PAL N
PAL 60
NTSC Comb
(625/50)
(525/60)
(625/50)
(525/60)
(525/60)
(625/50)
(525/60)
(525/60)
FP-Register Table
FP Reg.
Address
Number
of Bits
Mode
Function
Name
TVstndWr
TV Standard – Write
F2
12
w
writeable control register for managing the TV coding standard
bit [0] :
Manual / Automatic Select
mansel
0
1
Automatic
Manual
bit [3:1] :
bit [4] :
bit [5] :
TV standard for manual selection
x x x see table above
settv
Latch the TV standard manually
lattv
1
latch (reset automatically)
Composite / S-VHS select
svhssel
0
1
Composite
S-VHS
bit [9:6] :
Threshold for standard search results
score
1 1 1 1
0 0 0 0
perfect score (maximum score)
’no video’ (minimum score)
1 1 1 1
default
bit [11:10] reserved (must be set to zero)
The control register modes are
– w: write/read register
– r: read-only register
– A: register or register field has function only in VPX 3220 A
The mnemonics used in the Intermetall VPX demo software are given in the last column.
38
MICRONAS INTERMETALL
VPX 3220 A, VPX 216 B, VPX 3214 C
PRELIMINARY DATA SHEET
FP-Register Table
FP Reg.
Address
Number
of Bits
Mode
Function
Name
TVstndRd
TV Standard – Read
F3
12
r
Readable control register for managing the TV coding standard
bit [0] :
VACT suppress
0
1
enabled
suppressed
bit [1] :
Status of recognition routine
0
1
idle
running
bit [4:2] :
bit [5] :
TV standard detected (by recognition routines)
x x x
see table above
’No video’ flag
0
1
TV standard shown in bit [4:2] present
no video at selected input
bit [9:6] :
bit [10] :
bit [11] :
High score from video recognition routine (confidence level)
1 1 1 1 maximum confidence
0 0 0 0 minimum confidence
TV line standard (for TV standard from bit [4:2] above)
0
1
525/60
625/50
reserved
Vertical Standard
E7
12
w
Writeable control register for vertical locking
vsdt
bit [0]:
vertical standard lock enable
0
1
disabled
enabled
bit [11:1]
expected number of lines per field
Color Processing
1C
A0
NTSC tint angle, $512 = $π/4
tint
ACC reference; also used to control color saturation
ACCref
ACCref = 0:
ACCref = 1:
ACC turned off
minimal color saturation ie. color switched off
A3
A4
A8
ACC multiplier value for SECAM Dr chroma component to adjust C level
ACCr
ACCb
kilvl
r
ACC multiplier value for SECAM Db chroma component to adjust C level
b
amplitude color killer level
kilvl = 0:
killer disabled
The control register modes are
– w: write/read register
– r: read-only register
– A: register or register field has function only in VPX 3220 A
The mnemonics used in the Intermetall VPX demo software are given in the last column.
MICRONAS INTERMETALL
39
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
FP-Register Table
FP Reg.
Address
Number
of Bits
Mode
Function
Name
Automatic Gain Control
B2
12
w
sync amplitude reference
AGCref
AGCref = 0:
AGC disabled
Write 0 to FP register B5 after writing 0 to AGCref to disable the AGC
start value for AGC gain while vertical lock or AGC is inactive
AGC gain value
BE
20
12
12
w
r
sgain
gain
DVCO
58
12
12
w
r
crystal oscillator center frequency adjust, –2048..2047
dvco
59
crystal oscillator center frequency adjustment value for line lock mode.
true adjust value is DVCO – ADJUST.
adjust
For factory crystal alignment:
set DVCO=0, set lock mode, read crystal offset from ADJUST register and use
negative value for initial center frequency adjustment via DVCO.
26
12
w
line locked mode lock command/status
xlg
write:
read:
100
0
enable lock
disable lock
4095/0
locked / unlocked
Horizontal PLL
4B
12
w
gain of the horizontal PLL
bit [4:0]
bit [9:5]
gain for the integrating part of PLL control
gain for the proportional part of PLL control
if1
if2
bit [11:10] reserved
The control register modes are
– w: write/read register
– r: read-only register
– A: register or register field has function only in VPX 3220 A
The mnemonics used in the Intermetall VPX demo software are given in the last column.
40
MICRONAS INTERMETALL
VPX 3220 A, VPX 216 B, VPX 3214 C
PRELIMINARY DATA SHEET
4.9. Initial Values on Reset
PIXCLK LOW on Reset
Table of Initial Values
Type
Name
OFIFO
AFEND
IFC
Address
F0
Data
0A
0D
03
Description
2
I C
Half full level to 0A
(10 ), bus shuffler off
hex dec
2
I C
33
Video input 2, chroma ADC from Chroma input, clamp off for chroma ADC
IF compensation 0 dB/oct
2
I C
20
2
I C
YMAX
E0
FF
00
Open up all comparators, so that Alpha Key is always true (set)
2
I C
YMIN
E1
2
I C
UMAX
E2
7F
80
2
I C
UMIN
E3
2
I C
VMAX
E4
7F
80
2
I C
VMIN
E5
2
I C
CBM_BRI
CBM_CON
FORMAT
E6
00
Brightness to 0
2
I C
E7
20
Contrast to 1.0, noise shaping 9 to 8 bit via 1 bit rounding
2
I C
E8
F8
YUV 422, C ,C in binary offset, con/bri clamp to 16 , Gamma dither enabled, Alpha
r b dec
active low, Alpha median filter enabled
2
I C
OMUX
DRIVER_A
DRIVER_B
OENA
F1
F8
F9
F2
00
12
24
00
single clock, PIXCLK input, posedge triggered, HLEN counter disabled
Port A, PIXCLK, HF# and FE# strength to 2
Port B, HREF, VREF, PREF and ALPHA strength to 4
All outputs disabled
2
I C
2
I C
2
I C
PIXCLK HIGH on Reset
2
I C
OFIFO
AFEND
IFC
F0
33
20
E0
E1
E2
E3
E4
E5
E6
E7
E8
0B
0D
03
FF
00
7F
80
7F
80
00
20
F8
Half full level to 0B
(11 ), bus shuffler off
hex dec
2
I C
Video input 2, chroma ADC from Chroma input, clamp off for chroma ADC
IF compensation 0 dB/oct
2
I C
2
I C
YMAX
Open up all comparators, so that Alpha Key is always true (set)
2
I C
YMIN
2
I C
UMAX
2
I C
UMIN
2
I C
VMAX
2
I C
VMIN
2
I C
CBM_BRI
CBM_CON
FORMAT
Brightness to 0
2
I C
Contrast to 1.0, noise shaping 9- to 8-bit via 1-bit rounding
2
I C
YUV 422, C ,C in binary offset, con/bri clamp to 16 , Gamma dither enabled, Alpha
r b dec
active low, Alpha median filter enabled
2
I C
OMUX
DRIVER_A
DRIVER_B
OENA
F1
F8
F9
F2
08
12
24
5F
single clock, PIXCLK output, HLEN counter disabled
Port A, PIXCLK, HF# and FE# strength to 2
2
I C
2
I C
Port B, HREF, VREF, PREF and ALPHA strength to 4
All outputs enabled: synchronize HREF, VREF with PIXCLK
2
I C
MICRONAS INTERMETALL
41
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
PIXCLK LOW or HIGH on Reset
Table of Initial Values
Type
Name
Address
hex
Data
dec
Description
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
FP
TINT
1C
4B
58
59
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
A0
A8
B2
BE
E7
F0
0
664
0
Neutral tint
HPLL: if1 = 24
if2 = 20
DVCO
ADJUST
0
WinLoadTab1
12
1
1
0
704
704
17
WinLoadTab2
500
500
0
704
704
2070
30
ACCREF
KILVL
AGCREF
SGAIN
768
27
VSDT
523
114
CMDWD
Transport rate 20.25 MHz, sync timing mode Open, both windows latched, VACT en-
abled
FP
TVstndWr
F2
979
Manual TV standard select, composite signal
42
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
5. JTAG Boundary-Scan, Test Access Port (TAP)
5.2.2. Instruction Register
The instruction register chooses which one of the data
registers is placed between the TDI and TDO pins when
the select data register state is entered in the TAP con-
troller. When the select instruction register state is ac-
tive, the instruction register is placed between the TDI
and TDO.
The design of the Test Access Port, which is used for
Boundary-Scan Test conforms to standard IEEE
1149.1-1990, with one exception. Also included is a list
of the mandatory instructions supported, as well as the
optional instructions. This is only a brief overview of
some of the basics, as well as any optional features
which are incorporated. The IEEE 1149.1 document
may be necessary for a more concise description. Final-
ly, an adherence section goes through a checklist of top-
ics and describes how the design conforms to the stan-
dard.
Instructions
The following instructions are incorporated:
– bypass
– sample/preload
– extest
The implementation of the instructions HIGHZ and
CLAMP conforms to the supplement P1149.1/D11 (Oc-
tober 1992) to the standard 1149.1-1990.
– master mode
– ID code
5.1. General Description
– HIGHZ
– CLAMP
The TAP in the VPX is incorporated using the four signal
interface. The interface includes TCK, TMS, TDI, and
TDO. The optional TRESET signal is not used. This is
not needed because the chip has an internal power-on-
reset which will automatically steer the chip into the
TEST-LOGIC-RESET state. The goal of the interface is
to provide a means to test the boundary of the chip.
There is no support for internal or BIST(built-in self test).
The one exception to IEEE 1149.1 is that the TDO output
is shared with the ALPHA signal. This was done be-
cause of I/O restrictions on the chip (see section 5.3.
“Exceptions to IEEE 1149.1” for more information).
5.2.3. Boundary Scan Register
The boundary-scan register (BSR) consists of bound-
ary-scan cells (BSCs) which are distributed throughout
the chip. These cells are located at or near the I/O pad.
It allows sampling of inputs, controlling of outputs, and
shifting between each cell in a serial fashion to form the
BSR. This register is used to verify board interconnect.
Input Cell
The input cell is constructed to achieve capture only.
This is the minimal cell necessary since Internal Test
(INTEST) is not supported. The cell captures either the
system input in the CAPTURE-DR State or the previous
cells output in the SHIFT-DR State. The captured data
is then available to the next cell. No action is taken in the
UPDATE-DR State. See Figure 10–11 of IEEE 1149.1
for reference.
5.2. TAP Architecture
The TAP function consists of the following blocks: TAP-
controller, instruction register, boundary-scan register,
bypass register, optional device identification register,
and master mode register.
5.2.1. TAP Controller
Output Cell
The TAP Controller is responsible for responding to the
TCK and TMS signals. It controls the transition between
states of this machine. These states control selection of
the data or instruction registers and the actions which
occur in these registers. These include capture, shifting,
and update. See Fig. 5–1 of IEEE 1149.1 for TAP state
diagram.
The output cell will allow both capture and update. The
capture flop will obtain system information in the CAP-
TURE-DR State or previous cells information in the
SHIFT-DR state. The captured data is available to the
next cell. The captured or shifted data is downloaded to
the update flop during the UPDATE-DR state. The data
from the update flop is then multiplexed to the system
outputpinwhentheEXTESTinstructionisactive. Other-
wise, the normal system path exists where the signal
fromthesystemlogicflowstothesystemoutputpin. See
Fig. 10–12 of IEEE 1149.1 for reference.
MICRONAS INTERMETALL
43
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Tristate Cell
this chip at the end of the chain or bring the VPX TDO out
separately and not have it feed another chip in a chain.
Eachgroup of output signals which are tristatable is con-
trolled by a boundary scan cell (output cell type). This al-
lows either the normal system signal or the scanned sig-
nal to control the tristate control. In the VPX, there are
four such tristate control cells which control groups of
output signals (see section “Output Driver Tristate Con-
trol” for further information).
5.4. IEEE 1149.1-1990 Spec Adherence
This section defines the details of the IEEE1149.1 de-
sign for the VPX. It describes the function as outlined by
IEEE1149.1, section 12.3.1. The section of that docu-
ment is referenced in the description of each function.
Bidirect Cell
5.4.1. Instruction Register
The bidirect cell is comprised of an input cell and a tris-
tate cell as described in the IEEE standard. The signal
PIXCLK is a bidirectional signal.
(section 12.3.1.b.i of IEEE 1149.1-1990)
The instruction register is three bits long. No parity bit is
included. The pattern loaded in the instruction register
during CAPTURE-IR is binary “101” (MSB to LSB). The
two LSBs are defined by the spec to be “01” (bit 1 and
bit 0) while the MSB (bit 2) is set to “1”.
5.2.4. Bypass Register
This register provides a minimal path between TDI and
TDO. This is required for complicated boards where
many chips may be connected in serial.
5.4.2. Public Instructions
5.2.5. Device Identification Register
(Section 12.3.1.b.ii of IEEE 1149.1-1990)
A list of the public instructions is as follows:
This is an optional 32-bit register which contains the-
INTERMETALL identification code (JEDEC controlled),
part and revision number. This is useful in providing the
tester with assurance that the correct part and revision
are inserted into a PCB.
Instruction
EXTEST
Code (MSB to LSB)
000
SAMPLE/PRELOAD
ID CODE
001
5.2.6. Master Mode Data Register
010
This is an optional register used to control an 8-bit test
register in the chip. This register supports shift and up-
date. No capture is supported. This was done so the last
word can be shifted out for verification.
MASTER MODE
HIGHZ
011
100
CLAMP
110
5.3. Exception to IEEE 1149.1
BYPASS
100 – 111
There is one exception to IEEE 1149.1. The exception
is to paragraphs 3.1.1.c., 3.5.1.b, and 5.2.1.d (TEST-
LOGIC-RESET state). Because of pin limitations on the
chip, a pin is shared for two functions. When the circuit
is in the TEST-LOGIC-RESET state, the ALPHA signal
is driven out the TDO/ALPHA pin. When the circuit
leaves the TEST-LOGIC-RESET state, the TDO signal
is driven on this line. As long as the circuit is not in the
TEST-LOGIC-RESET state, all the rules for application
of the TDO signal adhere to the IEEE1149.1 spec.
The EXTEST and SAMPLE/PRELOAD instructions
both apply the boundary scan chain to the serial path.
The ID CODE instruction applies the ID register to the
serial chain. The BYPASS, the HIGHZ, and the CLAMP
instructions apply the bypass register to the serial chain.
TheMASTERMODEinstructionisatestdatainstruction
for public use. It provides the ability to control an 8-bit
test register in the chip.
Since the VPX uses the JTAG function as a boundary-
scan tool, the VPX does not sacrifice test of this pin since
it is verified by exercising JTAG function. The designer
of the PCB must make careful note of this fact, since he
will not be able to scan into chips receiving the ALPHA
signal via the VPX. The PCB designer may want to put
5.4.3. Self-test Operation
(Section 12.3.1.b.iii of IEEE 1149.1-1990). There is no
self-test operation included in the VPX design which is
accessible via the TAP.
44
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
5.4.4. Test Data Registers
5.4.5. Boundary-Scan Register
(Section 12.3.1.b.v of IEEE 1149.1-1990)
(Section 12.3.1.b.iv of IEEE 1149.1-1990).
The boundary-scan chain has a length of 38 shift regis-
ters. The scan chain order is specified in the section “Pin
Connections”.
The VPX includes the use of four test data registers.
They are the required bypass and boundary scan regis-
ters, the optional ID code register and the master mode
register.
5.4.6. Device Identification Register
The bypass register is, as defined, a 1-bit register ac-
cessed by codes 100 through 111, inclusive. Since the
design includes the ID code register, the bypass register
is not placed in the serial path upon power-up or Test-
Logic-Reset.
(Section 12.3.1.b.vi of IEEE 1149.1-1990)
The manufacturer’s identification code for-INTER-
METALL is “6C”
. The general implementation
(hex)
scheme uses only the 7 LSBs and excludes the MSB,
which is the parity bit. The part number is “4680”
.
(hex)
The master mode is an 8-bit test register which is used
to force the VPX into special test modes. This is reset
upon power-on-reset. This register supports shift and
update only. It is not recommended to access this regis-
ter. The loading of that register can drive the IC into an
undefined state.
The version code starts from “1”
and changes with
(hex)
every revision. The version number relates to changes
of the chip interface only.
5.4.7. Performance
(Section 12.3.1.b.vii of IEEE 1149.1-1990)
See section “Specification” for further information.
The Device Identification Register
Version
Part Number
7F
Manufacturer ID
0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1
31
28 27
12 11
8
7
1
0
2
4
6
8
0
0
d
9
MICRONAS INTERMETALL
45
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
TAP State Transitions
TDO could be used as Alpha keyer or LLC2 clock signal (see Pin
Description).
$F
1
0
Test-Logic-Reset
0
$C
$7
$4
1
1
1
Run / Idle
Select Data Reg
Select Instr. Reg
0
0
$6
$E
$A
1
1
Capture DR
Capture IR
0
0
$2
0
1
0
1
Shift DR
Shift IR
1
1
$1
$3
$9
$B
Exit1 DR
Exit1 IR
0
0
0
0
0
Pause DR
Pause IR
1
1
$0
$5
$8
Exit2 DR
Exit2 IR
1
1
$D
State Code
Update DR
Update IR
TDO inactive
TDO active
TMS=1
TMS=0
TMS=1
TMS=0
State transitions are dependend on the value of TMS, synchronized by TCK.
46
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
––*************************************************************
––
–– This is the BSDL for the 44-Pin Version of the VPXA design.
––
––*************************************************************
Library IEEE;
Use work.STD_1149_1_1990.ALL;
Entity VPXA_44 is
Generic (Physical_Pin_Map:string := ”UNDEFINED”);
Port(
––define ports
TDI,TCK,TMS:
TDO,HREF,VREF,PREF:
A:
PVDD,PVSS:
PIXCLK:
in bit;
out bit;
out bit_vector(7 downto 0);
linkage bit;
inout bit;
OEQ:
in bit;
HFQ,FEQ:
out bit;
B:
out bit_vector(7 downto 0);
inout bit;
SDA,SCL:
VSS,XTAL2,XTAL1,VDD:
RESQ:
linkage bit;
in bit;
AVDD,AVSS,VRT,ISGND:
CIN,VIN1,VIN2,VIN3:
linkage bit;
in bit
);
Attribute Pin_Map of VPXA_44 : Entity is Physical_Pin_Map;
constant Package_44 : Pin_Map_String :=
––map pins to signals
”TDI
: 1 ” &
”TCK
”TDO
”HREF
”VREF
”PREF
”A
: 2 ” &
: 3 ” &
: 4 ” &
: 5 ” &
: 6 ” &
: (7,8,9,10,14,15,16,17)” &
”PVDD : 11 ” &
”PIXCLK : 12 ” &
”PVSS
”OEQ
”HFQ
”FEQ
”B
: 13 ” &
: 18 ” &
: 19 ” &
: 20 ” &
: (21,22,23,24,25,26,27,28),” &
”SDA
”SCL
”VSS
: 29 ” &
: 30 ” &
: 31 ” &
”XTAL2 : 32 ” &
”XTAL1 : 33 ” &
”VDD
”RESQ
: 34 ” &
: 35 ” &
”AVDD : 36 ” &
”CIN
: 37 ” &
: 38 ” &
: 39 ” &
: 40 ” &
: 41 ” &
: 42 ” &
”AVSS
”VIN1
”VIN2
”VRT
”VIN3
”ISGND : 43 ” &
”TMS : 44 ” ;
Attribute Tap_Scan_In
of TDI
: signal is true;
––define JTAG Controls
Attribute Tap_Scan_Mode of TMS : signal is true;
Attribute Tap_Scan_Out of TDO : signal is true;
Attribute Tap_Scan_Clock of TCK
: signal is (10.0e6,Both);
––max frequency and levels TCK can be stopped at.
––define instr. length
Attribute Instruction_Length
of VPXA_44: entity is 3;
Attribute Instruction_Opcode
”EXTEST
of VPXA_44: entity is
(000),” &
––External Test
MICRONAS INTERMETALL
47
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
”SAMPLE
”IDCODE
(001),” &
(010),” &
––Sample/Preload
––ID Code
”MASTERMODE
”HIGHZ
(011),” &
(100),” &
––Master Mode (internal Test)
–– Highz
”CLAMP”
”BYPASS
(110),” &
(100,101,110,111),”;
–– Clamp
––Bypass
Attribute Register_Access
”BOUNDARY
of VPXA_44: entity is
(EXTEST,SAMPLE),” &
(BYPASS, HIGHZ, CLAMP),” &
(IDCODE),” &
––instr. vs register
––control
”BYPASS
”IDCODE[32]
”MASTERMODE[8]
(MASTERMODE) ”;
Attribute INSTRUCTION_Capture of VPXA_44: entity is ”101”;
––captured instr.
Attribute IDCODE_Register
Attribute Boundary_Cells
of VPXA_44: entity is
”0001” &
”0100011010000000” &
”0000” &
”1101100” &
”1”;
––initial rev
––part numb. 4680
––7F Count
––INTERMETALL Code–Parity
––Mandatory LSB
of VPXA_44: entity is ”BC_1,BC_4”;
–-BC_1 for output cell
––BC_4 for input cell
Attribute Boundary_Length
Attribute Boundary_Register
of VPXA_44: entity is 38;
of VPXA_44: entity is
––Boundary scan length
––Boundary scan defin.
––
num
” 37
” 36
” 35
” 34
” 33
” 32
” 31
” 30
” 29
” 28
” 27
” 26
” 25
” 24
” 23
” 22
” 21
” 20
” 19
” 18
” 17
” 16
” 15
” 14
” 13
” 12
” 11
” 10
cell port
function safe
ccel
disval rslt
(BC_4, VIN3, input,
(BC_4, VIN2, input,
(BC_4, VIN1, input,
(BC_4, CIN,
(BC_4, RESQ, input,
X
X
X
X
X
),” &
),” &
),” &
),” &
),” &
input,
(BC_1, *,
internal, X
input,
output3, X,
input,
),” & ––clock health
),” &
),” & ––open collector
),” &
),” & ––open collector
),” &
),” &
),” &
),” &
),” &
),” &
),” &
),” &
),” & ––control
),” &
),” &
),” & ––control
),” &
),” &
),” &
),” &
),” &
),” &
),” &
(BC_4, SCL,
(BC_1, SCL,
(BC_4, SDA,
(BC_1, SDA,
(BC_1, B(0),
(BC_1, B(1),
(BC_1, B(2),
(BC_1, B(3),
(BC_1, B(4),
(BC_1, B(5),
(BC_1, B(6),
(BC_1, B(7),
(BC_1, *,
(BC_1, FEQ,
(BC_1, HFQ,
(BC_1, *,
(BC_4, OEQ,
(BC_1, A(0),
(BC_1, A(1),
(BC_1, A(2),
(BC_1, A(3),
X
30,
1,
Z
X
output3, X,
output3, X,
output3, X,
output3, X,
output3, X,
output3, X,
output3, X,
output3, X,
output3, X,
control, X
output3, X,
output3, X,
control, X
28,
19,
19,
19,
19,
19,
19,
19,
19,
1,
1,
1,
1,
1,
1,
1,
1,
1,
Z
Z
Z
Z
Z
Z
Z
Z
Z
16,
16,
1,
1,
Z
Z
input,
X
output3, X,
output3, X,
output3, X,
output3, X,
7,
7,
7,
7,
1,
1,
1,
1,
Z
Z
Z
Z
(BC_1, CLKIO, control, X
(BC_4, PIXCLK,input,
(BC_1, PIXCLK,output3, X,
”
”
”
”
”
”
”
”
”
”
9
8
7
6
5
4
3
2
1
0
X
10,
1,
Z
),” & ––bidirect
),” & ––control
(BC_1, *,
control, X
output3, X,
output3, X,
output3, X,
output3, X,
(BC_1, A(4),
(BC_1, A(5),
(BC_1, A(6),
(BC_1, A(7),
(BC_1, PREF, output3, X,
(BC_1, VREF, output3, X,
(BC_1, HREF, output3, X,
7,
7,
7,
7,
16,
16,
16,
1,
1,
1,
1,
1,
1,
1,
Z
Z
Z
Z
Z
Z
Z
),” &
),” &
),” &
),” &
),” &
),” &
),”;
End VPXA_44;
48
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6. Specification
6.1. Outline Dimensions
2.35
± 0.1
10 x 1.27 = 12.7
+0.2
±0.1
1.27
1.2 x 45°
1
x 45 °
6
1
40
7
39
1.6
6
2
2
8.6
5
17
29
1.9 1.5
4.05
18
28
+0.25
± 0.1
16.5
17.4
0.1
±0.15
4.75
Fig. 6–1:
44-Pin Plastic Leaded Chip Carrier Package
(PLCC44)
Weight approximately 2.5 g
Dimensions in mm
±0.1
10 x 0.8 = 8
±0.05
0.8
44
34
1
33
23
11
12
22
±0.05
1.4
±0.25
±0.1
10
12
0.1
max. 1.6
Fig. 6–2: 44-Pin Plastic Thin-Quad-Flat-Pack
(PTQFP44F)
SPGS1234/1
Weight approximately 0.35 g
Dimensions in mm
MICRONAS INTERMETALL
49
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.2. Pin Connections and Short Descriptions
NC = not connected; leave vacant
LV = if not used, leave vacant
S.T.B. = shorted to BAGNDI if not used
DVSS = if not used, connect to DVSS
X = obligatory; connect as described in circuit diagram
AHVSS = connect to AHVSS
Pin No.
Connection
(if not used)
Pin Name
Type
Short Description
PLCC
PTQFP
44-pin
44-pin
1
2
39
40
NC
NC
TDI
IN
Boundary-Scan-Test Data Input
TCK
IN (+Pull-
up)
Boundary-Scan-Test Clock Input
3
41
NC
TDO
OUT
OUT
OUT
Boundary-Scan-Test Data Output if TAP is
active (see remarks on Boundary-Scan
Test)
ALPHA
LLC2
If Test Access Port (TAP) is in Test-Logic-
2
Reset State: Alpha Key Signal (I C Reg.
EA
bit[3] = 0)
hex
If Test Access Port (TAP) is in Test-Logic-
Reset State: LLC/2 = 13 MHz clock signal
2
(I C Reg. EA
bit[3] = 1)
hex
4
5
6
42
43
44
NC
NC
NC
HREF
VREF
OUT
OUT
Horizontal Reference
Vertical Reference
PREF
OUT
OUT
IN
Programmable Interrupt
ODD/EVEN
ODD/EVEN Frame Identifier
2
2
I C-ADDR
I C-Initialization Control by positive edge of
RES:
2
PREF = 0 : I C device address 0
PREF = 1 : I C device address 1
(for more information see I C description)
2
2
7
1
2
3
4
5
6
NC
NC
NC
NC
A7
OUT
Port 1 – Video Data Output
Port 1 – Video Data Output
Port 1 – Video Data Output
Port 1 – Video Data Output
Supply Voltage Pad Circuits
8
A6
OUT
9
A5
OUT
10
11
12
A4
OUT
PVDD
PIXCLK
SUPPLY
NC
OUT
IN
Pixel Clock I/O Synchronous mode
Asynchronous mode
2
2
I C-INIT
IN
I C-Initialization Control by positive edge of
RES:
2
PIXCLK = 0 : I C ROM table 0
PIXCLK = 1 : I C ROM table 1
(for more information see I C description)
2
2
13
7
PVSS
SUPPLY
Supply Voltage Pad Circuits
50
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Pin Connections and Short Descriptions, continued
Pin No.
Connection
(if not used)
Pin Name
Type
Short Description
PLCC
PTQFP
44-pin
44-pin
14
8
NC
NC
NC
NC
VSS
NC
A3
A2
A1
A0
OE
OUT
OUT
OUT
OUT
IN
Port 1 – Video Data Output
Port 1 – Video Data Output
Port 1 – Video Data Output
Port 1 – Video Data Output
Output Ports Enable
15
9
16
10
11
12
13
17
18
19
HF
OUT
OUT
OUT
Asynchronous Mode: FIFO half full, active
low
FSY
LLC
Synchronous Mode (20.25 MHz): Front
Sync
Synchronous Mode (13.5 MHz):
2 x PIXCLK = 27 MHz
20
14
NC
FE
OUT
OUT
Asynchronous Mode: FIFO empty, active
low
VACT
Synchronous Mode: active video
Port 2 – Video Data Output
Port 2 – Video Data Output
Port 2 – Video Data Output
Port 2 – Video Data Output
Port 2 – Video Data Output
Port 2 – Video Data Output
Port 2 – Video Data Output
Port 2 – Video Data Output
21
22
23
24
25
26
27
28
29
15
16
17
18
19
20
21
22
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
B7
B6
B5
B4
B3
B2
B1
B0
SDA
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2
OUT (Pull-
down/IN)
I C Data
2
30
24
NC
SCL
OUT (Pull-
down/IN)
I C Clock
31
32
33
34
35
36
37
38
25
26
27
28
29
30
31
32
RES
IN
Reset input
VSS
SUPPLY
SUPPLY
OSC OUT
OSC IN
SUPPLY
AIN
Supply Voltage for digital circuitry
Supply Voltage for digital circuitry
Crystal
VDD
XTAL2
XTAL1
AVDD
CIN
Crystal
Supply Voltage for analog circuitry
Chroma Input (SVHS)
Supply Voltage for analog circuitry
NC
AVSS
SUPPLY
MICRONAS INTERMETALL
51
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Pin No.
Connection
(if not used)
Pin Name
Type
Short Description
PLCC
PTQFP
44-pin
44-pin
39
33
34
35
36
37
38
NC
NC
VIN1
VIN2
VRT
AIN
Video 1 or Luminance (SVHS) Input
Video 2 Input
40
AIN
41
Reference
AIN
Reference Voltage Top (ADC)
Video 3 Input
42
NC
NC
VIN3
ISGND
TMS
43
SUPPLY
IN (Pull-up)
Signal Ground
44
Boundary-Scan-Test Mode Select
52
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.3. Pin Descriptions (Pin Numbers for PLCC44)
Pins 21 to 28 – Video Port B (Fig. 6–8)
The output characteristics of these pins belong to the
characteristics of TTL output driver type B.
Pins 44, 1 – JTAG Input Pins TMS, TDI (Fig. 6–6)
Mode Select and Data Input signal for the JTAG Test Ac-
cess Port (TAP). These inputs have small pull-ups and
input stages with Schmitt trigger characteristics.
2
Pin 29 – I C Data SDA (Fig. 6–7)
2
This pin connects to the I C-bus data line.
2
Pin 2 – JTAG Input Pin TCK (Fig. 6–5)
Clock input pin for JTAG Test Access Port (TAP). This in-
put has an input stage with Schmitt trigger characteris-
tics and no pull-up.
Pin 30 – I C Clock SCL (Fig. 6–7)
2
This pin connects to the I C-bus clock line.
Pin 31 – Reset Input RES (Fig. 6–5)
A low level on this pin resets the circuit.
Pin 3 – JTAG Output Pin TDO (Fig. 6–8)
DataoutputforJTAGTestAccessPort(TAP), andoutput
pin for the ALPHA key signal, if the TAP is in Test-Logic-
Reset state. The output circuit belongs to the character-
istics of TTL output driver type B.
Pin 32 – Ground, Digital Circuitry VSS
Pin 33 – Supply Voltage, Digital Circuitry VDD
Pins 34, 35 – XTAL1 Crystal Input and XTAL2 Crystal
Output (Fig. 6–11)
Pins 4 to 6 – Reference Signals HREF, VREF, and PREF
(Fig. 6–8)
Thesepinsareconnectedtoa20.25MHzcrystaloscilla-
tor which is digitally tuned by integrated shunt capaci-
tances. An external clock can be fed into XTAL1. In this
case clock frequency adjustment must be switched off.
These signals are internally generated sync signals.
Their output characteristics belong to the output driver
type B.
Pins 7 to 10, 14 to 17 – Video Port A (Fig. 6–8)
The output characteristics of these pins belong to the
characteristics of output driver type A.
Pin 36 – Supply Voltage, Analog Circuitry AVDD
Pin 37 – Chroma Input CIN (Fig. 6–10, Fig. 6–14)
This pin is connected to the S-VHS chroma signal. A re-
sistive divider is used to bias the input signal to the
middle of the converter input range. CIN can only be
connected to the chroma (Video 2) AD converter. The
signal must be AC-coupled.
Pin 11 – Supply Voltage, Pad Circuitry PVDD
Pin 12 – Pixel Clock PIXCLK (Fig. 6–9)
This signal is either input or output depending on the se-
lected mode. In synchronous mode it has the character-
istics of TTL output driver type A. In asynchronous mode
it has TTL Schmitt trigger input characteristics. PIXCLK
is the reference clock for the video data transmission
ports A[7:0] and B[7:0]. Moreover, the state of the
PIXCLK signal at the inactive going edge of RES deter-
Pin 38 – Ground, Analog Front-end AVSS
Pins 39, 40, 42 – Video Input 1–3 VIN1,VIN2,VIN3
(Fig. 6–12)
2
mines which I C_INIT table will be loaded (see section
These are the analog video inputs. A CVBS, S-VHS
luma signal is converted using the luma (Video 1) AD
converter. The VIN1 input can also be switched to the
chroma (Video 2) ADC. The input signal must be AC-
coupled.
4.9.)
Pin 13 – Ground, Pad Circuitry PVSS
Pin 18 – Output Enable Input Signal (Fig. 6–5)
The output enable input signal has TTL Schmitt trigger
input characteristics. It controls the tristate condition of
both video ports.
Pin 41 – Reference Voltage Top VRT (Fig. 6–13)
Via this pin, the reference voltage for the AD converters
is decoupled. The pin is connected with 10 µF/47 nF to
the Signal Ground Pin.
Pins 19, 20 – HF, FE, (Fig. 6–8)
These pins have different functionality depending on
which video data output mode is selected. The output
circuits belong to the characteristics of TTL output driver
type A.
Pin 43 – Signal Ground for Analog Input ISGND
This is the high-quality ground reference for the video
input signals.
MICRONAS INTERMETALL
53
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.4. Pin Configuration
TDI
TCK
TDO (ALPHA, LLC2)
HREF
VREF
PREF (ODD/EVEN)
TMS
ISGND
VIN3
VRT
VIN2
6
5
4
3
2
1 44 43 42 41 40
A7
A6
A5
A4
7
VIN1
AVSS
CIN
39
38
37
36
35
34
33
32
31
30
29
8
9
VPX 3220 A,
VPX 3216 B
10
11
12
13
14
15
16
17
AVDD
XTAL1
XTAL2
VDD
VSS
RES
SCL
SDA
PVDD
PIXCLK
PVSS
A3
Top View
A2
A1
A0
18 19 20 21 22 23 24 25 26 27 28
OE
HF (FSY, LLC)
FE (VACT)
B7
B0
B1
B2
B3
B6
B4
Fig. 6–3: 44-pin PLCC package.
B5
TDI
TCK
TMS
TDO (ALPHA, LLC2)
HREF
ISGND
VIN3
VREF
PREF (ODD/EVEN)
VRT
VIN2
44 43 42 41 40 39 38 37 36 35 34
1
33
32
31
30
29
28
27
26
25
24
23
A7
A6
A5
VIN1
AVSS
CIN
AVDD
XTAL1
XTAL2
VDD
VSS
2
3
VPX 3220 A,
VPX 3216 B
4
A4
PVDD
PIXCLK
PVSS
A3
5
6
7
Top View
8
9
A2
A1
A0
RES
SCL
SDA
10
11
12 13 14 15 16 17 18 19 20 21 22
OE
B0
B1
B2
B3
B4
HF (FSY, LLC)
FE (VACT)
B7
B6
Fig. 6–4: 44-pin PTQFP package.
B5
54
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.5. Pin Circuits
PVDD
P
OUT
IN
N
PVSS
Fig. 6–5: TCK, OE, RES
Fig. 6–8: A[7:0], B[7:0], HREF, VREF, PREF, HF,
FE, TDO
P
on
PVDD
P
PVDD
P
IN / OUT
Fig. 6–6: JTAG Inputs TMS, TDI
N
PVSS
Fig. 6–9: Input/Output PIXCLK
Pin
VRT
VIN1,
VIN2,
VIN3,
off
2
Fig. 6–7: I C Interface SDA, SCL
CIN
ThecharacteristicsoftheSchmittTriggersaredependentofthesupply
of VDD/VSS.
Fig. 6–10: Unselected Video Inputs
MICRONAS INTERMETALL
55
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
AVDD
AVDD
XTAL2
XTAL1
P
N
VIN1
CIN
N
N
N
N
0.5M
f
ECLK
To ADC2
AVSS
AVSS
bias
Fig. 6–11: Crystal Oscillator
AVDD
VIN1
CIN
To ADC2
AVDD
VIN1
VIN2
VIN3
N
N
N
AVSS
clamping
To ADC1
AVSS
2
clamping or bias is selectable via I C reg. 33
bit[3]
hex
Fig. 6–14: Video Inputs ADC2
clamping
Fig. 6–12: Video Inputs ADC1
AVDD
–
P
BIAS
+
Pin
ADC Reference
AVSS
Fig. 6–13: Reference Voltage VRT
56
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6. Electrical Characteristics
6.6.1. Absolute Maximum Ratings
Symbol
Parameter
Pin
Min.
Max.
Unit
Name
T
Ambient Temperature
Storage Temperature
Junction Temperature
Supply Voltage, all Supply Inputs
Input Voltage of PIXCLK, TMS, TDI
Input Voltage
0
65
°C
°C
°C
V
A
T
T
–40
125
S
J
0
125
V
–0.3
6
SUB
1)
1)
PVSS – 0.5
PVSS – 0.5
VSS – 0.5
PVDD + 0.5
V
TCK
6
6
V
Input Voltage
SDA,
SCL
V
Signal Swing
A[7:0],
B[7:0],
PIXCLK,
HREF,
VREF,
PREF,
HF, FE,
TDO
PVSS – 0.5
PVDD + 0.5
V
Maximum ∆ | VDD – AVDD |
0.5
0.1
V
V
Maximum ∆ | VSS – PVSS |
Maximum ∆ | VSS – AVSS |
Maximum ∆ | PVSS – AVSS |
1)
Note: external voltage exceeding PVDD+0.5V should not be applied to these pins even when they are three-stated.
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the
“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi-
mum ratings conditions for extended periods may affect device reliability.
MICRONAS INTERMETALL
57
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Limitations due to Package Characteristics (test conditions at T = 65 °C and T = 125 °C)
A
j
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
R
R
Thermal Resistance Junction-Case of
PTQFP44
5
K/W
thJC
Thermal Resistance Ambient of PTQFP44
68
K/W
mW
still air
thA
P
max
Maximum Power Radiation of PTQFP44
due to the thermal resistance of the pack-
age
890
still air, no cooling
R
R
Thermal Resistance Junction-Case of
PLCC44 without internal heat sink
11
55
K/W
K/W
mW
thJC
thA
Thermal Resistance Ambient (still air) of
PLCC44 without internal heat sink
P
max
Maximum Power Radiation of PLCC44
without internal heat sink due to the ther-
mal resistance of the package
1089
still air, no cooling
R
R
Thermal Resistance Junction-Case of
PLCC44 with internal heat sink
8
K/W
K/W
mW
thJC
thA
Thermal Resistance Ambient (still air) of
PLCC44 with internal heat sink
44
P
max
Maximum Power Radiation of PLCC44 with
internal heat sink due to the thermal resis-
tance of the package
1370
still air, no cooling
58
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.2. Recommended Operating Conditions
Symbol
Parameter
Pin
Min.
Typ.
Max.
Unit
Name
ASUP
DSUP
PSUP
Analog Supply Voltage
Digital Supply Voltage
Pad Supply Voltage
Clock Frequency
AVDD
VDD
4.75
4.75
3.0
5.0
5.25
5.25
3.6
V
5.0
V
PVDD
3.3
V
f
XTAL1,
XTAL2
20.25
MHz
OSC
6.6.3. Power Consumption
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
supply current VPX 3220 A
between VDD and VSS
between AVDD and AVSS
between PVDD and PVSS
DD
115
35
135
44
155
53
mA
mA
mA
application dependent
I
supply current VPX 3216 B
between VDD and VSS
between AVDD and AVSS
between PVDD and PVSS
DD
86
mA
mA
mA
35
44
53
application dependent
The diagrams below illustrate some of the possible output modes and their impact on the power consumption. These
values are worst case numbers in terms of number of active output drivers. Only the video data interface A[7:0] and
B[7:0], and the clock signals PIXCLK have to be considered. As a first order approximation, the remaining signals have
no impact on the power consumption.
1.4
1.3
1.2
1.1
1.0
0.9
1.1
1.0
0.9
0.8
0.7
0.6
1370 mW: PLCC + heatsink
1089 mW: PLCC
VPX 3220 A
VPX 3216 B
890 mW: TQFP
1089 mW: PLCC
27MHz
20MHz
27MHz
20MHz
13MHz
27MHz
20MHz
13MHz
13MHz
27MHz
20MHz
13MHz
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
Cload [pF]
Cload [pF]
Based on a worst case scenario of 18 active output pins, no static loads, and a typical power consumption.
MICRONAS INTERMETALL
59
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.4. Characteristics, Reset
at T = 0 to 65 °C, V
= 4.75 to 5.25 V, f = 20.25 MHz for min./max. values
A
SUP
at T = 60 °C, V
= 5 V, f = 20.25 MHz for typical values
C
SUP
Symbol
Parameter
Min.
50
Typ.
Max.
Unit
Test Conditions
t
t
t
External Reset Hold Time
Internal Reset Hold Time
ns
µs
µs
RES EXT
RES INT
RES INT2
3.2
xtal osc. is working
2
Internal Register Setup after Reset (I C Ini-
tialization)
200
6.6.5. Input Characteristics of RES and OE
Symbol
Parameter
Min.
–0.5
2.0
Typ.
Max.
0.8
6
Unit
V
Test Conditions
V
V
V
V
Input Voltage LOW
IL
Input Voltage HIGH
–
V
IH
Trigger Level at Transition High to Low
Trigger Level at Transition Low to High
1.2
1.6
V
TRHL
TRLH
V
6.6.6. Recommended Crystal Characteristics
Symbol
Parameter
Min.
Typ.
–
Max.
65
Unit
°C
Test Conditions
T
A
Operating Ambient Temperature
Resonance Frequency
0
–
f
P
20.250
–
MHz
C = 13 pF,
L
T
A
= 25 °C
∆f /f
Accuracy of Adjustment
–
–
–
–
±20
±30
ppm
ppm
T
A
= 25 °C
P
P
∆f /f
Frequency Temperature Drift
over operating temperature
range with respect to fre-
quency at 25 °C
P
P
C
C
R
Shunt Capacitance
Motional Capacitance
Series Resistance
3
–
–
7
pF
fF
Ω
0
1
r
18
–
30
6.6.7. XTAL Input Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
V
I
Clock Input Voltage, XTAL1
1.3
V
PP
capacitive coupling of
XTAL1, XTAL2 open
60
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.8. Characteristics, Analog Video Inputs
Symbol
Parameter
Pin
Name
Min.
Typ.
Max.
2.5
Unit
V
Test Conditions
V
VIN
Analog Input Voltage
Input Capacitance
VIN1
VIN2
VIN3
CIN
0
C
C
C
13
pF
nF
nF
V
IN
= 1.5 V
IN
Input Coupling Capacitor
Video Inputs
VIN1–3
CIN
680
1
CP
CP
Input Coupling Capacitor
Chroma Input
MICRONAS INTERMETALL
61
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.9. Characteristics, Analog Front-End and ADCs
Symbol
Parameter
Pin Name
Min.
1.8
Typ.
2.0
Max.
2.2
Unit
Test Conditions
min. AGC Gain
max. AGC Gain
V
V
V
Full Scale Input Voltage, Video 1
Full Scale Input Voltage, Video 1
VIN1,
VIN2,
VIN3
V
PP
V
PP
V
VIN
0.5
0.6
0.7
VIN
Video 1 Input Clamping Level,
CVBS
1.0
Binary Level = 68 LSB
min. AGC Gain
VINCL
V
V
Full Scale Input Voltage, Chroma
CIN,
VIN1
1.08
1.2
1.2
1.32
V
V
CIN
PP
Video 2 Input Clamping Level,
CVBS
Binary Level = 68 LSB
VINCL
V
Video 2 Input Bias Level,
SVHS Chroma
–
1.5
2
–
V
CINB
R
Video 2 Input Resistance
SVHS Chroma
1.4
2.6
kΩ
CIN
Binary Code for Open
Chroma Input
VIN1
CIN
128
Q
Input Clamping Current
Resolution
VIN1–3,
CIN
–16
15
steps
CL
I
Input Clamping Current per step
Reference Voltage Top
Video 1 Bandwidth
0.7
2.5
1
1.3
2.8
µA
CL
V
VRT
2.6
10
V
10 µF/10 nF, 1 GΩ Probe
–3 dB for full-scale signal
–3 dB for full-scale signal
at 1 MHz
VRT
BW
MHz
MHz
dB
BW
Video 2 Bandwidth
10
XTALK
THD
SNDR
Crosstalk, any Two Video Inputs
Distortion
–56
–50
45
–42
dB
at 1 MHz, 5th harmonics
at 1 MHz, only one output
Video Signal to Noise
and Distortion Ratio
VIN1–3,
CIN
41
dB
INL
Video Integral Non-Linearity,
static
±1
LSB
Code Density
Code Density
DNL
DG
DP
Video Differential Non-Linearity
Video Differential Gain
±0.5
±0.8
±3
3
LSB
%
300 mV , 4.4 MHz on ramp
PP
Video Differential Phase
deg
300 mV , 4.4 MHz on ramp
PP
Dependency between SNR and Power Supply
45
44
43
42
41
40
39
38
Both ADCs are working and routed to A[7:0], and B[7:0].
All Interfaces are working with maximum driver strength
Bandwidth measurement is performed up to 5 MHz.
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
PVDD [V]
62
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.10. Characteristics of the JTAG Interface
TCK
800 Ω
800 Ω
TDO
Clock signal of the Test-Access Port. It is used to syn-
chronize all JTAG functions. When JTAG operations are
not being performed, this pin should be driven to VSS.
The input stage of the TCK uses a TTL Schmitt Trigger.
I = 4 mA
50 pF
TMS, TDI
Test Mode Selection and Test Data Input. Both signals
are inputs with a TTL compatible input specification. To
comply with JTAG specification they use pull-ups at their
input stage. The input stage of the TMS and TDI uses a
TTL Schmitt Trigger.
Fig. 6–15: TDO Test Circuit
TDO
Test Data Output. This signal is multiplexed with the
function ALPHA. The output specification conforms to
the specification of the TTL output driver type B.
Symbol
Parameter
Min.
Typ.
Max.
0.6
Unit
V
Test Conditions
V
V
Output Voltage LOW
Output Voltage HIGH
OL
2.4
–
PVDD
V
OH
A special VDD, VSS supply is used only to support the digital output pins. This means inherently that in case of tristate conditions, external
sources should not drive these signals above the voltage PVDD which supplies the output pins.
V
Input Voltage LOW
–0.5
2.0
0.8
6
V
V
IL
V
IH
Input Voltage HIGH
for input pin TCK
–
–
V
IH
Input Voltage HIGH
for input pin TDI, TMS
2.0
PVDD
+ 0.3
V
Φ
Φ
Φ
C
JTAG Cycle Time
TCK High Time
TCK Low Time
100
50
–
–
–
–
–
–
ns
ns
ns
CYCL
H
L
I
50
Input Capacitance
of Pins TCK
pF
pF
of Pins TDI and TMS
C
Output Capacitance (Pin TDO)
pF
O
I
I
I
Input Pull-up Current (Pins TDI and TMS)
Input Leakage Current (Pin TCK)
Output Leakage Current (Pin TDO)
mA
µA
µA
V = V
I SS
IH
V
SS
≤V ≤V
I DD
I
TAP controller is in TEST-
RESET state
O
Schmitt Trigger Hysteresis
This specification defines the Schmitt Trigger Hysteresis of the inputs TCK, TMS, and TDI.
V
Trigger Level at Transition High to Low
Trigger Level at Transition Low to High
1.2
1.6
V
V
TRHL
TRLH
V
MICRONAS INTERMETALL
63
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.10.1. Timing of the Test Access Port TAP
Φ
CYCL
Φ
Φ
H
L
TCK
t
S
t
H
TDI, TMS
TDO
t
D
t
t
OFF
ON
Fig. 6–16: Timing of Test Access Port TAP
Symbol
Parameter
Min.
Typ.
3
Max.
Unit
Test Conditions
t
S
t
H
t
D
TMS, TDI Setup Time
TMS, TDI Hold Time
ns
ns
ns
3
4
4
TCK to TDO Propagation Delay for Valid
Data
35
40
45
t
t
TDO Turn-on Delay
TDO Turn-off Delay
35
35
40
40
45
45
ns
ns
ON
OFF
64
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
2
6.6.11. Characteristics, I C Bus Interface
Symbol
Parameter
Pin
Name
Min.
1.5
Typ.
Max.
2.0
3.0
–
Unit
V
Test Conditions
V
V
Input Trigger Level
High to Low
SDA,
SCL
0.3*VDD
0.6*VDD
ITF
Input Trigger Level
Low to High
2.5
V
ITR
V
V
Input Trigger Hysteresis
Output Low Voltage
0.5
–
–
–
V
ITH
0.4
0.6
V
V
I = 3 mA
l
I = 6 mA
l
OL
V
Input Capacitance
–
–
–
–
–
–
20
pF
µA
ns
IH
I
t
t
f
t
t
Input Leakage Current
Signal Fall Time
–1
–
1
V vV vV
ss i dd
l
300
1000
400
C =400 pF
L
F
Signal Rise Time
–
ns
R
Clock Frequency
SCL
0
kHz
ns
SCL
s
Setup Time PREF to RES
Hold Time PREF to RES
PREF
10
10
ns
h
The state of PREF and PIXCLK pins are sampled at the
high (inactive) going edge of RES in order to determine
two power-on parameters (see Fig. 6–17).
V
V
V
V
IOH
IOL
IOH
IOL
RES
2
PREF determines the I C address:
PREF
PREF=0: Address ³1000 011
bin
bin
PREF=1: Address ³1000 111
t
t
t
t
s
h
PIXLCK determines the internal ROM table which is
2
used to initialize some of I C and FP registers (see sec-
+0:0
tion 4.9.)
V
V
IOH
PIXCLK
IOL
s
h
2
Fig. 6–17: I C Selection:
Slave Address (PREF) and
Init Table (PIXCLK)
MICRONAS INTERMETALL
65
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.12. Digital Video Interface
The following timing specifications refer to the timing diagrams of sections 6.6.12.1., 6.6.12.2., 6.6.12.3., and 6.6.12.4.
For pin driver specific values (driver types A and B) see 6.6.13.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
OE: see 6.6.5.
PIXCLK: Synchronous Mode
t
Cycle Time at 13.5 MHz internal Data Rate
74
ns
ns
CLK13
CLK20
t
Cycle Time at 20.25 MHz internal Data
Rate
49.4
k
Duty Cycle Φ / (Φ
Φ )
H
50
%
PIXCLK
H
L +
t
t
Output Signal Hold Time for
H2
A [7:0]
B [7:0]
ALPHA
15
16
16
16
17
17
18
19
19
ns
ns
ns
Output Signal Hold Time of VACT
3
4
6
ns
H3
LLC (is only available in synchronous output mode at a transport rate of 13.5 MHz.)
t
Cycle Time
37
18
10
ns
ns
ns
LLC
Φ
Pulse width ’HIGH’
12
7
24
12
H
t
H1
Output Signal Hold Time for PIXCLK
66
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
PIXCLK: Asynchronous Mode
V
V
Input Voltage LOW
–0.5
2.0
0.8
V
V
IL
Input Voltage HIGH
for input pin PIXCLK
–
PVDD +
0.3
IH
V
V
Trigger Level at Transition High to Low
Trigger Level at Transition Low to High
Cycle Time
1.2
1.6
V
TRHL
V
TRLH
Φ
Φ
Φ
35
ns
ns
ns
CYCL
Minimum Pulse width ’HIGH’
Minimum Pulse width ’LOW’
–
–
–
–
H
L
t
D
Delay PIXCLK(input) to
A [7:0]
11
ns
ns
ns
ns
ns
B [7:0]
20
20
tbd
20
neg. edge of FE
pos. edge of HF
ALPHA
A special PVDD, PVSS supply is used only to support the digital output pins. This means, inherently, that in case of
tristate conditions, external sources should not drive these signals above the voltage PVDD which supplies the output
pins.
All timing specifications are based on the following assumptions:
– the load capacitance of the fast pins (output driver type A) is C = 30 pF,
A
– the load capacitance of the remaining pins (output driver type B) is C = 50 pF;
B
– no static currents are assumed;
– the driving capability of the pads is STR = 4, which means that 5 of 8 output drivers are enabled.
The typical case specification relates to:
– the ambient temperature is T = 25 °C, which relates to a junction temperature of T = 70 °C;
A
J
– the power supply of the pad circuits is PVDD = 3.3 V, and the power supply of the digital parts is VDD = 5.0 V.
The best case specification relates to:
– a junction temperature of T = 0 °C;
J
– the power supply of the pad circuits is PVDD = 3.6 V, and the power supply of the digital parts is VDD = 5.25 V.
The worst case specification relates to:
– a junction temperature of T = 125 °C;
J
– the power supply of the pad circuits is PVDD = 3.0 V, and the power supply of the digital parts is VDD = 4.75 V.
Rise times are specified as a transition between 0.6 V to 2.4 V. Fall times are defined as a transition between 2.4 V to
0.6 V.
MICRONAS INTERMETALL
67
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.12.1. Characteristics, Synchronous Mode, 13.5 MHz Data Rate, “Single Clock”
LLC
PIXCLK
A[7:0],
B[7:0],
ALPHA
VACT
Data and VACT valid!
Detailed Timing
t
LLC
2.4 V
1.5 V
0.6 V
LLC
t
RA
t
H1
t
FA
t
FA
2.4 V
1.5 V
0.6 V
PIXCLK
A[7:0]
t
/t
RA FA
t
RA
t
H2
2.4 V
1.5 V
0.6 V
t
/t
RB FB
2.4 V
1.5 V
0.6 V
B[7:0],
ALPHA
t
t
H3
t
FA
RA
2.4 V
1.5 V
0.6 V
VACT
0 ns
18.5 ns
37 ns
55.5 ns
74 ns
92.5 ns
111 ns
68
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.12.2. Characteristics, Synchronous Mode, 20.25 MHz Data Rate, “Single Clock”
PIXCLK
A[7:0],
B[7:0],
ALPHA
VACT
Detailed Timing
t
CLK20
t
FA
t
RA
2.4 V
1.5 V
0.6 V
PIXCLK
A[7:0]
t
H2
t
/t
RA FA
2.4 V
1.5 V
0.6 V
t
/t
RB FB
2.4 V
1.5 V
0.6 V
B[7:0],
ALPHA
t
t
H3
t
FA
RA
2.4 V
1.5 V
0.6 V
VACT
0 ns
25 ns
50 ns
75 ns
100 ns
MICRONAS INTERMETALL
69
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.12.3. Characteristics, Synchronous Mode, 13.5 MHz Data Rate, “Double Clock”
PIXCLK
Byte 1 Byte 2 Byte 1 Byte 2 Byte 1 Byte 2 Byte 1 Byte 2
A[7:0]
ALPHA
VACT
Detailed Timing
t
CLK13
t
FA
t
RA
2.4 V
1.5 V
0.6 V
PIXCLK
A[7:0]
t
H2
t
/t
t
H2
RA FA
2.4 V
1.5 V
0.6 V
t
/t
RB FB
2.4 V
1.5 V
0.6 V
ALPHA
B[7:0]
t
t
H3
t
FA
RA
2.4 V
1.5 V
0.6 V
VACT
0 ns
18.5 ns
37 ns
55.5 ns
74 ns
92.5 ns
111 ns
70
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.12.4. Characteristics, Asynchronous Mode
negative slope of PIXCLK, depending on the setting of
2
the I C reg. F1
bit[2]. In asynchronous mode, the
hex
PIXCLK is always a single edge clock. If luma and chro-
ma data should be transferred via A-port (double clock
mode), then each data requires a complete clock cycle
of PIXCLK. A complete pixel (luma and chroma) needs
two complete clock cycles.
If the digital video interface is in asynchronous mode,
then the data transfer is controlled by an external clock
signal. Therefore, theinterfacesignalPIXCLKisusedas
an input signal. The video data refers to the positive or
PIXCLK (in)
pos. edge triggered
PIXCLK (in)
neg. edge triggered
A[7:0],
B[7:0],
ALPHA
FE
Detailed Timing
Φ
CYCL
Φ
Φ
Φ
H
L
2.4 V
1.5 V
0.6 V
PIXCLK (in)
pos. edge triggered
Φ
L
H
2.4 V
1.5 V
0.6 V
PIXCLK (in)
neg. edge triggered
t
/t
t
D
RA FA
2.4 V
1.5 V
0.6 V
A[7:0]
t
/t
RB FB
2.4 V
1.5 V
0.6 V
B[7:0],
ALPHA
t
t
D*
t
FA
RA
2.4 V
1.5 V
0.6 V
FE
0 ns
25 ns
50 ns
75 ns
100 ns
MICRONAS INTERMETALL
71
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Start and End of an Asynchronous Transfer Mode
internal clock
VACT
video data
input pointer
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
output pointer
0
if half full level
2
(I C Reg. F0
is 15
hex)
FE
HF
PIXCLK
Note: The positive slope of FE and the negative slope of HF is determined by internal timing!
There is no relation to any pin signal.
input pointer
n
output pointer
n–15 n–14 n–13 n–12 n–11 n–10 n–9 n–8 n–7 n–6 n–5 n–4 n–3 n–2 n–1
n
PIXCLK (input)
Video Data A[7:0], B[7:0]
if half full level
2
(I C Reg. F0
is 15
hex)
HF
FE
72
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
strength = 7
6.6.13. Characteristics, TTL Output Driver
Thedriversoftheoutputpadsareimplementedasapar-
allelconnectionof8tristatebuffersofthesamesize. The
buffers are enabled depending on the desired driver
strength. This opportunity offers the advantage of adapt-
ing the driver strength to on-chip and off-chip
constraints, e.g. to minimize the noise resulting from
steep signal transitions.
strength w 6
strength w 5
strength w 4
strength w 3
strength w 2
strength w 1
strength w 0
The driving capability/strength is controlled by the state
2
of the two I C registers F8
and F9
.
hex
hex
F8
Pad Driver Strength – TTL Output Pads Type A
bit [2:0] : Driver strength of Port A[7:0]
bit [5:3] : Driver strength of PIXCLK, HF and FE
bit [7:6] : additional PIXCLK driver strength
strength = bit [5:3] | {bit[7:6], 0}
F9
Pad Driver Strength – TTL Output Pads Type B
bit [2:0] : Driver strength of Port B[7:0]
bit [5:3] : Driver strength of HREF, VREF, PREF and
ALPHA/TDO
Fig. 6–18: Block diagram of the output stages
MICRONAS INTERMETALL
73
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.13.1. TTL Output Driver Type A
Symbol
Parameter
Min.
65
Typ.
RT
Max.
0
Unit
Test Conditions
Ambient Temperature
Supply
T
A
°C
VDD,
4.75
5.0
5.25
V
AVDD
PVDD
3.0
2
3.3
5
3.6
10
V
Pad Supply
t
t
I
I
I
I
Rise time
ns
C = 30 pF, strength = 5
l
RA
FA
Fall time
2
5
10
ns
C = 30 pF, strength = 5
l
(0)
Output High Current (strength = 0)
Output Low Current (strength = 0)
Output High Current (strength = 7)
Output Low Current (strength = 7)
High-Impedance Output Capacitance
–1.37
1.75
–11
14
–2.25
3.5
–18
28
5
–2.87
4.5
–25
36
mA
mA
mA
mA
pF
V
OH
V
OH
V
OH
V
OH
= 0.6 V
= 2.4 V
= 0.6 V
= 2.4 V
OH
(0)
OL
(7)
OH
(7)
OL
C
8
O
6.6.13.2. TTL Output Driver Type B
Symbol
Parameter
Min.
65
Typ.
RT
Max.
0
Unit
°C
Test Conditions
Ambient Temperature
Supply
T
A
VDD,
4.75
5.0
5.25
V
AVDD
PVDD
3.0
6
3.3
12
3.6
25
V
Pad Supply
t
t
I
I
I
I
Rise time
ns
C = 50 pF, strength = 5
l
RB
FB
OH
Fall time
6
12
25
ns
C =50 pF, strength = 5
l
(0)
(0)
Output High Current (strength = 0)
Output Low Current (strength = 0)
Output High Current (strength = 7)
Output Low Current (strength = 7)
High-Impedance Output Capacitance
–0.63
0.81
–5
–1.13
1.81
–9
–1.38
2.38
–12
19
mA
mA
mA
mA
pF
V
OH
V
OH
V
OH
V
OH
= 2.4 V
= 0.6 V
= 2.4 V
= 0.6 V
OL
(7)
OH
(7)
6.5
14.5
5
OL
C
8
O
74
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
6.6.14. Characteristics, Enable/Disable of Output
Signals
RESET State:
IftheTAP-controllerisnotintheEXTESTmode, thenthe
RESET-state defines the state of all digital outputs. The
only exception is made for the data output of the bound-
ary scan interface TDO. If the circuit is in reset condition
(RES = 0), then all output interfaces are in tristate mode.
In order to enable the output pins of the VPX to achieve
thehighimpedance/tristatemode, variouscontrolshave
been implemented. The following paragraphs give an
overview of the different tristate modes of the output sig-
nals. It is valid for all output pins, except the XTAL2
(which is the oscillator output) and the VRT pin (which is
an analog reference voltage).
2
I C Control:
The tristate condition of groups of signals can also be
2
controlled by setting the I C-Register F2 . If the circuit
hex
is neither in EXTEST mode nor RESET state, then the
BS (Boundary-Scan) Mode:
2
I C-Register F2
tate condition or not. The I C-Register #F1 uses differ-
ent bits for different groups of outputs (see “I C-Register
defines whether the output is in tris-
hex
2
The tristate control by the test access port TAP for
boundary-scan has the highest priority. Even if the TAP-
controller is in the EXTEST or CLAMP mode, the tristate
behavior is only defined by the state of the different
boundary scan registers for enable control. If the TAP
controller is in HIGHZ mode, then all output pins are in
tristate mode independently of the state of the different
boundary scan registers for enable control.
2
Table”).
Output Enable Input OE:
The output enable signal OE only effects the video out-
put ports. If the previous three conditions do not cause
the output drivers to go into high impedance mode, then
the OE signal defines the driving conditions of the video
data ports.
2
EXTEST
RESET
I C
OE#
Driver Stages
active
–
–
–
Output driver stages are defined by the state of the different
boundary-scan enable registers.
inactive
inactive
inactive
inactive
active
–
–
Output drivers are in high impedance mode.
inactive
inactive
inactive
= 0
= 1
= 1
–
Output drivers are in high impedance mode. PIXCLK is working.
Output drivers HREF, VREF, PREF, FE, HF are working.
–
= 1
Output drivers of ALPHA, A[7:0], B[7:0], and C[7:0] are in high impedance
mode.
inactive
inactive
= 1
= 0
Outputs ALPHA, A[7:0], B[7:0], and C[7:0] are working
Remark: EXTEST mode is an instruction conforming to the standard for Boundary-Scan Test IEEE 1149.1 – 1990
MICRONAS INTERMETALL
75
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Output Enable by Pin OE
OE
t
t
ON
OFF
Signals
A[7:0], B[7:0],
ALPHA
Symbol
Parameter
Min.
–0.5
2.0
Typ.
Max.
0.8
6
Unit
Test Conditions
V
IL
Input Voltage LOW
V
V
V
IH
Input Voltage HIGH
–
for Input pins OE, RES
V
V
Trigger Level at Transition High to Low
Trigger Level at Transition Low to High
Output Enable OE of A[7:0], B[7:0], ALPHA
1.2
1.6
6
V
TRHL
V
TRLH
t
ns
ns
ON
OFF
t
Output Disable OE of A[7:0], B[7:0], AL-
PHA
8
76
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Video Pixel Decoder Family Addendum
1. Introduction for Addendum
tems require that the inactive period of HREF also has
a fixed length: they use the inactive going edge of HREF
to reset their counters, count afterwards a certain
amount of clocks and then strobe the preprogrammed
number of data almost regardless of the state of VACT
signal. That’s why this new timing mode was introduced.
VPX 3214C has two additional features compared to the
VPX 3220A and VPX 3216B:
– another output timing mode called NewVACT and
– low power mode.
In this mode signal at VACT pin has an unpredictable be-
havior and NewVACT signal is available at the HREF pin
carrying all the information. It goes inactive, stays inac-
tive for the programmable number of transport rate
clocks. This inactive phase is at least 8 clocks long and
can be extended in clock units to the maximum length of
2. New Output Timing – NewVACT
The VPX family operates with a system and sampling
clock of 20.25 MHz. When the oscillator is not locked to
the line frequency of the processed video signal, the
numberofsamplespervideoscanlinecanvaryfromline
to line. The HREF signal marks the active video line and
has a fixed width of 1056 clocks. The inactive part of the
HREF can therefore vary in length. The same principle
applies to the VACT signal, the difference being that the
activelengthofVACTequalsthenumberofoutputpixels
times transport rate of either 20.25 or 13.5 MHz. This be-
havior of HREF and VACT signals is well suited for the
systems using state machines to handle these signals
and data delivered from VPX. On the other hand this be-
havior causes problems in case the system uses plain
counters to decide when to strobe the data. These sys-
2
23 by writing the field [3:0] of the OFIFO register (I C ad-
dress 0xF0). After that NewVACT goes active exactly
before the first valid video data, so it still can be used as
qualifier for the start of data. It stays active for the rest
of the line regardless of the number of valid video data,
soitcannotbeusedastheend-qualifier. Thesystemus-
ing the data has to count properly and strobe only the
valid data.
After reset, the VPX operates in its usual output timing
mode. Therearetworegisterscontrollingthenewmode.
2
The FP register is used to switch it on and off and I C
registerisusedtocontrolthelengthoftheHREFinactive
period.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
t
t
t
Hold Time of inactive going NewVACT after
PIXCLK
20
ns
HNVL
HNVH
HV
Hold Time of active going NewVACT after
PIXCLK
15
10
ns
ns
Hold Time of VREF change after PIXCLK
NewVACT–Timing (13.5/20.25MHz)
PIXCLK
HREF
oddfield changes
1. data
2. data
evenfield changes
VREF
DATA
......
MICRONAS INTERMETALL
77
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
Detailed Timing – inactive going NewVACT and
both VREF edges in Even Field
2.4 V
1.5 V
0.6 V
PIXCLK
t
HNVL
2.4 V
1.5 V
0.6 V
NewVACT
(on HREF pin)
t
HV
2.4 V
1.5 V
0.6 V
VREF
Detailed Timing – active going NewVACT and
both VREF edges in Odd Field
2.4 V
1.5 V
0.6 V
PIXCLK
t
HNVH
2.4 V
1.5 V
0.6 V
NewVACT
(on HREF pin)
t
HV
2.4 V
1.5 V
0.6 V
VREF
2
I C Reg.
Address
Number
of Bits
Mode
Function
Name
F0
8
w
Output FIFO
OFIFO
hfull
FIFO Control: (only available in Asynchronous Mode)
bit [4:0] : FIFO Flag – Half Full Level (interface signal HF)
NewVACT Control: (only available in Synchronous Mode)
bit [3:0] : Additional length of NewVACT inactive period.
Total length in clocks equals 8 + bit[3:0]
bit [4] : reserved (must be set to zero)
bit [7:5] : Bus Shuffler
shuf
000 Out[23:0] = In[23:0]
001,
010 Out[23:0] = In[7:0, 23:8]
011 Out[23:0] = In[15:0, 23:16]
100 Out[23:0] = In[15:8, 23:16, 7:0]
101,
110 Out[23:0] = In[7:0, 15:8, 23:16]
111 Out[23:0] = In[23:16, 7:0, 15:8]
Meaning:
In[23:0] : Data from Color Space Stage
Out[23:0] : Data to Output FIFO
The control register modes are
– w: write/read register
– d: register is double latched
– r: read-only register
– v: register is latched with vsync
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
The mnemonics used in the Intermetall VPX demo software are given in the last column.
78
MICRONAS INTERMETALL
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
3. Low power mode
scan line in which VPX is switched into low power mode.
During the low power mode all the I C and FP registers
2
Inordertoaccommodatepowerconsumptioncriticalap-
plications, low power mode is introduced. It can be
turned on and off through the I C register 0xAA. There
are three levels of low power. When any of them is
turned on, VPX waits for at least one complete video
scan line in order to complete all internal tasks and then
goes into three-state mode. The exact moment is not
precisely defined, so care should be taken to deactivate
the system using VPX data before the end of the video
are preserved, so that VPX restores its normal operation
as soon as low power mode is turned off without need for
2
2
any reinitialization. On the other hand all the I C and FP
registers can be read / written as usual. The only excep-
2
tion is the third level (value of 3 in I C register 0xAA) of
2
low power. In that mode, I C speeds above 100 kbit/sec
2
are not allowed. In modes 1 and 2, I C can be used up
to the full speed of 400 kbit/sec.
2
I C Reg.
Address
Number
of Bits
Mode
Function
Name
AA
8
w
Low power
bit [1:0] : Low power
lowpow
00 active mode
01 outputs three–stated; clock divided by 2; I C full speed
10 outputs three–stated; clock divided by 4; I C full speed
2
2
2
11
outputs three–stated; clock divided by 8; I C only up to 100 kbit/sec
The control register modes are
– w: write/read register
– d: register is double latched
– r: read-only register
– v: register is latched with vsync
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
The mnemonics used in the Intermetall VPX demo software are given in the last column.
MICRONAS INTERMETALL
79
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
4. Data Sheet History
1. Data sheet “VPX 3220 A, VPX 3216 B Video Pixel
Decoder”, Aug. 25, 1995, 6251-368-1PD: First prelimi-
nary release of the data sheet.
2. Data sheet “VPX 3220 A, VPX 3216 B, VPX 3214 C
Video Pixel Decoders”, July 1, 1996, 6251-368-2PD:
Second preliminary release of the data sheet. Major
changes:
– VPX 3214 C has been included
– Fig. 6–1: package dimensions changed
MICRONAS INTERMETALL GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
All information and data contained in this data sheet are with-
out any commitment, are not to be considered as an offer for
conclusion of a contract nor shall they be construed as to
create any liability. Any new issue of this data sheet invalidates
previous issues. Product availability and delivery dates are ex-
clusively subject to our respective order confirmation form; the
same applies to orders based on development samples deliv-
ered. By this publication, MICRONAS INTERMETALL GmbH
does not assume responsibility for patent infringements or
other rights of third parties which may result from its use.
Reprinting is generally permitted, indicating the source. How-
ever, our prior consent must be obtained in all cases.
E-mail: docservice@intermetall.de
Internet: http://www.intermetall.de
Printed in Germany
Order No. 6251-368-2PD
80
MICRONAS INTERMETALL
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