SMCP-672061E-30MQ [TEMIC]
FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28;
| 型号： | SMCP-672061E-30MQ |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28 先进先出芯片 CD |
| 文件： | 总17页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M672061E
16 K ꢀ 9 CMOS With Programmable Half Full Flag Parallel
FIFO Rad Tolerant
Description
The M672061E implements a first-in first-out algorithm, Using an array of eight transistors (8 T) memory cell, the
featuring asynchronous read/write operations. The FULL M672061E combine an extremely low standby supply
and EMPTY flags prevent data overflow and underflow. current (typ = 0.1 µA) with a fast access time at 15 ns
The Expansion logic allows unlimited expansion in word over the full temperature range. All versions offer battery
size and depth with no timing penalties. Twin address backup data retention capability with a typical power
pointers automatically generate internal read and write consumption at less than 2 µW.
addresses, and no external address information are
For military/space applications that demand superior
required for the TEMIC FIFOs. Address pointers are
levels of performance and reliability the M672061E is
automatically incremented with the write pin and read
processed according to the methods of the latest revision
pin. The 9 bits wide data are used in data communications
of the MIL STD 883 (class B or S) ,ESA SCC 9000 or
applications where a parity bit for error checking is
QML.
necessary. The Retransmit pin reset the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Features
D First-in first-out dual port memory
D 16384 × 9 organisation
D Fully expandable by word width or depth
D Asynchronous read/write operations
D Empty, full and half flags in single device mode
D Retransmit capability
D Fast Flag and access times: 15, 30 ns
D Wide temperature range : – 55 °C to + 125 °C
D Programmable Half Full Flag
D Bi-directional applications
D Battery back-up operation : 2 V data retention
D TTL compatible
D Single 5 V ± 10 % power supply
D High Performance SCMOS Technology
Rev. C – June 30, 1999
1
M672061E
Interface
Block Diagram
16384 x 9
16384
Pin Configuration
FP 28 pin 400 mils
(top view)
W
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
I
8
I
3
I
2
I
1
I
0
2
I
I
I
I
4
3
5
6
7
4
5
6
FL/RT
RS
XI
7
FF
8
EF
Q
Q
Q
Q
Q
9
XO/PHF
0
1
2
3
8
10
11
12
13
14
Q
Q
Q
Q
R
7
6
5
4
GND
2
Rev. C – June 30, 1999
M672061E
Pin Names
NAMES
DESCRIPTION
NAMES
FF
DESCRIPTION
I0–8
Q0–8
W
Inputs
Full Flag
Outputs
XO/PHF
Expansion Out/Programmable Half-
Full Flag
Write Enable
Read Enable
Reset
XI
Expansion IN
First Load/Retransmit
Power Supply
Ground
R
FL/RT
VCC
GND
RS
EF
Empty Flag
Signal Description
the Read Enable (R) and Write Enable (W) inputs must be
in the high state during the period shown in figure 1 (i.e.
Data In (I0 - I8)
Data inputs for 9 - bit data
t
before the rising edge of RS) and should not change
RSS
until t
after the rising edge of RS. Otherwise, pulse
RSR
write (or read) low during the reset operation has to effect
to load the Programmable Half Full Flag register grow the
Reset (RS)
Reset occurs whenever the Reset (RS) input is taken to a data Inputs I -I (or data outputs Q -Q ) (shown in figure
0
8
0
8
low state. Reset returns both internal read and write 2). In these two cases the Full Flag and the Programmable
pointers to the first location. A reset is required after Half Full Flag are reseted to high and the Empty Flag to
power-up before a write operation can be enabled. Both low.
Rev. C – June 30, 1999
3
M672061E
Figure 1. Reset (no write to Programmable Half Full Flag register)
t
(t
WR
RR)
Notes : 1. EF, FF and HF may change status during reset, but flags will be valid at t
.
RSC
2. W and R = VIH around the rising edge of RS.
Figure 2. Reset (write (read) to Programmable Half Full Flag register)
t
WR
RR)
(t
RS
t
t
WPW
WC
RC)
t
RSR
t
(t
( RPW)
W
(R)
t
t
DS
DH
I –I
0
8
DATA VALID
–
(Q0 Q8)
Write Enable (W)
Read Enable (R)
A write cycle is initiated on the falling edge of this input
if the Full Flag (FF) is not set. Data set-up and hold times
must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the
Ram array, regardless of any current read operation.
A read cycle is initiated on the falling edge of the Read
Enable (R) provided that the Empty Flag (EF) is not set.
The data is accessed on a first in/first out basis, not with
standing any current write operations. After Read Enable
(R) goes high, the Data Outputs (Q0 - Q8) will return to
a high impedance state until the next Read operation.
When all the data in the FIFO stack has been read, the
Empty Flag (EF) will go low, allowing the “final” read
cycle, but inhibiting further read operations whilst the
data outputs remain in a high impedance state. Once a
valid write operation has been completed, the Empty Flag
(EF) will go high after tWEF and a valid read may then
be initiated. When the FIFO stack is empty, the internal
read pointer is blocked from R, so that external changes
to R will have no effect on the empty FIFO stack.
Once half the memory is filled, and during the falling
edge of the next write operation, the Programmable
Half-Full Flag (PHF) will be set to low and remain in this
state until the difference between the write and read
pointers is less than or equal to half of the total available
memory in the device. The Programmable Half-Full Flag
(PHF) is then reset by the rising edge of the read
operation.
To prevent data overflow, the Full Flag (FF) will go low,
inhibiting further write operations. On completion of a
valid read operation, the Full Flag (FF) will go high after
TRFF, allowing a valid write to begin. When the FIFO
stack is full, the internal write pointer is blocked from W,
First Load/Retransmit (FL/RT)
so that external changes to W will have no effect on the This is a dual-purpose input. In the Depth Expansion
full FIFO stack.
Mode, this pin is connected to ground to indicate that it
4
Rev. C – June 30, 1999
M672061E
is the first loaded (see Operating Modes). In the Single operations when the read pointer is equal to the write
Device Mode, this pin acts as the retransmit input. The pointer, indicating that the device is empty.
Single Device Mode is initiated by connecting the
Expansion In (XI) to ground.
Expansion Out/Half-Full Flag (XO/HF)
The M672061E can be made to retransmit data when the
Retransmit Enable Control (RT) input is pulsed low. A
This is a dual-purpose output. In the single device mode,
retransmit operation will set the internal read point to the
when Expansion In (XI) is connected to ground, this
first location and will not affect the write pointer. Read
output acts as an indication of a half-full memory.
Enable (R) and Write Enable (W) must be in the high state
The M672061E offers a variable offset for the Half Full
condition. The offset is loaded into a register during a
reset cycle . When RS is low, the Programmable Half Full
during retransmit. The retransmit feature is intended for
use when a number of writes equals to or less than the
depth of the FIFO has occured since the last RS cycle. The
retransmit feature is not compatible with the Depth
Expansion Mode and will affect the Programmable
Half-Full Flag (PHF), in accordance with the relative
locations of the read and write pointers.
Flag (PHF) can be loaded from the DATA inputs I -I by
0
8
pulsing W low or from the DATA outputs Q –Q by
0
8
pulsing R low. The offset options are listed in table 1. If
PHF is not loaded during the reset cycle, the default offset
will be the half of the total memory of the device.
The Programmable Half-Full Flag (PHF) will be set to
low and will remain set until the difference between the
write and read pointers is less than or equal to the
Programmable offset (if the Half Full Flag register has
been loaded during the reset cycle) or the half of the total
memory (if the Half Full register has not been loaded
during the reset cycle).
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is
connected to GND to indicate an operation in the single
device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth
Expansion or Daisy Chain modes.
In the Depth Expansion Mode, Expansion In (XI) is
connected to Expansion Out (XO) of the previous device.
This output acts as a signal to the next device in the Daisy
Chain by providing a pulse to the next device when the
previous device reaches the last memory location.
Full Flag (FF)
The Full Flag (FF) will go low, inhibiting further write
operations when the write pointer is one location less than
the read pointer, indicating that the device is full. If the
read pointer is not moved after Reset (RS), the Full Flag
(FF) will go low after 16384 writes.
Data Output (Q0 - Q8)
DATA output for 9-bit wide data. This data is in a high
impedance condition whenever Read (R) is in a high state.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read
Rev. C – June 30, 1999
5
M672061E
Functional Description
Operating Modes
is in a Single Device Configuration when the Expansion In
(XI) control input is grounded (see Figure 3). In this mode
Single Device Mode
A single M672061E may be used when the application the Programmable Half-Full Flag (PHF), which is an
requirements are for 16384 words or less. The M672061E active low output, is shared with Expansion Out (XO).
Figure 3. Block Diagram of Single 16384 × 9.
PHF
(HALF–FULL FLAG)
(W)
9
(R)
(Q)
READ
WRITE
9
DATA
DATA
OUT
IN
(I)
M
672061
(EF)
(RT)
EMPTY FLAG
RETRANSMIT
FULL FLAG (FF)
(RS)
RESET
EXPANSION IN (XI)
Status flags (EF, FF and PHF) can be detected from any
device. Figure 4 demonstrates an 18-bit word width by
Width Expansion Mode
Word width may be increased simply by connecting the using two M672061E. Any word width can be attained by
corresponding input control signals of multiple devices. adding additional M672061E.
Figure 4. Block Diagram of 16384 × 18 FIFO Memory Used in Width Expansion Mode.
PHF
PHF
18
9
9
DATA (I)
IN
(R) READ
(EF) EMPTY FLAG
(RT) RETRANSMIT
WRITE
(W)
M
M
FULL FLAG
RESET
(FF)
672061
672061
(RS)
9
9
XI
XI
18
(Q) DATA
OUT
Note : 3. Flag detection is accomplished by monitoring the FF, EF and the PHF signals on either (any) device used in the width
expansion configuration. Do not connect any output control signals together.
6
Rev. C – June 30, 1999
M672061E
Table 1 : Programmable Half Full Flag Offset
I8
0
I7
0
I6
0
I5
0
I4
0
I3
0
I2
0
I1
0
I0
0
OFFSET
0
0
0
0
0
0
0
0
0
1
32
64
0
0
0
0
0
0
0
1
0
...
1
0
0
0
0
0
0
0
0
8192 (Half Full)
Default Offset
...
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
16384-64
16384-32
1
Table 2 : Reset and retransmit
Single Device Configuration/Width Expansion Mode
INPUTS
INTERNAL STATUS
Read Pointer Write Pointer
OUTPUTS
MODE
RS
0
RT
X
XI
0
EF
0
FF
1
PHF
Reset
Location Zero
Location Zero
Location Zero
Unchanged
1
Retransmit
Read/Write
1
0
0
X
X
X
X
(4)
(4)
1
1
0
Increment
Increment
X
X
Note : 4. Pointer will increment if flag is high.
Table 3 : Reset and First Load Truth Table
Depth Expansion/Compound Expansion Mode
INPUTS
INTERNAL STATUS
OUTPUTS
MODE
RS
0
FL
0
XI
(5)
(5)
(5)
Read Pointer
Write Pointer
Location Zero
Location Zero
X
EF
FF
1
Reset First Device
Reset All Other Devices
Read/Write
Location Zero
Location Zero
X
0
0
0
1
1
1
X
X
X
Note : 5. XI is connected to XO of previous device.
See fig. 5.
2. All other devices must have FL in the high state.
Depth Expansion (Daisy Chain) Mode
3. The Expansion Out (XO) pin of each device must be
connected to the Expansion In (XI) pin of the next
device. See figure 5.
The M672061E can be easily adapted for applications
which require more than 16384 words. Figure 5
demonstrates Depth Expansion using three M672061E.
Any depth can be achieved by adding additional 672061.
4. External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires that all
EF’s and all FFs be ØRed (i.e. all must be set to
generate the correct composite FF or EF). See figure 5.
The M672061E operates in the Depth Expansion
configuration if the following conditions are met :
1. The first device must be designated by connecting the
First Load (FL) control input to ground.
Rev. C – June 30, 1999
7
M672061E
5. The Retransmit (RT) function and Programmable In the write flow-through mode (figure 19), the FIFO
Half-Full Flag (PHF) are not available in the Depth stack allows a single word of data to be written
Expansion Mode.
immediately after a single word of data has been read
from a full FIFO stack. The R line causes the FF to be
reset, but the W line, being low, causes it to be set again
in anticipation of a new data word. The new word is
loaded into the FIFO stack on the leading edge of W. The
W line must be toggled when FF is not set in order to write
new data into the FIFO stack and to increment the write
pointer.
Compound Expansion Module
It is quite simple to apply the two expansion techniques
described above together to create large FIFO arrays (see
figure 6).
Bidirectional Mode
Applications which require data buffering between two
systems (each system being capable of Read and Write
operations) can be created by coupling M672061E as
shown in figure 7. Care must be taken to ensure that the
appropriate flag is monitored by each system (i.e. FF is
monitored on the device on which W is in use ; EF is
monitored on the device on which R is in use). Both Depth
Expansion and Width Expansion may be used in this
mode.
Data Flow – Through Modes
Two types of flow-through modes are permitted : a read
flow-through and a write flow-through mode. In the read
flow-through mode (figure 18) the FIFO stack allows a
single word to be read after one word has been written to
an empty FIFO stack. The data is enabled on the bus at
(tWEF + tA) ns after the leading edge of W which is
known as the first write edge and remains on the bus until
the R line is raised from low to high, after which the bus
will go into a three-state mode after tRHZ ns. The EF line
will show a pulse indicating temporary reset and then will
be set. In the interval in which R is low, more words may
be written to the FIFO stack (the subsequent writes after
the first write edge will reset the Empty Flag) ; however,
the same word (written on the first write edge) presented
to the output bus as the read pointer will not be
incremented if R is low. On toggling R, the remaining
words written to the FIFO will appear on the output bus
in accordance with the read cycle timings.
8
Rev. C – June 30, 1999
M672061E
Figure 5. Block Diagram of 49152 × 9 FIFO Memory (Depth expansion).
XO
W
R
FF
9
EF
FL
6
9
M
9
672061
Q
V
CC
FULL
EMPTY
FF
9
EF
FL
M
672061
EF
FL
FF
9
M
672061
RS
XI
Figure 6. Compound FIFO Expansion.
Q
0
– Q
Q
Q
– Q
– Q
Q
Q
– Q
– Q
8
9
17
17
(N–8)
N
N
Q
0
– Q
8
9
(N–8)
M 672061
M 672061
DEPTH
EXPANSION
BLOCK
M 672061
R . W . RS
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
I
0
– I
I
9
– I
8
17
I
– I
N
(N–8)
I
0
– I
I
9
– I
I – I
(N–8) N
8
17
Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4.
7. For Flag detection see section on Width Expansion and Figure 3.
Figure 7. Bidirectional FIFO Mode.
R
EF
B
W
A
M
B
FF
A
PHF
B
672061
I
Q
B 0–8
A 0–8
SYSTEM A
SYSTEM B
Q
A 0–8
I
B 0–8
M
R
A
672061
W
B
PHF
EF
A
FF
B
A
Rev. C – June 30, 1999
9
M672061E
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC – GND) . . . . . . . . . . . . . . . . . . – 0.3 V to 7.0 V
Input or Output voltage applied : . . . . (GND – 0.3 V) to (Vcc + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . – 65 °C to + 150 °C
OPERATING RANGE
Military
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
– 55 °C to + 125 °C
Vcc = 5 V ± 10 %
Vcc = 5 V ± 10 %
Automotive
– 40 °C to + 125 °C
DC Parameters
Parameter
Description
Operating supply current
Standby supply current
Power down current
M 672061-30
M 672061-15
UNIT
mA
VALUE
Max
I
150
1.5
165
1.5
CCOP (8)
I
mA
Max
CCSB (9)
I
400
400
µA
Max
CCPD (10)
Notes : 8. Icc measurements are made with outputs open.
9. R = W = RS = FL/RT = VIH.
10. All input = Vcc.
PARAMETER
DESCRIPTION
M672061E
UNIT
µA
µA
V
VALUE
ILI (11)
Input leakage current
± 1
± 10
0.8
2.2
2.2
0.4
2.4
8
Max
Max
Max
Min
Min
Max
Min
Max
Max
ILO (12)
Output leakage current
Input low voltage
Input high voltage
Input high voltage
Output low voltage
Output high voltage
Input capacitance
Output capacitance
VIL (13)
VIH (13)
VIH (13)
VOL (14)
VOH (14)
C IN (15)
C OUT (15)
V
V
V
V
pF
pF
8
Notes : 11. 0.4 ≤ Vin ≤ Vcc.
12. R = VIH, 0.4 ≤ VOUT ≤ VCC.
13. VIH max = Vcc + 0.3 V. VIL min = –0.3 V or –1 V pulse width 50 ns. For XI input VIH= 2.6V (Com), VIH= 2.8V (Mil, Auto, Ind)
14. Vcc min, IOL = 8 mA, IOH = –2 mA.
15. This parameter is sampled and not tested 100 % – TA = 25 °C – F = 1 MHz.
Input timing reference levels
Output reference levels
Output load
: 1.5 V
: 1.5 V
: See figure 8
AC Test Conditions
Input pulse levels
Input rise/Fall times
: Gnd to 3.0 V
: 5 ns
10
Rev. C – June 30, 1999
M672061E
Figure 8. Output Load.
5 V
500 Ω
TO
OUTPUT
PIN
30 pF*
333 Ω
* includes jig and scope capacitance
M672061E
– 30
M672061E
– 15
SYMBOL (16) SYMBOL (17)
READ CYCLE
PARAMETER (3) (7)
UNIT
MIN.
MAX.
MIN.
MAX.
READ CYCLE
TRLRL
tRC
Read cycle time
40
–
–
25
–
–
15
–
ns
ns
ns
ns
ns
ns
ns
ns
TRLQV
tA
Access time
30
–
TRHRL
tRR
Read recovery time
10
30
3
10
15
0
TRLRH
tRPW
tRLZ
tWLZ
tDV
Read pulse width (19)
Read low to data low Z (20)
Write low to data low Z (20, 21)
Data valid from read high
Read high to data high Z (20)
–
–
TRLQX
–
–
TWHQX
TRHQX
3
–
3
–
5
–
5
–
TRHQZ
tRHZ
–
20
–
15
WRITE CYCLE
TWLWL
WRITE CYCLE
tWC
tWPW
tWR
tDS
Write cycle time
Write pulse width (19)
Write recovery time
Data set-up time
Data hold time
40
30
10
18
0
–
–
–
–
–
25
15
10
9
–
–
–
–
–
ns
ns
ns
ns
ns
TWLWH
TWHWL
TDVWH
TWHDX
RESET CYCLE
TRSLWL
TRSLRSH
TWHRSH
TRSHWL
tDH
0
RESET CYCLE
tRSC
tRS
Reset cycle time
40
30
40
10
–
–
–
–
25
15
25
10
–
–
–
–
ns
ns
ns
ns
Reset pulse width (19)
Reset set-up time
tRSS
tRSR
Reset recovery time
RETRANSMIT CYCLE
RETRANSMIT
CYCLE
TRTLWL
TRTLRTH
TWHRTH
TRTHWL
FLAGS
tRTC
tRT
Retransmit cycle time
40
–
–
–
–
25
15
15
10
–
–
–
–
ns
ns
ns
ns
Retransmit pulse width (19)
Retransmit set-up time (20)
Retransmit recovery time
30
tRTS
tRTR
30
10
FLAGS
TRSLEFL
TRSLFFH
TRLEFL
TRHFFH
TEFHRH
TWHEFH
TWLFFL
TWLHFL
TRHHFH
TFFHWH
tEFL
Reset to EF low
–
–
30
30
30
30
–
–
–
25
25
15
17
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHFH, tFFH
tREF
Reset to HF/FF high
Read low to EF low
Read high to FF high
Read width after EF high
Write high to EF high
Write low to FF low
Write low to HF low
Read high to HF high
Write width after FF high
–
–
tRFF
–
–
tRPE
30
–
15
–
tWEF
tWFF
tWHF
tRHF
30
30
30
30
–
15
17
25
25
–
–
–
–
–
–
–
tWPF
30
15
Rev. C – June 30, 1999
11
M672061E
M672061E
– 30
M672061E
– 15
SYMBOL (16) SYMBOL (17)
PARAMETER (3) (7)
UNIT
MIN.
MAX.
MIN.
MAX.
EXPANSION
TWLXOL
TWHXOH
TXILXIH
TXIHXIL
TXILRL
tXOL
tXOH
tXI
Read/Write to XO low
–
30
30
–
–
15
15
–
ns
ns
ns
ns
ns
Read/Write to XO high
XI pulse width
–
–
30
10
10
15
10
10
tXIR
tXIS
XI recovery time
XI set–up time
–
–
–
–
Notes : 16. STD symbol.
17. ALT symbol.
18. Timings referenced as in ac test conditions.
19. Pulse widths less than minimum value are not allowed.
20. Values guaranteed by design, not currently tested.
21. Only applies to read data flow-through mode.
22. All parameters tested only.
Figure 9. Asynchronous Write and Read Operation.
12
Rev. C – June 30, 1999
M672061E
Figure 10. Full Flag from Last Write to First Read.
Figure 11. Empty Flag from Last Read to First Write.
Figure 12. Retransmit.
Note : 23. EF, FF and PHF may change status during Retransmit, but flags will be valid at t
.
RTC
Rev. C – June 30, 1999
13
M672061E
Figure 13. Empty Flag Timing
Figure 14. Full Flag Timing
Figure 15. Programmable Half-Full Flag Timing.
PROGRAMMABLE
PROGRAMMABLE
HALF FULL OFFSET OR LESS
HALF FULLOFFSETORLESS
MORE THAN HALF FULL
14
Rev. C – June 30, 1999
M672061E
Figure 16. Expansion Out.
Figure 17. Expansion In.
Figure 18. Read Data Flow – Through Mode.
Rev. C – June 30, 1999
15
M672061E
Figure 19. Write Data Flow – Through Mode.
16
Rev. C – June 30, 1999
M672061E
Ordering Information
TEMPERATURE RANGE
PACKAGE
DEVICE SPEED
FLOW
M
M
DP
67206EV
30
/883
15 ns
30 ns
blank
/883
MQ
SV
=
=
=
=
MHS standards
MIL-STD 883 CLASS B or S
QML–Q
QML–V
Preview*
CP =
DP = Flat pack 28 pins 400 mils
0 = Die form
32 pins 300 mils side brazed
672061 = 16384 × 9 FIFO
EV = Very low power and rad tolerant
M = Military
S = Space
–55° to +125°C
–55° to +125°C
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits
described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
Rev. C – June 30, 1999
17
相关型号：
SMCP-672061EV-15
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
SMCP-672061EV-15/883
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
SMCP-672061EV-30/883
FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
SMCP-672061EV-30MQ
FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
SMCP-672061EV-30SV
FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
SMCP-672061FV-15/883
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
SMCP-672061FV-15SB
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28,Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
SMCP-672061HV-15SB
FIFO, 16KX9, 15ns, Asynchronous, CDIP28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROCHIP
SMCP-672061HV-15SCC
Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable FlagWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ATMEL
SMCP-672061HV-30SB
FIFO, 16KX9, 30ns, Asynchronous, CDIP28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROCHIP
SMCP-672061HV-30SCC
Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable FlagWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ATMEL
SMCP-67206E-15/883
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TEMIC
©2020 ICPDF网 联系我们和版权申明