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TFDS4500-TR3 [TEMIC]

Interface Circuit, STAGGERED, MODULE-8;
TFDS4500-TR3
型号： TFDS4500-TR3
厂家： TEMIC SEMICONDUCTORS    TEMIC SEMICONDUCTORS
描述：

Interface Circuit, STAGGERED, MODULE-8
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中文：  中文翻译
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4500 Series  
Integrated Infrared Transceiver Module IrDA (SIR)  
Features  
D Compliant to IrDA 1.0 Standard  
D IrDA Data Rates Up to 115.2 kbps D Low Power Consumption  
Baud Rate  
D Two Package Options  
D AGC for EMI Immunity  
D 0- to 3.0-m Range  
– S Option – Side View  
– T Option – Top View  
D Wide Supply Voltage Range (2.7 V – 5.5 V)  
D Open Collector IRED Driver  
D Low Profile  
D Few External Components Required  
Description  
The TFDS4500 and TFDT4500 are infrared transceivers The internal IRED driver can be connected by an external  
for data communication systems. The transceivers are current control resistor to an independent unregulated  
compliant to the IrDA standard and allow data rates up to power supply, V . This adds circuit design flexibility  
CC2  
115 kbit/s. An internal AGC (Automatic Gain Control) and efficient serial drive capability for external IREDs for  
ensures proper operation under adverse EMI conditions.  
high power applications.  
Pin Configurations  
TFDT4500  
TFDS4500  
8
7
6
5
IRED  
Anode  
1
2
3
4
5
6
7
8
IRED Anode  
IRED Cathode  
Txd (Input)  
Rxd (Output)  
NC  
1
IRED  
Cathode  
Txd  
NC  
2
3
Rxd  
V
(Supply Voltage)  
V
CC1  
CC1  
SC (Sensitivity Control)  
GND  
SC  
GND  
4
Functional Block Diagram  
V
CC1  
Driver  
Rxd  
Amplifier  
Comparator  
IRED Anode  
AGC  
Logic  
SC  
Txd  
IRED Cathode  
Open Collector Driver  
GND  
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70737.  
TEMIC Semiconductors  
1
S–51444—Rev. A, 14-Jul-97  
Pre-Release Information  
4500 Series  
Absolute Maximum Ratings  
Parameter  
Symbol  
Test Conditionsa  
Minb Typc  
Maxb  
Unit  
Supply Voltage Range  
V
–0.5  
–0.5  
6
6
CC1  
V
Voltage Range of IRED Drive Output  
IRED anode pin, Txd LOW  
All pins except IRED cathode pin and  
IRED anode pin (See IRED Current)  
Input Currents  
10  
mA  
Output Sinking Current  
Power Dissipation  
25  
200  
125  
70  
P
(See Derating Curve)  
mW  
tot  
Junction Temperature  
T
J
Ambient Temperature Range (Operating)  
Storage Temperature Range  
Soldering Temperature  
T
0
A
_C  
T
stg  
–25  
215  
85  
t = 20 s  
240  
100  
500  
1
Average IRED Current  
I
I
(DC)  
(RP)  
(PK)  
IRED  
mA  
A
Repetitive Pulsed IRED Current  
Peak IRED Current  
I
t < 90 ms, Duty Cycle < 20%  
t < 2 ms, Duty Cycle < 10%  
IRED  
IRED  
IRED Anode Voltage  
V
–0.5  
–0.5  
–0.5  
6
IREDA  
Transmitter Data Input Voltage  
Receiver Data Output Voltage  
Virtual source size  
V
V
V
V
+ 0.5  
V
Txd  
CC  
CC  
+ 0.5  
Rxd  
d
Method: (1-1/e)  
2.5  
2.8  
mm  
Maximum Intensity for Class1  
Operation of IEC 825 or EN60825  
EN60825, 1.1.1.997  
400  
mW/sr  
Notes  
a. Reference point GND pin unless otherwise noted.  
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.  
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.  
Current Derating  
600  
Maximum Duty Cycle 20%  
400  
200  
Current derating as a  
function of the maximum  
forward current of IRED  
and maximum duty cycle.  
0
0
20  
40  
60  
80  
100  
120  
140  
Ambient Temperature T (_C)  
A
2
TEMIC Semiconductors  
S–51444—Rev. A, 14-Jul-97  
Pre-Release Information  
4500 Series  
Specifications  
Parameter  
Symbol  
Test Conditionsa  
Minb  
Typc Maxb  
Unit  
Transceiver  
Supported Data Rates  
Supply Voltage Range  
2.4  
2.7  
115.2  
kBit/s  
V
V
Reduced Function Down to 2.5 V  
5
5.5  
2.5  
1.5  
CCl  
V
V
= 5.5 V  
= 2.7 V  
1.3  
1.0  
CC1  
CC1  
Supply Current, V  
Pin  
I
mA  
CCl  
S
Leakage Current of IR Emitter,  
IRED Anode Pin  
V
OFF, Txd LOW, V  
T = –25 to 85_C  
= 6 V  
CC1  
CC2  
I
S
0.005  
0.5  
50  
mA  
ms  
Transceiver Power On Settling Time  
Receiver  
T = "15_, SIR Mode, SC = LOW  
T = "15_, SIR Mode, SC = HIGH  
0.020  
0.010  
5000  
0.035  
0.015  
Minimum Detection Threshold  
Irradiance  
E
emin  
d
0.006  
3300  
8000  
–2  
T = "90_, V = 5 V, SIR Mode  
Wm  
Maximum Detection Threshold  
CC  
E
emax  
d
Irradiance  
T = "90_, V = 3 V, SIR Mode  
15000  
CC  
Logic Low Receiver Input Irradiance  
Output Voltage Rxd  
E
SC = HIGH or LOW  
0.004  
0.8  
emax(low)  
V
Active, C = 15 pF, R = 2.2 kW  
Non-Active, C = 15 pF, R = 2.2 kW  
0.5  
4
OL  
V
V
V
– 0.5  
CC  
OH  
Output Current  
V
< 0.8 V  
mA  
ns  
OL  
Rise and Fall Time  
t , t  
r
C = 15 pF, R = 2.2 kW  
20  
200  
20  
f
2.4 kBits/s, Input Pulse Length  
1.41  
1.41  
3
1.41 ms to / of Bit Length  
16  
Rxd Signal Electrical  
Output Pulse Width  
t
p
115.2 kBits/s, Input Pulse Length  
8
2
3
1.41 ms to / of Bit Length  
16  
Output Level = 0.5 x V  
@
CC1  
t
t
1
ms  
dl  
2
e, f  
E = 0.040 W/m  
e
Output Delay Time (Rxd)  
Output Level = 0.5 x V  
6.5  
2
dt  
CC1  
g
Jitter  
t
j
Over a period of 10 bit, 115.2 kBIT/s  
Recovery from last transmitted pulse to  
1.1 x threshold sensitivity  
Latency  
t
100  
0.3  
800  
L
Transmitter  
Driver Current IRED  
Current limiting resistor in series to IRED:  
I
D
0.5  
0.8  
A
V
R
S
= 8.2 W, V  
= 5 V  
CC2  
Logic Low Transmitter Input Voltage  
Logic High Transmitter Input Voltage  
V
(Txd)  
(Txd)  
0
IL  
V
2.4  
V
CC  
IH  
Current limiting resistor in series to IRED:  
IeH  
45  
140  
200  
mW/sr  
R
S
= 8.2 W @ 5 V  
= 5 V, T = "15_  
CC2  
Output Radiant Intensity  
IeL  
Logic Low Level  
0.04  
mW/sr  
Angle of Half Intensity  
T
"24  
_
Peak Wavelength of Emission  
Halfwidth of Emission Spectrum  
l
p
850  
900  
nm  
60  
115.2-kHz Square Wave Signal  
Duty Cycle: 1.1  
Optical Rise/Fall Time  
Overshoot, Optical  
t , t  
200  
600  
25  
ns  
%
ms  
R
F
Over a period of 10 bits, independent of  
information content.  
Rising Edge Peak-to-Peak Jitter  
t
j
0.2  
Notes  
a. Unless otherwise specified T = 25_C, V = 5 V.  
A
CC  
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.  
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.  
–8  
d. BER = 10 (IrDA Specification)  
e.  
t
dl  
= delay of leading edge of output signal related to leading edge of optical input signal.  
f.  
t
= delay of trailing edge of output signal related to trailing edge of optical input signal.  
dt  
g. Leading edge of output signal.  
TEMIC Semiconductors  
3
S–51444—Rev. A, 14-Jul-97  
Pre-Release Information  
4500 Series  
Pin Assignment and Description  
Pin  
“S”  
“T”  
Option Option  
Pin Name  
Description  
I/O  
O
Active  
LOW  
8
1
7
1
2
3
IRED Anode  
IRED Anode  
IRED Cathode IRED Cathode, internally connected to driver transistor  
O
LOW  
Txd  
Rxd  
NC  
Transmitter Data Input  
I
HIGH  
Receiver Data Output, push-pull CMOS driver output capable of driving a standard  
CMOS or TTL load. No external pull-up or pull-down resistor is required.  
2
6
3
4
5
6
O
LOW  
No connection  
Supply voltage, 2.7 V to 5.5 V (Refer to 4000 Series Application Note for using  
V
CC1  
V
as shutdown pin)  
CC1  
5
4
7
8
SC  
GND  
Sensitivity control  
I
HIGH  
Ground  
a
Guide Pins  
“S” Option—Guide Pins (two), for surface mounting  
“T” Option—Guide Pins (two), used only for through-hole mounting  
–
–
b
Stand-off Pins  
Note  
a. Refer to application notes for connecting “S” option guide pins on PCB.  
b. Refer to application notes for connecting “T” option as a side view, through-hole device for wave soldering application.  
4
TEMIC Semiconductors  
S–51444—Rev. A, 14-Jul-97  
Pre-Release Information  
4500 Series  
TFDT, Top View Option  
E
E
1
A
2
R
1
A
3
A
1
Millimeters  
Inches  
Tolerance  
Tolerance  
Typical  
Typical  
Dim  
(")  
(")  
A
7.6  
0.5  
0.3  
0.3  
0.3  
0.3  
0.299  
0.169  
0.096  
0.085  
0.059  
0.020  
0.012  
0.012  
0.012  
0.012  
A
A
A
A
4.3  
1
2
3
4
d (EJECTION MARKS  
FRONT & BACKSIDE  
2.45  
2.15  
1.5  
θ
1
C
C
1
+0.1/  
− 0.05  
+0.004/  
− 0.002  
e
b
0.25  
0.5  
0.010  
0.020  
0.034  
E
2
C
0.1  
0.004  
+0.14/  
− 0.16  
+0.0055/  
− 0.0063  
C
1
0.86  
E
4
D
5.95  
5.45  
3.75  
1.8  
0.25  
0.25  
0.25  
0.25  
0.5  
0.5  
–
0.234  
0.215  
0.148  
0.074  
0.512  
0.256  
0.450  
0.236  
0.256  
0.050  
0.093  
0.008  
0.063  
0.010  
0.069  
0.079  
30_  
0.010  
0.010  
0.010  
0.010  
0.020  
0.020  
–
E
3
D
1
2
D
d
E
13.0  
6.5  
E
1
2
3
4
E
E
E
11.43  
6
0.5  
0.5  
–
0.02  
0.02  
–
R
4
R
3
θ
Tangential  
6.5  
3
e
1.27  
2.35  
0.2  
D
e
e
0.15  
0.2  
–
0.006  
0.008  
–
1
2
D
1
R
R
R
R
θ
1.6  
D
1
2
3
4
2
0.25  
1.75  
2
–
–
e
e
1
2
–
–
–
–
30_  
5_  
–
–
1
θ
θ
3_  
5
5_  
3_  
2
5_  
5_  
5
3
A
b
A
4
R
2
θ
2
TEMIC Semiconductors  
S–51444—Rev. A, 14-Jul-97  
5
Pre-Release Information  
4500 Series  
TFDS, Side View Option  
E
E
1
R
1
A
1
A
A
3
A
2
A
4
Millimeters  
Tolerance  
Inches  
Tolerance  
C
d (EJECTION MARKS  
FRONT & BACKSIDE  
Typical  
Typical  
Dim  
(")  
(")  
C
2
C
e
1
C
3
A
5.3  
4.3  
0.3  
0.3  
0.3  
0.3  
–
0.209  
0.169  
0.112  
0.124  
0.059  
0.012  
0.012  
0.012  
0.012  
–
q
1
A
A
A
A
1
2
3
4
E
E
2
q
2
2.85  
3.15  
1.5  
3
E
5
+0.004/  
-0.002  
b
0.25  
+0.1/-0.05  
0.010  
E
4
c
0.15  
0.5  
0.1  
0.1  
–
.0059  
0.020  
0.006  
0.004  
0.004  
–
C
C
1
0.16  
+0.012/  
-0.008  
C
C
0.58  
0.86  
+0.3/-0.2  
0.023  
0.034  
2
+0.0055/  
-0.0063  
+0.14/-0.16  
3
D
5.95  
5.45  
3.75  
1.8  
0.25  
0.25  
0.25  
2.34  
0.215  
0.148  
0.074  
0.512  
0.256  
0.450  
0.463  
0.236  
0.256  
0.050  
0.093  
0.264  
0.063  
0.008  
0.069  
0.0787  
30_  
0.110  
0.010  
0.010  
0.010  
0.020  
0.020  
–
D
1
R
3
D2  
d
q
4
Tangential  
R
4
E
13.0  
6.5  
0.5  
0.5  
–
D
E
1
E
2
E
3
E
4
E
5
D
1
11.43  
11.75  
6
–
–
D
2
0.5  
0.5  
–
0.02  
0.02  
–
6.5  
e
1.27  
2.35  
6.7  
e
e
0.15  
0.4  
–
0.006  
0.016  
–
1
2
q
6
R
R
R
R
q
1.6  
1
2
3
4
R
2
0.2  
–
–
c
q
1.75  
2.0  
–
–
5
–
–
L
30_  
15_  
180_  
5_  
–
–
1
2
3
4
5
6
q
q
q
q
q
–
30_  
–
–6_  
5
180_  
5_  
–6_  
5
q
3
b
e
1
5_  
3_  
2_  
0.2  
5_  
3_  
90_  
0.6  
90_  
2_  
e
2
L
0.024  
–0.008  
6
TEMIC Semiconductors  
S–51444—Rev. A, 14-Jul-97  
Pre-Release Information  
4500 Series  
Recommended SMD Pads for Transceiver  
1.27  
TFDT  
0.7  
1.4  
1
2
3
4
5
6
7
8
8.89  
TFDS  
11.75  
5.08  
2.54  
2.54  
1.43  
8
7
6
5
1.8  
0.63  
8.25  
1
0.63  
+0.1 (2x)  
1
4.13  
2.2  
1
2
3
4
2.54  
2.54  
5.08  
Dimensions in mm  
Ordering Information  
Order Part Number  
Qty/Reel  
TFDS4500-TR3  
TFDT4500-TR3  
750 Pieces  
750 Pieces  
All TEMIC transceivers are classified as IEC 825-1 Accessible Emission Limit (AEL) Class 1 based upon the current proposed draft scheduled to go  
into effect on January 1, 1997. AEC Class 1 LED devices are considered eye safe.  
TEMIC Semiconductors  
7
S–51444—Rev. A, 14-Jul-97  
Pre-Release Information  

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