U4256BM-NFS [TEMIC]
PLL Frequency Synthesizer, BICMOS, PDSO20, SSOP-20;
| 型号： | U4256BM-NFS |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | PLL Frequency Synthesizer, BICMOS, PDSO20, SSOP-20 |
| 文件： | 总14页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U4256BM
Frequency Synthesizer for Radio Tuning
Description
The U4256BM is a single chip frequency synthesizer in System) applications. It is controlled by 3-wire bus and
BICMOS technology. Together with the AM/FM IC contains also Digital to Analog Converters (DACs) for
U4255BM, it performs a complete AM/FM car radio front automatic alignment of the AM/FM tuner.
end, which is recommended also for RDS (Radio Data
Features
Reference oscillator up to 15 MHz (tuned)
Oscillator buffer output (for AM up/down conversion)
Two programmable 16-bit dividers
Four programmable switching outputs (open drain)
Three DACs for software controlled tuner alignment
Low power consumption
Fine-tuning steps: AM ≥ 1 kHz, FM ≥ 2 kHz
Fast response time due to integrated loop push-pull stage
High S/N ratio
3-wire bus (enable, clock and data; 3 V and 5 V micro-
controllers acceptable)
Integrated band gap
necessary
only one supply voltage
Block Diagram
SWO1 SWO2 SWO3 SWO4
10
7
8
9
Tuning
13
OSCIN
R–
divider
Oscillator
Switching outputs
12
DAC3
3–bit
OSCOUT
5
DAC3
V
Ref
15
OSC
buffer
MX2LO
DAC2
DAC1
4
DAC2
17
16
18
CLK
DATA
EN
3W–
bus
interface
3
DAC1
V
AM/FM
Ref
6
VS
1
19
FM–
preamp
N–
divider
Phase
detector
Current
sources
FMOSCIN
PDO
2
Band-gap
PD
20
14
11
96 11799
GNDan
V5
GND
Figure 1. Block diagram
Ordering Information
Extended Type Number
Package
SSO20
SSO20
Remarks
U4256BM-AFS
U4256BM-AFSG3
Taped and reeled
Rev. A2, 03-Nov-98
1 (14)
Preliminary Information
U4256BM
Pin Description
Pin
1
Symbol
PDO
Function
Analog output
1
20
19
18
17
16
15
14
13
GNDan
FMOSCIN
EN
PDO
2
PD
Current output
2
3
DAC1
Output 1,
digital to analog converter
Output 2,
digital to analog converter
Output 3,
digital to analog converter
Supply voltage analog part
Switching output 1
Switching output 2
Switching output 3
Switching output 4
Ground, digital part
PD
4
5
DAC2
DAC3
3
4
DAC1
DAC2
DAC3
VS
CLK
6
VS
7
SWO1
SWO2
SWO3
SWO4
GND
5
6
7
8
DATA
8
U4256BM
9
MX2LO
10
11
12
13
14
15
16
17
18
19
20
SWO1
SWO2
SWO3
V5
OSCOUT Oscillator output
OSCIN
V5
Oscillator input
OSCIN
Capacitor band gap
MX2LO Oscillator buffer output
12
11
9
OSCOUT
GND
DATA
CLK
EN
Data input
Clock
10
Enable
SWO4
FMOSCIN FM-oscillator input
GNDan Ground, analog part
96 11944
Figure 2. Pinning
Circuit Description
Functional Description
The U4256BM is especially designed for AM up/down
converter systems, together with the tuner U4255BM.
Due to the integrated DACs, an automatic tuner
alignment is possible. All the functions of the U4256BM
can be software controlled via a serial 3-wire bus,
consisting of Enable, Clock and Data. The format and
procedure for the data transfer from the microcontroller
is shown in figures 3, 4 and table Data Transfer. All
requested data have to be transferred via 16-bit or 24-bit
commands. Due to the 8-bit structure, the serial output
interface of a microcontroller can be used for the data
transfer. The PLL functions can be controlled by 24-bit
commands, while the alignment functions are controlled
by 16-bit commands. The alignment function control
normally is set once by switching on the tuner. Then the
tuner automatically will be aligned. The data for
alignment are stored in a separate EPROM. Via integrated
capacitors it is possible to tune the reference oscillator
(this function is controlled via the 3-wire bus).
The U4256BM is a single chip PLL circuit, designed for
AM/FM RDS (Radio Data System) applications. The
special design allows to build automatic alignment tuner
systems. Two programmable DACs (Digital to Analog
Converter) support the computer controlled alignment.
The U4256BM has a very fast response time of maximum
800 s (at 2 mA, fref = 100 kHz, measured on MPX
signal). It performs a high signal to noise ratio.
Only one supply voltage is necessary, due to a
integrated band gap.
The U4256BM is controlled via 3-wire bus.
2 (14)
Rev. A2, 03-Nov-98
Preliminary Information
U4256BM
Absolute Maximum Ratings
All voltages are referred to GND (Pin 15)
Parameters
Symbol
Value
Unit
V
Analog supply voltage
Input voltage
Pin 6
V
S
8 to 15
–0.3 to +12
–1 to +5
15
Pins 16, 17 and 18
Pins 7, 8, 9 and 10
Pins 7, 8, 9 and 10
V
I
V
Output current
I
mA
V
O
Output drain voltage
Ambient temperature range
Storage temperature range
Junction temperature
Electrostatic handling
V
OD
T
amb
–40 to +85
–40 to +125
125
°C
°C
°C
V
T
stg
T
j
V
ESD
t.b.d.
Thermal Resistance
Parameters
Symbol
Value
140
Unit
K/W
Junction ambient
when soldered to PCB
R
thJA
Operating Range
All voltages are referred to GND (Pin 15)
Parameter
Symbol
Min.
8
Typ.
8.5
Max.
14
Unit
Supply voltage range
Ambient temperature
Input frequency
Pin 6
V
S
V
°C
Tamb
RFi
–40
70
+85
160
65535
15
Pin 19
MHz
Programmable divider
Crystal oscillator
SF
2
Pins 12 and 13
fXTAL
0.1
MHz
Electrical Characteristics
Test conditions (unless otherwise specified): V = +8.5 V, T
= +25°C
S
amb
Parameters
Supply voltage
Test Conditions / Pins
Symbol
Min.
Typ.
8.5
10
Max.
12
Unit
V
Pin 6
Analog supply voltage
Supply current
Analog supply current
OSCIN
V
A
8
Pin 20
I
4.5
100
20
mA
A
Pin 13
f = 0.1 to 15 MHz
Pin 19
Input voltage
V
OSC
mV
rms
FMOSCIN
Input voltage
f = 70 to 120 MHz
f = 120 to 160 MHz
Pin 2
V
FMOSC
V
FMOSC
40
150
mV
mV
rms
rms
PD
Output current 1
Output current 2
Output current 3
Output current 4
Leakage current
PD = 2.5 V
PD = 2.5 V
PD = 2.5 V
PD = 2.5 V
PD = 2.5 V
20
80
25
100
500
2000
30
120
600
2400
20
µA
µA
µA
µA
nA
± IPD
400
1600
± IPDL
Rev. A2, 03-Nov-98
3 (14)
Preliminary Information
U4256BM
Electrical Characteristics (continued)
Test conditions (unless otherwise specified): V = +8.5 V, T
= +25°C
S
amb
Parameters
Test Conditions / Pins
Pin 1
– (V – V
Symbol
Min.
100
Typ.
200
Max.
Unit
PDO
Saturation voltage HIGH
LOW
V
),
V
SATH
500
400
mV
mV
SATH
A
PDOFM
I = 15 mA
V
SATL
SWO1, SWO2, SWO3, SWO4 (open drain) Pins 7, 8, 9 and 10
I = 1 mA,
V7,8,9,10 = 8.5 V
Output leakage current
HIGH
LOW
I
100
400
nA
OHL
Output voltage
DAC1, DAC2
Output current
Output voltage
V
SWOL
100
mV
Pins 3 and 4
I
1
mA
V
DAC1, 2
V
0.3
0.6
V – 0.5
S
DAC1, 2
Gain range (resolution 256 steps)
Offset range (resolution 24 steps)
DAC 3
2.3
0.7
–0.6
V
Pin 5
Output current
I
1
6
mA
V
DAC3
Output voltage (resolution 16 steps)
MX2LO
V
0.25
DAC3
Output AC voltage
At Pin15: 47 pF and 1 k
V
80
120
1.9
200
2.1
mV
V
MX2LO
pp
Output DC voltage
V
DC
1.6
3-Wire Bus Description
16-bit command
14858
EN
DATA
CLK
LSB
BYTE 1
MSB LSB
BYTE 2
MSB
24-bit command
EN
DATA
CLK
LSB
BYTE 1
MSB LSB
BYTE 2
MSB LSB
BYTE 3
MSB
e.g., Divider
IPD3
IPD4
IPD1
IPD2
25
27 28
26
R–Divider
211
OSCB
21
24
29 210
212
0
20
22 23
213 214 215
0
0
1
2
P–2 P–2 P–2
Status 0
Addr.
Figure 3. Pulse diagram
4 (14)
Rev. A2, 03-Nov-98
Preliminary Information
U4256BM
Data Transfer
A
MSB
BYTE 2
LSB
MSB
BYTE 1
LSB
ADDR.
Oscillator tuning function
1 0 8pF 32pF 16pF 8pF 4pF 2pF 1pF 0.5pF
B85 B84 B83 B82 B81 B80 B79 B78
B77 B76 B75 B74 B73 B72
B
MSB
Byte 3
STATUS 0
LSB MSB
BYTE 2
LSB
MSB
BYTE 1
LSB
ADDR.
R – DIVIDER
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
IPD IPD
1,2 3,4
OSCB
0 = on,
1 = off
P–2 P–2 P–2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B71 B70
B69
B68 B67 B66
B65
B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 B53 B52 B51 B50
C
MSB
BYTE 2
LSB MSB
BYTE 1
LSB
ADDR.
DAC1 – GAIN & OFFSET
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
O–2 O–2 O–2 O–2 O–2 O–2 G–2 G–2 G–2 G–2 G–2 G–2 G–2 G–2
B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36
D
MSB
Byte 3
STATUS 1
LSB
MSB
BYTE 2
LSB
MSB
BYTE 1
LSB
ADDR.
N – DIVIDER
15
2
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
AM = 1 SWO4 SWO3 SWO2 SWO1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
FM = 0
1=off,
0=on
1=off,
0=on
1=off,
0=on
1=off,
0=on
B35
B34
B33
B32
B31
B30
B29
B28 B27 B25 B24 B23 B22 B22 B21 B20 B19 B18 B17 B16 B15 B14
E
MSB
BYTE 2
LSB MSB
BYTE 1
LSB
ADDR.
DAC2 – GAIN & OFFSET
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
O–2 O–2 O–2 O–2 O–2 O–2 G–2 G–2 G–2 G–2 G–2 G–2 G–2 G–2
B13 B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Rev. A2, 03-Nov-98
5 (14)
Preliminary Information
U4256BM
Timing Information
Parameters
Test Conditions / Pins
Symbol
Min.
2.0
Typ.
Max.
Unit
3-wire bus, ENABLE, DATA, CLOCK
Pins 16, 17, 18
Input voltage
HIGH
LOW
V
BUS
V
BUS
V
V
MHz
1.0
1.0
Clock frequency
Period of CLK
HIGH
LOW
t
H
250
250
ns
ns
ns
t
L
Rise time EN, DA, CLK
Fall time EN, DA, CLK
Set-up time
t
400
100
r
f
s
t
ns
ns
ns
ns
t
100
250
0
Hold time EN
t
HEN
HDA
Hold time DA
t
Bus Timing
t
R
t
F
Enable
Data
t
t
HEN
S
t
F
t
R
tHDA
t
S
t
R
t
F
Clock
t
H
t
L
96 11826
Figure 4. Bus timing
6 (14)
Rev. A2, 03-Nov-98
Preliminary Information
U4256BM
Bus Control
The charge pump current can be choosen by setting the The gain of DAC1 has a range of 0.7 x V(PDO) to
2.15 x V(PDO). V(PDO) is the PLL tuning voltage
output. This range is divided into 256 steps. So one step
is approximately (2.15–0.7)/256 = 5.664 m. The gain can
be controlled by the Bits 36 to 43 (G–2 to G–2 ) as
following:
Bits IPD1, 2 (Bit 71) and IPD3, 4 (Bit 70) as following:
IPD (µA)
25
IPD1, 2
IPD3, 4
0
0
1
1
0
1
0
1
0
7
100
500
Gain
DAC1
Approx.
B43 B42 B41 B40 B39 B38 B37 B36
2000
0.7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0.70566
0.71133
0.71699
...
The oscillator buffer output can be switched by the OSCB
Bit as following (Bit 69):
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
MX2LO AC Voltage
OSCB
...
0
...
0
...
1
...
1
...
0
...
1
...
0
...
1
ON
0
1
1.00019
...
...
1
...
1
...
1
...
1
...
1
...
1
...
0
...
1
OFF
2.1386
2.14434
2.15 m
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
The DAC3 output voltage can be controlled by the
0
2
Bits P-2 to P-2 (Bits 66 to 68) as following:
DAC3 Offset Approx.
Bit68
Bit67
Bit66
The offset of DAC1 has a range of 0.5 to –0.6. This range
is divided into 64 steps. So one step is approximately
1.1V/63 = 17.2 m. The offset can be controlled by the Bits
0.5 V
1.1 V
1.8 V
2.4 V
3.1 V
3.7 V
4.4 V
5.0 V
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
5
44 to 49 (O–2 to O–2 ) as following:
Offset DAC1 B49 B48 B47 B46 B45 B44
Approx.
0.5
0.4828
0.4656
0.4484
...
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
...
0
...
1
...
1
...
1
...
1
...
0
–0.0156
...
The FM/AM function can be controlled by setting the
FM/AM Bit 34 as following:
...
1
...
1
...
1
...
1
...
0
...
1
0.5656
–0.5828
–0.6
FM/AM
FM
Bit 34
1
1
1
1
1
0
1
1
1
1
1
1
0
1
AM
The tuning capacity for the crystal oscillator has a range
of 0.5 pF to 71.5 pF. The values are coded binary. The
tuning can be controlled by the Bits 78 to 85 as following:
The switching output SWO1 to SWO4 can be controlled
as following (Bits 30 to 33):
C
(pF)
B85 B84 B83 B82 B81 B80 B79 B78
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Switch Output
SWOx = ON
SWOx = OFF
Bit
0
0.5
1.0
1.5
...
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
...
1
...
0
...
0
...
0
...
0
...
0
...
0
...
0
63.5
71.5
0
0
0
0
0
0
0
0
Rev. A2, 03-Nov-98
7 (14)
Preliminary Information
U4256BM
The gain of DAC2 has a range of 0.7 x V(PDO) to The offset of DAC2 has a range of 0.5 to –0.6. This range
2.15 x V(PDO). V(PDO) is the PLL tuning voltage is divided into 64 steps. So one step is approximately
output. This range is divided into 256 steps. So one step 1.1V/63 = 17.2 m. The offset can be controlled by the
0
5
is approximately (2.15–0.7)/256 = 5.664 m. The gain can Bits 8 to 13 (O–2 to O–2 ) as following:
0
7
be controlled by the bits 0 to 7 (G–2 to G–2 ) as
following:
Offset DAC2 B13 B12
Approx.
B11 B10
B9
B8
Gain
DAC2
Approx.
B7 B6 B5 B4 B3 B2 B1 B0
0.5
0.4828
0.4656
0.4484
...
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0.7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0.70566
0.71133
0.71699
...
...
0
...
1
...
1
...
1
...
1
...
0
0
0
0
0
0
0
1
0
–0.0156
...
0
0
0
0
0
0
1
1
...
1
...
1
...
1
...
1
...
0
...
1
...
0
...
0
...
1
...
1
...
0
...
1
...
0
...
1
0.5656
–0.5828
–0.6
1.00019
...
1
1
1
1
1
0
...
1
...
1
...
1
...
1
...
1
...
1
...
0
...
1
1
1
1
1
1
1
2.1386
2.14434
2.15 m
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
Input / Output Interface Circuits
PDO
PD
PD is the current charge pump output of the PLL. The
current can be controlled by setting the Bits IDP1, 2 and
IDP3, 4. The loop filter has to be designed corresponding
to the choosen pump current and the internal reference
frequency. A recommendation can be found in the
application circuit.
PDO is the loop amplifier output of the PLL. The bipolar
output stage is a rail-to-rail amplifier.
V5
14859
V5
C
PDO
PD
Figure 5.
8 (14)
Rev. A2, 03-Nov-98
Preliminary Information
U4256BM
FMOSCIN
FMOSCIN is the preamplifier input for the FM/AM oscillator signal.
FMOSCIN
AMOSCIN
14860
Figure 6.
MX2LO
EN, DATA, CLK
MX2LO is the buffered output of the crystal oscillator.
All functions can be controlled via a 3-wire bus consisting
of ENABLE, DATA and CLOCK. The bus is designed for
microcontrollers which operate with 3 V supply voltage.
Details of the data transfer protocol are shown in the table
‘Data Transfer’.
V5
V5
VDD
OSCIN
EN
DATA
CLK
MX2LO
14863
14861
Figure 7.
Figure 9.
DAC 1, 2 and 3
SWO1, 2, 3 and 4
DAC 1 to 3 are the outputs for automatic tuner alignment.
VS
All switching outputs are ‘open drain’ and can be set and
reset by software control. Details are described in the data
transfer protocol.
SWO1
SWO2
SWO3
SWO4
DAC1
14862
14864
Figure 8.
Figure 10.
Rev. A2, 03-Nov-98
9 (14)
Preliminary Information
U4256BM
OSCIN, OSCOUT
A crystal resonator (up to 16 Mhz) is connected between
OSCIN and OSCOUT in order to generate the reference
frequency. The complete application circuit is shown in
figure 15. If a reference is available, it can be applied at
OSCIN. The minimum voltage should be 100mVrms. In
this case, pin OSCOUT has to be open.
VDD
OSCIN
VDD
OSCOUT
14865
Figure 11.
Application Information
Function of DAC1, 2 in the FM Mode
Function of DAC1, 2 in the AM Mode
In AM mode, DAC1, 2 can be used as standard DAC
converters. The resolution of 8 bit is controlled via the
gain bits in a range of approximately 0.5 V to 7 V,
depending on the offset value.
For automatic tuner alignment, the DAC1 and 2 of the
U4256BM can be controlled by setting gain and offset
values. The following figure shows the principle of the
operation in FM mode. The gain is in the range of
0.7 to 2.15. The offset range is +0.5 V to –0.6 V. For
alignment, DAC1 and 2 are connected to the varicaps of
the preselection filter and the IF filter. For alignment,
offset and gain is set for having the best tuner tracking
FMOSCIN Sensitivity
Vi (mV on 50
)
rms
150
100
50
PDO
DAC1,2
Gain
+/–
Offset
14907
0
0
20
40
60
80
100
120 140 160
Frequency (MHz)
Figure 12.
Figure 13.
10 (14)
Rev. A2, 03-Nov-98
Preliminary Information
U4256BM
Oscillator Tuning Function Schematic
Cx1
Cx2
INV
.5p
8p
32p 16p 8p
4p
2p
1p
.5p
1p
2p
4p
8p 16p 32p 8p
B78
B79
B80
B81
B82
B83
B84
B85
Figure 14.
Application Circuit
EN
CLK DATA
V5
GND
C12
100 nF
C9
33 pF
R5
5.1 kΩ
33 pF
C8
47 pF
4 MHz
13 12
20
19
18
17
16
15
14
11
C1
10 pF
R2
600 Ω
U4256BM
FM
OSC
1
2
3
5
6
4
7
8
9
10
C16
C5
C6
330 pF
C7
10 nF
R4
C15
C4
10 kΩ
10 nF
100 nF
C14
10 nF
100 µF
R3
10 nF
100 Ω
DAC1 DAC2 DAC3 VS
8 ... 12 V
SWO1 SWO2 SWO3 SWO4
9611257
Figure 15. Application circuit
Rev. A2, 03-Nov-98
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Preliminary Information
U4256BM
Application Board Schematic
Figure 16. Application borad schematic
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Rev. A2, 03-Nov-98
Preliminary Information
U4256BM
Package Information
Package SSO20
Dimensions in mm
5.7
5.3
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
5.85
20
11
technical drawings
according to DIN
specifications
13007
1
10
Rev. A2, 03-Nov-98
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Preliminary Information
U4256BM
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC Semiconductor GmbH semiconductor division has been able to use its policy of continuous improvements
to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
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Preliminary Information
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