UAA145 [TEMIC]
Phase Control Circuit for Industrial Applications; 相位控制电路用于工业应用
| 型号： | UAA145 |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Phase Control Circuit for Industrial Applications |
| 文件： | 总11页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UAA145
Phase Control Circuit for Industrial Applications
Description
The UAA145 is a bipolar integrated circuit, designed to circuits to be drastically reduced. The versatility of the
provide phase control for industrial applications. It device is further enhanced by the provision of a large
permits the number of components in thyristor drive number of pins giving access to internal circuit points.
Features
Applications
Industrial power control
Separate pulse output synchronized by mains
half wave
Silicon controlled rectifier
Output pulse-width is freely adjustable
Phase angle variable from >0° to <180°
High-impedance phase shift input
Package: DIP16 (special case)
Less than 3° pulse symmetry between two half-cycles
or phase of different integrated circuits
Output pulse blocking
Block Diagram
9
6
Pulse inhibit
16
Voltage
synchronisation
PHW
NHW
Channel
selection
R
Ramp generator
Comparator
10
14
Puls
generator
Memory
S
7
Pos. / Neg.
half wave
Supply
–V
Ref
15
+15
–15
13
3
1
8
11
2
95 11298
PHW = Positive half wave
NHW = Negative half wave
Figure 1. Block diagram
TELEFUNKEN Semiconductors
1 (11)
Rev. A1, 29-May-96
UAA145
General Description
Ramp Generator
The operation of the circuit is best explained with the help
of the block diagram shown in figure 1. It comprises a
synchronizing stage, ramp generator, voltage
com-parator, pulse generator, channel selecting stage and
two output amplifiers. The circuit diagram in figure 2 also
shows the external components and terminal connections
necessary for operation of the circuit.
Transistor T7 amplifies the zero-crossover switching
pulses. During the sync process capacitor CS at Pin 7 is
charged to the operating voltage of reference diode Z4,
i.e., to approximately 8.5 V, the charging time being
always less than the duration of the sync pulse. The
capacitor discharges via resistor RS during each
half-cycle. The discharge voltage is of the same
As can be seen from figure 2, the circuit requires two magnitude as the charge voltage, and is determined by Z3.
supply rails i.e. a +15 V and a –15 V. The positive voltage To ensure an approximately linear ramp waveform, the
is applied directly to Pin 1, while an external series voltage is allowed to decay up to ca. 0.7 CsRs. Because
resistor in each line is used to connect the negative Z-diodes Z3 and Z4 have the same temperature
voltage Pin 13 and Pin 15. In the following circuit characteristics, the timing of the ramp zero crossover
description each section of the block diagrams is point in relation to that of the sync. pulse is constant, and
discussed separately.
consequently the pulse phasing rear limit is also very
stable.
Synchronization Stage
Pin 9 is connected, via a voltage divider (22 k and Rp),
to the ac line (sync. signal source). A pulse is generated
during each zero crossover of the sync. input. The pulse
duration depends on the resistance Rp and has a value of
50 to 100 s. (figure 2).
In addition to providing zero voltage switching pulses this
section of the circuit generates blocking signals for use in
the channel selecting stage.
Figure 2. Block diagram and basic circuit
2 (11)
TELEFUNKEN Semiconductors
Rev. A1, 29-May-96
UAA145
pulse can be monitored by means of an oscilloscope ap-
Comparator (Differential Amplifier)
and Memory
plied to Pin 6. The Pin 11 pulse waveform is that at C , and
t
the waveforms at Pin 10 and Pin 11 are those of the output
pulses.
In the (voltage) comparator stage, the ramp voltage is
compared with the shift voltage V applied to Pin 8. The
comparator switches whenever the instantaneous ramp
voltage is the same as the shift voltage (corresponding to
the desired phase angle), thereby causing the memory to
be set, i.e. the integrated thyristor in memory is to be
turned on. The time delay between the signal input and
the comparator output signal is proportional to the
required phase angle. Design of the circuit is such that the
memory content is reset only during the instant of zero
crossover, the reset signal always overriding the set
signal. This effectively prevents the generation of
additional output pulses and causes any pulse already
started to be immediately inhibited on application of an
inhibit signal to Pin 6. The memory content can also be
reset via Pin 6. Thus the memory ensures that any noise
(negative voltage transients) superimposed on the shift
signal at Pin 8 cannot give rise to the generation of
multiple pulses during the half-cycle.
Pulse Generator
(Monostable Multivibrator)
The memory setting pulse also triggers a monostable
stage. The duration of the pulse produced by the mono-
stable is determined by C and Rt, connected to Pin 2 and
t
Pin 11.
Channel Selection and Output
Amplifier
A pulse is produced at either output Pin 10 or Pin 14 if
transistor T20 or T19 respectively is cut-off. The pulses
derived from the pulse generator are applied to the output
transistors via OR gates controlled by the half-cycle
signals derived from the sync stage. During the positive
half-cycle no signal is applied from the sync stage to T19
so that an output pulse is produced at Pin 14. The same is
valid for Pin 10 during the negative half-cycle.
Figure 3. Pulse diagram
Influence of External Components,
Syncronization Time
An ideal 0 to 180 shift range and perfect half-cycle pulse
timing symmetry are attained, if the sync pulse duration
is kept short. However, there is a lower pulse duration
limit, which is governed by the time required to charge
capacitor Cs (figure 5).
Pulse Diagram
Figure 3 shows the pulse voltage waveforms measured at
various points of the circuit, all signals being time
referenced to the sync signal shown at the top. The input
circuit limits any signal applied to 0.8 V at Pin 9. The
sync pulse can be measured at Pin 16, whereas the ramp
waveform and the pulse phasing rear limit ( h) are at
Pin 7. The time relationship between the shift voltage ap-
plied to Pin 8 and the ramp waveform is indicated by
dotted lines. A pulse trigger signal is produced whenever
As can be seen, it takes about 35 s to charge Cs. The sync
time can be altered by adjustment of Rp, the relationship
between Rp and the sync time being shown in figure 6.
The ratio of R and Rp determines the width of internal
sync pulse, tsync, at Pin 16. The pulse shape is valid only
for sync pulse of 230 V∼. The lower the sync voltage,
longer is the sync pulse.
A minimum of 50 s (max. 200 s) input sync pulse is
the ramp crosses the shift level. The memory control required for a pulse symmetry of
3°.
TELEFUNKEN Semiconductors
3 (11)
Rev. A1, 29-May-96
UAA145
95 11299
600
500
400
300
200
100
0
Sync. Time
vsync
V
=230V
R=22k
Sync.
t
2
t
Sync.
v14
v10
Pin16
v10,14
t
h
v
1000
0.1
1
10
( k
100
95 10106
R
P
)
Figure 4. Pulse phasing
Figure 6.
P 20mA/div.
7
Output Pulse Width
The output pulse width can be varied by adjustment of Rt
and Ct. In figure 11 pulse width is shown plotted as a func-
tion of Rt for Ct = 50 nF.
–0mA
P 2V/div.
7
The output pulse always finishes at zero crossover. This
means that if there is a minimum pulse width requirement
(for example, when the load is inductive) provision must
be made for a corresponding pulse phasing rear limit. The
output stages are arranged so that the transistors are cut
off when a pulse is produced. Consequently, the thyristor
trigger pulse current flows via the external load resistors,
this current being passed by the transistors during the
period when no output pulse is produced. During this
period the output voltage drops to the transistor saturation
level and is therefore load dependent. Figure 12 shows
the relationship between saturation voltage and load
current.
–0V
95 10105
Figure 5. Charging time 10 s/div.
Pulse Phasing Limits
The pulse phasing front limit is determined by limiting
the maximum shift voltage applied to Pin 8 which is thus
adjustable by external circuitry. This can be done by
connecting a Z-diode between Pin 8 and Pin 3. The pulse
phasing rear limit, h, is the residual phase angle of the
output pulses when the shift voltage V is zero. Since
h coincides with the zero crossover point of the ramp, it
can be adjusted by variation of the time constant CsRs
(figure 14). Figure 10 shows the pulse phasing rear limit
plotted as a function of Rs.
Shift Characteristic
In figure 13 the angle of phase shift is shown plotted as a
function of the voltage applied to Pin 8 for a pulse phasing
rear limit of approximately 0 . Because the ramp wave-
form is a part of the exponential function, the shift curve
is also exponential.
The limitation of the shift voltage to approximately 8.5 V
is due to the internal Z-diode Z4, which has a voltage
spread of 7 to 9 V.
Pulse Blocking
The output pulses can be blocked via Pin 6, the memory
content being erased whenever Pin 6 is connected to +VS
(Pin 1). This effectively de-activates the pulse generator;
any output pulse in the process of generation is inter-
rupted.
The waveforms in figures 7 to 9 show the output pulse
phase shift as a function of V . It can be seen from the
oscillograms, the instants at which pulses are released
coincide with the intersections of the ramp and the shift
voltage.
Pulse blocking can be accomplished either via relay
contacts or a PNP switching transistor (figure 14).
4 (11)
TELEFUNKEN Semiconductors
Rev. A1, 29-May-96
UAA145
P Ramp 2V/div.
200
160
120
7
Pulse Phasing Rear Limit
V =0, C =100nF
B
s
–0mA
P Ref. Voltage 2V/div.
8
0V
80
40
0
V
20V/div.
14
0V
V
20V/div.
10
–0V
95 10107
95 10108
95 10294
Figure 7. Output pulses phase shift 2 ms/div
200
0
40
80
R ( k
120
)
160
95 10295
s
Figure 10.
10
8
Output Pulse Width
P Ref. Voltage 2V/div.
8
C =50nF
P Ramp 2V/div.
7
t
6
0V
V
20V/div.
20V/div.
14
0V
V
4
2
0
10
0V
Figure 8. Output pulses phase shift 2 ms/div
200
0
40
80
120
)
160
95 10296
R ( k
t
Figure 11.
P Ref. Voltage 2V/div.
8
P Ramp 2V/div.
7
0V
V
20V/div.
20V/div.
14
0V
V
10
0V
Figure 9. Output pulses phase shift 2 ms/div
TELEFUNKEN Semiconductors
5 (11)
Rev. A1, 29-May-96
UAA145
200
160
120
0.6
0.5
Saturation
Output Voltages
0.4
0.3
0.2
0.1
0
80
40
0
Shift Characteristics
=0, =f (V )
h
8
10
40
0
2
4
6
8
0
10
20
30
95 10297
V ( V )
8
95 10298
I , I ( mA )
10 14
Figure 12.
Figure 13.
Absolute Maximum Ratings
Reference point Pin 3, Tamb = 25°C, unless otherwise specified
Parameters
Symbol
VS
Value
18
Unit
V
Positive supply voltage
Shift voltage
Pin 1
Pin 8
V
V
VS1
5
V
V
Reverse voltage, control input
Negative supply current
Pin 11
–VIR
–IS
15
V
Pin 13
Pin 15
25
5
mA
Synchronization current
Control input pulse current
Output currents
Pin 9
20
3
mA
mA
mA
Isync
II
Pin 11
Pin 10
Pin14
IO
20
20
Total power dissipation
Tamb 70°C
Ptot
550
mW
Junction temperature
Ambient temperature range
Storage temperature range
Tj
125
°C
°C
°C
Tamb
Tstg
–25 to +70
–25 to +125
Thermal Resistance
Parameters
Symbol
Value
100
35
Unit
K/W
Junction ambient
Junction case
6 (11)
TELEFUNKEN Semiconductors
Rev. A1, 29-May-96
UAA145
DC Characteristics
VS1 = 13 to 16 V, –IS13 = 15 mA, reference point Pin 3, figure 2, Tamb = 25 C, unless otherwise specified
Parameters
Positive supply current
Test Conditions / Pin
Symbol
IS
Min.
12
Typ.
Max.
30
Unit
mA
VS = 16 V
Pin 1
Voltage limitation
–IS13 = 15 mA
–IS15 = 3.5 mA
Pin 13
Pin 15
–VZ2
–VZ3
VZ4
7.0
7.0
7.0
9.0
9.0
9.0
V
VS = 13 V, V9 = 0V Pin 16
VS = 16 V, Pin 8
8 = 13 V,
V7 = 0V, I9 = 0.3 mA
Input current
I
10
V
Ct-potential shift current VS = VI2 =13 V,
VI7 = 3 V, I 8 = 5
II
4.5
10
mA
mA
Ct-charging current
VS = 13 V,
–II
30
62
VI2 =VI7 = 0 V
V
=
8
CS-charging current
–II
20
mA
VS = VI2 =V 8 = 13 V
VI7
=
Output saturation voltage VS = VI2 =16 V,
VI7 = V 8 = 0 V,
II11 = 50
VOsat
VOsat
0.3
0.3
1.0
1.0
V
AC Characteristics
Tamb= 25 C, figures 2, 4 and 14
Parameters
Rise time
Test Conditions / Pin
Symbol
tr
Min.
Type.
Max.
0.5
0.5
Unit
Pin 10
Pin 14
Pulse width
Pin 10
Pin 14
tp
tp
0.1
0.1
4
4
ms
°
Pulse phasing difference f = 50 Hz
for two half-waves
3
3
Inter lC phasing
difference
f = 50 Hz
°
Pulse phasing front limit f = 50 Hz, figure 4
Pulse phasing rear limit f = 50 Hz, figures 4 and 10
177
°
°
Angle of current flow = 0 to 177° at V 8 = 0.2 to 7.5 V, h = 0°, figures 4 and 13
TELEFUNKEN Semiconductors
7 (11)
Rev. A1, 29-May-96
UAA145
Figure 14. Test circuit for ac characteristics
Applications
Parallel connection for three-phase current applications
Figure 15. Parallel connection for three-phase current applications. For polyphase operation connect all Pins 15 and Pins 16.
To ensure good pulse phasing symmetry as well as effective for all three devices becomes that of the Z-diode
identical shift characteristics in three-phase applications, with the lowest operating voltage. In this way all the CS
when three devices are employed, two parallel capacitors are charged and discharged to the same voltage
connection pins (figure 15) are provided on each device. levels. By symmetrical adjustment of the time constants
Besides the supply pins, the input pins 15 and 16 are to be with resistors RS, good pulse phasing symmetry and
paralleled. If this is done, then all the Z4 and Z3 diodes are identical shift characteristics are attained.
connected in parallel so that the reference voltage
8 (11)
TELEFUNKEN Semiconductors
Rev. A1, 29-May-96
UAA145
Figure 16. Speed control with tacho-generator
TELEFUNKEN Semiconductors
9 (11)
Rev. A1, 29-May-96
UAA145
Dimensions in mm
Case:
DIP 16
(Special case)
10 (11)
TELEFUNKEN Semiconductors
Rev. A1, 29-May-96
UAA145
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of
continuous improvements to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain
such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.
TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
TELEFUNKEN Semiconductors
11 (11)
Rev. A1, 29-May-96
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