5962-9153101VXA [TI]
HEX ECL TO TTL TRANSLATOR, TRUE OUTPUT, CDIP24, CERAMIC, DIP-24;
| 型号： | 5962-9153101VXA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX ECL TO TTL TRANSLATOR, TRUE OUTPUT, CDIP24, CERAMIC, DIP-24 驱动 CD 输出元件 接口集成电路 锁存器 转换器 电平转换器 驱动程序和接口 |
| 文件： | 总10页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
100325
Low Power Hex ECL-to-TTL Translator
General Description
Features
n Pin/function compatible with 100125
n Meets 100125 AC specifications
n 50% power reduction of the 100125
n Differential inputs with built in offset
n Standard FAST® outputs
The 100325 is a hex translator for converting F100K logic
levels to TTL logic levels. Differential inputs allow each circuit
to be used as an inverting, non-inverting or differential re-
ceiver. An internal reference voltage generator provides VBB
for single-ended operation, or for use in Schmitt trigger appli-
cations. All inputs have 50 kΩ pull-down resistors. When the
inputs are either unconnected or at the same potential the
outputs will go low.
n 2000V ESD protection
n −4.2V to −5.7V operating range
n Available to Microcircuit Drawing
(SMD) 5962-9153101
When used in single-ended operation the apparent input
threshold of the true inputs is 20 mV to 40 mV higher (posi-
tive) than the threshold of the complementary inputs. The
VEE and VTTL power may be applied in either order.
Logic Diagram
Pin Names
D0–D5
Description
Data Inputs
D0–D5
Q0–Q5
Inverting Data Inputs
Data Outputs
DS100314-4
FAST® is a registered trademark of Fairchild Semiconductor.
© 1998 National Semiconductor Corporation
DS100314
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Connection Diagrams
Truth Table
Inputs
Outputs
24-Pin DIP
Dn
L
Dn
H
L
Qn
L
H
L
H
L
L
H
H
L
Open
VEE
L
Open
VEE
VBB
VBB
L
L
L
L
H
H
H
L
VBB
VBB
H
DS100314-1
=
=
H
L
HIGH Voltage Level
LOW Voltage Level
24-Pin Quad Cerpak
DS100314-2
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage Applied to Output
=
in HIGH State (with VCC 0V)
Current Applied to Output
in LOW State (Max)
−0.5V to VCC
twice the rated IOL (mA)
Above which the useful life may be impaired.
ESD (Note 2)
≥2000V
Storage Temperature (TSTG
)
−65˚C to +150˚C
Recommended Operating
Conditions
Case Temperature (TC)
Military
Maximum Junction Temperature (TJ)
Ceramic
+175˚C
−7.0V to +0.5V
−0.5V to +6.0V
VEE to +0.5V
VEE Pin Potential to Ground Pin
VTTL Pin Potential to Ground Pin
Input Voltage (DC)
−55˚C to +125˚C
−5.7V to −4.2V
Supply Voltage (VEE
)
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
=
=
=
=
=
=
VEE −4.2V to −5.7V, VCC VCCA GND, TC −55˚C to +125˚C, CL 50 pF, VTTL +4.5V to +5.5V
Symbol
Parameter
Min
Max
Units
TC
Conditions
Notes
= =
IVBB −3 µA, VEE −4.2V
VBB
Output Reference Voltage
−1380 −1260
0˚C to +125˚C
(Notes 3,
4, 5)
=
=
VEE −5.7V
mV
IVBB −2.1 mA
=
IVBB −3 mA
−1396 −1260
−55˚C
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
−1165
−870
mV
−55˚C to +125˚C Guaranteed HIGH Signal for All Inputs
(with One Input Tied to VBB
−55˚C to +125˚C Guaranteed LOW Signal for All Inputs
(with One Input Tied to VBB
(Notes 3,
4, 5, 6)
)
−1830 −1475
mV
(Notes 3,
4, 5, 6)
)
=
=
VOH
2.5
2.4
0.5
150
mV
0˚C to +125˚C
−55˚C
IOH −2.0 mA
VIN VIH
(Max)
(Notes 3,
4, 5)
or VIL (Min)
=
−55˚C to +125˚C IOL 20 mA
VOL
Output LOW Voltage
mV
mV
VDIFF
Input Voltage Differential
−55˚C to +125˚C Required for Full Output Swing
−55˚C to +125˚C
(Notes 3,
4, 5)
VCM
Common Mode Voltage
Input HIGH Current
Input LOW Current
−2000
−500
mV
µA
(Notes 3,
4, 5, 6)
= =
VIN VIH (Max), D0–D5 VBB ,
IIH
350
500
0˚C to +125˚C
−55˚C
(Notes 3,
4, 5)
=
D0–D5 VIL
(Min)
=
=
IIL
0.50
µA
−55˚C to +125˚C VIN VIL
D0–D5 VBB
(Notes 3,
4, 5)
(Min),
=
IOS
Output Short Circuit
Current
−150
−60
250
mA
−55˚C to +125˚C VOUT GND
(Notes 3,
4, 5)
Test One Output at a Time
=
−55˚C to +125˚C VOUT 5.5V
ICEX
Output HIGH
µA
(Notes 3,
4, 5)
Leakage Current
VEE Power Supply Current
=
IEE
−35
−12
65
mA
mA
−55˚C to +125˚C D0–D5 VBB
(Notes 3,
4, 5)
=
ITTL
VTTL Power Supply Current
−55˚C to +125˚C D0–D5 VBB
(Notes 3,
4, 5)
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, + 25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing V /V
.
OH OL
3
www.national.com
AC Electrical Characteristics
=
=
=
VEE −4.2V to −5.7V, VCC GND, VTTL +4.5V to +5.5V
=
=
=
Symbol
Parameter
TC −55˚C
TC +25˚C
TC +125˚C
Units
Conditions
Notes
Min
1.50
Max
Min
1.60
Max
Min
Max
=
tPLH
tPHL
Propagation Delay
Data to Output
5.00
4.70
1.70
5.70
ns
CL 50 pF
(Notes 7,
8, 9)
Figures 1, 3
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25˚C, temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).
Switching Waveform
DS100314-6
FIGURE 1. Propagation Delay
www.national.com
4
Test Circuits
DS100314-5
Notes:
=
=
=
−4.5V, V
TTL
V
CC
0V, V
+5V
EE
=
L1 and L2 equal length 50Ω impedance lines
=
R
50Ω terminator internal to scope
T
Decoupling 0.1 µF from GND to V , V and V
CC EE TTL
All unused outputs are loaded with 500Ω to GND
=
=
Fixture and stray capacitance 15 pF
C
L
FIGURE 2. AC Test Circuit for 15 pF Loading
5
www.national.com
Test Circuits (Continued)
DS100314-8
Notes:
=
=
=
−4.5V, V
TTL
V
0V, V
+5V
CC
EE
=
L1 and L2 equal length 50Ω impedance lines
=
R
50Ω terminator internal to scope
T
Decoupling 0.1 µF from GND to V , V and V
CC EE TTL
All unused outputs are loaded with 500Ω to GND
=
=
Fixture and stray capacitance 50 pF
C
L
FIGURE 3. AC Test Circuit for 50 pF Loading
www.national.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
24 Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)
NS Package Number J24E
24 Lead Quad Cerpak (F)
NS Package Number W24B
7
www.national.com
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Response Group
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Fax: 65-2504466
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www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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Products > Military/Aerospace > Logic > ECL > 100325
100325 Product Folder
Low Power Hex ECL-to-TTL Translator
General
Description
Package
& Models
Samples
& Pricing
Features
Datasheet
Datasheet
Title
Size in Kbytes Date
Receive via Email
Download
View Online
100325 Low Power Hex ECL-to-
TTL Translator
View Online Download Receive via Email
View Online Download Receive via Email
125 Kbytes
106 Kbytes
17-Aug-98
100325 Mil-Aero Datasheet
MN100325-X
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Package Availability, Models, Samples & Pricing
Budgetary
Pricing
Samples &
Electronic
Orders
Std
Pack
Size
Package
Type Pins MSL
Models
Package
Marking
Part Number
Status
SPICE IBIS
Qty $US each
[logo]¢Z¢S¢4¢A$E
100325DMQB /Q
5962-
rail
of
15
Full
production
CERDIP
MSL
5962-9153101MXA
24
N/A
N/A
50+ $37.6000
Buy Now
Buy Now
9153101MXA
[logo]¢Z¢S¢4¢A
Q$E 100325
FMQB 5962
-9153101
rail
of
14
Full
production
CERQUAD
CERDIP
MSL
MSL
MSL
5962-9153101MYA
5962-9153101VXA
100325WFQMLV
24
24
24
N/A
N/A
N/A
N/A
N/A
50+ $45.2000
MYA
rail [logo]¢Z¢S¢4¢A$E
50+ $265.0000 of 100325J-QMLV
Full
production
15 5962-9153101VXA
[logo]¢Z¢S¢4¢A
rail
of
N/A
100325WF
QMLV 5962
F9153101
VYA$E
CERQUAD
Preliminary N/A
Preliminary N/A
[logo]¢Z¢S¢4¢A
RM100325WF
QMLV WFR#
¢R
rail
of
N/A
CERQUAD
MSL
RM100325WFQMLV
24
N/A
$E
[logo]¢Z¢S¢4¢A
100325W-
QMLV 5962
-9153101
rail
50+ $265.0000 of
14
Full
production
CERQUAD
MSL
5962-9153101VYA
24
N/A
N/A
VYA $E
General Description
The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow
each circuit to be used as an inverting, non-inverting or differential receiver. An internal reference voltage
generator provides VBB for single-ended operation, or for use in Schmitt trigger applications. All inputs have
50 k Ohm pull-down resistors. When the inputs are either unconnected or at the same potential the outputs
will go low.
When used in single-ended operation the apparent input threshold of the true inputs is 20 mV to 40 mV
higher (positive) than the threshold of the complementary inputs. The VEE and VTTL power may be applied in
either order.
Features
●
●
●
●
●
●
●
●
Pin/function compatible with 100125
Meets 100125 AC specifications
50% power reduction of the 100125
Differential inputs with built in offset
Standard FAST outputs
2000V ESD protection
-4.2V to -5.7V operating range
Available to Microcircuit Drawing (SMD) 5962-9153101
[Information as of 5-Aug-2002]
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