5962-9756001Q2A [TI]
军用 4 通道、2 输入、4.5V 至 5.5V 双极或门 | FK | 20 | -55 to 125;
| 型号： | 5962-9756001Q2A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 军用 4 通道、2 输入、4.5V 至 5.5V 双极或门 | FK | 20 | -55 to 125 栅 逻辑集成电路 栅极 |
| 文件： | 总19页 (文件大小：853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDAS113B – APRIL 1982 – REVISED DECEMBER 1994
SN54ALS32, SN54AS32 . . . J PACKAGE
SN74ALS32, SN74AS32 . . . D OR N PACKAGE
(TOP VIEW)
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
1A
1B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
4B
4A
4Y
3B
3A
3Y
description
1Y
2A
These devices contain four independent 2-input
positive-OR gates. They perform the Boolean
functions Y = A • B or Y = A + B in positive logic.
2B
2Y
GND
8
The
SN54ALS32
and
SN54AS32
are
characterized for operation over the full military
temperature range of –55°C to 125°C. The
SN74ALS32andSN74AS32arecharacterizedfor
operation from 0°C to 70°C.
SN54ALS32, SN54AS32 . . . FK PACKAGE
(TOP VIEW)
FUNCTION TABLE
(each gate)
3
2
1
20 19
18
1Y
NC
2A
4
5
6
7
8
4A
NC
4Y
NC
3B
INPUTS
OUTPUT
Y
17
16
15
14
A
B
X
H
L
H
X
L
H
H
L
NC
2B
9 10 11 12 13
NC – No internal connection
†
logic symbol
logic diagram (positive logic)
1
1
1A
2
1A
2
3
6
8
≥ 1
3
6
1Y
2Y
3Y
4Y
1Y
2Y
3Y
4Y
1B
1B
4
4
2A
5
2A
5
2B
9
2B
3A
10
3B
12
4A
13
4B
9
3A
8
10
3B
11
12
4A
4B
11
13
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDAS113B – APRIL 1982 – REVISED DECEMBER 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54ALS32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS32
MIN NOM
SN74ALS32
MIN NOM
UNIT
MAX
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–0.4
4
0.8
–0.4
8
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS32
SN74ALS32
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
–2
V
CC
–2
OH
CC
OH
OL
OL
0.25
0.4
0.25
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
0.1
20
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.1
–112
4
–0.1
–112
4
mA
mA
mA
mA
§
V
O
= 2.25 V
–20
–30
O
V = 4.5 V
I
1.9
2.6
1.9
2.6
CCH
CCL
V = 0
I
4.9
4.9
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
¶
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54ALS32
SN74ALS32
MIN
3
MAX
18
MIN
3
MAX
14
t
t
PLH
A or B
Y
ns
3
16
3
12
PHL
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDAS113B – APRIL 1982 – REVISED DECEMBER 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54AS32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS32
SN74AS32
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–2
0.8
–2
20
70
V
IL
I
I
mA
mA
°C
OH
20
OL
T
A
–55
125
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS32
SN74AS32
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
= –2 mA
= 20 mA
V
–2
V –2
CC
V
OH
OL
OH
OL
CC
I
0.35
0.5
0.1
0.35
0.5
0.1
V
I
I
I
I
I
I
= 5.5 V,
V = 7 V
I
mA
µA
mA
mA
mA
mA
I
= 5.5 V,
V = 2.7 V
I
20
20
IH
IL
= 5.5 V,
V = 0.4 V
I
–0.5
–112
12
–0.5
–112
12
§
= 5.5 V,
V
O
= 2.25 V
–30
–30
O
= 5.5 V,
V = 4.5 V
I
7.3
7.3
CCH
CCL
= 5.5 V,
V = 0
I
16.5
26.6
16.5
26.6
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
¶
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54AS32
SN74AS32
MIN
1
MAX
MIN
1
MAX
t
t
7.5
6.5
5.8
5.8
PLH
A or B
Y
ns
1
1
PHL
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDAS113B – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-86836012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
86836012A
SNJ54ALS
32FK
5962-8683601DA
5962-9756001Q2A
ACTIVE
ACTIVE
CFP
W
14
20
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8683601DA
SNJ54ALS32W
LCCC
FK
POST-PLATE
5962-
9756001Q2A
SNJ54AS
32FK
5962-9756001QCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9756001QC
A
SNJ54AS32J
JM38510/37501B2A
JM38510/37501BCA
M38510/37501B2A
M38510/37501BCA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
LCCC
CDIP
FK
J
20
14
20
14
1
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
JM38510/
37501B2A
JM38510/
37501BCA
FK
J
POST-PLATE
A42
JM38510/
37501B2A
JM38510/
37501BCA
SN54ALS32J
SN54AS32J
SN74ALS32D
ACTIVE
ACTIVE
ACTIVE
CDIP
CDIP
SOIC
J
J
14
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
-55 to 125
-55 to 125
0 to 70
SN54ALS32J
SN54AS32J
ALS32
D
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
SN74ALS32DE4
SN74ALS32DG4
SN74ALS32DR
SN74ALS32DRE4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
14
14
14
14
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
0 to 70
ALS32
ALS32
ALS32
ALS32
Green (RoHS
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74ALS32DRG4
SN74ALS32N
ACTIVE
SOIC
PDIP
D
14
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
ALS32
ACTIVE
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
SN74ALS32N
SN74ALS32N3
SN74ALS32NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS32N
ALS32
ALS32
ALS32
AS32
SN74ALS32NSR
SN74ALS32NSRE4
SN74ALS32NSRG4
SN74AS32D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
NS
D
14
14
14
14
14
14
14
14
14
14
14
14
14
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
SO
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
SOIC
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
Green (RoHS
& no Sb/Br)
SN74AS32DBR
SN74AS32DBRE4
SN74AS32DBRG4
SN74AS32DE4
SN74AS32DG4
SN74AS32DR
DB
DB
DB
D
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
AS32
Green (RoHS
& no Sb/Br)
AS32
Green (RoHS
& no Sb/Br)
AS32
Green (RoHS
& no Sb/Br)
AS32
D
50
Green (RoHS
& no Sb/Br)
AS32
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
AS32
SN74AS32DRE4
SN74AS32DRG4
SN74AS32N
D
Green (RoHS
& no Sb/Br)
AS32
D
Green (RoHS
& no Sb/Br)
AS32
N
Pb-Free
(RoHS)
SN74AS32N
SN74AS32N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
SN74AS32NE4
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AS32N
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74AS32NSR
SN74AS32NSRE4
SN74AS32NSRG4
SNJ54ALS32FK
ACTIVE
SO
SO
NS
14
14
14
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
74AS32
ACTIVE
ACTIVE
ACTIVE
NS
NS
FK
2000
2000
1
Green (RoHS
& no Sb/Br)
0 to 70
74AS32
74AS32
SO
Green (RoHS
& no Sb/Br)
0 to 70
LCCC
TBD
-55 to 125
5962-
86836012A
SNJ54ALS
32FK
SNJ54ALS32J
SNJ54ALS32W
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
SNJ54ALS32J
W
5962-8683601DA
SNJ54ALS32W
SNJ54AS32FK
ACTIVE
LCCC
FK
J
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9756001Q2A
SNJ54AS
32FK
SNJ54AS32J
ACTIVE
CDIP
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9756001QC
A
SNJ54AS32J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 :
Catalog: SN74ALS32, SN74AS32
•
Military: SN54ALS32, SN54AS32
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALS32DR
SN74ALS32NSR
SN74AS32DBR
SN74AS32DR
SOIC
SO
D
14
14
14
14
14
2500
2000
2000
2500
2000
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
6.5
8.2
8.2
6.5
8.2
9.0
10.5
6.6
2.1
2.5
2.5
2.1
2.5
8.0
12.0
12.0
8.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
NS
DB
D
SSOP
SOIC
SO
9.0
SN74AS32NSR
NS
10.5
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALS32DR
SN74ALS32NSR
SN74AS32DBR
SN74AS32DR
SOIC
SO
D
14
14
14
14
14
2500
2000
2000
2500
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
38.0
38.0
NS
DB
D
SSOP
SOIC
SO
SN74AS32NSR
NS
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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