5962R2122001VXC [TI]
耐辐射加固保障 (RHA)、10MHz 至 6.5GHz 3dB BW 单端转差分放大器 | FFM | 12 | -40 to 125;
| 型号： | 5962R2122001VXC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射加固保障 (RHA)、10MHz 至 6.5GHz 3dB BW 单端转差分放大器 | FFM | 12 | -40 to 125 放大器 |
| 文件： | 总22页 (文件大小：1580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRF0206-SP
ZHCSMI2A –NOVEMBER 2022 –REVISED DECEMBER 2022
TRF0206-SP 单通道、10MHz 至6.5GHz、3dB 带宽、ADC 驱动器放大器
1 特性
2 应用
• 已通过QMLV（QML V 级）MIL-PRF-38535 认
证，SMD 5962R2122001VXC
– 耐辐射加固保障(RHA) 能力高达100krad (Si)
总电离剂量(TID)
– 单粒子锁定(SEL) 对于LET 的抗扰度= 75MeV-
cm2/mg
• 支持军用级温度范围
• 直接驱动射频采样或GSPS ADC
• 适用于航天和国防应用
• 消除具有出色增益或相位平衡的
无源射频平衡-非平衡变压器
• 高速数字转换器
• 耐辐射应用
• 命令和数据处理系统
• 通信负载
（-55°C 至125°C）
• 可用作ADC 驱动器，具备出色的单端至差分转换
性能
• 也可在差分至单端模式下运行，用作DAC 缓冲器
• 6.5GHz，3dB 带宽
• 4.8GHz，1dB 增益平坦度
• 单端至差分的固定功率增益为12.5dB
• OIP3 性能：
– 2 GHz 时为38dBm
– 6 GHz 时为32dBm
• P1dB 性能：
3 说明
TRF0206-SP 是一款超高性能耐辐射射频放大器，专
门针对射频 (RF) 应用进行了优化。在驱动高性能
ADC12DJ3200QML-SP 等模数转换器 (ADC) 时，交
流耦合应用需要进行单端至差分转换，此款器件是这类
应用的理想之选。片上匹配元件可对印刷电路板(PCB)
实现方案进行简化，并在可用带宽内提供最高性能。此
器件采用德州仪器 (TI) 先进的互补 BiCMOS 工艺制
造，并采用航天级LCCC 封装。
该器件由 3.3V 单轨电源供电。下电功能还有助于实现
节能。
– 2 GHz 时为12dBm
– 6GHz 时为10dBm
• 噪声系数：
封装信息(1)
– 2 GHz 时为8dB
– 6 GHz 时为9dB
• 增益和相位不平衡：±0.4dB/±3 度
• 关断特性
封装尺寸（NOM）
器件型号
封装
FFM（LCCC-FC，
12）
TRF0206-SP
6.00mm x 6.10mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 3.3V 单电源运行
• 有效电流：130mA
PD
VDD
TRF0206-SP
+
ADC12DJ3200QML-SP
Rs = 50 Ω
–
50 Ω
驱动高速ADC 的TRF0206-SP
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA52
TRF0206-SP
ZHCSMI2A –NOVEMBER 2022 –REVISED DECEMBER 2022
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Table of Contents
8 Application and Implementation..................................16
8.1 Application Information............................................. 16
9 Typical Application........................................................17
9.1 TRF0206-SP Driving AFE7950-SP Receiver............17
10 Power Supply Recommendations..............................18
11 Layout...........................................................................18
11.1 Layout Guidelines................................................... 18
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 Device Support....................................................... 20
12.2 Documentation Support ......................................... 20
12.3 接收文档更新通知................................................... 20
12.4 支持资源..................................................................20
12.5 Trademarks.............................................................20
12.6 Electrostatic Discharge Caution..............................20
12.7 术语表..................................................................... 20
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Quality Conformance Inspection.................................7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................15
Information.................................................................... 20
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2022) to Revision A (December 2022)
Page
• 将状态从预告信息更改为“量产数据”.............................................................................................................1
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5 Pin Configuration and Functions
13 GND
(Thermal
Pad)
12 OUTM
11 OUTP
INM 5
INP 6
图5-1. TRF0206-SP FFM Package, 12-Pin LCCC-FC (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
GND
NO.
1, 4, 7, 10
GND
Ground
INP / INM
6, 5
11, 12
2
I
O
I
Differential signal input
Differential signal output
OUTP / OUTM
PD
Power down signal. Supports 1.8 V and 3.3 V Logic. 0 = chip enabled. 1 = power down
Test pin. Short to ground
TP1
8
—
TP2
VDD
3
9
Test pin. Short to ground
3.3 V supply
—
P
Thermal Pad
13
Thermal pad. Connect to ground on board.
—
(1) I = input, O = output, P = power, GND = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
3.7
UNIT
V
Supply voltage, VDD
–0.3
INP, INM
20
dBm
V
Input level
EN
3.7
–0.3
–65
Junction temperature, TJ
Temperature
150
150
ºC
Storage temperature, Tstg
ºC
Continuous power dissipation
See thermal information
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.2
NOM
3.3
MAX
UNIT
V
VDD
TA
Supply voltage
3.45
Ambient air temperature
Junction temperature
25
°C
–55
TJ
125
°C
6.4 Thermal Information
DEVICE
THERMAL METRIC(1)
FFM (LCCC)
PINS
69.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
54.5
44.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
42
ΨJT
44.5
ΨJB
RθJC(bot)
36.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
The specifications shown below correspond to the respectively identified subgroup temperature, unless otherwise noted. Test
conditions are at TA = 25 oC, VDD = 3.3 V, Single-ended input with RS = 50 Ω, output with ZL = 100 Ωdifferential, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
SUBGROUP (1)
MIN
TYP
MAX UNIT
AC PERFORMANCE
SSBW Small-signal 3-dB bandwidth
LSBW Large-signal 3-dB bandwidth
Bandwidth for 1.5-dB flatness
Vo = 100 mVPP
6.5
6.5
GHz
GHz
GHz
dB
Vo = 1 VPP
4.8
S21
S11
S12
Power Gain
f = 2 GHz
12.5
-10
Input return loss
Reverse isolation
f = 10 MHz to 4 GHz
f = 10 MHz to 4 GHz
f = 10 MHz to 5 GHz
dB
-35
dB
ImbGAIN Gain Imbalance
± 0.4
dB
ImbPHA
degree
s
Phase Imbalance
f = 10 MHz to 5 GHz
f = 2 GHz
± 3
-30
SE
CMRR using the formula (S21-
CMRR S31) / (S21+S31). Port-1: INP,
Port-2: OUTP, Port-3: OUTM
dB
f = 0.5 GHz, Po = +2 dBm
f = 1 GHz, Po = +2 dBm
f = 2 GHz, Po = +2 dBm
f = 4 GHz, Po = +2 dBm
f = 0.5 GHz, Po = +2 dBm
f = 1 GHz, Po = +2 dBm
f = 2 GHz, Po = +2 dBm
f = 4 GHz, Po = +2 dBm
f = 0.5 GHz
-65
-60
-60
-60
-65
-65
-68
-58
8.5
10
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
dBm
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
f = 1 GHz
OP1dB Output 1-dB compression point
f = 2 GHz
12
f = 4 GHz
10.5
10
f = 6 GHz
f = 0.5 GHz, Po = -5 dBm per tone
(10 MHz spacing)
65
62
58
55
55
32
35
38
35
32
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
f = 1 GHz, Po = -5 dBm per tone (10
MHz spacing)
f = 2 GHz, Po = -5 dBm per tone (10
MHz spacing)
OIP2
Output second-order intercept point
f = 4 GHz, Po = -5 dBm per tone (10
MHz spacing)
f = 6 GHz, Po = -5 dBm per tone (10
MHz spacing)
f = 0.5 GHz, Po = -5 dBm per tone
(10 MHz spacing)
f = 1 GHz, Po = -5 dBm per tone (10
MHz spacing)
f = 2 GHz, Po = -5 dBm per tone (10
MHz spacing)
OIP3
Output third-order intercept point
f = 4 GHz, Po = -5 dBm per tone (10
MHz spacing)
f = 6 GHz, Po = -5 dBm per tone (10
MHz spacing)
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6.5 Electrical Characteristics (continued)
The specifications shown below correspond to the respectively identified subgroup temperature, unless otherwise noted. Test
conditions are at TA = 25 oC, VDD = 3.3 V, Single-ended input with RS = 50 Ω, output with ZL = 100 Ωdifferential, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
SUBGROUP (1)
MIN
TYP
7.5
7.5
8
MAX UNIT
f = 0.5 GHz
dB
dB
dB
dB
dB
f = 1 GHz
f = 2 GHz
f = 4 GHz
f = 6 GHz
NF
Noise Figure
9
9
IMPEDANCE
ZO-DIFF Differential output impedance
ZIN Single ended input impedance
TRANSIENT
f = DC (internal to the device)
5
Ω
Ω
50
With INM terminated with 50 Ω
Output max operating range
(differential)
VOMAX
VOSAT
TREC
1.7
3.5
VPP
VPP
ns
Output saturated voltage level
(differential)
f = 4 GHz
Using a 0.5 VP input pulse of width
2 ns
Over-drive recovery time
0.35
POWER SUPPLY
IQA
Active current
Power-down quiescent current
Current on VDD pin, PD = 0
Current on VDD pin, PD = 1
[1, 2, 3]
[1, 2, 3]
85
2
130
7
170
16
mA
mA
IQPD
ENABLE
VPDHIGH PD pin logic HIGH
VPDLOW PD pin logic LOW
1.55
V
0.7
100
300
V
PD = HIGH (1.8 V logic)
PD = HIGH (3.3 V logic)
50
200
3
µA
µA
pF
ns
ns
IPDBIAS PD bias current (current on PD pin)
CPD
TON
TOFF
PD pin capacitance
Turn-on time
50% VPD to 90% RF
50% VPD to 10% RF
200
100
Turn-off time
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6.6 Quality Conformance Inspection
SUBGROUP(1)
DESCRIPTION
Static tests at
TEMPERATURE (°C)
1
2
25
125
−55
25
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
5
125
−55
25
6
7
8A
8B
9
125
−55
25
10
11
125
−55
(1) MIL-STD-883, Method 5005 –Group A
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6.7 Typical Characteristics
TA = 25°C, VDD = 3.3 V, input source impedance is 50 Ωsingle-ended, output load is 100 Ωdifferential unless otherwise
specified.
20
18
16
14
12
10
8
20
18
16
14
12
10
8
-55 C
-40 C
25 C
85 C
105 C
6
6
4
4
3.15 V
3.3 V
3.45 V
2
2
0
0
0
2000
4000
6000
8000
10000
0
2000
4000
6000
8000
10000
Frequency (MHz)
Frequency (MHz)
图6-1. Power Gain Across Temperature
图6-2. Power Gain Across VDD
0
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
0
2000
4000
6000
8000
10000
0
2000
4000
6000
8000
10000
Frequency (MHz)
Frequency (MHz)
图6-3. Return Loss Across Temperature
图6-4. Return Loss Across VDD
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
0
2000
4000
6000
8000
10000
0
2000
4000
6000
8000
10000
Frequency (MHz)
Frequency (MHz)
图6-5. Reverse Isolation Across Temperature
图6-6. Reverse Isolation Across VDD
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6.7 Typical Characteristics (continued)
TA = 25°C, VDD = 3.3 V, input source impedance is 50 Ωsingle-ended, output load is 100 Ωdifferential unless otherwise
specified.
45
40
35
30
25
20
15
45
40
35
30
25
20
15
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
Pout / tone = −5 dBm, 10 MHz tone spacing
图6-7. OIP3 Across Temperature
Pout / tone = −5 dBm, 10 MHz tone spacing
图6-8. OIP3 Across VDD
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
-40
-50
-60
-70
-80
-90
-100
-55 C
-40 C
25 C
85 C
105 C
-55 C
-40 C
25 C
85 C
105 C
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
At (2f1-f2) frequency; f2 > f1, Pout / tone = −5 dBm,
At (2f2-f1) frequency; f2 > f1, Pout / tone = −5 dBm,
10 MHz tone spacing
10 MHz tone spacing
图6-9. IMD3 Lower Frequency
图6-10. IMD3 Higher Frequency
80
70
60
50
40
30
20
80
70
60
50
40
30
20
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
At (f2-f1) frequency; f2 > f1, Pout / tone = −5 dBm, 10
At (f2-f1) frequency; f2 > f1, Pout / tone = −5 dBm, 10
MHz tone spacing
MHz tone spacing
图6-11. OIP2 Lower Frequency Across Temperature
图6-12. OIP2 Lower Frequency Across VDD
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6.7 Typical Characteristics (continued)
TA = 25°C, VDD = 3.3 V, input source impedance is 50 Ωsingle-ended, output load is 100 Ωdifferential unless otherwise
specified.
80
70
60
50
40
30
20
80
70
60
50
40
30
20
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
At (f2+f1) frequency; f2 > f1, Pout / tone = −5 dBm,
At (f2+f1) frequency; f2 > f1, Pout / tone = −5 dBm,
10 MHz tone spacing
10 MHz tone spacing
图6-13. OIP2 Higher Frequency Across Temperature
图6-14. OIP2 Higher Frequency Across VDD
-20
-20
-30
-40
-50
-60
-70
-80
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
-30
-40
-50
-60
-70
-80
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
Pout = +2 dBm
Pout = +2 dBm
图6-15. HD2 Across Temperature
图6-16. HD2 Across VDD
-20
-30
-40
-50
-60
-70
-80
-20
-30
-40
-50
-60
-70
-80
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
Pout = +2 dBm
Pout = +2 dBm
图6-17. HD3 Across Temperature
图6-18. HD3 Across VDD
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6.7 Typical Characteristics (continued)
TA = 25°C, VDD = 3.3 V, input source impedance is 50 Ωsingle-ended, output load is 100 Ωdifferential unless otherwise
specified.
-30
-40
-50
-60
-70
-80
-90
-30
-40
-50
-60
-70
-80
-90
500 MHz
500 MHz
1800 MHz
3000 MHz
4000 MHz
1800 MHz
3000 MHz
4000 MHz
-6
-4
-2
0
2
4
6
-6
-4
-2
0
2
4
6
Output Power (dBm)
Output Power (dBm)
图6-19. HD2 vs Output Power
图6-20. HD3 vs Output Power
16
16
-55 C
-40 C
25 C
85 C
105 C
14
12
10
8
14
12
10
8
3.15 V
3.3 V
6
6
3.45 V
4
4
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
图6-21. Output P1 dB Across Temperature
图6-22. Output P1 dB Across VDD
14
12
10
8
14
12
10
8
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
6
6
4
4
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
图6-23. NF Across Temperature
图6-24. NF Across VDD
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6.7 Typical Characteristics (continued)
TA = 25°C, VDD = 3.3 V, input source impedance is 50 Ωsingle-ended, output load is 100 Ωdifferential unless otherwise
specified.
1
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
-4
-5
-55 C
-40 C
25 C
85 C
105 C
-55 C
-40 C
25 C
85 C
105 C
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
图6-25. Gain Imbalance
图6-26. Phase Imbalance
0
-10
-20
-30
-40
-50
-60
-70
0
-10
-20
-30
-40
-50
-60
-70
-55 C
-40 C
25 C
85 C
105 C
3.15 V
3.3 V
3.45 V
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
图6-27. CMRR Across Temperature
图6-28. CMRR Across VDD
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6.7 Typical Characteristics (continued)
TA = 25°C, VDD = 3.3 V, input source impedance is 50 Ωsingle-ended, output load is 100 Ωdifferential unless otherwise
specified.
4
3
2
1
0
0
1000 2000 3000 4000 5000 6000 7000 8000
Frequency (MHz)
Input = +5 dBm
图6-29. Saturation Voltage
图6-30. Single-Ended S11
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7 Detailed Description
7.1 Overview
The TRF0206-SP is a very high-performance amplifier optimized for radio frequency (RF) and intermediate
frequency (IF) with signal bandwidths up to 7 GHz. The device is ideal for ac-coupled applications that may
require a single-ended to differential conversion when driving an analog-to-digital converter (ADC). The chip has
a 2-stage architecture and provides about 13 dB of gain when configured for single-ended inputs driven from a
50-Ωsource. This chip can also work as as a Diff-to-SE amplifier to act as a DAC buffer.
This chip does not require any pull up or pull down components on PCB and thereby it simplifies the layout and
ensures the highest performance over the whole bandwidth.
The input and output are ac coupled. The chip is powered with 3.3 V supply. A power-down feature is also
available for this chip.
7.2 Functional Block Diagram
The following figure shows the functional block diagram of TRF0206-SP. It essentialy has 2-stages with voltage
feedback configuration.
TRF0206-SP
–
+
–
+
7.3 Feature Description
The TRF0206-SP includes the following features:
• Fully differential amplifier
• Single supply operation
• Power-down option
7.3.1 Fully-Differential Amplifier
The TRF0206-SP is a voltage feedback fully-differential amplifier (FDA) with fixed gain by architecture.
TRF0206-SP is most suited to operate as a single-ended to differential amplifier by terminating the INM pin by a
50 Ωresistor and driving the INP pin directly with no external components.
This amplifier has non-linearity cancellation circuits, which provides excellent linearity performance over a wide
range of frequencies.
The output of the amplifier has a low DC impedance. If required, then the output of the amplifier can be matched
to a load by adding appropriate series resistors or attenuator pad.
7.3.2 Single Supply Operation
TRF0206-SP operates on a single 3.3 V supply. The input and output bias voltages are set internally. Therefore,
the signal path has to be ac-coupled on the board at all 4 RF input and output pins. Single supply operation
simplifies the board design.
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7.3.3 Power Down Option
There is power-down functionality for this device. The PD pin can be used to power-down the amplifier. This pin
supports both 1.8 V and 3.3 V digital logics and is referenced to the GND. A logic 1 turns the device off placing
the device into a low quiescent current state.
Note that, when disabled, the signal path is still present through the internal circuits. Input signals applied to a
disabled device still appear at the outputs at some lower level through this path as they would for any disabled
feedback amplifier.
7.4 Device Functional Modes
TRF0206-SP has 2 functional modes: Active mode and Power-down mode. The functional modes are controlled
by the PD pin as described in the previous section.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
8.1.1 Driving a High-Speed ADC
A common application of TRF0206-SP is to drive a high-speed ADC such as ADC12DJ3200QML-SP or
AFE7950 which have differential input. Conventionally passive baluns are used to drive Gsps ADCs due to non-
availability of high-BW, linear amplifiers. TRF0206-SP is an active balun that has excellent bandwidth flatness,
gain, and phase imbalance comparable to or exceeding costly passive baluns.
A typical interface circuit for ADC12DJ3200QML-SP is shown in the following figure. Depending on the ADC and
system requirement, this circuit can be simplified or can be more complex.
Anti-aliasing filter
Resistive matching pad
50 Ω
TRF0206-SP
ADC12DJ3200QML-SP
图8-1. Interfacing with High-Speed ADC
图 8-1 shows two sections of the circuit between the driver amp and the ADC – namely the matching pad (or
attenuator pad) and the anti-aliasing filter. Small form-factor RF quality passive components are recommended
for these circuits. The output swing of TRF0206-SP is well suited to drive these ADCs full-scale at the same time
not over-driving it avoiding the need for any voltage limiting device at the ADC.
8.1.2 Calculating Output Voltage Swing
This section gives an idea of the output voltage swings for different input power levels as a quick reference. The
output is terminated with 100 Ωdifferential load in this case and power gain of 13 dB is assumed.
Pi, Vi
50
Po, Vo
TRF0206-SP
图8-2. Power and Voltage Levels
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Voltage gain = 20*log (Vo/Vi)
2
Power gain = 10*log (Po/Pi) = 10*log ((Vo 2/100)/(Vi /50)) = 20*log (Vo/Vi) - 3 dB
(1)
表8-1. Output Voltage Swings for Different Input Power Levels
Input
Output
Pi (dBm)
−20
Vi (Vpp)
0.063
0.112
0.2
Po (dBm)
Vo (Vpp)
0.4
−7
−2
3
0.71
−15
1.263
1.785
−10
0.283
6
−7
8.1.3 Thermal Considerations
The TRF0206-SP is packaged in a 6.10 mm × 6.20 mm LCCC-FC package that has excellent thermal
properties. The chip has a thermal pad underneath that should be connected to a ground plane. The ground
plane should be shorted to the other ground pins of the chip at four corners if possible to allow heat propagation
to the top layer of the PCB. There should be a thermal via that connects the thermal pad plane on the top layer
of the PCB to the inner layer ground planes to allow heat propagation to the inner layers.
The total power dissipation needs to be limited to keep the device junction temperature below 150°C for
instantaneous power and below 125°C for continuous power.
9 Typical Application
9.1 TRF0206-SP Driving AFE7950-SP Receiver
This section describes an RF receiver chain in which TRF0206-SP is working as a S2D (SE-to-Diff) amp and
driving a receive channel of AFE7950-SP.
3.3 V
100 pF
100 pF
3.9 pF
3.9 pF
0.2 nH
0.2 nH
10
10
10
10
11
12
100 pF
100 pF
9
OUTP
OUTM
To AFE7950-SP RX
VDD
6
5
INP
INM
1
4
7
10
GND
GND
GND
GND
2
PD
8
3
AFE matching network
TP1
TP2
TPAD 13
TRF0206-SP
图9-1. TRF0206-SP in Receive Chain driving AFE7950-SP ADC
图 9-1 is a generic schematics of a design in which TRF0206-SP drives an AFE7950-SP receive channel. The
exact values of the components depend on the frequency band for which the AFE7950-SP front-end is matched.
9.1.1 Design Requirements
The AFE7950-SP receive channel is required to be matched to 2.3 GHz.
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9.1.2 Detailed Design Procedure
The TRF0206-SP is configured as a S2D amplifier. The section close to TRF0206-SP output is an attenuator
pad which is meant for robust matching. The section close to AFE7950-SP is the matching network for the AFE
which is channel and channel frequency dependent. The matching components are chosen based on the AFE
return-loss data and some trial and error since the manufactured board parameters can influence the exact
component values.
10 Power Supply Recommendations
TRF0206-SP requires a single 3.3 V supply. Supply decoupling is critical to high-frequency performance.
Typically 2 or 3 capacitors are used for supply decoupling. The lowest-value capacitor should be a small form-
factor component that is placed closest to the VDD pin of the device. There should be bulk decoupling capacitor
that is of bigger value and size which can be placed next to the small capacitor. Additional layout
recommendations are given in the Layout section.
11 Layout
11.1 Layout Guidelines
TRF0206-SP is a wide-band feedback amplifer with about 13 dB of gain. When designing with a wide-band RF
amplifier with relatively high gain, certain board layout precautions must be taken to ensure stability and optimum
performance. TI recommends that the board be multi-layered to maintain signal and power integrity and thermal
performance. The following figure shows an example of a good layout. In this figure, only the top layer is shown.
It is recommended to route the RF input and output lines as grounded coplanar waveguide (GCPW) lines. The
second layer should be a continuous ground layer without any ground-cuts near the amplifier area. The output
differential lines have to be matched in length to minimize phase imbalance. Use small footprint passive
components wherever possible. Care should be given also for the input side layout. The INP routing should be a
50-Ω line and the termination on INM pin should have low parasitics by placing the ac-coupling cap and the 50-
Ωresistor very close to the device. Use a RF quality 50-Ωresistor for termination. Ensure that ground planes on
the top and internal layers are well stitched with vias.
As 图 11-1 shows, place thermal vias under the device that connect the top thermal pad with ground planes in
the inner layers of PCB. Also connect the thermal pad to the top layer ground plane through the ground pins.
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11.2 Layout Example
Thermal vias under the device,
connected to top layer ground for
improved heat dissipa on
TRF0206-SP
device
50- termina on
resistor (0201) on INM
pin very close to the
cap
Supply decoupling caps
(0201 and 0402) placed
very close to the device
图11-1. Layout Example –Placement and Top Layer Layout
The TRF0206-SP device can be evaluated using the TRF0206-SP EVM board, which can be ordered from
TRF0206-SP product folder. Additional information about the evaluation board construction and test setup is
given in the TRF0206-SP EVM User's Guide.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, TRF0206-SP EVM User's Guide
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962R2122001VXC
ACTIVE
LCCC
FFM
12
50
RoHS & Green
Call TI
Level-1-NA-UNLIM
-55 to 125
5962R
2122001VXC
TRF0206FFM
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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