74ACT299DCQR [TI]
ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20;
| 型号： | 74ACT299DCQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20 CD 输出元件 |
| 文件： | 总10页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1993
54AC/74AC299 54ACT/74ACT299
#
8-Input Universal Shift/Storage
Register with Common Parallel I/O Pins
General Description
The ’AC/’ACT299 is an 8-bit universal shift/storage register
Features
Y
I
and I
reduced by 50%
OZ
CC
Common parallel I/O for reduced pin count
Y
Y
Y
with TRI-STATE outputs. Four modes of operation are
É
possible: hold (store), shift left, shift right and load data. The
parallel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional outputs
Additional serial inputs and outputs for expansion
Four operating modes: shift left, shift right, load and
store
are provided for flip-flops Q , Q to allow easy serial cas-
7
cading. A separate active LOW Master Reset is used to
reset the register.
0
Y
Y
Y
Y
TRI-STATE outputs for bus-oriented applications
Outputs source/sink 24 mA
’ACT299 has TTL-compatible inputs
Standard Military Drawing (SMD)
Ð ’AC299: 5962-88754
Ð ’ACT299: 5962-88771
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
TL/F/9893–1
IEEE/IEC
TL/F/9893–2
Pin Assignment
for LCC
TL/F/9893–3
TL/F/9893–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9893
RRD-B30M75/Printed in U. S. A.
Pin Names
Description
Clock Pulse Input
CP
DS
DS
S , S
0
MR
OE , OE
2
I/O –I/O
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
TRI-STATE Output Enable Inputs
Parallel Data Inputs or
0
7
1
1
0
7
TRI-STATE Parallel Outputs
Serial Outputs
Q , Q
0
7
Functional Description
Truth Table
Inputs
The ’AC/’ACT299 contains eight edge-triggered D-type flip-
flops and the interstage logic necessary to perform synchro-
nous shift left, shift right, parallel load and hold operations.
The type of operation is determined by S and S , as shown
Response
MR
S
S
CP
1
0
L
X
X
X
Asynchronous Reset;
e
Parallel Load; I/On x
0
1
in the Truth Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q and Q
are also brought out on other pins for expansion in serial
shifting of longer words.
Q –Q
0
LOW
7
H
H
H
L
H
H
L
L
Q
n
0
7
Shift Right; DS0 x Q ,
0
Q
0 x Q , etc.
1
H
H
L
L
L
L
Shift Left, DS7 x Q ,
7
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initiated
by the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
Q
7 x Q , etc.
6
H
X
Hold
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
e
L
LOW-to-HIGH Transition
A HIGH signal on either OE or OE disables the TRI-
2
1
STATE buffers and puts the I/O pins in the high impedance
state. In this condition the shift, hold, load and reset opera-
tions can still occur. The TRI-STATE buffers are also dis-
abled by HIGH signals on both S and S in preparation for
1
0
a parallel load operation.
2
Logic Diagram
TL/F/9893–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
(Unless Otherwise Specified)
)
CC
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
’AC
’ACT
2.0V to 6.0V
4.5V to 5.0V
DC Input Diode Current (I
)
IK
e b
b
a
V
V
0.5V
a
20 mA
20 mA
I
I
Input Voltage (V )
I
0V to V
0V to V
CC
e
V
CC
0.5V
Output Voltage (V
)
O
CC
b
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
0.5V to V
CC
Operating Temperature (T )
A
74AC/ACT
54AC/ACT
DC Output Diode Current (I
)
OK
b
b
a
40 C to 85 C
§
§
55 C to 125 C
e b
b
a
V
V
0.5V
a
20 mA
20 mA
a
O
O
§
§
e
V
0.5V
CC
Minimum Input Edge Rate (DV/Dt)
’AC Devices
a
0.5V
DC Output Voltage (V
)
O
CC
g
DC Output Source or Sink Current (I
)
O
50 mA
V
V
from 30% to 70% of V
CC
IN
@
3.3V, 4.5V, 5.5V
125 mV/ns
125 mV/ns
CC
DC V
or Ground Current
CC
g
Per Output Pin (I or I
CC
)
50 mA
Minimum Input Edge Rate (DV/Dt)
’ACT Devices
GND
)
b
a
65 C to 150 C
Storage Temperature (T
§
§
STG
V
V
from 0.8V to 2.0V
@
IN
Junction Temperature (T )
J
CDIP
PDIP
4.5V, 5.5V
CC
175 C
§
140 C
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Obviously the databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. National
does not recommend operation of FACTTM circuits outside databook specifi-
cations.
DC Electrical Characteristics For ’AC Family Devices
74AC
54AC
74AC
e
e
T
A
V
CC
(V)
T
55 C to 125 C
A
e
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
b a
40 C to 85 C
§
§
§
Guaranteed Limits
§
Typ
e
0.1V
V
V
V
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
IH
OUT
b
V
V
V
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
OUT
0.1V
0.1V
IL
b
or V
CC
e b
OUT
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
I
50 mA
OH
e
*V
IN
V
or V
IH
12 mA
IL
b
b
b
3.0
4.5
5.5
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
V
I
24 mA
24 mA
OH
e
e
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V or V
IL IH
12 mA
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
I
24 mA
24 mA
OH
e
I
Maximum Input
Leakage Current
V
I
V , GND
CC
IN
g
g
g
1.0
5.5
0.1
1.0
mA
*All outputs loaded; threshold on input associated with output under test.
4
DC Electrical Characteristics For ’AC Family Devices
74AC
54AC
74AC
e
e
T
A
V
CC
(V)
T
A
55 C to 125 C
e
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
b a
40 C to 85 C
§
§
Guaranteed Limits
§
§
Typ
e
²
Minimum Dynamic
Output Current
I
I
I
5.5
5.5
50
86
mA
mA
V
V
V
1.65V Max
OLD
OHD
CC
OLD
b
b
e
3.85V Min
OHD
50
75
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
5.5
4.0
80.0
40.0
mA
mA
or GND
e
I
Maximum I/O
Leakage Current
V (OE)
I
V , V
IL IH
OZT
e
e
g
g
g
3.0
0.3
5.5
V
V
V
CC
, GND
, GND
I
V
CC
O
*All outputs loaded; threshold on input associated with output under test.
²
Maximum test duration 20 ms, one output loaded at a time.
@
@
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V
Note: I and I
IN
.
CC
CC
@
@
for 54AC 25 C is identical to 74AC 25 C.
I
§
§
CC
DC Electrical Characteristics For ’ACT Family Devices
74ACT
54ACT
74ACT
e
e
T
A
V
CC
(V)
T
A
55 C to 125 C
e
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
b a
40 C to 85 C
§
§
Guaranteed Limits
§
§
Typ
e
0.1V
V
V
V
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
OUT
V
b
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
3.0
4.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
OUT
or V
0.1V
0.1V
IL
b
CC
e b
OUT
Minimum High Level
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
I
50 mA
OH
V
e
*V
IN
OH
V
IL
or V
IH
b
b
4.5
5.5
0.0001
3.86
4.86
3.70
4.70
3.76
4.76
I
24 mA
24 mA
V
V
e
e
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
V or V
IL IH
IN
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
I
24 mA
24 mA
OL
V
e
e
I
Maximum Input
Leakage Current
V
V
V
, GND
IN
I
CC
g
g
g
1.0
5.5
0.1
1.0
mA
b
2.1V
I
I
I
I
Maximum I /Input
CC
5.5
5.5
5.5
0.6
1.6
50
1.5
75
mA
mA
mA
V
V
V
V
CCT
OLD
OHD
CC
I
CC
e
²
Minimum Dynamic
Output Current
1.65V Max
e
3.85V Min
OLD
OHD
b
b
50
75
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
5.5
4.0
80.0
40.0
mA
mA
or GND
e
I
Maximum I/O
Leakage Current
V (OE)
I
V , V
IL IH
OZT
e
g
g
g
3.0
0.3
5.5
V
V
V
V
, GND
CC
, GND
I
e
O
CC
@
@
limit for 54ACT 25 C is identical to 74ACT 25 C.
Note: I
§
§
CC
*All outputs loaded; thresholds on input associated with output under test.
²
Maximum test duration 2.0 ms, one output loaded at a time.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
e
e
C
C
Input Capacitance
4.5
pF
pF
V
5.0V
5.5V
IN
CC
CC
Power Dissipation
Capacitance
PD
170
V
5
AC Electrical Characteristics
74AC
54AC
e b
74AC
e b
40 C
T
55 C
§
T
§
A
to 125 C
A
e a
A
V *
CC
(V)
T
C
25 C
§
a
a
Symbol
Parameter
to 85 C
50 pF
Units
§
§
e
50 pF
L
e
e
C
50 pF
C
L
L
Min
Typ
Max
Min
Max
Min
Max
f
t
Maximum Input
Frequency
3.3
5.0
90
130
124
173
70
80
80
105
max
MHz
ns
Propagation Delay
CP to Q or Q
PLH
3.3
5.0
8.5
5.5
14.0
9.5
20.5
14.0
1.0
1.0
25.5
17.5
7.0
4.5
22.0
15.0
0
7
(Shift Left or Right)
t
Propagation Delay
CP to Q or Q
PHL
3.3
5.0
8.5
5.5
14.5
10.0
21.5
14.5
1.0
1.0
26.5
18.0
7.0
5.0
23.0
16.0
ns
0
7
(Shift Left or Right)
t
t
t
t
t
t
t
t
Propagation Delay
CP to I/O
3.3
5.0
9.0
6.0
14.5
10.0
20.5
14.5
1.0
1.0
24.5
17.0
7.5
5.0
22.5
16.0
PLH
PHL
PHL
PHL
PZH
PZL
PHZ
PLZ
ns
ns
ns
ns
ns
ns
ns
ns
n
Propagation Delay
CP to I/O
3.3
5.0
10.0
6.5
16.0
11.0
23.0
16.0
1.0
1.0
26.5
18.5
8.5
6.0
24.5
17.5
n
Propagation Delay
MR to Q or Q
3.3
5.0
9.0
5.5
15.5
10.5
22.5
15.5
1.0
1.0
27.0
18.5
7.5
5.0
25.0
17.0
0
7
Propagation Delay
MR to I/O
3.3
5.0
9.0
5.5
15.0
10.0
21.5
15.0
1.0
1.0
26.5
18.0
7.5
5.0
24.0
16.5
n
Output Enable Time
OE to I/O
3.3
5.0
7.0
4.5
12.0
8.5
18.0
12.5
1.0
1.0
22.0
15.0
6.0
4.0
19.5
13.5
n
Output Enable Time
OE to I/O
3.3
5.0
7.0
5.0
12.5
8.0
18.0
12.5
1.0
1.0
23.5
16.0
6.0
4.0
20.5
14.0
n
Output Disable Time
OE to I/O
3.3
5.0
6.5
3.5
13.0
9.5
18.5
14.0
1.0
1.0
22.5
17.0
5.5
3.0
19.5
15.0
n
Output Disable Time
OE to I/O
3.3
5.0
5.5
3.5
11.5
8.0
17.0
12.5
1.0
1.0
21.5
16.0
4.5
2.0
19.0
13.5
n
g
*Voltage Range 3.3 is 3.3V 0.3V.
g
Voltage Range 5.0 is 5.0V 0.5V.
AC Operating Requirements
74AC
54AC
e b
74AC
e b
40 C
T
55 C
§
T
A
§
A
to 125 C
e a
A
V *
CC
(V)
T
C
25 C
§
a
a
Symbol
Parameter
to 85 C
e
50 pF
Units
§
§
e
50 pF
L
e
C
50 pF
C
L
L
Typ
Guaranteed Minimum
t
t
t
t
t
t
t
t
t
Setup Time, HIGH or LOW
S
3.3
5.0
3.0
2.0
8.0
5.0
9.5
7.0
8.5
5.5
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
or S to CP
1
0
b
b
Hold Time, HIGH or LOW
or S to CP
3.3
5.0
3.0
1.5
0.5
1.0
2.0
2.5
0.5
1.0
h
S
0
1
Setup Time, HIGH or LOW
I/O to CP
n
3.3
5.0
2.0
1.0
5.5
3.5
6.0
4.0
6.0
4.0
s
b
b
Hold Time, HIGH or LOW
I/O to CP
n
3.3
5.0
2.0
1.0
0
1.0
1.5
2.0
0
1.0
h
Setup Time, HIGH or LOW
DS or DS to CP
3.3
5.0
2.5
1.5
6.5
4.0
7.5
5.0
7.0
4.5
s
0
7
b
b
Hold Time, HIGH or LOW
DS or DS to CP
3.3
5.0
2.0
1.0
0
1.0
1.5
1.5
0.5
1.0
h
0
7
CP Pulse Width, LOW
3.3
5.0
3.5
2.0
4.5
3.5
5.5
5.0
5.0
3.5
w
w
rec
MR Pulse Width, LOW
3.3
5.0
4.0
2.0
4.5
3.5
5.5
5.0
5.0
3.5
Recovery Time
MR to CP
3.3
5.0
0
0.5
1.5
1.5
2.5
2.5
1.5
1.5
g
*Voltage Range 3.3 is 3.3V 0.3V
g
Voltage Range 5.0 is 5.0V 0.5V
6
AC Electrical Characteristics
74ACT
54ACT
e b
74ACT
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
e
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
C
L
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
f
t
Maximum Input
Frequency
max
5.0
5.0
120
170
8.5
70
110
MHz
ns
Propagation Delay
CP to Q or Q
PLH
4.0
4.0
12.5
13.5
1.0
1.0
15.5
16.0
3.0
3.5
14.0
15.0
0
7
(Shift Left or Right)
t
Propagation Delay
CP to Q or Q
PHL
5.0
9.0
ns
0
7
(Shift Left or Right)
t
t
t
t
t
t
t
t
Propagation Delay
CP to I/O
PLH
PHL
PHL
PHL
PZH
PZL
PHZ
PLZ
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.5
5.0
4.0
4.0
2.5
2.0
2.0
2.5
8.5
9.5
12.5
15.0
15.0
14.5
12.0
12.0
12.5
11.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
15.0
18.0
18.0
17.5
14.0
14.5
14.5
14.0
4.5
4.5
4.0
3.5
1.5
1.5
2.0
2.0
13.5
16.5
18.0
17.5
13.0
13.5
13.5
12.5
ns
ns
ns
ns
ns
ns
ns
ns
n
Propagation Delay
CP to I/O
n
Propagation Delay
MR to Q or Q
14.0
13.0
8.0
0
7
Propagation Delay
MR to I/O
n
Output Enable Time
OE to I/O
n
Output Enable Time
OE to I/O
8.0
n
Output Disable Time
OE to I/O
8.5
n
Output Disable Time
OE to I/O
8.0
n
g
*Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
74ACT
54ACT
e b
74ACT
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
e
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
C
L
C
C
L
L
Typ
Guaranteed Minimum
t
t
t
t
t
t
t
Setup Time, HIGH or LOW
or S to CP
1
s
5.0
5.0
5.0
5.0
5.0
5.0
2.0
5.0
6.5
5.5
ns
ns
ns
ns
ns
ns
S
0
Hold Time, HIGH or LOW
or S to CP
h
s
b
2.0
1.5
1.0
4.0
1.0
4.5
1.0
1.5
4.5
1.5
5.5
1.5
1.0
4.5
1.0
5.0
1.0
S
0
1
Setup Time, HIGH or LOW
I/O to CP
n
Hold Time, HIGH or LOW
I/O to CP
n
h
s
b
1.0
Setup Time, HIGH or LOW
DS or DS to CP
1.5
0
7
Hold Time, HIGH or LOW
DS or DS to CP
h
w
b
1.0
0
7
CP Pulse Width
HIGH or LOW
5.0
5.0
5.0
2.0
4.0
3.5
1.5
5.0
5.0
1.5
4.5
3.5
1.5
ns
ns
ns
t
t
MR Pulse Width, LOW
2.0
0
w
Recovery Time
MR to CP
rec
g
*Voltage Range 5.0 is 5.0V 0.5V.
7
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACT 299
P
C
QR
Temperature Range Family
Special Variations
e
e
e
e
74AC
54AC
Commercial
Military
Commercial TTL-Compatible
Military TTL-Compatible
X
QR
Devices shipped in 14 reels
×
Commercial grade device with
burn-in
e
e
74ACT
54ACT
e
QB
Military grade device with
environmental and burn-in
processing shipped in tubes
Device Type
Package Code
Temperature Range
e
e
e
e
e
P
D
F
L
Plastic DIP
Ceramic DIP
Flatpak
Leadless Ceramic Chip Carrier (LCC)
Small Outline Package (SOIC)
e
e
b a
C
M
Commercial ( 40 C to 85 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
S
Physical Dimensions inches (millimeters)
20 Terminal Ceramic Leadless Chip Carrier (LCC)
NS Package Number E20A
8
Physical Dimensions inches (millimeters) (Continued)
20 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J20A
20 Lead Small Outline Integrated Circuit (SOIC)
NS Package Number M20B
9
Ý
Lit. 114631-1
Physical Dimensions inches (millimeters) (Continued)
20 Lead Molded Dual-In-Line Package (N)
NS Package Number N20B
20 Lead Ceramic FLATPAK
NS Package Number W20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
2900 Semiconductor Drive
P.O. Box 58090
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Tel: 1(800) 272-9959
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Tel: (3) 558-9999
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Hong Kong Ltd.
Sumitomo Chemical
Engineering Center
Bldg. 7F
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