74ALVCH16271DLG4 [TI]

12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS; 12位至24位复用总线交换器具有三态输出
74ALVCH16271DLG4
型号: 74ALVCH16271DLG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS
12位至24位复用总线交换器具有三态输出

解复用器 逻辑集成电路 光电二极管 输出元件
文件: 总15页 (文件大小:222K)
中文:  中文翻译
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SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments Widebus™  
Family  
OEA  
LE1B  
2B3  
1
2
3
4
5
6
7
8
9
10  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEB  
CLKENA2  
2B4  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
GND  
2B2  
GND  
2B5  
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
2B1  
2B6  
V
CC  
V
CC  
A1  
A2  
A3  
2B7  
2B8  
2B9  
DESCRIPTION/ORDERING INFORMATION  
This 12-bit to 24-bit bus exchanger is designed for  
1.65-V to 3.6-V VCC operation.  
GND 11  
A4 12  
A5 13  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
The SN74ALVCH16271 is intended for applications in  
which two separate data paths must be multiplexed  
onto, or demultiplexed from, a single data path. This  
device is particularly suitable as an interface  
between conventional DRAMs and high-speed  
microprocessors.  
14  
15  
16  
17  
A6  
A7  
A8  
A9  
GND 18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A data is stored in the internal A-to-B registers on the  
low-to-high transition of the clock (CLK) input,  
provided that the clock-enable (CLKENA) inputs are  
low. Proper control of these inputs allows two  
sequential 12-bit words to be presented as a 24-bit  
word on the B port.  
A10  
A11  
A12  
1B8  
1B7  
V
CC  
V
CC  
1B1  
1B2  
1B6  
1B5  
Transparent latches in the B-to-A path allow  
asynchronous operation to maximize memory access  
throughput. These latches transfer data when the  
latch-enable (LE) inputs are low. The select (SEL)  
line selects 1B or 2B data for the A outputs. Data flow  
is controlled by the active-low output enables (OEA,  
OEB).  
GND  
1B3  
LE2B  
SEL  
GND  
1B4  
CLKENA1  
CLK  
line  
space  
To ensure the high-impedance state during power up or power down, the output enables should be tied to VCC  
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the  
driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
TA  
PACKAGE(1)  
Tube  
SN74ALVCH16271DL  
SN74ALVCH16271DLR  
SSOP - DL  
TSSOP - DGG  
ALVCH16271  
-40°C to 85°C  
Tape and reel  
Tape and reel  
SN74ALVCH16271DGGR ALVCH16271  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
FUNCTION TABLES  
line space  
OUTPUT ENABLE  
INPUTS  
OUTPUTS  
OEA  
OEB  
A
1B, 2B  
Z
H
H
L
H
L
Z
Z
Active  
Z
H
L
Active  
Active  
L
Active  
A-TO-B STORAGE (OEB = L)  
INPUTS  
CLKENA2  
OUTPUTS  
CLKENA1  
CLK  
A
X
L
1B  
2B  
(1)  
(1)  
H
L
H
X
X
L
X
1B0  
2B0  
L
H
X
X
L
L
H
L
X
X
X
L
H
A0  
H
(1) Output level before the indicated steady-state input conditions were established  
B-TO-A STORAGE (OEA = L)  
INPUTS  
OUTPUT  
A
LE  
H
H
L
SEL  
X
1B  
X
2B  
X
(1)  
A0  
(1)  
X
X
X
A0  
H
L
X
L
H
L
L
H
H
X
X
L
L
L
L
L
X
H
H
(1) Output level before the indicated steady-state input conditions were  
established  
2
SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
LOGIC DIAGRAM (POSITIVE LOGIC)  
29  
2
CLK  
LE1B  
27  
30  
LE2B  
CLKENA1  
55  
56  
CLKENA2  
OEB  
28  
1
SEL  
LE  
1D  
23  
1B1  
2B1  
OEA  
G1  
1
1
LE  
1D  
8
A1  
6
CE  
C1  
1D  
CE  
C1  
1D  
1 of 12 Channels  
3
SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
-0.5  
-0.5  
-0.5  
-0.5  
MAX  
4.6  
UNIT  
VCC  
VI  
Supply voltage range  
Input voltage range  
V
Except I/O ports(2)  
I/O ports(2)(3)  
4.6  
V
VCC + 0.5  
VCC + 0.5  
-50  
VO  
IIK  
Output voltage range(2)(3)  
Input clamp current  
V
VI < 0  
mA  
mA  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
-50  
Continuous output current  
Continuous current through each VCC or GND  
±50  
±100  
64  
DGG package  
DL package  
θJA  
Package thermal impedance(4)  
Storage temperature range  
°C/W  
°C  
56  
Tstg  
-65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) This value is limited to 4.6 V maximum.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
RECOMMENDED OPERATING CONDITIONS(1)  
MIN  
MAX  
UNIT  
VCC  
Supply voltage  
1.65  
3.6  
V
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
0.65 × VCC  
VIH  
High-level input voltage  
1.7  
2
V
V
0.35 × VCC  
0.7  
0.8  
VCC  
VCC  
-4  
VIL  
Low-level input voltage  
VI  
Input voltage  
0
0
V
V
VO  
Output voltage  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
-12  
-12  
-24  
4
IOH  
High-level output current  
Low-level output current  
mA  
mA  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
12  
IOL  
12  
24  
t/v  
Input transition rise or fall rate  
Operating free-air temperature  
10  
ns/V  
TA  
-40  
85  
°C  
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
4
SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
ELECTRICAL CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
1.65 V to 3.6 V  
1.65 V  
2.3 V  
MIN TYP(1)  
VCC - 0.2  
MAX  
UNIT  
IOH = -100 µA  
IOH = -4 mA  
IOH = -6 mA  
1.2  
2
VOH  
2.3 V  
1.7  
2.2  
2.4  
2
V
IOH = -12 mA  
2.7 V  
3 V  
IOH = -24 mA  
IOL = 100 µA  
IOL = 4 mA  
IOL = 6 mA  
3 V  
1.65 V to 3.6 V  
1.65 V  
2.3 V  
0.2  
0.45  
0.4  
VOL  
V
2.3 V  
0.7  
IOL = 12 mA  
2.7 V  
0.4  
IOL = 24 mA  
VI = VCC or GND  
VI = 0.58 V  
3 V  
0.55  
±5  
II  
3.6 V  
µA  
1.65 V  
1.65 V  
2.3 V  
25  
-25  
45  
VI = 1.07 V  
VI = 0.7 V  
II(hold)  
VI = 1.7 V  
2.3 V  
-45  
75  
µA  
VI = 0.8 V  
3 V  
VI = 2 V  
3 V  
-75  
VI = 0 to 3.6 V(2)  
VO = VCC or GND  
VI = VCC or GND,  
3.6 V  
±500  
±10  
40  
(3)  
IOZ  
3.6 V  
µA  
µA  
µA  
pF  
pF  
ICC  
ICC  
Ci  
IO = 0  
3.6 V  
One input at VCC - 0.6 V,  
Other inputs at VCC or GND  
3 V to 3.6 V  
3.3 V  
750  
Control inputs VI = VCC or GND  
3.5  
9
Cio A or B ports  
VO = VCC or GND  
3.3 V  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to  
another.  
(3) For I/O ports, the parameter IOZ includes the input leakage current.  
TIMING REQUIREMENTS  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)  
VCC = 2.5 V  
± 0.2 V  
VCC = 3.3 V  
± 0.3 V  
VCC = 2.7 V  
UNIT  
MIN  
MAX  
130  
MIN  
MAX  
130  
MIN  
MAX  
130  
fclock  
tw  
Clock frequency  
MHz  
ns  
Pulse duration, CLK high or low  
3.3  
2.6  
1.7  
1.6  
0.6  
0.9  
1
3.3  
2.1  
1.5  
1.3  
0.6  
0.9  
0.9  
3.3  
1.7  
1.3  
1
A before CLK↑  
B before LE  
tsu  
Setup time  
Hold time  
ns  
ns  
CLKEN before CLK↑  
A after CLK↑  
0.7  
1.1  
0.9  
th  
B after LE  
CLKEN after CLK↑  
5
SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
SWITCHING CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)  
VCC = 2.5 V  
± 0.2 V  
VCC = 3.3 V  
± 0.3 V  
VCC = 1.8 V  
TYP  
VCC = 2.7 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
130  
1
MAX  
MIN  
MAX  
MIN  
130  
1
MAX  
fmax  
130  
MHz  
CLK  
B
B
A
8
7
7
7
8
7
6.2  
5.3  
6
5
4.7  
5.9  
6.2  
6.1  
4.6  
4.3  
4
1
1.4  
1.4  
1.3  
1
tpd  
ns  
LE  
1
4.8  
5.2  
5.1  
4.2  
SEL  
1.1  
1
6.4  
6
ten  
OEB or OEA  
OEB or OEA  
B or A  
B or A  
ns  
ns  
tdis  
1.4  
5.4  
1.7  
OPERATING CHARACTERISTICS  
TA = 25°C  
VCC = 2.5 V VCC = 3.3 V  
PARAMETER  
TEST CONDITIONS  
UNIT  
TYP  
92  
TYP  
105  
76  
Outputs enabled  
A to B  
B to A  
Outputs disabled  
Outputs enabled  
Outputs disabled  
61  
Cpd  
Power dissipation capacitance  
CL = 0,  
f = 10 MHz  
pF  
39  
43  
11  
13  
6
SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
PARAMETER MEASUREMENT INFORMATION  
VCC = 1.8 V  
2 × V  
CC  
S1  
Open  
1 k  
From Output  
Under Test  
TEST  
S1  
GND  
t
pd  
Open  
C = 30 pF  
(see Note A)  
L
t
/t  
/t  
2 × V  
CC  
GND  
PLZ PZL  
1 kΩ  
t
PHZ PZH  
LOAD CIRCUIT  
t
w
V
CC  
V
CC  
V /2  
CC  
V /2  
CC  
Input  
Timing  
Input  
V
/2  
CC  
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
t
su  
t
h
V
CC  
Output  
Control  
(low-level  
enabling)  
Data  
Input  
V
CC  
V
/2  
CC  
V /2  
CC  
V /2  
CC  
V /2  
CC  
0 V  
0 V  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
t
t
PLZ  
PZL  
Output  
Waveform 1  
V
CC  
V
CC  
V /2  
CC  
Input  
V /2  
CC  
V /2  
CC  
S1 at 2 × V  
V
OL  
+ 0.15 V  
CC  
V
OL  
(see Note B)  
0 V  
t
t
PHZ  
PZH  
t
t
PLH  
PHL  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
V
OH  
− 0.15 V  
V /2  
CC  
Output  
V /2  
CC  
V /2  
CC  
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2 ns, t 2 ns.  
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
Figure 1. Load Circuit and Voltage Waveforms  
7
SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
PARAMETER MEASUREMENT INFORMATION  
VCC = 2.5 V ± 0.2 V  
2 × V  
CC  
S1  
Open  
GND  
500 Ω  
From Output  
Under Test  
TEST  
S1  
t
pd  
Open  
C = 30 pF  
(see Note A)  
L
t
/t  
/t  
2 × V  
CC  
GND  
PLZ PZL  
500 Ω  
t
PHZ PZH  
LOAD CIRCUIT  
t
w
V
CC  
V
CC  
V /2  
CC  
V /2  
CC  
Input  
Timing  
Input  
V
/2  
CC  
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
t
su  
t
h
V
CC  
Output  
Control  
(low-level  
enabling)  
Data  
Input  
V
CC  
V
/2  
CC  
V /2  
CC  
V /2  
CC  
V /2  
CC  
0 V  
0 V  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
t
t
PLZ  
PZL  
Output  
Waveform 1  
V
CC  
V
CC  
V /2  
CC  
Input  
V /2  
CC  
V /2  
CC  
S1 at 2 × V  
V
OL  
+ 0.15 V  
CC  
V
OL  
(see Note B)  
0 V  
t
t
PHZ  
PZH  
t
t
PLH  
PHL  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
V
OH  
− 0.15 V  
V /2  
CC  
Output  
V /2  
CC  
V /2  
CC  
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2 ns, t 2 ns.  
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
Figure 2. Load Circuit and Voltage Waveforms  
8
SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017GJULY 1995REVISED SEPTEMBER 2004  
PARAMETER MEASUREMENT INFORMATION  
VCC = 2.7 V AND 3.3 V ± 0.3 V  
6 V  
S1  
Open  
TEST  
S1  
500 Ω  
From Output  
Under Test  
t
Open  
6 V  
GND  
pd  
GND  
t
t
/t  
PLZ PZL  
/t  
C = 50 pF  
L
500 Ω  
PHZ PZH  
(see Note A)  
t
w
LOAD CIRCUIT  
2.7 V  
0 V  
1.5 V  
1.5 V  
Input  
2.7 V  
0 V  
Timing  
Input  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
t
su  
t
h
2.7 V  
0 V  
Data  
Input  
2.7 V  
0 V  
1.5 V  
1.5 V  
Output  
Control  
(low-level  
enabling)  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
t
t
PLZ  
PZL  
Output  
Waveform 1  
S1 at 6 V  
3 V  
2.7 V  
0 V  
1.5 V  
Input  
1.5 V  
1.5 V  
V
OL  
+ 0.3 V  
V
OL  
(see Note B)  
t
t
PZH  
PHZ  
t
t
PHL  
PLH  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
V
OH  
− 0.3 V  
1.5 V  
1.5 V  
1.5 V  
Output  
(see Note B)  
0 V  
OL  
VOLTAGE WAVEFORMS  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
ENABLE AND DISABLE TIMES  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
Figure 3. Load Circuit and Voltage Waveforms  
9
PACKAGE OPTION ADDENDUM  
www.ti.com  
6-Dec-2006  
PACKAGING INFORMATION  
Orderable Device  
74ALVCH16271DGGRE4  
74ALVCH16271DLG4  
74ALVCH16271DLRG4  
SN74ALVCH16271DGGR  
SN74ALVCH16271DL  
SN74ALVCH16271DLR  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
DGG  
56  
56  
56  
56  
56  
56  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SSOP  
SSOP  
TSSOP  
SSOP  
SSOP  
DL  
DL  
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DGG  
DL  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DL  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Jul-2007  
TAPE AND REEL INFORMATION  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Jul-2007  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
(mm)  
24  
SN74ALVCH16271DGGR DGG  
SN74ALVCH16271DLR DL  
56  
56  
MLA  
MLA  
8.6  
15.8  
1.8  
3.1  
12  
16  
24  
32  
Q1  
Q1  
330  
32  
11.35  
18.67  
TAPE AND REEL BOX INFORMATION  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
SN74ALVCH16271DGGR  
SN74ALVCH16271DLR  
DGG  
DL  
56  
56  
MLA  
MLA  
333.2  
346.0  
333.2  
346.0  
31.75  
49.0  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001  
DL (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0.025 (0,635)  
48  
0.0135 (0,343)  
0.008 (0,203)  
0.005 (0,13)  
M
25  
0.010 (0,25)  
0.005 (0,13)  
0.299 (7,59)  
0.291 (7,39)  
0.420 (10,67)  
0.395 (10,03)  
Gage Plane  
0.010 (0,25)  
0°ā8°  
1
24  
0.040 (1,02)  
0.020 (0,51)  
A
Seating Plane  
0.004 (0,10)  
0.008 (0,20) MIN  
PINS **  
0.110 (2,79) MAX  
28  
48  
0.630  
56  
DIM  
0.380  
(9,65)  
0.730  
A MAX  
A MIN  
(16,00) (18,54)  
0.370  
(9,40)  
0.620  
0.720  
(15,75) (18,29)  
4040048/E 12/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MO-118  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998  
DGG (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0,27  
0,17  
M
0,08  
0,50  
48  
25  
6,20  
6,00  
8,30  
7,90  
0,15 NOM  
Gage Plane  
0,25  
1
24  
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
48  
56  
64  
DIM  
A MAX  
12,60  
12,40  
14,10  
13,90  
17,10  
16,90  
A MIN  
4040078/F 12/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,  
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.  
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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Applications  
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logic.ti.com  
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Security  
www.ti.com/opticalnetwork  
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Copyright © 2007, Texas Instruments Incorporated  

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