ADS1259QPWRQ1 [TI]
适用于高动态范围系统、具有低漂移电压基准的汽车类 24 位、14.4kSPS、单通道 Δ-Σ ADC | PW | 20 | -40 to 125;
| 型号： | ADS1259QPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于高动态范围系统、具有低漂移电压基准的汽车类 24 位、14.4kSPS、单通道 Δ-Σ ADC | PW | 20 | -40 to 125 光电二极管 转换器 |
| 文件： | 总15页 (文件大小：551K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS1259-Q1
ZHCSCA2 –MARCH 2014
ADS1259-Q1 汽车用，14.4kSPS，24 位模数转换器
具有集成低漂移基准
1 特性
3 说明
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
ADS1259-Q1 是一款精密，低漂移，24 位模数转换器
(ADC)。 此器件可在数据速率高达 14.4kSPS 时执行
高分辨率转换，并因此非常适合于测量宽动态范围内快
速变化的信号。 一个集成的低噪声，低漂移
2.5V 基准免除了对于外部电压基准的需要，从而减少
了系统成本和组件数量。
–
–
–
温度等级：-40°C 至 125°C
人体模型 (HBM) 静电放电 (ESD) 分类等级 2
充电器件模型 (CDM) ESD 分类等级 C4B
•
•
•
可编程数据速率：10SPS 至 14.4kSPS
单周期稳定数字滤波器
高性能：
此转换器使用一个四阶、固有稳定、三角积分 (ΔΣ) 调
制器，此调制器提供出色的噪声性能和线性。 此器件
可将集成振荡器、外部晶振或外部时钟用作 ADC 时钟
源。
–
–
–
–
1.2kSPS 时的有效位数 (ENOB) 为 21.3
积分非线性 (INL)：3ppm
偏移漂移：0.05μV/°C
一个快速响应输入超范围检测器标志是否出现一个输入
超范围事件。 为了增加嘈杂汽车应用环境中的数据完
整性，ADS1259-Q1 提供一个可选校验和字节与一个
冗余转换数据读取功能。
增益漂移：0.5ppm/°C
•
•
•
•
•
•
•
内部基准：2.5V，漂移 10ppm/°C
内部 2% 精准振荡器
输入信号超范围检测
ADS1259-Q1 运行时的功率为 13mW，而在节电模式
下的功耗少于 25μW。 TI 提供的 ADS1259-Q1 器件采
用薄型小外形尺寸 (TSSOP)-20 封装，可在 -40°C 至
125°的温度范围内完全额定运行。
可选校验和与冗余数据读取功能以增加数据完整性
SPI™- 兼容接口，模式 1
模拟电源：5V 或者 ±2.5V
数字电源：2.7V 至 5V
器件信息
2 应用范围
订货编号
封装
封装尺寸
•
•
汽车传动
电动汽车
ADS1259QPWRQ1 TSSOP (20)
6.5mm x 4.4mm
空白
空白
空白
ADS1259-Q1 简化方框图
AVDD
REFP REFN REFOUT
SYNCOUT
DVDD
XTAL1/CLKIN
XTAL2
Clock
Generator
2.5-V
Reference
fCLK / 8
AINP
AINN
RESET/PWDN
START
DS
Programmable
Digital Filter
Calibration
Engine
Modulator
Control
and
Serial
DRDY
SCLK
DIN
Out-of-Range
Detection
Interface
DOUT
CS
ADS1259-Q1
AVSS
DGND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLASE20
ADS1259-Q1
ZHCSCA2 –MARCH 2014
www.ti.com.cn
目录
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
Residue................................................................... 7
器件文档和支持........................................................ 8
8.1 Trademarks............................................................... 8
8.2 Electrostatic Discharge Caution................................ 8
8.3 Glossary.................................................................... 8
机械封装和可订购信息............................................. 9
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Terminal Configuration and Functions................ 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 5
7
8
9
4 修订历史记录
日期
修订版本
注释
2014 年 3 月
*
最初发布版本
2
Copyright © 2014, Texas Instruments Incorporated
ADS1259-Q1
www.ti.com.cn
ZHCSCA2 –MARCH 2014
5 Terminal Configuration and Functions
20-Terminal TSSOP
PW Package
(Top View)
AINP
AINN
1
2
20
19
18
17
16
15
14
13
12
11
AVDD
AVSS
3
REFN
RESET/PWDN
START
4
REFP
SYNCOUT
5
REFOUT
DVDD
6
CS
SCLK
DIN
7
DGND
8
BYPASS
XTAL2
DOUT
9
10
XTAL1/CLKIN
DRDY
Terminal Functions
TERMINAL
NAME
TYPE
DESCRIPTION
NO.
1
AINP
Analog input
Analog input
Digital input
Digital input
Digital output
Digital input
Digital input
Digital input
Digital output
Digital output
Positive analog input
Negative analog input
2
AINN
3
RESET/PWDN
START
SYNCOUT
CS
Reset or power down; reset is active-low; hold low for power down.
Start conversions, active-high
Sync clock output (f(CLK) / 8)
SPI chip-select, active-low
SPI clock input
4
5
6
7
SCLK
8
DIN
SPI data input
9
DOUT
DRDY
SPI data output
10
Data-ready output, active-low
Internal oscillator: DGND
11
XTAL1/CLKIN
Digital input
External clock: clock input
Crystal oscillator: external crystal1
12
13
14
15
16
17
18
19
20
XTAL2
BYPASS
DGND
DVDD
REFOUT
REFP
Digital
Analog
Digital
Digital
External crystal2, otherwise no connection
Core voltage bypass. Connect a 1-µF capacitor to DGND.
Digital ground
Digital power supply
Analog output
Analog input
Analog input
Analog
Positive internal reference output. Connect a 1-µF capacitor, CREFOUT, to AVSS.
Positive reference input. Connect a 1-µF capacitor, CREFIN, to REFN.(1)
Negative reference input(1)
REFN
AVSS
Negative analog power supply and negative internal reference output
Positive analog power supply
AVDD
Analog
(1) Leave unused reference inputs unconnected or tie to AVDD.
Copyright © 2014, Texas Instruments Incorporated
3
ADS1259-Q1
ZHCSCA2 –MARCH 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating ambient temperature range (unless otherwise noted)
MIN
–0.3
MAX
UNIT
AVDD to AVSS
AVSS to DGND
DVDD to DGND
7
V
V
V
V
–2.8
0.3
7
–0.3
Analog input voltage
AINN, AINP, REFN, REFP
AVSS – 0.3
AVDD + 0.3
CS, DIN, RESET/PDWN, SCLK, START,
XTAL1/CLKIN
Digital input voltage
DGND – 0.3
DVDD + 0.3
V
Input current, continuous
Any terminal except supply terminals
–10
–40
10
mA
°C
Operating junction temperature, TJ
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
–60
–2
MAX
150
2
UNIT
°C
Tstg
Storage temperature range
Human-body model (HBM) ESD stress voltage(2)
Charged-device model (CDM) ESD stress voltage(2)
kV
(1)
V(ESD)
–1
1
kV
(1) Electrostatic discharge (ESD) to measure device sensitivity or immunity to damage caused by assembly-line electrostatic discharges
into the device.
(2) Meets or exceeds the passing level per AEC-Q100.
4
Copyright © 2014, Texas Instruments Incorporated
ADS1259-Q1
www.ti.com.cn
ZHCSCA2 –MARCH 2014
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVDD to AVSS
Analog power supply
4.75
–2.6
2.7
5.0
–2.5
3.3
5.25
0
V
V
V
AVSS to DGND
Digital power supply
DVDD to DGND
5.25
ANALOG INPUTS
Absolute input voltage
Differential input voltage(1)
VOLTAGE REFERENCE INPUTS
AINP or AINN
AVSS – 0.1
–Vref
AVDD + 0.1
Vref
V
V
V(IN) = (V(AINP) – V(AINN)
)
AVDD – AVSS +
0.2
Reference input voltage
Vref = (V(REFP) – V(REFN)
)
0.5
2.5
V
Absolute negative reference voltage REFN
Absolute positive reference voltage REFP
EXTERNAL CLOCK SOURCES (f(CLK)
AVSS – 0.1
REFN + 0.5
AVSS
REFP – 0.5
AVDD + 0.1
V
V
AVSS + 2.5
)
Crystal oscillator
Frequency
Frequency
Duty cycle
2
0.1
7.3728
7.3728
8
8
MHz
MHz
External clock
40%
60%
DIGITAL INPUTS
High-level input voltage, VIH
Low-level input voltage, VIL
TEMPERATURE RANGE
Operating ambient temperature, TA
0.8 DVDD
DGND
DVDD
V
V
0.2 DVDD
–40
125
°C
(1) Excluding the effects of offset and gain error.
6.4 Thermal Information
PW
THERMAL METRIC(1)
UNIT
(20 TERMINALS)
RθJA
Junction-to-ambient thermal resistance
86.9
21
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
39.1
0.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
38.4
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014, Texas Instruments Incorporated
5
ADS1259-Q1
ZHCSCA2 –MARCH 2014
www.ti.com.cn
6.5 Electrical Characteristics
Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V,
DVDD = 3.3 V, external f(CLK) = 7.3728 MHz, external Vref = 2.5 V, and f(DATA) = 60 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input impedance
Common-mode input impedance
SYSTEM PERFORMANCE
Resolution (no missing codes)
Data rate, f(DATA)
120
500
kΩ
kΩ
24
10
Bits
SPS
μVRMS
ppm
μV
14,400
Noise (input referred)
Shorted inputs, See SBAS424 for more information.
Best-fit method
0.7
Integral nonlinearity, INL
Offset voltage (input referred)
Offset voltage after calibration(1)
Offset drift
–10
±3
10
–250
±40
250
±1
μV
TA = –40°C to 125°C
0.05
±0.05%
±0.0002%
0.5
0.25
μV/°C
Gain error(2)
–0.5%
0.5%
Gain error after calibration(1)
Gain drift
TA = –40°C to 125°C
2.5
ppm/°C
Normal-mode rejection ratio, NMRR
Common-mode rejection ratio, CMRR
AVDD, AVSS power-supply rejection ratio, PSRR
DVDD power supply-rejection ratio, PSRR
OUT-OF-RANGE DETECTION
Threshold level
See SBAS424.
120
60 Hz, ac(3)
60 Hz, ac(3)
60 Hz, ac(3)
100
85
dB
dB
dB
95
85
110
AVSS + 150 mV ≤ V(AINP), V(AINN) ≤ AVDD – 150 mV
AVSS + 150 mV ≤ V(AINP), V(AINN) ≤ AVDD – 150 mV
±105
±0.5
%FSR
%FSR
Threshold level accuracy
VOLTAGE REFERENCE INPUTS
Average reference input current
Average reference input current drift
INTERNAL VOLTAGE REFERENCE
Reference output voltage
Accuracy
AVSS ≤ V(REFP) , V(REFN) ≤ AVDD
350
0.2
nA
nA/°C
V(REFOUT) = (REFOUT – AVSS)
TA = 25°C
2.5
10
V
–0.4%
–10
0.4%
40
Temperature drift
TA = –40°C to 125°C
ppm/°C
mA
Drive current (sink and source)
Load regulation
10
10
1
μV/mA
s
Turn-on settling time
±0.001% settling, CREFIN = 1 μF, CREFOUT = 1 μF
Long-term stability
0 to 1000 hours
70
30
ppm
ppm
Thermal hysteresis
CLOCK SOURCE (f(CLK)
)
Internal oscillator frequency
7.3728
±0.2%
20
MHz
ms
Internal oscillator accuracy
–2%
2%
External crystal oscillator start-up time(4)
18-pF load capacitors
DIGITAL INPUTS AND OUTPUTS (DVDD = 2.7 V to 5.25 V)
IOH = 1 mA
0.8 DVDD
High-level output voltage, VOH
V
V
IOH = 8 mA
IOL = 1 mA
IOL = 8 mA
0.75 DVDD
0.2 DVDD
Low-level output voltage, VOL
0.2 DVDD
0.1
Input hysteresis
Input leakage
V
0 < V(DIGITAL INPUT) < DVDD
–10
10
μA
(1) Calibration accuracy is on the level of noise (signal and ADC), reduced by the effect of 16-reading averaging.
(2) Excludes internal reference error.
(3) f(DATA) = 14.4 kSPS. Placing a notch of the digital filter at 60 Hz (setting f(DATA) = 10 SPS or 60 SPS) further improves the common-
mode rejection and power-supply rejection of this input frequency.
(4) External crystal start-up time can vary with crystal manufacturer and over temperature.
6
Copyright © 2014, Texas Instruments Incorporated
ADS1259-Q1
www.ti.com.cn
ZHCSCA2 –MARCH 2014
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C, AVDD = 2.5 V,
AVSS = –2.5 V, DVDD = 3.3 V, external f(CLK) = 7.3728 MHz, external Vref = 2.5 V, and f(DATA) = 60 SPS (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Operating
(internal reference enabled)
2.3
5
mA
Standby mode
(internal reference enabled)
200
Absolute analog supply current (AVDD, AVSS)
Digital supply current (DVDD)
Power dissipation
Standby mode
(internal reference disabled)
μA
μA
1
1
Power-down mode
Operating
500
700
300
(internal oscillator(5)
)
Standby mode
(internal oscillator)
160
1
Power-down mode
(external CLKIN, SCLK stopped,
digital inputs maintained at VIH or VIL voltage levels)
10
28
Operating
13
(internal reference enabled, internal oscillator)
Standby mode
(internal reference enabled, internal oscillator)
1.5
mW
Standby mode
(internal reference disabled, internal oscillator)
0.5
10
Power-down mode
μW
(5) Internal oscillator current: 40 µA (typ.)
7 Residue
See SBAS424 for any information on the ADS1259-Q1 device that is not covered in the foregoing sections.
Copyright © 2014, Texas Instruments Incorporated
7
ADS1259-Q1
ZHCSCA2 –MARCH 2014
www.ti.com.cn
8 器件文档和支持
8.1 Trademarks
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
8.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
8
Copyright © 2014, Texas Instruments Incorporated
ADS1259-Q1
www.ti.com.cn
ZHCSCA2 –MARCH 2014
9 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 要获得这份数据表的浏览器版本，请查阅左侧导航栏。
Copyright © 2014, Texas Instruments Incorporated
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS1259QPWRQ1
ACTIVE
TSSOP
PW
20
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AD1259Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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