ADS1605 [TI]
18-Bit, 1.25MSPS Analog-to-Digital Converter; 18位， 1.25MSPS模拟数字转换器
| 型号： | ADS1605 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-Bit, 1.25MSPS Analog-to-Digital Converter |
| 文件： | 总37页 (文件大小：846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀꢇ ꢈꢉ ꢊꢋ ꢌꢋ
ꢍ ꢎ ꢏꢐ ꢑꢒꢂ ꢅ ꢑꢂ ꢓ ꢄ ꢒꢄ ꢅꢏ ꢐ ꢔꢕ ꢑꢎꢖ ꢗ ꢘ ꢅꢗ ꢘ
FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
D
D
D
D
Data Rate: 1.25MSPS
Signal-to-Noise Ratio: 93dB
Total Harmonic Distortion: −101dB
The ADS1625 and ADS1626 are high-speed, high-precision,
delta-sigma analog-to-digital converters (ADCs) with 18-bit
resolution. The data rate is 1.25 mega samples per second
(MSPS), the bandwidth (−3dB) is 615kHz, and passband
ripple is less than 0.0025dB (to 550kHz). Both devices offer
the same outstanding performance at these speeds with a
signal-to-noise ratio up to 93dB, total harmonic distortion
down to −101dB, and a spurious-free dynamic range up to
103dB. The ADS1626 includes an adjustable first-in, first-out
buffer (FIFO) for the output data.
Spurious-Free Dynamic Range: 103dB
Linear Phase with 615kHz Bandwidth
Passband Ripple: 0.0025dB
Adjustable FIFO Output Buffer (ADS1626 only)
Selectable On-Chip Reference
Directly Connects to TMS320C6000 DSPs
Adjustable Power Dissipation: 150 to 515mW
Power Down Mode
The input signal is measured against a voltage reference that
can be generated on-chip or supplied externally. The digital
output data are provided over a simple parallel interface that
easily connects to digital signal processors (DSPs). An
out-of-range monitor reports when the input range has been
exceeded. The ADS1625/6 operate from a +5V analog
supply (AVDD) and +3V digital supply (DVDD). The digital
I/O supply (IOVDD) operates from +2.7 to +5.25V, enabling
the digital interface to support a range of logic families. The
analog power dissipation is set by an external resistor and
can be reduced when operating at slower speeds. A
power-down mode, activated by a digital I/O pin, shuts down
all circuitry. The ADS1625/6 are offered in a TQFP-64
package using TI PowerPAD technology.
Supplies: Analog
Digital
+5V
+3V
Digital I/O +2.7V to +5.25V
APPLICATIONS
D
D
D
D
D
Scientific Instruments
Automated Test Equipment
Data Acquisition
Medical Imaging
The ADS1625 and ADS1626, along with their 16-bit,
5MSPS counterparts, the ADS1605 and ADS1606, are
well-suited for the demanding measurement requirements
of scientific instrumentation, automated test equipment,
data acquisition, and medical imaging.
Vibration Analysis
VREFP VREFN VMID RBIAS VCAP
AVDD DVDD IOVDD
PD
Reference and Bias Circuits
REFEN
RESET
CLK
CS
I/O
Interface
AINP
AINN
∆Σ
Modulator
Digital
Filter
RD
DRDY
OTR
ADS1626 Only
DOUT[17:0]
FIFO
ADS1625
ADS1626
FIFO_LEV[2:0]
AGND
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
ꢌꢚ ꢛ ꢓꢜ ꢕ ꢝꢞ ꢛꢟ ꢓ ꢍꢝꢍ ꢄꢎ ꢠꢑ ꢘ ꢡꢏ ꢅꢄꢑꢎ ꢄꢢ ꢣꢤ ꢘ ꢘ ꢗꢎꢅ ꢏꢢ ꢑꢠ ꢥꢤꢦ ꢐꢄꢣ ꢏꢅꢄ ꢑꢎ ꢧꢏ ꢅꢗꢇ ꢌꢘ ꢑꢧꢤ ꢣꢅꢢ
ꢣ ꢑꢎ ꢠꢑꢘ ꢡ ꢅꢑ ꢢ ꢥꢗ ꢣ ꢄ ꢠꢄ ꢣ ꢏ ꢅꢄ ꢑꢎꢢ ꢥ ꢗꢘ ꢅꢨꢗ ꢅꢗ ꢘ ꢡꢢ ꢑꢠ ꢝꢗꢩ ꢏꢢ ꢞꢎꢢ ꢅꢘ ꢤꢡ ꢗꢎꢅ ꢢ ꢢꢅ ꢏꢎꢧ ꢏꢘ ꢧ ꢪ ꢏꢘ ꢘ ꢏ ꢎꢅꢫꢇ
ꢌꢘ ꢑ ꢧꢤꢣ ꢅ ꢄꢑ ꢎ ꢥꢘ ꢑ ꢣ ꢗ ꢢ ꢢ ꢄꢎ ꢒ ꢧꢑ ꢗ ꢢ ꢎꢑꢅ ꢎꢗ ꢣꢗ ꢢꢢ ꢏꢘ ꢄꢐ ꢫ ꢄꢎꢣ ꢐꢤꢧ ꢗ ꢅꢗ ꢢꢅꢄ ꢎꢒ ꢑꢠ ꢏꢐ ꢐ ꢥꢏ ꢘ ꢏꢡ ꢗꢅꢗ ꢘ ꢢꢇ
Copyright 2003−2007, Texas Instruments Incorporated
www.ti.com
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE−LEAD
(1)
ADS1625IPAPT
ADS1625IPAPR
ADS1626IPAPT
ADS1626IPAPR
Tape and Reel, 250
Tape and Reel, 1000
Tape and Reel, 250
Tape and Reel, 1000
ADS1625
ADS1626
HTQFP−64
HTQFP−64
PAP
PAP
−40°C to +85°C
−40°C to +85°C
ADS1625I
ADS1626I
(1)
For the most current specifications and package information, refer to our web site at www.ti.com.
PRODUCT FAMILY
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
PRODUCT
ADS1605
ADS1606
ADS1625
ADS1626
RESOLUTION
16 Bits
DATA RATE
FIFO?
No
ADS1625/26
−0.3 to +6
UNIT
5.0MSPS
5.0MSPS
1.25MSPS
1.25MSPS
AVDD to AGND
V
V
V
V
16 Bits
18 Bits
18 Bits
Yes
No
DVDD to DGND
−0.3 to +3.6
−0.3 to +6
IOVDD to DGND
Yes
AGND to DGND
−0.3 to +0.3
100, Momentary
10, Continuous
−0.3 to AVDD + 0.3
−0.3 to IOVDD + 0.3
+150
Input Current
mA
mA
V
This integrated circuit can be damaged by ESD.
Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions.
Input Current
Analog I/O to AGND
Digital I/O to DGND
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10s)
V
Failure to observe proper handling and installation procedures can
cause damage.
°C
°C
°C
°C
−40 to +105
−60 to +150
+260
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
2
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
= 40MHz, External V
REF
= +3V, V = 2.0V, FIFO disabled, and
CM
CLK
R
BIAS
= 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
0dBFS
1.467V
1.165V
0.735V
V
V
V
V
REF
REF
REF
REF
−2dBFS
−6dBFS
−20dBFS
Differential input voltage (V
(AINP − AINN)
)
IN
0.147V
Common-mode input voltage (V
(AINP + AINN) / 2
)
CM
2.0
V
0dBFS
−0.1
0.1
4.7
4.2
V
V
Absolute input voltage
(AINP or AINN with respect to AGND)
−2dBFS input and smaller
Dynamic Specifications
f
CLK
Data rate
MSPS
1.25ǒ Ǔ
40MHz
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 10kHz, −2dBFS
= 10kHz, −6dBFS
= 10kHz, −20dBFS
= 100kHz, −2dBFS
= 100kHz, −6dBFS
= 100kHz, −20dBFS
= 500kHz, −2dBFS
= 500kHz, −6dBFS
= 500kHz, −20dBFS
= 10kHz, −2dBFS
= 10kHz, −6dBFS
= 10kHz, −20dBFS
= 100kHz, −2dBFS
= 100kHz, −6dBFS
= 100kHz, −20dBFS
= 500kHz, −2dBFS
= 500kHz, −6dBFS
= 500kHz, −20dBFS
= 10kHz, −2dBFS
= 10kHz, −6dBFS
= 10kHz, −20dBFS
= 100kHz, −2dBFS
= 100kHz, −6dBFS
= 100kHz, −20dBFS
= 500kHz, −2dBFS
= 500kHz, −6dBFS
= 500kHz, −20dBFS
93
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
90
76
93
90
Signal-to-noise ratio (SNR)
70
76
93
90
76
−101
−103
−96
−95
−101
−98
−114
−110
−96
92
Total harmonic distortion (THD)
−90
89
76
91
89
Signal-to-noise and distortion (SINAD)
69
76
93
90
76
3
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
= 40MHz, External V
REF
= +3V, V
CM
= 2.0V, FIFO disabled, and
CLK
R
BIAS
= 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 10kHz, −2dBFS
104
106
99
= 10kHz, −6dBFS
= 10kHz, −20dBFS
= 100kHz, −2dBFS
= 100kHz, −6dBFS
= 100kHz, −20dBFS
= 500kHz, −2dBFS
= 500kHz, −6dBFS
= 500kHz, −20dBFS
97
103
102
120
113
99
Spurious-free dynamic range (SFDR)
92
f
1
f
2
= 495kHz, −2dBFS
= 505kHz, −2dBFS
Intermodulation distortion (IMD)
−98
4
dB
ns
Aperture delay
Digital Filter Characteristics
f
CLK
Passband
0
kHz
550ǒ Ǔ
40MHz
Passband ripple
0.0025
dB
f
CLK
−0.1dB attenuation
−3.0dB attenuation
kHz
575ǒ Ǔ
40MHz
Passband transition
f
CLK
kHz
615ǒ Ǔ
40MHz
f
f
CLK
CLK
Stop band
MHz
dB
39.3ǒ Ǔ
0.7ǒ Ǔ
40MHz
40MHz
Stop band attenuation
Group delay
72
40MHz
µs
20.8ǒ Ǔ
f
CLK
40MHz
Settling time
To 0.001%
µs
36.8ǒ Ǔ
f
CLK
Static Specifications
Resolution
18
Bits
Bits
No missing codes
Input referred noise
Integral nonlinearity
Differential nonlinearity
Offset error
18
1.5
3.5
0.5
0.05
1
LSB, rms
LSB
−2.0dBFS signal
LSB
%FSR
ppmFSR/°C
%
Offset error drift
Gain error
0.25
10
Gain error drift
Excluding reference drift
ppm/°C
dB
Common-mode rejection
Power-supply rejection
at DC
at DC
75
65
dB
4
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
= 40MHz, External V
REF
= +3V, V = 2.0V, FIFO disabled, and
CM
CLK
R
BIAS
= 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
Voltage Reference
V
= (VREFP − VREFN)
2.5
3.75
0.75
2.3
3.0
4.0
1.0
2.5
50
3.2
4.25
1.25
2.8
V
REF
VREFP
VREFN
VMID
V
V
V
V
REF
drift
Internal reference (REFEN = low)
Internal reference (REFEN = low)
ppm/°C
ms
Startup time
Clock Input
Frequency (f
Duty Cycle
15
)
1
40
50
55
MHz
%
CLK
f
= 40MHz
45
CLK
Digital Input/Output
V
V
V
V
0.7 IOVDD
DGND
IOVDD
V
V
IH
0.3 IOVDD
IL
I
I
= 50µA
= 50µA
0.8 IOVDD
V
OH
OL
OH
0.2 IOVDD
10
V
OL
Input leakage
DGND < V
DIGIN
< IOVDD
µA
Power-Supply Requirements
AVDD
DVDD
IOVDD
4.75
2.7
5.25
3.3
5.25
135
105
35
V
V
2.7
V
REFEN = low
REFEN = high
110
85
27
3
mA
mA
mA
mA
AVDD current (I
DVDD current (I
)
AVDD
)
DVDD
IOVDD current (I
)
IOVDD = 3V
5
IOVDD
AVDD = 5V, DVDD = 3V, IOVDD = 3V,
REFEN = high
515
5
645
mW
mW
Power dissipation
PD = low, CLK disabled
Temperature Range
Specified
−40
−40
−60
+85
+105
+150
°C
°C
Operating
Storage
°C
Thermal Resistance, q
25
°C/W
°C/W
JA
PowerPAD soldered to PCB with 2oz.
trace and copper pad.
q
0.5
JC
(1)
The specification limits for VREF, VREFP, VREFN, and VMID apply when using the internal or an external reference. The internal reference
voltages are bounded by the limits shown. When using an external reference, the limits indicate the allowable voltages that can be applied to the
reference pins.
5
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SBAS280E − JUNE 2003 − REVISED MAY 2007
DEFINITIONS
Absolute Input Voltage
Offset Error
Absolute input voltage, given in volts, is the voltage of each
analog input (AINN or AINP) with respect to AGND.
Offset Error, given in % of FSR, is the output reading when
the differential input is zero.
Aperture Delay
Offset Error Drift
Aperture delay is the delay between the rising edge of CLK
and the sampling of the input signal.
Offset error drift, given in ppm of FSR/_C, is the drift over
temperature of the offset error. The offset error is specified
as the larger of the drift from ambient (TA = 25_C) to the
minimum or maximum operating temperatures.
Common-Mode Input Voltage
Common-mode input voltage (VCM) is the average voltage
of the analog inputs:
Signal-to-Noise Ratio (SNR)
SNR, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
(AINP ) AINN)
2
f
CLK/2 (the Nyquist frequency) excluding the first six
harmonics of the input signal and the dc component.
Differential Input Voltage
Differential input voltage (VIN) is the voltage difference
between the analog inputs: (AINP−AINN).
Signal-to-Noise and Distortion (SINAD)
SINAD, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
Differential Nonlinearity (DNL)
f
CLK/2 (the Nyquist frequency) including the harmonics of
DNL, given in least-significant bits (LSB) of the output
code, is the maximum deviation of the output code step
sizes from the ideal value of 1LSB.
the input signal but excluding the dc component.
Spurious Free Dynamic Range (SFDR)
SFDR, given in dB, is the difference between the rms
amplitude of the input signal to the rms amplitude of the
peak spurious signal.
Full-Scale Range (FSR)
FSR is the difference between the maximum and minimum
measurable input signals. For the ADS1625,
FSR = 2 × 1.467VREF
.
Total Harmonic Distortion (THD)
THD, given in dB, is the ratio of the sum of the rms value
of the first six harmonics of the input signal to the rms value
of the input signal.
Gain Error
Gain error, given in %, is the error of the full-scale input
signal with respect to the ideal value.
Gain Error Drift
Gain error drift, given in ppm/_C, is the drift over
temperature of the gain error. The gain error is specified as
the larger of the drift from ambient (TA = 25_C) to the
minimum or maximum operating temperatures.
Integral Nonlinearity (INL)
INL, given in least significant bits (LSB) of the output code,
is the maximum deviation of the output codes from a best-
fit line.
Intermodulation Distortion (IMD)
IMD, given in dB, is measured while applying two input
signals of the same magnitude, but with slightly different
frequencies. It is calculated as the difference between the
rms amplitude of the input signal to the rms amplitude of
the peak spurious signal.
6
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SBAS280E − JUNE 2003 − REVISED MAY 2007
PIN ASSIGNMENTS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AGND
AVDD
AGND
AINN
FIFO_LEV[2] (ADS1626 Only)
ADS1625
ADS1626
FIFO_LEV[1] (ADS1626 Only)
FIFO_LEV[0] (ADS1626 Only)
NC
3
4
5
AINP
DOUT[17]
6
AGND
AVDD
RBIAS
AGND
AVDD
AGND
AVDD
REFEN
IOVDD
DGND
NC
DOUT[16]
TQFP PACKAGE
(TOP VIEW)
7
DOUT[15]
8
DOUT[14]
PowerPADTM
9
DOUT[13]
10
11
12
13
14
15
16
DOUT[12]
DOUT[11]
DOUT[10]
DOUT[9]
DOUT[8]
DOUT[7]
DOUT[6]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Terminal Functions
TERMINAL
NAME
AGND
AVDD
AINN
NO.
TYPE
DESCRIPTION
1, 3, 6, 9, 11, 55, 57
Analog
Analog
Analog ground
2, 7, 10, 12, 58
Analog supply
4
Analog input
Analog input
Analog
Negative analog input
Positive analog input
AINP
5
RBIAS
REFEN
NC
8
Terminal for external analog bias setting resistor
Internal reference enable. Internal pull-down resistor of 170kΩ to DGND.
Must be left unconnected
13
Digital input: active low
16, 45, 49, 50
PD
17
Digital input: active low
Digital
Power down all circuitry. Internal pull-up resistor of 170kΩ to DGND.
Digital supply
DVDD
DGND
RESET
CS
18, 26, 52
15, 19, 25, 51, 54
Digital
Digital ground
20
21
Digital input: active low
Digital input: active low
Digital input: active low
Digital output
Reset digital filter
Chip select
RD
22
Read enable
OTR
23
Active when analog inputs are out of range
Data ready on falling edge
DRDY
DOUT [17:0]
FIFO_LEV[2:0]
24
Digital output: active low
Digital output
27−44
46−48
Data output. DOUT[17] is the MSB and DOUT[0] is the LSB.
Digital input
FIFO level (for the ADS1626 only). FIFO_LEV[2] is MSB.
NOTE: These terminals must be left unconnected on the ADS1625.
IOVDD
CLK
14, 53
56
Digital
Digital input
Analog
Digital I/O supply
Clock input
VCAP
VREFN
VMID
59
Terminal for external bypass capacitor connection to internal bias voltage
Negative reference voltage
60, 61
62
Analog
Analog
Midpoint voltage
VREFP
63, 64
Analog
Positive reference voltage
7
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SBAS280E − JUNE 2003 − REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION
t2
t1
CLK
t2
t3
t4
t4
DRDY
t6
t5
DOUT[17:0]
Data N
Data N + 1
Data N + 2
NOTE: CS and RD tied low.
Figure 1. Data Retrieval Timing (ADS1625, ADS1626 with FIFO Disabled)
RD, CS
t7
t8
DOUT[17:0]
Figure 2. DOUT Inactive/Active Timing (ADS1625, ADS1626 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 1 AND FIGURE 2
SYMBOL
DESCRIPTION
MIN
20
1
TYP
25
MAX
1000
50
UNIT
t
1
ns
MHz
ns
CLK period (1/f
)
CLK
1/t
1
40
f
CLK
t
2
10
CLK pulse width, high or low
t
3
10
ns
Rising edge of CLK to DRDY low
t
4
16 t
1
ns
DRDY pulse width high or low
t
10
15
15
15
ns
Falling edge of DRDY to data invalid
5
t
6
ns
Falling edge of DRDY to data valid
t
7
ns
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
Falling edge of RD and/or CS active (low) to DOUT active.
t
8
ns
NOTE: DOUT[17:0] and DRDY load = 10pF.
8
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CLK
RESET
t11
t9
t12
t10
DRDY
t3
Settled
Data
DOUT[17:0]
NOTE: CS and RD tied low.
Figure 3. Reset Timing (ADS1625, ADS1626 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 3
SYMBOL
DESCRIPTION
MIN
50
TYP
MAX
UNIT
ns
t
3
10
Rising edge of CLK to DRDY low
t
9
ns
RESET pulse width
t
9
ns
Delay from RESET active (low) to DRDY forced high and DOUT forced low
RESET rising edge to falling edge of CLK
10
t
−5
10
ns
11
DRDY
Cycles
t
12
46
Delay from DOUT active to valid DOUT (settling to 0.001%)
NOTE: DOUT[17:0] and DRDY load = 10pF.
9
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t1
t2
CLK
t2
t13
t14
DRDY
t15
t16
CS(1
)
t21
t17
t20
R
D
t18
t19
DOUT[17:0]
D1
D2
DL(2)
(1) CS may be tied low.
(2) The number of data readings (DL) is set by the FIFO level.
Figure 4. Data Retrieval Timing (ADS1626 with FIFO Enabled)
RD, CS
t7
t8
DOUT[17:0]
Figure 5. DOUT Inactive/Active Timing (ADS1626 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5
SYMBOL
DESCRIPTION
MIN
20
TYP
MAX
UNIT
t
1
25
1000
ns
ns
ns
CLK period (1/f
)
CLK
t
2
10
CLK pulse width, high or low
t
7
7
7
15
15
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
t
8
ns
ns
Falling edge of RD and/or CS active (low) to DOUT active.
Rising edge of CLK to DRDY high
t
13
12
CLK
Cycles
(1)
t
14
32 × FIFO Level
DRDY period
CLK
Cycles
t
15
1
DRDY positive pulse width
t
0
0
ns
ns
ns
ns
RD high hold time after DRDY goes low
CS low before RD goes low
RD negative pulse width
16
t
17
t
18
10
10
t
19
t
20
t
21
RD positive pulse width
CLK
Cycles
2
0
RD high before DRDY toggles
RD high before CS goes high
ns
NOTE: DOUT[17:0] and DRDY load = 10pF.
(1)
See FIFO section for more details.
10
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CLK
t11
t9
RESET
t26
t25
DRDY
t23
t24
R
D
Figure 6. Reset Timing (ADS1626 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 6
SYMBOL
DESCRIPTION
MIN
50
TYP
MAX
UNIT
ns
t
9
RESET pulse width
t
11
−5
10
ns
RESET rising edge to falling edge of CLK
CLK
Cycles
t
32
32
RD pulse low after RESET goes high
23
CLK
Cycles
t
24
RD pulse high before first DRDY pulse after RESET goes high
DRDY low after RESET goes low
CLK
Cycles
t
25
32 × (FIFO level + 1)
DRDY
Cycles
See Table 4
t
26
Delay from RESET high to valid DOUT (settling to 0.001%)
11
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TYPICAL CHARACTERISTICS
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
unless otherwise noted.
= 40MHz, External V
CLK REF
= +3V, V
CM
= 2.0V, and R = 37kΩ,
BIAS
A
SPECTRAL RESPONSE
0
SPECTRAL RESPONSE
0
−
fIN = 10kHz, 2dBFS
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
SNR = 93dB
THD = 101dB
SFDR = 104dB
−
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
0
0
0
125
250
375
500
625
0
0
0
125
250
375
500
625
Frequency (kHz)
Frequency (kHz)
SPECTRAL RESPONSE
SPECTRAL RESPONSE
0
0
−
fIN = 100kHz, 2dBFS
SNR = 93dB
THD = 95dB
SFDR = 97dB
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
125
250
375
500
625
125
250
375
500
625
Frequency (kHz)
Frequency (kHz)
SPECTRAL RESPONSE
SPECTRAL RESPONSE
0
0
−
fIN = 500kHz, 2dBFS
SNR = 93dB
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
THD = 114dB
SFDR = 120dB
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
125
250
375
500
625
125
250
375
500
625
Frequency (kHz)
Frequency (kHz)
12
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TYPICAL CHARACTERISTICS (continued)
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
unless otherwise noted.
= 40MHz, External V
CLK REF
= +3V, V
CM
= 2.0V, and R = 37kΩ,
BIAS
A
NOISE HISTOGRAM
INTERMODULATION RESPONSE
0
9k
fIN1 = 495kHz
fIN2 = 505kHz
VIN = 0V
8k
−
−
−
−
20
40
60
80
−
IMD = 98dB
7k
6k
5k
4k
3k
2k
1k
0
−
−
−
−
100
120
140
160
400
450
500
550
600
Frequency (MHz)
Output Code (LSB)
SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION,
AND SPURIOUS−FREE DYNAMIC RANGE
vs INPUT SIGNALAMPLITUDE
SIGNAL−TO−NOISE RATIO
vs INPUT FREQUENCY
110
100
90
80
70
60
50
40
30
20
10
95
90
85
80
75
70
SFDR
−
−
VIN
VIN
=
=
2dBFS
6dBFS
THD
SNR
−
= 20dBFS
VIN
fIN = 100kHz
−
−
−
−
−
−
−
10
70
60
50
40
30
20
0
1k
10k
100k
1M
Input Signal Amplitude, VIN (dB)
Input Frequency, fIN (Hz)
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT FREQUENCY
−
−
−
−
80
130
125
120
115
110
105
100
95
85
90
95
−
−
VIN
=
20dBFS
−
VIN
VIN
=
2dBFS
−
−
−
−
−
100
105
110
115
120
−
VIN
VIN
=
=
6dBFS
=
6dBFS
−
2dBFS
−
= 20dBFS
VIN
90
1k
10k
100k
1M
1k
10k
100k
1M
Input Frequency, fIN (Hz)
Input Frequency, fIN (Hz)
13
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TYPICAL CHARACTERISTICS (continued)
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
unless otherwise noted.
= 40MHz, External V
CLK REF
= +3V, V
CM
= 2.0V, and R
BIAS
= 37kΩ,
A
SIGNAL−TO−NOISE RATIO
TOTAL HARMONIC DISTORTION
vs INPUT COMMON−MODE VOLTAGE
95
vs INPUT COMMON−MODE VOLTAGE
−
−
−
−
80
85
90
95
94
−
VIN
=
=
2dBFS
93
92
91
90
89
88
87
86
85
−
−
−
VIN
=
=
2dBFS
VIN
6dBFS
−
−
−
100
105
110
VIN
6dBFS
fIN = 100kHz
2.7
fIN = 100kHz
1.5
1.7
1.9
2.1
2.3
2.5
2.9
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
Input Common−Mode Voltage, VCM (V)
Input Common−Mode Voltage, VCM (V)
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT COMMON−MODE VOLTAGE
SIGNAL−TO−NOISE RATIO
vs CLK FREQUENCY
110
105
100
95
92
90
88
83
84
82
80
−
= 6dBFS
VIN
Ω
RBIAS = 30k
Ω
RBIAS = 37k
−
= 2dBFS
VIN
90
Ω
RBIAS = 45k
85
Ω
RBIAS = 50k
80
Ω
RBIAS = 60k
75
fIN = 100kHz
2.7
70
−
fIN = 100kHz, 6dBFS
65
1.5
1.7
1.9
2.1
2.3
2.5
2.9
10
15
20 25
30
35
40
45
50
55
60
Input Common−Mode Voltage, VCM (V)
CLK Frequency, fCLK (MHz)
TOTAL HARMONIC DISTORTION
vs CLK FREQUENCY
SPURIOUS−FREE DYNAMIC RANGE
vs CLK FREQUENCY
−
−
−
−
−
75
110
105
100
95
−
fIN = 100kHz, 6dBFS
Ω
RBIAS = 60k
80
85
90
95
Ω
RBIAS = 30k
Ω
RBIAS = 50k
Ω
RBIAS = 45k
Ω
RBIAS = 45k
RBIAS = 37k
RBIAS = 50k
Ω
RBIAS = 37k
90
Ω
85
Ω
Ω
RBIAS = 30k
−
−
100
105
80
−
fIN = 100kHz, 6dBFS
Ω
RBIAS = 60k
75
10
15
20 25
30
35
40
45
50
55
60
10
15
20 25
30
35
40
45
50
55
60
CLK Frequency, fCLK (MHz)
CLK Frequency, fCLK (MHz)
14
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TYPICAL CHARACTERISTICS (continued)
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
unless otherwise noted.
= 40MHz, External V
CLK REF
= +3V, V
CM
= 2.0V, and R
BIAS
= 37kΩ,
A
SIGNAL−TO−NOISE RATIO
vs TEMPERATURE
100
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
−
−
−
−
−
91
93
95
97
99
95
−
−
VIN
VIN
=
=
2dBFS
6dBFS
−
= 2dBFS
VIN
90
85
80
75
70
−
VIN
=
20dBFS
−
−
−
101
103
105
−
VIN
=
20dBFS
−
VIN
=
6dBFS
fIN = 100kHz
fIN = 100kHz
−
−
−
−
40
15
10
35
60
85
40
15
10
35
60
85
_
_
Temperature ( C)
Temperature ( C)
SPURIOUS−FREE DYNAMIC RANGE
vs TEMPERATURE
POWER−SUPPLY CURRENT
vs TEMPERATURE
120
100
80
60
40
20
0
106
104
102
100
98
−
VIN
=
6dBFS
IAVDD (REFEN = Low)
IAVDD (REFEN = High)
−
VIN
=
20dBFS
IDVDD + IIOVDD
−
VIN
=
2dBFS
96
94
Ω
R
f
BIAS = 37k
fIN = 100kHz
DVDD = IOVDD = 3V
CLK = 40MHz
92
−
−
15
−
−
40
10
35
60
85
40
15
10
35
60
85
_
_
Temperature ( C)
Temperature ( C)
SUPPLY CURRENT vs CLK FREQUENCY
AVDD = 5V, DVDD = IOVDD = 3V, REFEN = High
IAVDD (RBIAS = 37kΩ)
ANALOG SUPPLY CURRENT vs RBIAS
125
105
85
65
45
25
5
140
130
120
110
100
90
REFEN = Low
REFEN = High
IAVDD (RBIAS = 60kΩ)
80
IDVDD + IIOVDD
70
60
fCLK = 40MHz
35
50
5
15
25
35
45
55
65
30
40
45
50
55
60
CLK Frequency, fCLK (MHz)
RBIAS (kΩ)
15
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TYPICAL CHARACTERISTICS (continued)
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
unless otherwise noted.
= 40MHz, External V
CLK REF
= +3V, V
CM
= 2.0V, and R = 37kΩ,
BIAS
A
INTEGRAL NONLINEARITY
4
DIFFERENTIAL NONLINEARITY
0.5
−
fIN = 100Hz, 2dBFS
0.4
0.3
0.2
0.1
0
3
2
1
0
1
2
3
4
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100k 80k 60k 40k 20k
0
20k 40k 60k 80k 100k
100k 80k 60k 40k 20k
0
20k 40k 60k 80k 100k
Output Code (LSB)
Output Code (LSB)
16
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positive digital output code of 7FFFh. Likewise, the most
negative measurable differential input is –1.467VREF, which
produces the most negative digital output code of 8000h.
OVERVIEW
The ADS1625 and ADS1626 are high-performance
delta-sigma ADCs with a default oversampling ratio of 32.
The modulator uses an inherently stable 2-1-1 pipelined
The ADS1625/6 supports a very wide range of input
signals. For VREF = 3V, the full scale input voltages are
4.4V. Having such a wide input range makes out-of-range
signals unlikely. However, should an out-of-range signal
occur, digital output OTR will go high.
delta-sigma
modulator architecture incorporating
proprietary circuitry that allows for very linear high-speed
operation. The modulator samples the input signal at
40MSPS (when fCLK = 40MHz). A low-ripple, linear-phase
digital filter decimates the modulator output to provide data
output word rates of 1.25MSPS with a signal passband out
to 615kHz.
To achieve the highest analog performance, it is
recommended that the inputs be limited to 1.165VREF
(−2dBFS). For VREF
=
3V, the corresponding
recommended input range is 3.78V.
Conceptually, the modulator and digital filter measure the
differential input signal, VIN = (AINP – AINN), against the
scaled differential reference, VREF = (VREFP – VREFN),
as shown in Figure 7. The voltage reference can either be
generated internally or supplied externally. An 18-bit paral-
lel data bus, designed for direct connection to DSPs, out-
puts the data. A separate power supply for the I/O allows
flexibility for interfacing to different logic families. Out-of-
range conditions are indicated with a dedicated digital out-
put pin. Analog power dissipation is controlled using an ex-
ternal resistor. This allows reduced dissipation when
operating at slower speeds. When not in use, power con-
sumption can be dramatically reduced using the PD pin.
The analog inputs must be driven with a differential signal
to achieve optimum performance. The recommended
common-mode
voltage
of
the
input
signal,
AINP ) AINN
VCM
+
, is 2.0V. For signals larger than
2
−2dBFS, the input common-mode voltage needs to be
raised in order to meet the absolute input voltage
specifications. The Typical Characteristics show how
performance varies with input common-mode voltage.
In addition to the differential and common-mode input
voltages, the absolute input voltage is also important. This
is the voltage on either input (AINP or AINN) with respect
to AGND. The range for this voltage is:
The ADS1626 incorporates an adjustable FIFO for the out-
put data. The level of the FIFO is set by the FIFO_LEV[2:0]
pins. Other than the FIFO, the ADS1625 and ADS1626 are
identical, and together are referred to as the ADS1625/6.
−0.1V < (AINN or AINP) < 4.6V.
If either input is taken below –0.1V, ESD protection diodes
on the inputs will turn on. Exceeding 4.6V on either input
will result in degradation in the linearity performance. ESD
protection diodes will also turn on if the inputs are taken
above AVDD (+5V).
ANALOG INPUTS (AINP, AINN)
The ADS1625/6 measures the differential signal,
VIN = (AINP − AINN), against the differential reference,
VREF = (VREFP – VREFN). The reference is scaled
internally so that the full-scale differential input voltage is
1.467VREF. That is, the most positive measurable
differential input is 1.467VREF, which produces the most
For signals below –2dBFS, the recommended absolute
input voltage is:
0.1V < (AINN or AINP) < 4.2V
Keeping the inputs within this range provides for optimum
performance.
VREFP VREFN
IOVDD
Σ
VREF
1.467
1.467VREF
OTR
VIN
AINP
AINN
ADS1626 Only
Σ∆
Modulator
Digital
Filter
Parallel
Interface
DOUT[17:0]
Σ
FIFO
FIFO_LEV[2:0]
Figure 7. Conceptual Block Diagram
17
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input to AGND, improve linearity and should be placed as
close to the pins as possible. Place the drivers close to the
inputs and use good capacitor bypass techniques on their
supplies; usually a smaller high-quality ceramic capacitor
in parallel with a larger capacitor. Keep the resistances
used in the driver circuits low—thermal noise in the driver
circuits degrades the overall noise performance. When the
signal can be ac-coupled to the ADS1625/6 inputs, a
simple RC filter can set the input common-mode voltage.
The ADS1625/6 is a high-speed, high-performance ADC.
Special care must be taken when selecting the test
equipment and setup used with this device. Pay particular
attention to the signal sources to ensure they do not limit
performance when measuring the ADS1625/6.
INPUT CIRCUITRY
The ADS1625/6 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are charged
by the inputs and then discharged internally with this cycle
repeating at the frequency of CLK. Figure 8 shows a
conceptual diagram of these circuits. Switches S2 represent
the net effect of the modulator circuitry in discharging the
sampling capacitors, the actual implementation is different.
The timing for switches S1 and S2 is shown in Figure 9.
ADS1625
ADS1626
S1
AINP
AINN
S2
10pF
8pF
Ω
392
40pF
Ω
Ω
392
392
VIN
2
VMID
−
S1
0.01µF
Ω
49.9
AINP
OPA2822
(2)
S2
(1)
VCM
100pF
10pF
8pF
Ω
1k
Ω
392
1µF
(2)
Ω
392
ADS1625
ADS1626
VMID
(1)
VCM
100pF(3)
AGND
(2)
40pF
Ω
392
VIN
Ω
1k
2
0.01µF
Ω
49.9
Figure 8. Conceptual Diagram of Internal
Circuitry Connected to the Analog Inputs
AINN
OPA2822
Ω
392
(2)
(1)
VCM
100pF
Ω
392
1µF
AGND
tSAMPLE = 1/fCLK
(1) Recommended VCM = 2.0V.
(2) Optional ac−coupling circuit provides common−mode input voltage.
On
Off
S1
S2
≤
(3) Increase to 390pF when fIN 100kHz for improved SNR and THD.
On
Off
Figure 10. Recommended Driver Circuit Using the
OPA2822
Figure 9. Timing for the Switches in Figure 2
DRIVING THE INPUTS
22pF
24.9Ω
AINP
392Ω
THS4503
392Ω
100pF
100pF
392Ω
392Ω
−VIN
The external circuits driving the ADS1625/6 inputs must
be able to handle the load presented by the switching
capacitors within the ADS1625/6. Input switches S1 in
Figure 9 are closed approximately ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ of the
sampling period, tsample, allowing only ≈12ns for the
internal capacitors to be charged by the inputs, when
fCLK = 40MHz.
ADS1625
ADS1626
VCM
+VIN
24.9
Ω
AINN
100pF
22pF
Figure 10 and Figure 11 show the recommended circuits
when using single-ended or differential op amps,
respectively. The analog inputs must be driven
differentially to achieve optimum performance. The
external capacitors, between the inputs and from each
Figure 11. Recommended Driver Circuits Using
the THS4503 Differential Amplifier
18
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and VREFN = 1V. The external circuitry must be capable
of providing both a dc and a transient current. Figure 13
shows a simplified diagram of the internal circuitry of the
reference when the internal reference is disabled. As with
the input circuitry, switches S1 and S2 open and close as
shown in Figure 9.
REFERENCE INPUTS (VREFN, VREFP, VMID)
The ADS1625 can operate from an internal or external
voltage reference. In either case, reference voltage VREF is
set by the differential voltage between VREFN and VREFP:
VREF = (VREFP – VREFN). VREFP and VREFN each use
two pins, which should be shorted together. VMID equals
approximately 2.5V and is used by the modulator. VCAP
connects to an internal node, and must also be bypassed
with an external capacitor. For the best analog performance,
ADS1625
ADS1626
S1
it is recommended that an external reference voltage (VREF
of 3.0V be used.
)
VREFP
VREFP
S2
Ω
300
50pF
INTERNAL REFERENCE (REFEN = LOW)
VREFN
VREFN
S1
To use the internal reference, set the REFEN pin low. This
activates the internal circuitry that generates the reference
voltages. The internal reference voltages are applied to
the pins. Good bypassing of the reference pins is critical
to achieve optimum performance and is done by placing
the bypass capacitors as close to the pins as possible.
Figure 12 shows the recommended bypass capacitor
values. Use high quality ceramic capacitors for the smaller
values. Avoid loading the internal reference with external
circuitry. If the ADS1625/6 internal reference is to be used
by other circuitry, buffer the reference voltages to prevent
directly loading the reference pins.
Figure 13. Conceptual Internal Circuitry for the
Reference When REFEN = High
Figure 14 shows the recommended circuitry for driving
these reference inputs. Keep the resistances used in the
buffer circuits low to prevent excessive thermal noise from
degrading performance. Layout of these circuits is critical;
make sure to follow good high-speed layout practices.
Place the buffers, and especially the bypass capacitors, as
close to the pins as possible. VCAP is unaffected by the
setting on REFEN and must be bypassed when using the
internal or an external reference.
ADS1625
ADS1626
VREFP
VREFP
10µF
0.1µF
Ω
µ
392
22µF
F
0.001
ADS1625
ADS1626
VMID
22µF
0.1µF
VREFP
VREFP
OPA2822
10µF
0.1µF
µ
10
F
4V
2.5V
1V
22µF
µ
0.1
F
Ω
392
VREFN
VREFN
µ
µ
22 F
22
F
0.1µ
F
µ
0.001
F
10µF
0.1µF
0.1µF
VMID
OPA2822
VCAP
10µ
F
µ
0.1
F
Ω
392
µ
AGND
22
F
µ
0.001
F
VREFN
VREFN
Figure 12. Reference Bypassing When Using the
Internal Reference
OPA2822
µ
0.1
F
F
10µ
F
EXTERNAL REFERENCE (REFEN = HIGH)
VCAP
To use an external reference, set the REFEN pin high. This
deactivates the internal generators for VREFP, VREFN
and VMID, and saves approximately 25mA of current on
the analog supply (AVDD). The voltages applied to these
pins must be within the values specified in the Electrical
Characteristics table. Typically VREFP = 4V, VMID = 2.5V
µ
0.1
AGND
Figure 14. Recommended Buffer Circuit When
Using an External Reference
19
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CLOCK INPUT (CLK)
Table 2. Output Code Versus Input Signal
INPUT SIGNAL
(INP – INN)
IDEAL OUTPUT
(1)
The ADS1625/6 requires an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with any
high-speed data converter, a high quality clock is essential
for optimum performance. Crystal clock oscillators are the
recommended CLK source; other sources, such as
frequency synthesizers, are usually not adequate. Make
sure to avoid excess ringing on the CLK input; keeping the
trace as short as possible will help.
CODE
OTR
(2)
(> 0dB)
≥ +1.467V
REF
1FFFFh
1FF57h
00001h
1
0
0
≥ +1.467V
(0dB)
REF
+1.467VREF
2
17 * 1
0
00000h
3FFFFh
0
0
−1.467VREF
2
17 * 1
Measuring high-frequency, large-amplitude signals
requires tight control of clock jitter. The uncertainty during
sampling of the input from clock jitter limits the maximum
achievable SNR. This effect becomes more pronounced
with higher frequency and larger magnitude inputs.
Fortunately, the ADS1625/6 oversampling topology
reduces clock jitter sensitivity over that of Nyquist rate
converters like pipeline and successive approximation
converters by a factor of √32.
200A8h
20000h
0
1
217
ǒ
Ǔ
Ǔ(2)
v −1.467VREF
217 * 1
217
ǒ
v −1.467VREF
217 * 1
(1)
(2)
Excludes effects of noise, INL, offset and gain errors.
Large step inputs.
OUT-OF-RANGE INDICATION (OTR)
In order to not limit the ADS1625/6 SNR performance,
keep the jitter on the clock source below the values shown
in Table 1. When measuring lower frequency and lower
amplitude inputs, more CLK jitter can be tolerated. In
determining the allowable clock source jitter, select the
worst-case input (highest frequency, largest amplitude)
that will be seen in the application.
If the output code on DOUT[17:0] exceeds the positive or
negative full-scale, the out-of-range digital output OTR will
go high on the falling edge of DRDY. When the output code
returns within the full-scale range, OTR returns low on the
falling edge of DRDY.
DATA RETRIEVAL
Table 1. Maximum Allowable Clock Source Jitter
for Different Input Signal Frequencies and
Amplitude
Data retrieval is controlled through a simple parallel
interface. The falling edge of the DRDY output indicates
new data are available. To activate the output bus, both CS
and RD must be low, as shown in Table 3. On the
ADS1625, both of these signals can be tied low. On the
ADS1626 with FIFO enabled, only CS can be tied low
because RD must toggle to operate the FIFO. See the
FIFO section for more details. Make sure the DOUT bus
does not drive heavy loads (> 20pF), as this will degrade
performance. Use an external buffer when driving an edge
connector or cables.
MAXIMUM
ALLOWABLE
CLOCK SOURCE
JITTER (RMS)
INPUT SIGNAL
MAXIMUM
MAXIMUM
FREQUENCY
AMPLITUDE
500kHz
−2dB
−20dB
−2dB
7ps
50ps
35ps
285ps
500kHz
100kHz
100kHz
−20dB
Table 3. Truth Table for CS and RD
DATA FORMAT
CS
0
RD
0
DOUT[17:0]
Active
The 18-bit output data is in binary two’s complement format,
as shown in Table 2. Under normal operation, the output
codes range between 200A8h to 1FF57h. Signals less than
−1.467VREF will clip at 200A8h and likewise, signals greater
than 1.467VREF will clip at 1FF57h. For large step changes
on the inputs, the output clips at the positive full-scale value
of 1FFFFh (positive transients) or the negative full-scale
value of 20000h (negative transients).
0
1
High impedance
High impedance
High impedance
1
0
1
1
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RESETTING THE ADS1625
RESETTING THE ADS1626
The ADS1625 and ADS1626 with FIFO disabled are
asynchronously reset when the RESET pin is taken low.
During reset, all of the digital circuits are cleared,
DOUT[17:0] are forced low, and DRDY forced high. It is
recommended that the RESET pin be released on the
falling edge of CLK. Afterwards, DRDY goes low on the
second rising edge of CLK. Allow 46 DRDY cycles for the
digital filter to settle before retrieving data. See Figure 3 for
the timing specifications.
The ADS1626 with the FIFO enabled requires a different
reset sequence than the ADS1625, as shown in Figure 16.
Ignore any DRDY toggles that occur while RESET is low.
Release RESET on the rising edge of CLK, then
afterwards toggle RD to complete the reset sequence.
CLK
Reset can be used to synchronize multiple ADS1625s. All
devices to be synchronized must use a common CLK
input. With the CLK inputs running, pulse RESET on the
falling edge of CLK, as shown in Figure 15. Afterwards, the
converters will be converting synchronously with the
RESET
Ignore
t26
DRDY
DRDY
outputs
updating
simultaneously.
After
R
D
synchronization, allow 46 DRDY cycles (t12) for output
data to fully settle.
Toggle RD to complete reset sequence
Figure 16. Resetting the ADS1626 with the FIFO
Enabled
ADS16251
RESET
Clock
RESET
CLK
DRDY
DRDY1
After resetting, the settling time for the ADS1626 is 46 CLK
cycles, regardless of the FIFO level. Therefore, for higher
FIFO levels, it takes fewer DRDY cycles to settle because
the DRDY period is longer. Table 4 shows the number of
DRDY cycles required to settle for each FIFO level.
DOUT[17:0]
DOUT[17:0]1
ADS16252
RESET
CLK
DRDY
DRDY2
DOUT[17:0]
DOUT[17:0]2
Table 4. ADS1626 Reset Settling
FILTER SETTLING TIME AFTER RESET
(t in units of DRDY cycles )
26
FIFO LEVEL
CLK
2
4
23
12
8
RESET
t12
6
8
6
DRDY1
10
12
14
5
4
Settled
Data
DOUT[17:0]1
4
DRDY2
Settled
Data
DOUT[17:0]2
Synchronized
Figure 15. Synchronizing Multiple Converters
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SETTLING TIME
IMPULSE RESPONSE
Figure 18 plots the normalized response for an input applied
at t = 0. The X-axis units of time are DRDY cycles. As shown
in Figure 18, the peak of the impulse takes 26 DRDY cycles
to propagate to the output. For fCLK = 40MHz, a DRDY cycle
is 0.8µs in duration and the propagation time (or group delay)
is 26 × 0.8µs = 20.8µs.
The settling time is an important consideration when
measuring signals with large steps or when using a
multiplexer in front of the analog inputs. The ADS1625/6
digital filter requires time for an instantaneous change in
signal level to propagate to the output.
Be sure to allow the filter time to settle after applying a large
step in the input signal, switching the channel on a
multiplexer placed in front of the inputs, resetting the
ADS1625/6, or exiting the power-down mode.
1.0
0.8
0.6
0.4
0.2
0
Figure 17 shows the settling error as a function of time for a
full-scale signal step applied at t = 0. This figure uses DRDY
cycles for the time scale (X-axis). After 46 DRDY cycles, the
settling error drops below 0.001%. For fCLK = 40MHz, this
corresponds to a settling time of 36.8µs.
101
100
−
−
0.2
0.4
0
10
20
30
40
50
60
Time (DRDY cycles)
10−1
10−2
10−3
10−4
Figure 18. Impulse Response
25
30
35
40
45
50
Settling Time (DRDY cycles)
Figure 17. Settling Time
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FREQUENCY RESPONSE
0.0025
0.0020
0.0015
0.0010
0.0005
0
The linear phase FIR digital filter sets the overall frequency
response. Figure 19 shows the frequency response from dc
to 20MHz for fCLK = 40MHz. The frequency response of the
ADS1625/6 filter scales directly with CLK frequency. For
example, if the CLK frequency is decreased by half (to
20MHz), the values on the X-axis in Figure 19 would need to
be scaled by half, with the span becoming dc to 10MHz.
fCLK = 40MHz
−0.0005
−0.0010
−0.0015
−0.0020
−0.0025
Figure 20 shows the passband ripple from dc to 550kHz
(fCLK = 40MHz). Figure 21 shows a closer view of the
passband transition by plotting the response from 500kHz
to 640kHz (fCLK = 40MHz).
0
100
200
300
400
500
600
Frequency (kHz)
The overall frequency response repeats at multiples of the
CLK frequency. To help illustrate this, Figure 22 shows the
response out to 120MHz (fCLK = 40MHz). Notice how the
passband response repeats at 40MHz, 80MHz and
120MHz; it is important to consider this when there is
high-frequency noise present with the signal. The
modulator bandwidth extends to 100MHz. High-frequency
noise around 40MHz and 80MHz will not be attenuated by
either the modulator or the digital filter. This noise will alias
back in-band and reduce the overall SNR performance
unless it is filtered out prior to the ADS1625/6. To prevent
this, place an anti-alias filter in front of the ADS1625/6 that
rolls off before 39MHz.
Figure 20. Passband Ripple
1
0
−
−
−
−
−
−
1
2
3
4
5
6
20
fCLK = 40MHz
fCLK = 40MHz
0
−
−
−
−
20
40
60
80
600
500
520
540
560
580
620
640
Frequency (kHz)
Figure 21. Passband Transition
−
−
−
100
120
140
0
2
4
6
8
10
12 14
16 18
20
20
0
fCLK = 40MHz
Frequency (MHz)
−
−
−
−
20
40
60
80
Figure 19. Frequency Response.
−
−
−
100
120
140
0
20
40
60
80
100
120
Frequency (MHz)
Figure 22. Frequency Response Out to 120MHz
23
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of RD, the second data are present on the data output pins.
Continue this way until all the data have been read from the
FIFO, making sure to take RD high when complete.
Afterwards, wait until DRDY toggles and repeat the
readback cycle. Figure 23 shows an example readback
when FIFO_LEV[2:0] = 010 (level = 4).
FIFO (ADS1626 ONLY)
The ADS1626 includes an adjustable level first-in first-out
buffer (FIFO) for the output data. The FIFO allows data to
be temporarily stored within the ADS1626 to provide more
flexibility for the host controller when retrieving data. Pins
FIFO_LEV[2:0] set the level or depth of the FIFO. Note that
these pins must be left unconnected on the ADS1625. The
FIFO is enabled by setting at least one of the FIFO_LEV
inputs high. Table 5 shows the corresponding FIFO level
and DRDY period for the different combinations of
FIFO_LEV[2:0] settings. For the best performance when
using the FIFO, it is recommended to:
Readback considerations
The exact number of data readings set by the FIFO level
must be read back each time DRDY toggles. The one
exception is that readback can be skipped entirely. In this
case, the DRDY period increases to 512 CLK period.
Figure 24 illustrates an example when readback is
skipped with the FIFO level = 4. Do not read back more or
less readings from the FIFO than set by the level. This
interrupts the FIFO operation and can cause DRDY to stay
low indefinitely. If this occurs, the RESET pin must be
toggled followed by a RD pulse. This resets the ADS1626
FIFO and also the digital filter, which must settle
afterwards before valid data is ready. See the section,
Resetting the ADS1626, for more details. Also note that
the RD signal is independent of the CS signal. Therefore,
when multiple devices are used, the RD signal should not
be shared. Alternatively, individual RD signals can be
generated by performing an OR operation with the CS
signal.
1. Set IOVDD = 3V.
2. Synchronize data retrieval with CLK.
3. Minimize loading on outputs DOUT[17:0].
4. Ensure rise and fall times on CLK and RD are 1ns or
longer.
Table 5. FIFO Buffer Level Settings for the
ADS1626
FIFO_LEV[2:0]
FIFO BUFFER LEVEL
DRDY PERIOD
000
0: disabled,
32/f
CLK
operates like ADS1625
001
010
011
100
101
110
111
2
4
64/f
CLK
Setting the FIFO Level
128/f
192/f
256/f
320/f
384/f
448/f
CLK
CLK
CLK
CLK
CLK
CLK
The FIFO level setting is usually a static selection that is
set when power is first applied to the ADS1626. If the FIFO
level needs to be changed after powerup, there are two
options. One is to asynchronously set the new value on pin
FIFO_LEV[2:0] then toggle RESET. Remember that the
ADS1626 will need to settle after resetting. See the
section, Resetting the ADS1626, for more details. The
other option avoids requiring a reset, but needs
synchronization of the FIFO level change with the
readback. The FIFO_LEV[2:0] pins have to be changed
after RD goes high after reading the first data, but before
RD goes low to read the last data from the FIFO. The new
FIFO level becomes active immediately and the DRDY
period adjusts accordingly. When decreasing the FIFO
level this way, make sure to give adequate time for
readback of the data before setting the new, smaller level.
Figure 25 illustrates an example of a synchronized FIFO
level change from 4 to 8.
6
8
10
12
14
FIFO Operation
The ADS1626 FIFO collects the number of output
readings set by the level corresponding to the
FIFO_LEV[2:0] setting. When the specified level is
reached, DRDY is pulsed high, indicating the data in the
FIFO are ready to be read. The DRDY period is a function
of the FIFO level, as shown in Table 5. To read the data,
make sure CS is low (it is acceptable to tie it low) and then
take RD low. The first, or oldest, data will be presented on
the data output pins. After reading this data, advance to the
next data reading by toggling RD. On the next falling edge
24
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DRDY
CS(1)
RD
(2)
Data1
Data2
Data3
Data4
DOUT[17:0]
(1) CS can be tied low.
(2) Data1 are the oldest data and Data4 are the most recent.
Figure 23. Example of FIFO Readback when FIFO Level = 4
128/fCLK
512/fCLK
DRDY
RD
Figure 24. Example of Skipping Readback when FIFO Level = 4
128/fCLK
256/fCLK
DRDY
RD
FIFO_LEV[2:0]
010 (Level = 4)
100 (Level = 8)
Change FIFO_LEV[2:0] here
Figure 25. Example of Synchronized Change of FIFO Level from 4 to 8
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ANALOG POWER DISSIPATION
POWER DOWN (PD)
An external resistor connected between the RBIAS pin
and the analog ground sets the analog current level, as
shown in Figure 26. The current is inversely proportional
to the resistor value. Table 6 shows the recommended
values of RBIAS for different CLK frequencies. Notice that
the analog current can be reduced when using a slower
frequency CLK input, because the modulator has more
time to settle. Avoid adding any capacitance in parallel to
When not in use, the ADS1625/6 can be powered down by
taking the PD pin low. All circuitry will be shutdown, including
the voltage reference. To minimize the digital current during
power down, stop the clock signal supplied to the CLK input.
There is an internal pull-up resistor of 170kΩ on the PD pin,
but it is recommended that this pin be connected to IOVDD
if not used. If using the ADS1626 with the FIFO enabled,
issue a reset after exiting the power-down mode. Make sure
to allow time for the reference to start up after exiting
power-down mode. The internal reference typically requires
15ms. After the reference has stabilized, allow at least 100
DRDY cycles for the modulator and digital filter to settle
before retrieving data.
R
BIAS, since this will interfere with the internal circuitry
used to set the biasing.
ADS1625
ADS1626
POWER SUPPLIES
RBIAS
Three supplies are used on the ADS1625/6: analog
(AVDD), digital (DVDD) and digital I/O (IOVDD). Each
supply must be suitably bypassed to achieve the best
performance. It is recommended that a 1µF and 0.1µF
ceramic capacitor be placed as close to each supply pin as
possible. Connect each supply-pin bypass capacitor to the
associated ground, see Figure 27. Each main supply bus
should also be bypassed with a bank of capacitors from
47µF to 0.1µF, as shown.
RBIAS
AGND
Figure 26. External Resistor Used to Set Analog
Power Dissipation
The IO and digital supplies (IOVDD and DVDD) can be
connected together when using the same voltage. In this
case, only one bank of 47µF to 0.1µF capacitors is needed
on the main supply bus, though each supply pin must still
be bypassed with a 1µF and 0.1µF ceramic capacitor.
Table 6. Recommended R
Resistor Values for
BIAS
Different CLK Frequencies
TYPICAL POWER
DATA
RATE
DISSIPATION WITH REFEN
HIGH
f
R
BIAS
CLK
10MHz 312.5kHz
20MHz 625kHz
65kΩ
60kΩ
50kΩ
37kΩ
150mW
305mW
390mW
515mW
30MHz 937.5kHz
40MHz 1.25MHz
26
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DVDD
µ
µ
µ
1 F
µ
0.1 F
47 F
4.7 F
IOVDD
AVDD
µ
µ
1 F
47 F
µ
µ
0.1 F
4.7 F
CP
CP
CP
µ
µ
0.1 F
4.7 F
µ
47 F
µ
1 F
58
57
55
54
53
52
51
1
AGND
AVDD
CP
2
3
If using separate analog and
digital ground planes, connect
together on the ADS1625/6 PCB.
6
AGND
CP
AVDD
AGND
7
9
DGND
AGND
ADS1625
ADS1626
||
µ
µ
NOTE: CP = 1 F 0.1 F
CP
AVDD
AGND
10
11
CP
12
AVDD
14
15
IOVDD
DGND
CP
18
19
25
26
CP
CP
Figure 27. Recommended Power-Supply Bypassing
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LAYOUT ISSUES
APPLICATIONS
INTERFACING THE ADS1625 TO THE
TMS320C6000
The ADS1625/6 is a very high-speed, high-resolution data
converter. In order to achieve the maximum performance,
careful attention must be given to the printed circuit board
(PCB) layout. Use good high-speed techniques for all
circuitry. Critical capacitors should be placed close to pins
as possible. These include capacitors directly connected
to the analog and reference inputs and the power supplies.
Make sure to also properly bypass all circuitry driving the
inputs and references.
Figure 28 illustrates how to directly connect the ADS1625
to the TMS320C6000 DSP. The processor controls
reading using output ARE. The ADS1625 is selected using
the DSP control output, CE2. The ADS1625 18-bit data
output bus is directly connected to the TMS320C6000 data
bus. The data ready output from the ADS1625, DRDY,
drives interrupt EXT_INT7 on the TMS320C6000.
There are two possible approaches for the ground plane on
the PCB: a single common plane or two separate planes, one
for the analog grounds and one for the digital grounds. When
using only one common plane, isolate the flow of current on
pin 58 from pin 1; use breaks on the ground plane to
accomplish this. Pin 58 carries the switching current from the
analog clocking for the modulator and can corrupt the quiet
analog ground on pin 1. When using two planes, it is
recommended that they be tied together right at the PCB. Do
not try to connect the ground planes together after running
separately through edge connectors or cables as this
reduces performance and increases the likelihood of latchup.
ADS1625
TMS320C6000
18
DOUT[17:0]
XD[17:0]
DRDY
EXT_INT7
CS
RD
CE2
ARE
In general, keep the resistances used in the driving circuits
for the inputs and reference low to prevent excess thermal
noise from degrading overall performance. Avoid having
the ADS1625/6 digital outputs drive heavy loads. Buffers
on the outputs are recommended unless the ADS1625/6
is connected directly to a DSP or controller situated
nearby. Additionally, make sure the digital inputs are
driven with clean signals as ringing on the inputs can
introduce noise.
Figure 28. ADS1625—TMS320C6000 Interface
Connection
INTERFACING THE ADS1626 TO THE
TMS320C6000
Figure 29 illustrates how to directly connect the ADS1626
to the TMS320C6000 DSP. The processor controls
reading using output ARE. The ADS1626 is permanently
selected by grounding the CS pin. The ADS1626 18-bit
data output bus is directly connected to the TMS320C6000
data bus. The data ready output from the ADS1626,
DRDY, drives interrupt EXT_INT7 on the TMS320C6000.
The ADS1625/6 uses TI PowerPAD technology. The
PowerPAD is physically connected to the substrate of the
silicon inside the package and must be soldered to the
analog ground plane on the PCB using the exposed metal
pad underneath the package for proper heat dissipation.
Please refer to application report SLMA002, located at
www.ti.com, for more details on the PowerPAD package.
ADS1626
TMS320C6000
18
DOUT[17:0]
XD[17:0]
DRDY
CS
EXT_INT7
ARE
RD
Figure 29. ADS1626—TMS320C6000 Interface
Connection
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INTERFACING THE ADS1625 TO THE
TMS320VC5510
INTERFACING THE ADS1626 TO THE
TMS320VC5510
Figure 30 illustrates how to connect the ADS1625 to the
TMS320VC5510 DSP. The DSP controls reading using
output ARE. The ADS1625 is selected using the DSP
control output CE2. The ADS1625 18-bit data output bus
is directly connected to the TMS320VC5510 data bus. The
data ready output from the ADS1625, DRDY, drives the
INT3 interrupt line on the TMS320VC5510.
Figure 31 illustrates how to directly connect the ADS1626
to the TMS320VC5510 Digital Signal Processor. The
processor controls reading the ADC using the ARE output.
The ADS1626 is permanently selected by grounding the
CS pin. If there are any additional devices connected to the
TMS320VC5510 I/O space, address decode logic will be
required between the ADC and the DSP to prevent data
bus contention and ensure that only one device at a time
is selected. The ADS1626 18-bit data output bus is directly
connected to the TMS320VC5510. The data ready output
from the ADS1626, DRDY, drives interrupt INT3 on the
TMS320VC5510.
ADS1625
TMS320VC5510
18
DOUT[17:0]
D[17:0]
DRDY
INT3
ADS1626
TMS320VC5510
CS
RD
CE2
ARE
18
DOUT[17:0]
D[17:0]
DRDY
CS
INT3
ARE
Figure 30. ADS1625—TMS320VC5510 Interface
Connection
RD
Figure 31. ADS1626—TMS320VC5510 Interface
Connection
Code Composer Studio, available from TI, provides
support for interfacing TI DSPs through a collection of data
converter plugins. Check the TI web site, located at
www.ti.com/sc/dcplug-in, for the latest information on
ADS1625/6 support.
29
ꢍꢓ ꢋꢀ ꢙ ꢈ ꢉ
ꢍꢓ ꢋꢀ ꢙ ꢈ ꢙ
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
Revision History
DATE
REV
PAGE
SECTION
Readback Considerations Added last three sentences.
DESCRIPTION
5/16/07
E
24
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
30
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2007
PACKAGING INFORMATION
Orderable Device
ADS1625IPAPR
ADS1625IPAPRG4
ADS1625IPAPT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PAP
64
64
64
64
64
64
64
64
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
PAP
PAP
PAP
PAP
PAP
PAP
PAP
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS1625IPAPTG4
ADS1626IPAPR
ADS1626IPAPRG4
ADS1626IPAPT
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS1626IPAPTG4
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
(mm)
24
ADS1625IPAPR
ADS1625IPAPT
ADS1626IPAPR
ADS1626IPAPT
PAP
PAP
PAP
PAP
64
64
64
64
SITE 60
SITE 60
SITE 60
SITE 60
13.0
13.0
13.0
13.0
13.0
13.0
13.0
13.0
1.4
1.4
1.4
1.4
16
16
16
16
24
24
24
24
Q2
Q2
Q2
Q2
24
24
24
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
ADS1625IPAPR
ADS1625IPAPT
ADS1626IPAPR
ADS1626IPAPT
PAP
PAP
PAP
PAP
64
64
64
64
SITE 60
SITE 60
SITE 60
SITE 60
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
Pack Materials-Page 2
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