ADS4449IZCRT_技术文档

ADS4449

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SBAS603 –APRIL 2013

Quad-Channel, 14-Bit, 250-MSPS, Low-Power ADC

Check for Samples: ADS4449

1

FEATURES

DESCRIPTION

The ADS4449 is a high-linearity, quad-channel, 14-

bit, 250-MSPS, analog-to-digital converter (ADC).

The four ADC channels are separated into two blocks

with two ADCs each. Designed for low power

consumption and high spurious-free dynamic range

(SFDR), the device has low-noise performance and

outstanding SFDR over a large input frequency

range.

2

•

Quad Channel

14-Bit Resolution

Maximum Sampling Data Rate: 250 MSPS

Power Dissipation:

–

365 mW per Channel

•

Spectral Performance at 170-MHz IF (typ):

–

SNR: 69 dBFS

SFDR: 86 dBc

•

DDR LVDS Digital Output Interface

Package: 144-Pin BGA (10-mm × 10-mm)

APPLICATIONS

•

Multi-Carrier GSM Cellular Infrastructure Base

Stations

•

RADAR and Smart Antenna Arrays

Multi-Carrier Multi-Mode Cellular Infrastructure

Base Stations

•

Active Antenna Arrays for Wireless

Infrastructures

Communications Test Equipment

0

DAB0P, DAB0M or

OVRABP, OVRABM

F_IN= 170 MHz

SFDR = 89 dBc

SNR = 69 dBFS

AINP,

AINM

14-Bit

ADC

14

DAB[13:1]P,

DAB[13:1]M

Digital

Block

−20

SINAD = 68.9 dBFS

CLKOUTABP,

CLKOUTABM

THD = 85 dBc

BINP,

BINM

14-Bit

ADC

−40

Output

Formatter

CLKINP,

CLKINM

DDR

LVDS

−60

−80

CINP,

CINM

14-Bit

ADC

DCD0P, DCD0M or

OVRCDP, OVRCDM

Digital

Block

DINP,

DINM

14-Bit

ADC

14

DCD[13:1]P,

DCD[13:1]M

−100

−120

CLKOUTCDP,

CLKOUTCDM

Common

Mode

VCM

Configuration Registers

0

25

50

75

100

125

Frequency (MHz)

G005

Figure 1. Spectrum For 170-MHz Input Frequency

Figure 2. Basic Block Diagram

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS4449

SBAS603 –APRIL 2013

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE AND ORDERING INFORMATION⁽¹⁾

PACKAGE

DESIGNATOR

SPECIFIED TEMPERATURE

RANGE

PRODUCT

PACKAGE-LEAD

ADS4449

BGA-144

ZCR

–40°C to +85°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

VALUE

–0.3 to +3.6

UNIT

V

AVDD33

Supply voltage range

Voltage between

AVDD

–0.3 to +2.1

V

DRVDD

–0.3 to +2.1

V

AVSS and DRVSS

AVDD and DRVDD

AVDD33 and DRVDD

AVDD33 and AVDD

XINP, XINM

CLKP, CLKM⁽²⁾

RESET, SCLK, SDATA, SEN, PDN

Operating free-air, T_A

Operating junction, T_J

Storage, T_stg

–0.3 to +0.3

V

–2.4 to +2.4

V

–2.4 to +3.9

V

–2.4 to +3.9

V

–0.3 to minimum (1.9, AVDD + 0.3)

–0.3 to +3.9

V

Voltage applied to input pins

Temperature

V

–40 to +85

°C

+150

–65 to +150

Electrostatic discharge (ESD)

rating

Human body model (HBM)

2

kV

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP and CLKM is less than

| 0.3 V |). This recommendation prevents the ESD protection diodes at the clock input pins from turning on.

2

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THERMAL INFORMATION

ADS4449

ZCR (BGA)

144 PINS

35.9

THERMAL METRIC⁽¹⁾

UNITS

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

5.1

12.6

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

12.4

θ_JCbot

N/A

SPACER

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

UNIT

SUPPLIES

AVDD33

AVDD

3.15

1.8

3.3

1.9

1.8

3.45

2.0

V

Supply voltage

DRVDD

1.7

2.0

ANALOG INPUTS

Differential input voltage range

2

V_PP

V

Input common-mode voltage

V_CM± 0.025

Analog input common-mode current (per input pin of each channel)

VCM current capability

1.5

5

µA/MSPS

mA

2-V_PPinput amplitude⁽¹⁾

400

500

MHz

Maximum analog input frequency

1.4-V_PPinput amplitude

MHz

CLOCK INPUTS

Input clock sample rate

184

0.2

250

MSPS

V_PP

Sine wave, ac-coupled

LVPECL, ac-coupled

1.5

1.6

V_PP

Input clock amplitude differential

(V_CLKP– V_CLKM

)

LVDS, ac-coupled

0.7

V_PP

LVCMOS, single-ended, ac-coupled

1.8

V_PP

Input clock duty cycle

DIGITAL OUTPUTS

40%

50%

60%

Maximum external load capacitance from each output pin to DRVSS

(default strength)

C_LOAD

3.3

pF

R_LOAD

Differential load resistance between the LVDS output pairs (LVDS mode)

100

Ω

TEMPERATURE RANGE

T_A

Operating free-air temperature

–40

+85

+105

+125

°C

Recommended

Maximum rated⁽²⁾

T_J

Operating junction temperature

(1) See the Theory of Operation section.

(2) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.

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SPECIAL PERFORMANCE MODES

Best performance can be achieved by writing certain modes depending upon source impedance, band of

operation and sampling speed. Table 1 summarizes the different these modes.

Table 1. High-Performance Modes Summary⁽¹⁾

SPECIAL MODES SUMMARY

INPUT FREQUENCIES

(Up to 125 MHz)

INPUT FREQUENCIES

(> 125 MHz)

SPECIAL MODE NAME

ADDRESS (Hex)

DATA (Hex)

High-frequency mode

F1

58

70

88

A0

20

Not required

Optional

Must

Optional

High SNR mode⁽²⁾

(1) See the Serial Interface Registers section for details.

(2) High SNR mode improves SNR typically by 1 dB at 170 MHz input frequency. See the Using High SNR Mode Register Settings section.

ELECTRICAL CHARACTERISTICS

Typical values are at T_A= +25°C, full temperature range is T_MIN= –40°C to T_MAX= +85°C, ADC clock frequency = 250 MHz,

50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

RESOLUTION

Default resolution

ANALOG INPUTS

14

Bits

Differential input full-scale

Common mode input voltage

Input resistance, differential

Input capacitance, differential

2

1.15

700

3.3

V_PP

V

VCM

R_IN

At 170-MHz input frequency

Ω

C_IN

pF

With a 50-Ω source driving the ADC

analog inputs

Analog input bandwidth, 3 dB

500

MHz

DYNAMIC ACCURACY

E_O

Offset error

Specified across devices and channels

Specified across channels within a device

–15

–5

15

5

mV

As a result of internal

reference inaccuracy

alone

%FS

E_G

Gain error⁽¹⁾

Of channel alone

±0.2

%FS

Channel gain error temperature coefficient⁽¹⁾

0.001

Δ%/°C

POWER SUPPLY⁽²⁾

I_AVDD33

3.3-V analog supply

1.9-V analog supply

1.8-V digital supply

Total

51

350

355

1.47

400

6

mA

W

I_AVDD

Supply current

I_DRVDD

P_TOTAL

1.6

52

P_{DISS(standby)}Power dissipation

P_DISS(global)

Standby

mW

Global power-down

(1) There are two sources of gain error: internal reference inaccuracy and channel gain error.

(2) A 185-MHz, full-scale, sine-wave input signal is applied to all four channels.

4

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ELECTRICAL CHARACTERISTICS (continued)

Typical values are at T_A= +25°C, full temperature range is T_MIN= –40°C to T_MAX= +85°C, ADC clock frequency = 250 MHz,

50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

DYNAMIC AC CHARACTERISTICS⁽³⁾

f_IN= 40 MHz

71.1

71

dBFS

dBc

f_IN= 70 MHz

f_IN= 140 MHz

f_IN= 170 MHz

f_IN= 220 MHz

f_IN= 307 MHz

f_IN= 350 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 140 MHz

f_IN= 170 MHz

f_IN= 220 MHz

f_IN= 307 MHz

f_IN= 350 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 140 MHz

f_IN= 170 MHz

f_IN= 220 MHz

f_IN= 307 MHz

f_IN= 350 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 140 MHz

f_IN= 170 MHz

f_IN= 220 MHz

f_IN= 307 MHz

f_IN= 350 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 140 MHz

f_IN= 170 MHz

f_IN= 220 MHz

f_IN= 307 MHz

f_IN= 350 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 140 MHz

f_IN= 170 MHz

f_IN= 220 MHz

f_IN= 307 MHz

f_IN= 350 MHz

69.5

69

SNR

Signal-to-noise ratio

67.5

68.5

67.5

67

70.9

70.8

69.3

68.8

68.3

66.8

66.3

84

SINAD

SFDR

THD

Signal-to-noise and distortion ratio

Spurious-free dynamic range

Total harmonic distortion

66.9

78.5

75

87

dBc

85

dBc

86

dBc

84

dBc

78

dBc

77

dBc

83

dBc

84

dBc

82

dBc

83

dBc

82

dBc

76

dBc

75

dBc

96

dBc

87

dBc

86

dBc

HD2

Second-order harmonic distortion⁽⁴⁾

78.5

86

dBc

84

dBc

78

dBc

77

dBc

83

dBc

89

dBc

85

dBc

HD3

Third-order harmonic distortion

79.5

86

dBc

85

dBc

80

dBc

78

dBc

(3) Phase and amplitude imbalances onboard must be minimized to obtain good performance.

(4) The minimum value across temperature is ensured by bench characterization.

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ELECTRICAL CHARACTERISTICS (continued)

Typical values are at T_A= +25°C, full temperature range is T_MIN= –40°C to T_MAX= +85°C, ADC clock frequency = 250 MHz,

50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

DYNAMIC AC CHARACTERISTICS (continued)

f_IN= 40 MHz

100

95

dBc

LSBs

f_IN= 70 MHz

f_IN= 140 MHz

f_IN= 170 MHz

f_IN= 220 MHz,

f_IN= 307 MHz

f_IN= 350 MHz

Worst spur

(non HD2, HD3)

87

95

85

DNL

INL

Differential nonlinearity

Integral nonlinearity

-0.95

±0.5

±1.5

±5.25

LSBs

Recovery to within 1% (of final value) for

6-dB output overload with sine-wave input

Clock

cycle

Input overload recovery

1

With a full-scale, 220-MHz signal on

aggressor channel and no signal on victim

channel

Crosstalk

90

dB

PSRR

AC power-supply rejection ratio

For 50-mV_PPsignal on AVDD supply

< 30

DIGITAL CHARACTERISTICS

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level '0' or '1'. AVDD33 = 3.3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS⁽¹⁾(RESET, SCLK, SDATA, SEN, PDN)

All digital inputs support 1.8-V logic

levels. SPI supports 3.3-V logic levels.

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.25

V

All digital inputs support 1.8-V logic

levels. SPI supports 3.3-V logic levels.

0.45

RESET, SCLK, PDN pins V_HIGH= 1.8 V

10

0

µA

High-level input

current

I_IH

SEN⁽²⁾pin

V_HIGH= 1.8 V

RESET, SCLK, PDN pins V_LOW= 0 V

SEN pin V_LOW= 0 V

0

Low-level input

current

I_IL

10

DIGITAL OUTPUTS (SDOUT)

DRVDD –

0.1

V_OH

V_OL

High-level output voltage

Low-level output voltage

DRVDD

0

V

0.1

DIGITAL OUTPUTS, LVDS INTERFACE

(DAB[13:0]P, DAB[13:0]M, DCD[13:0]P, DCD[13:0]M, CLKOUTABP, CLKOUTABM, CLKOUTCDP, CLKOUTCDM)

V_ODH

V_ODL

V_OCM

High⁽³⁾

Standard-swing LVDS

270

350

–350

1.05

465

mV

V

Output differential

voltage

Low

–465

–270

Output common-mode voltage

(1) RESET, SDATA, and SCLK have an internal 150-kΩ pull-down resistor.

(2) SEN has an internal 150-kΩ pull-up resistor to DRVDD.

(3) With an external 100-Ω termination.

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TIMING REQUIREMENTS⁽¹⁾

Typical values are at +25°C, AVDD33 = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, sine-wave input clock, C_LOAD= 3.3 pF⁽²⁾, and

R_LOAD= 100 Ω⁽³⁾, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ns

t_A

Aperture delay

0.7

1.2

1.6

Aperture delay matching

Between any two channels of the same device

±70

ps

Between two devices at the same temperature and

DRVDD supply

Variation of aperture delay

Aperture jitter

±150

140

ps

fs rms

µs

t_J

Time to valid data after coming out of global power

down

100

Wake up time

Time to valid data after coming out of channel power

down

10

13

14

µs

Output clock

cycles

Default latency in 14-bit mode

Digital gain enabled

Output clock

cycles

ADC latency⁽⁴⁾⁽⁵⁾

Output clock

cycles

Digital gain and offset correction enabled

OUTPUT TIMING⁽⁶⁾

t_SU

Data setup time^(7)(8)(9)

t_H

Data valid to CLKOUTxxP zero-crossing

0.6

0.85

0.84

ns

Data hold time^(7)(8)(9)

CLKOUTxxP zero-crossing to data becoming invalid

Differential clock duty cycle (CLKOUTxxP –

CLKOUTxxM)

LVDS bit clock duty cycle

50%

Input clock falling edge cross-over to output clock

t_PDI

Clock propagation delay⁽⁵⁾falling edge cross-over, 184 MSPS ≤ sampling

frequency ≤ 250 MSPS

0.25 × t_S+ t_delay

ns

Input clock falling edge cross-over to output clock

t_delay

Delay time

falling edge cross-over, 184 MSPS ≤ sampling

frequency ≤ 250 MSPS

6.9

8.65

10.5

t_RISE

t_FALL

,

Data rise and fall time

Rise time measured from –100 mV to +100 mV

0.1

ns

t_CLKRISE

t_CLKFALL

,

Output clock rise and fall

time

(1) Timing parameters are ensured by design and characterization and are not tested in production.

(2) C_LOADis the effective external single-ended load capacitance between each output pin and ground.

(3) R_LOADis the differential load resistance between the LVDS output pair.

(4) ADC latency is given for channels B and D. For channels A and C, latency reduces by half of the output clock cycles.

(5) Overall latency = ADC latency + t_PDI

.

(6) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time

specifications take into account the effect of jitter on the output data and clock.

(7) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

(8) Note that these numbers are taken with delayed output clocks by writing the following registers: address A9h, value 02h; and address

ACh, value 60h. Refer to the Serial Interface Registers section. By default after reset, minimum setup time and minimum hold times are

520 ps each.

(9) The setup and hold times of a channel are measured with respect to the same channel output clock.

Table 2. LVDS Timings Across Lower Sampling Frequencies

SETUP TIME (ns)

HOLD TIME (ns)

SAMPLING FREQUENCY

(MSPS)

MIN

0.89

1.06

TYP

1.03

1.21

MAX

MIN

0.82

0.95

TYP

1.01

1.15

MAX

210

185

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PARAMETRIC MEASUREMENT INFORMATION

LVDS OUTPUT TIMING

Figure 3 shows a timing diagram of the LVDS output voltage levels. Figure 4 shows the latency described in the

Timing Requirements table.

DxnP

Logic 0

V_ODL

Logic 1

V_ODH

DxnM

V_OCM

GND

Figure 3. LVDS Output Voltage Levels

N+12

N+3

N+4

N+11

N+2

N+1

N+10

Sample

N

Input

Signal

t_A

CLKINM

CLKINP

Input

Clock

CLKOUTABM

(CLKOUTCDM)

CLKOUTABP

(CLKOUTCDP)

10 Clock Cycles

DDR

LVDS

t_PDI

Output Data

DABP, DABM

(DCDP, DCDM)

Ch B

Ch A

Ch B

Ch A

Ch B

Ch A

Ch B

Ch A

Ch B

Ch A

Ch B

Ch A

Ch B

Ch A

Ch B

Ch A

Ch B

Ch A

(Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C)

(Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C)

N

N+1

N-1

N-10

N-9

N-8

N-7

Figure 4. Latency Timing

8

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PARAMETRIC MEASUREMENT INFORMATION (continued)

All 14 data bits of one channel are included in the digital output interface at the same time, as shown in Figure 5.

Channel A and C data are output on the rising edge of the output clock while channels B and D are output on the

falling edge of the output clock.

CLKOUTABM

CLKOUTABP

DAB[13:0]P,

DAB[13:0]M

DA[13:0]P,

DA[13:0]M

DB[13:0]P,

DB[13:0]M

DA[13:0]P,

DA[13:0]M

DB[13:0]P,

DB[13:0]M

DA[13:0]P,

DA[13:0]M

DB[13:0]P,

DB[13:0]M

Sample N

Sample N + 1

Sample N + 2

CLKOUTCDM

CLKOUTCDP

DCD[13:0]P,

DCD[13:0]M

DC[13:0]P,

DC[13:0]M

DD[13:0]P,

DD[13:0]M

DC[13:0]P,

DC[13:0]M

DD[13:0]P,

DD[13:0]M

DC[13:0]P,

DC[13:0]M

DD[13:0]P,

DD[13:0]M

Sample N

Sample N + 1

Sample N + 2

Figure 5. LVDS Output Interface Timing

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PIN CONFIGURATION

ZCR PACKAGE

BGA-144

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

AVDD

AVSS

CINM

CINP

AVDD

VCM

AVDD

BINM

BINP

AVDD

A

B

C

D

E

F

DINP

AVDD

AVSS

VCM

NC

AVDD

AVSS

DRVSS

NC

AVSS

AVDD33

CLKINM

AVSS

AVDD33

CLKINP

AVSS

AVDD

AVSS

AVDD

AVSS

AINM

AINP

DINM

AVSS

AVDD

AVSS

VCM

AVDD

AVDD33

DCD13M

DCD12M

DCD11M

DCD10M

DCD9M

DCD8M

DCD7M

AVDD33

DCD13P

DCD12P

DCD11P

DCD10P

DCD9P

DCD8P

DCD7P

DRVSS

NC

DRVSS

RESET

DRVDD

DRVSS

SCLK

DRVSS

SDATA

DRVDD

DAB2M

DAB2P

DRVSS

SEN

PDN

AVDD33

DAB13P

DAB12P

DAB11P

DAB10P

DAB9P

DAB8P

DAB7P

AVDD33

DAB13M

DAB12M

DAB11M

DAB10M

DAB9M

DAB8M

DAB7M

DRVDD

SDOUT

DAB6P

DAB5P

DAB4P

DAB3P

NC

G

H

J

DCD6P

DCD5P

DCD4P

DCD3P

DCD6M

DCD5M

DCD4M

DCD3M

DRVDD

DCD2P

DCD2M

DRVDD

DAB6M

DAB5M

DAB4M

DAB3M

K

L

DCD1P

DCD0P/

DCD1M

DCD0M/

DAB1M

DAB0M/

DAB1P

DAB0P/

CLKOUT

CDP

CLKOUT

CDM

CLKOUT

ABM

CLKOUT

ABP

M

OVRCDP OVRCDM OVRABM OVRABP

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PIN FUNCTIONS

I/O

DESCRIPTION

NAME

NUMBER

B12

AINM

AINP

I

Negative differential analog input for channel A

Positive differential analog input for channel A

Analog 3.3-V power supply

C12

AVDD33

B6, B7, E1, E2, E11, E12

A1, A2, A5, A8, A11, A12,

B3, B4, B9, B10, D1, D2,

D11, D12

AVDD

AVSS

I

Analog 1.9-V power supply

Analog ground

B2, B5, B8, B11, C2-C5,

C8-C11, D4-D9

BINM

BINP

A9

A10

A3

I

Negative differential analog input for channel B

Positive differential analog input for channel B

Negative differential analog input for channel C

Positive differential analog input for channel C

Negative differential clock input

CINM

I

CINP

A4

I

CLKINM

C6

I

CLKINP

C7

I

Positive differential clock input

CLKOUTABM

CLKOUTABP

CLKOUTCDM

CLKOUTCDP

M9

M10

M4

M3

O

Negative differential LVDS clock output for channel A and B

Positive differential LVDS clock output for channel A and B

Negative differential LVDS clock output for channels C and D

Positive differential LVDS clock output for channels C and D

DAB[13:1]P,

DAB0P/OVRABP,

DAB[13:1]M,

F11, F12, G11, G12,

H9-H12, J8-J12, K8-K12,

L7-L12, M7, M8, M11, M12

O

DDR LVDS outputs for channels A and B.

DDR LVDS outputs for channels C and D.

DAB0M/OVRABM

DCD[13:1]P,

DCD0P/OVRCDP,

DCD[13:1]M,

F1, F2, G1, G2, H1-H4,

J1-J5, K1-K5, L1-L6, M1,

M2, M5, M6

DCD0M/OVRCDM

DINM

DINP

C1

B1

I

Negative differential analog input for channel D

Positive differential analog input for channel D

F3, F10, H5-H8, J6, J7, K6,

K7

DRVDD

I

Digital 1.8-V power supply

DRVSS

NC

E4-E9, F4-F9

I

-

Digital ground

E3, G3, G4, G5

Do not connect

PDN

E10

I

Power-down control; active high. Logic high is power down.

Hardware reset; active high

Serial interface clock input

Serial interface data input

Serial interface data output

Serial interface enable

RESET

SCLK

SDATA

SDOUT

SEN

G6

I

G7

I

G8

G10

I

O

I

G9

VCM

A6, A7, D3, D10

O

Common-mode voltage for analog inputs. All VCM pins are internally connected together.

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FUNCTIONAL BLOCK DIAGRAM

DAB0P, DAB0M or

OVRABP, OVRABM

AINP,

AINM

14-Bit

ADC

14

DAB[13:1]P,

DAB[13:1]M

Digital

Block

CLKOUTABP,

CLKOUTABM

BINP,

BINM

14-Bit

ADC

Output

Formatter

CLKINP,

CLKINM

DDR

LVDS

CINP,

CINM

14-Bit

ADC

DCD0P, DCD0M or

OVRCDP, OVRCDM

Digital

Block

DINP,

DINM

14-Bit

ADC

14

DCD[13:1]P,

DCD[13:1]M

CLKOUTCDP,

CLKOUTCDM

Common

Mode

VCM

Configuration Registers

12

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TYPICAL CHARACTERISTICS

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

0

F_IN= 40 MHz

F_IN= 70 MHz

SFDR = 84 dBc

SNR = 71.1 dBFS

SINAD = 70.9 dBFS

THD = 84 dBc

SFDR = 87 dBc

SNR = 70.9 dBFS

SINAD = 70.8 dBFS

THD = 84 dBc

−20

−40

−60

−80

−100

−120

−100

−120

0

25

50

75

100

125

0

25

50

75

100

125

Frequency (MHz)

G001

G002

Figure 6. FFT FOR 40-MHz INPUT SIGNAL

Figure 7. FFT FOR 70-MHz INPUT SIGNAL

0

−20

0

−20

F_IN= 100 MHz

F_IN= 140 MHz

SFDR = 85 dBc

SNR = 70.2 dBFS

SINAD = 70.1 dBFS

THD = 84 dBc

SFDR = 87 dBc

SNR = 69.7 dBFS

SINAD = 69.6 dBFS

THD = 84 dBc

−40

−60

−80

−100

−120

−100

−120

0

25

50

75

100

125

0

25

50

75

100

125

Frequency (MHz)

G003

G004

Figure 8. FFT FOR 100-MHz INPUT SIGNAL

Figure 9. FFT FOR 140-MHz INPUT SIGNAL

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

0

F_IN= 170 MHz

F_IN= 230 MHz

SFDR = 89 dBc

SNR = 69 dBFS

SINAD = 68.9 dBFS

THD = 85 dBc

SFDR = 86 dBc

SNR = 68.6 dBFS

SINAD = 68.5 dBFS

THD = 84 dBc

−20

−40

−60

−80

−100

−120

−100

−120

0

25

50

75

100

125

0

25

50

75

100

125

Frequency (MHz)

G005

G006

Figure 10. FFT FOR 170-MHz INPUT SIGNAL

Figure 11. FFT FOR 230-MHz INPUT SIGNAL

0

−20

0

−20

Each Tone at

−7 dBFS Amplitude

f_IN1= 45 MHz

f_IN2= 50 MHz

Each Tone at

−36 dBFS Amplitude

f_IN1= 45 MHz

f_IN2= 50 MHz

2−Tone IMD = 87 dBFS

SFDR = 92 dBFS

2−Tone IMD = 99 dBFS

SFDR = 99 dBFS

−40

−60

−80

−100

−120

−100

−120

0

25

50

75

100

125

0

25

50

75

100

125

Frequency (MHz)

G007

G008

Figure 12. FFT FOR TWO-TONE INPUT SIGNAL

(–7 dBFS)

Figure 13. FFT FOR TWO-TONE INPUT SIGNAL

(–36 dBFS)

14

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

0

Each Tone at

−7 dBFS Amplitude

f_IN1= 185.1 MHz

f_IN2= 190.1 MHz

−36 dBFS Amplitude

f_IN1= 185.1 MHz

f_IN2= 190.1 MHz

−20

2−Tone IMD = 97 dBFS

SFDR = 102 dBFS

2−Tone IMD = 101 dBFS

SFDR = 100 dBFS

−40

−60

−80

−100

−120

−100

−120

0

25

50

75

100

125

0

25

50

75

100

125

Frequency (MHz)

G009

G010

Figure 14. FFT FOR TWO-TONE INPUT SIGNAL

(–7 dBFS)

Figure 15. FFT FOR TWO-TONE INPUT SIGNAL

(–36 dBFS)

25

20

15

10

5

93

91

Input Frequency = 170 MHz

Temperature = −40 C

Temperature = 25 C

Temperature = 85 C

88

85

82

79

76

73

70

0

40

80

120 160 200 240 280 320 360 400

Input Frequency (MHz)

HD2 (dBc)

G011

G039

Figure 16. SPURIOUS-FREE DYNAMIC RANGE

vs INPUT FREQUENCY

Figure 17. HD2 DISTRIBUTION OVER MULTIPLE DEVICES

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

72

71

70

69

68

67

66

65

104

100

96

92

88

84

80

76

72

68

64

40 MHz

100 MHz

130 MHz

170 MHz

230 MHz

300 MHz

350 MHz

400 MHz

450 MHz

40

80

120 160 200 240 280 320 360 400

Input Frequency (MHz)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

Digital Gain (dB)

G012

G013

Figure 18. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY

Figure 19. SPURIOUS-FREE DYNAMIC RANGE

vs DIGITAL GAIN

75.5

130

120

110

100

90

74

Input Frequency = 70 MHz

SNR(dBFS)

SFDR(dBc)

SFDR(dBFS)

40 MHz

100 MHz

130 MHz

170 MHz

230 MHz

300 MHz

350 MHz

400 MHz

450 MHz

75

74.5

74

73

72

71

70

69

68

67

66

65

64

63

62

73.5

73

80

72.5

72

70

60

71.5

71

50

40

70.5

30

70

−70

20

−60

−50

−40

−30

−20

−10

0

Amplitude (dBFS)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

G015

Digital Gain (dB)

G014

Figure 20. SIGNAL-TO-NOISE RATIO vs DIGITAL GAIN

Figure 21. PERFORMANCE vs INPUT AMPLITUDE

16

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

120

110

100

90

74

94

92

90

88

86

84

82

80

78

72

Input Frequency = 185 MHz

73.5

73

71.5

71

72.5

72

70.5

70

80

70

71.5

71

60

69.5

69

50

70.5

70

40

SFDR (dBc)

SFDR (dBFS)

SNR

68.5

30

69.5

69

SFDR

SNR

20

−50

68

1.3

−40

−30

−20

−10

0

0.7

0.8

0.9

1

1.1

1.2

Amplitude (dBFS)

Input Common−Mode Voltage (V)

G016

G017

Figure 22. PERFORMANCE vs INPUT AMPLITUDE

Figure 23. PERFORMANCE vs

INPUT COMMON-MODE VOLTAGE

90

89

88

87

86

85

84

83

71

70.5

70

Input Frequency = 185 MHz

69.5

69

DRVDD = 1.7 V

DRVDD = 1.8 V

DRVDD = 1.9 V

DRVDD = 2 V

DRVDD = 1.7 V

DRVDD = 1.8 V

DRVDD = 1.9 V

DRVDD = 2 V

68.5

68

−40

−15

10

35

60

85

−40

−15

10

35

60

85

Temperature (°C)

G018

G019

Figure 24. SPURIOUS-FREE DYNAMIC RANGE vs

DRVDD SUPPLY AND TEMPERATURE

Figure 25. SIGNAL-TO-NOISE RATIO vs

DRVDD SUPPLY AND TEMPERATURE

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

90

89

88

87

86

85

84

83

82

71

70.5

70

Input Frequency = 185 MHz

69.5

69

68.5

68

AVDD = 1.8 V

AVDD = 1.9 V

AVDD = 2 V

AVDD = 1.8 V

AVDD = 1.9 V

AVDD = 2 V

−40

−15

10

35

60

85

−40

−15

10

35

60

85

Temperature (°C)

G020

G021

Figure 26. SPURIOUS-FREE DYNAMIC RANGE vs

AVDD SUPPLY AND TEMPERATURE

Figure 27. SIGNAL-TO-NOISE RATIO vs

AVDD SUPPLY AND TEMPERATURE

90

89

88

87

86

85

84

83

82

71

70.5

70

Input Frequency = 185 MHz

69.5

69

68.5

68

AVDD3V = 3.15 V

AVDD3V = 3.3 V

AVDD3V = 3.45 V

AVDD3V = 3.15 V

AVDD3V = 3.3 V

AVDD3V = 3.45 V

−40

−15

10

35

60

85

−40

−15

10

35

60

85

Temperature (°C)

G022

G023

Figure 28. SPURIOUS-FREE DYNAMIC RANGE vs

AVDD3V SUPPLY AND TEMPERATURE

Figure 29. SIGNAL-TO-NOISE RATIO vs

AVDD3V SUPPLY AND TEMPERATURE

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

100

98

96

94

92

90

88

86

84

82

80

78

76

71

92

91

90

89

88

87

86

85

84

83

82

72

Input Frequency = 185 MHz

70.5

70

71.5

71

69.5

69

70.5

70

68.5

68

69.5

69

67.5

67

68.5

68

66.5

66

67.5

67

SFDR

SNR

THD

65.5

65

0.2

0.5

0.8

1.1

1.4

1.7

2

2.3

25

30

35

40

45

50

55

60

65

70

75

Differential Clock Amplitudes (Vpp)

Input Clock Duty Cycle (%)

G024

G025

Figure 30. PERFORMANCE vs CLOCK AMPLITUDE

Figure 31. PERFORMANCE vs CLOCK DUTY CYCLE

0

Input Frequency = 185 MHz

F_IN= 185 MHz

−5

50−mV_PPSignal Superimposed on VCM

F_CM= 10 MHz, 50−mV_PP

SFDR = 76 dBc

−10

−15

−20

−25

−30

−35

−40

−45

−50

−55

−60

−20

Amlpitude(F_IN) = −1 dBFS

Amlpitude(F_CM) = −95 dBFS

Amplitude

F_IN+ F_CM= −77.2 dBFS

Amplitude

−40

F_IN− F_CM= −80.9 dBFS

−60

−80

−100

−120

0

50

100

150

200

250

300

0

25

50

75

100

125

Frequency of Input Common−Mode Signal (MHz)

Frequency (MHz)

G026

G027

Figure 32. COMMON-MODE REJECTION RATIO SPECTRUM

Figure 33. COMMON-MODE REJECTION RATIO vs

TEST SIGNAL FREQUENCY

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

−20

−25

−30

−35

−40

−45

−50

−55

−60

−65

−70

0

F_IN= 10 MHz

PSRR on AVDD Supply

PSRR on AVDD3V Supply

F_PSRR= 2 MHz, 50−mV_PP

Amlpitude(F_IN) = −1 dBFS

Amlpitude(F_PSRR) = −87 dBFS

Amplitude

F_IN+ F_PSRR= −60.6 dBFS

Amplitude

−20

−40

F_IN− F_PSRR= −60 dBFS

−60

−80

−100

−120

Input Frequency = 10 MHz

50−mV_PPSignal Superimposed on Supply

0

50

100

150

200

250

300

0

10

20

30

40

50

Frequency of Signal on Supply (MHz)

Frequency (MHz)

G028

G029

Figure 34. POWER-SUPPLY REJECTION RATIO

SPECTRUM FOR AVDD

Figure 35. POWER-SUPPLY REJECTION RATIO vs

TEST SIGNAL FREQUENCY

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

800

700

600

500

400

300

200

100

0

Input Frequency = 185 MHz

AVDD Power

AVDD3V Power

DRVDD Power

Input Frequency = 185 MHz

1

26

51

76 101 126 151 176 201 226 250

Sampling Speed (MSPS)

1

26

51

76 101 126 151 176 201 226 250

Sampling Speed (MSPS)

G030

G031

Figure 36. TOTAL POWER vs SAMPLING FREQUENCY

Figure 37. POWER BREAKUP vs SAMPLING FREQUENCY

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

250

87

83

70

80

75

240

230

220

210

200

190

87

91

87

83

70

80

75

95

91

87

75

83 80

70

91

87

50

100

150

200

250

300

350

400

450

Input Frequency, MHz

70

75

80

85

90

95

Figure 38. SPURIOUS-FREE DYNAMIC RANGE

(0-dB Gain)

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

250

90

88

86

79

82

84

76

240

230

220

210

200

190

90

88 86

84

82

79

76

90

84

88

86

82

79

76

50

74

100

76

150

200

250

300

350

400

450

Input Frequency, MHz

78

80

82

84

86

88

90

Figure 39. SPURIOUS-FREE DYNAMIC RANGE

(6-dB Gain)

22

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

250

66.5

68.5

67.5

69.8

69.4

70.2

68

69

67

66

240

230

220

210

200

190

70.6

65.5

69.4

68.5

66.5

69.8

67.5

70.2

66

69

68

67

69.8

69.4

68.5

69

67.5

66.5

70.2

66

67

68

50

100

150

200

250

300

350

400

450

Input Frequency, MHz

66

67

68

69

70

Figure 40. SIGNAL-TO-NOISE RATIO

(0-dB Gain)

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and

32k-point FFT, unless otherwise noted.

250

64.5

64.1

63.7

240

230

220

210

200

190

63.3

64.9

62.

62.9

64.7

64.5

64.1

63.7

64.9

63.3

64.7

62.9

64.7

64.5

63.3

62.9

64.613.7

64.5

62.5

50

100

150

200

250

300

350

400

450

Input Frequency, MHz

62.5

63

63.5

64

64.5

Figure 41. SIGNAL-TO-NOISE RATIO

(6-dB Gain)

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DEVICE CONFIGURATION

The ADS4449 can be configured with a serial programming interface (SPI), as described in the Serial Interface

section. In addition, the device has control pins that control power-down.

SERIAL INTERFACE

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), SDATA (serial interface input data), and SDOUT (serial interface

readback data) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data (SDATA) are

latched at every SCLK falling edge when SEN is active (low). Serial data are loaded into the register at every

16th SCLK falling edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits

are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits

form the register address and the remaining eight bits are the register data. The interface can function with SCLK

frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be

accomplished in one of two ways:

1. Either through a hardware reset by applying a high pulse on the RESET pin (of widths greater than 10 ns),

as shown in Figure 42; or

2. By applying a software reset. When using the serial interface, set the RESET bit (D1 in register 00h) high.

This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In

this case, the RESET pin is kept low.

Register Address

Register Data

SDATA

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

t_SLOADS

t_SLOADH

SEN

RESET

Figure 42. Serial Interface Timing

Table 3. Timing Characteristics for Figure 42

PARAMETER

SCLK frequency (equal to 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDI setup time

MIN

> dc

25

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

)

20

25

ns

25

ns

t_DH

SDI hold time

25

ns

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Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back, as shown in

Figure 43. This readback mode can be useful as a diagnostic check to verify the serial interface communication

between the external controller and ADC.

1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers except register

address 00h.

2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read.

3. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin (pin G10).

4. The external controller can latch the contents at the SCLK falling edge.

5. To enable register writes, reset the READOUT register bit to '0'.

Note that the contents of register 00h cannot be read back because the register contains RESET and READOUT

bits. When the READOUT bit is disabled, the SDOUT pin is in a high-impedance state. If serial readout is not

used, the SDOUT pin must not be connected (must float).

Register Address A[7:0] = 00h

A4 A2

A5 A3

Register Data D[7:0] = 01h

D4 D2

D5 D3

SDATA

A7

A6

A1

A0

D7

D6

D1

D0

SCLK

SEN

The SDOUT pin is in a high-impedance state (READOUT = 0).

SDOUT

a) Enable serial readout (READOUT = 1)

Register Address A[7:0] = 45h

A4 A2

A5 A3

Register Data D[7:0] = XX (don’t care)

D4 D2 D1

D6 D5 D3

SDATA

SCLK

A7

A6

A1

A0

D7

D0

SEN

0

1

0

SDOUT

The SDOUT pin functions as a serial readout (READOUT = 1).

b) Read contents of Register 45h. This register is initialized with 04h.

Figure 43. Serial Readout Timing Diagram

SDOUT comes out at the SCLK rising edge with an approximate delay (t_{SD_DELAY}) of 8 ns, as shown in Figure 44.

SCLK

t_{SD_DELAY}

SDOUT

Figure 44. SDOUT Delay Timing

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SERIAL INTERFACE REGISTERS

Table 4 summarizes the ADS4449 registers.

Table 4. Register Map

REGISTER

ADDRESS

REGISTER DATA

A[7:0] (Hex)

D7

D6

D5

D4

D3

D2

D1

RESET

0

D0

READOUT

0

00

01

0

LVDS SWING

DIGITAL GAIN

BYPASS CH B

25

2B

31

37

3D

DIGITAL GAIN CH B

TEST PATTERN CH B

TEST PATTERN CH A

TEST PATTERN CH D

TEST PATTERN CH C

0

DIGITAL GAIN

BYPASS CH A

DIGITAL GAIN CH A

DIGITAL GAIN CH D

DIGITAL GAIN CH C

DIGITAL GAIN

BYPASS CH D

DIGITAL GAIN

BYPASS CH C

OFFSET CORR

0

EN1

3F

40

42

CUSTOM PATTERN[13:8]

CUSTOM PATTERN[7:0]

0

DIGITAL ENABLE

SEL OVR

0

GLOBAL POWER

DOWN

45

A9

AC

C3

C4

DIS OVR ON LSB

0

CONFIG PDN PIN

CLOCKOUT DELAY PROG CH AB

ALWAYS WRITE

1

CLOCKOUT DELAY PROG CH CD

FAST OVR THRESH PROG

0

EN FAST OVR

THRESH

0

OFFSET CORR

EN2

CF

D6

D7

F1

58

59

70

71

88

89

A0

0

ALWAYS WRITE

1

0

ALWAYS WRITE

1

ALWAYS WRITE

1

0

HIGH FREQ

MODE

0

ENABLE LVDS SWING PROG

HIGH SNR MODE

CH A

0

ALWAYS WRITE

1

0

HIGH SNR MODE

CH B

0

ALWAYS WRITE

1

0

HIGH SNR MODE

CH D

0

ALWAYS WRITE

1

0

HIGH SNR MODE

CH C

0

ALWAYS WRITE

1

A1

FE

0

PDN CH D

PDN CH C

PDN CH A

PDN CH B

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DESCRIPTION OF SERIAL REGISTERS

Register Address 00h (Default = 00h)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

D0

RESET

READOUT

Bits D[7:2]

Bit D1

Always write '0'

RESET: Software reset applied

This bit resets all internal registers to the default values and self-clears to '0'.

READOUT: Serial readout

Bit D0

This bit sets the serial readout of the registers.

0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance

state. (default)

1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with

CMOS logic levels running from the DRVDD supply.

Register Address 01h (Default = 00h)

D7

D6

D5

D4

D3

D2

D1

0

D0

0

LVDS SWING

Bits D[7:2]

LVDS SWING: LVDS swing programmability

These bits program the LVDS swing only after the ENABLE LVDS SWING PROG bits

are set to '11'.

000000 = Default LVDS swing; ±350 mV with an external 100-Ω termination (default)

011011 = ±420-mV LVDS swing with an external 100-Ω termination

110010 = ±470-mV LVDS swing with an external 100-Ω termination

010100 = ±560-mV LVDS swing with an external 100-Ω termination

001111 = ±160-mV LVDS swing with an external 100-Ω termination

Bits D[1:0]

Always write '0'

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Register Address 25h (Default = 00h)

D7

D6

D5

D4

D3

D2

D1

TEST PATTERN CH B

D0

DIGITAL GAIN CH B

DIGITAL GAIN BYPASS CH B

Bits D[7:4]

DIGITAL GAIN CH B: Channel B digital gain programmability

These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for

channel B. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.

0000 = 0-dB gain (default)

0001 = 0.5-dB gain

0010 = 1-dB gain

0011 = 1.5-dB gain

0100 = 2-dB gain

0101 = 2.5-dB gain

0110 = 3-dB gain

0111 = 3.5-dB gain

1000 = 4-dB gain

1001 = 4.5-dB gain

1010 = 5-dB gain

1011 = 5.5-dB gain

1100 = 6-dB gain

Bit D3

DIGITAL GAIN BYPASS CH B: Channel B digital gain bypass

0 = Normal operation (default)

1 = Digital gain feature for channel B is bypassed

Bits D[2:0]

TEST PATTERN CH B: Channel B test pattern programmability

These bits program the test pattern for channel B.

000 = Normal operation (default)

001 = Outputs all 0s

010 = Outputs all 1s

011 = Outputs toggle pattern

Output data ([D:0]) are an alternating sequence of 01010101010101 and

10101010101010.

100 = Outputs digital ramp

Output data increments by one 14-bit LSB every clock cycle from code 0 to code

16383

101 = Outputs custom pattern

To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh

and 40h.

110 = Unused

111 = Unused

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Register Address 2Bh (Default = 00h)

D7

D6

D5

D4

D3

D2

D1

TEST PATTERN CH A

D0

DIGITAL GAIN CH A

DIGITAL GAIN BYPASS CH A

Bits D[7:4]

DIGITAL GAIN CH A: Channel A digital gain programmability

These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for

channel A. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.

0000 = 0-dB gain (default)

0001 = 0.5-dB gain

0010 = 1-dB gain

0011 = 1.5-dB gain

0100 = 2-dB gain

0101 = 2.5-dB gain

0110 = 3-dB gain

0111 = 3.5-dB gain

1000 = 4-dB gain

1001 = 4.5-dB gain

1010 = 5-dB gain

1011 = 5.5-dB gain

1100 = 6-dB gain

Bit D3

DIGITAL GAIN BYPASS CH A: Channel A digital gain bypass

0 = Normal operation (default)

1 = Digital gain feature for channel A is bypassed

Bits D[2:0]

TEST PATTERN CH A: Channel A test pattern programmability

These bits program the test pattern for channel A.

000 = Normal operation (default)

001 = Outputs all 0s

010 = Outputs all 1s

011 = Outputs toggle pattern

Output data ([D:0]) are an alternating sequence of 01010101010101 and

10101010101010.

100 = Outputs digital ramp

Output data increments by one 14-bit LSB every clock cycle from code 0 to code

16383

101 = Outputs custom pattern

To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh

and 40h.

110 = Unused

111 = Unused

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Register Address 31h (Default = 00h)

D7

D6

D5

D4

D3

D2

D1

TEST PATTERN CH D

D0

DIGITAL GAIN CH D

DIGITAL GAIN BYPASS CH D

Bits D[7:4]

DIGITAL GAIN CH D: Channel D digital gain programmability

These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for

channel D. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.

0000 = 0-dB gain (default)

0001 = 0.5-dB gain

0010 = 1-dB gain

0011 = 1.5-dB gain

0100 = 2-dB gain

0101 = 2.5-dB gain

0110 = 3-dB gain

0111 = 3.5-dB gain

1000 = 4-dB gain

1001 = 4.5-dB gain

1010 = 5-dB gain

1011 = 5.5-dB gain

1100 = 6-dB gain

Bit D3

DIGITAL GAIN BYPASS CH D: Channel D digital gain bypass

0 = Normal operation (default)

1 = Digital gain feature for channel A is bypassed

Bits D[2:0]

TEST PATTERN CH D: Channel D test pattern programmability

These bits program the test pattern for channel D.

000 = Normal operation (default)

001 = Outputs all 0s

010 = Outputs all 1s

011 = Outputs toggle pattern

Output data ([D:0]) are an alternating sequence of 01010101010101 and

10101010101010.

100 = Outputs digital ramp

Output data increments by one 14-bit LSB every clock cycle from code 0 to code

16383

101 = Outputs custom pattern

To program test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh and

40h.

110 = Unused

111 = Unused

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Register Address 37h (Default = 00h)

D7

D6

D5

D4

D3

D2

D1

TEST PATTERN CH C

D0

DIGITAL GAIN CH C

DIGITAL GAIN BYPASS CH C

Bits D[7:4]

DIGITAL GAIN CH C: Channel C digital gain programmability

These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for

channel C. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.

0000 = 0-dB gain (default)

0001 = 0.5-dB gain

0010 = 1-dB gain

0011 = 1.5-dB gain

0100 = 2-dB gain

0101 = 2.5-dB gain

0110 = 3-dB gain

0111 = 3.5-dB gain

1000 = 4-dB gain

1001 = 4.5-dB gain

1010 = 5-dB gain

1011 = 5.5-dB gain

1100 = 6-dB gain

Bit D3

DIGITAL GAIN BYPASS CH C: Channel C digital gain bypass

0 = Normal operation (default)

1 = Digital gain feature for channel A is bypassed

Bits D[2:0]

TEST PATTERN CH C: Channel C test pattern programmability

These bits program the test pattern for channel C.

000 = Normal operation (default)

001 = Outputs all 0s

010 = Outputs all 1s

011 = Outputs toggle pattern

Output data ([D:0]) are an alternating sequence of 01010101010101 and

10101010101010.

100 = Outputs digital ramp

Output data increments by one 14-bit LSB every clock cycle from code 0 to code

16383

101 = Outputs custom pattern

To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh

and 40h.

110 = Unused

111 = Unused

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Register Address 3Dh (Default = 00h)

D7

0

D6

0

D5

D4

0

D3

0

D2

0

D1

0

D0

0

OFFSET CORR EN1

Bits D[7:6]

Bit D5

Always write '0'

OFFSET CORR EN1: Offset correction setting

This bit enables the offset correction feature for all four channels after the DIGITAL

ENABLE bit is set to ‘1,’ correcting mid-code to 8191. In addition, write the OFFSET

CORR EN2 bit (register CFh, value 08h) for proper operation of the offset correction

feature.

0 = Offset correction disabled (default)

1 = Offset correction enabled

Bits D[4:0]

Always write '0'

Register Address 3Fh (Default = 00h)

D7

0

D6

0

D5

D4

D3

D2

D1

D0

CUSTOM

PATTERN D13

CUSTOM

PATTERN D12

CUSTOM

PATTERN D11

CUSTOM

PATTERN D10

CUSTOM

PATTERN D9

CUSTOM

PATTERN D8

Bits D[7:6]

Always write '0'

CUSTOM PATTERN D[13:8]

Set the custom pattern using these bits for all four channels.

Register Address 40h (Default = 00h)

Bits D[5:0]

D7

D6

D5

D4

D3

D2

D1

D0

CUSTOM

PATTERN D7

PATTERN D6

PATTERN D5

PATTERN D4

PATTERN D3

PATTERN D2

PATTERN D1

PATTERN D0

Bits D[7:0]

CUSTOM PATTERN D[7:0]

Set the custom pattern using these bits for all four channels.

Register Address 42h (Default = 00h)

D7

0

D6

0

D5

0

D4

0

D3

D2

0

D1

0

D0

0

DIGITAL ENABLE

Bits D[7:4]

Bit D3

Always write '0'

DIGITAL ENABLE

1 = Digital gain and offset correction features disabled

1 = Digital gain and offset correction features enabled

Bits D[2:0]

Always write '0'

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Register Address 45h (Default = 00h)

D7

0

D6

0

D5

0

D4

D3

D2

D1

0

D0

DIS OVR

ON LSB

SEL OVR

GLOBAL POWER DOWN

CONFIG PDN PIN

Bits D[7:5]

Bit D4

Always write '0'

DIS OVR ON LSB

0 = Effective ADC resolution is 13 bits (the LSB of a 14-bit output is OVR) (default)

1 = ADC resolution is 14 bits

Bit D3

Bit D2

SEL OVR: OVR selection

0 = Fast OVR selected (default)

1 = Normal OVR selected. See the Overrange Indication (OVRxx) section for details.

GLOBAL POWER DOWN

0 = Normal operation (default)

1 = Global power down. All ADC channels, internal references, and output buffers are

powered down. Wakeup time from this mode is slow (100 µs).

Bit D1

Bit D0

Always write '0'

CONFIG PDN PIN

Use this bit to configure PDN pin.

0 = The PDN pin functions as a standby pin. All channels are put in standby. Wake-up

time from standby mode is fast (10 µs). (default)

1 = The PDN pin functions as a global power-down pin. All ADC channels, internal

references, and output buffers are powered down. Wake-up time from global power

mode is slow (100 µs).

Register Address A9h (Default = 00h)

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

CLOCKOUT DELAY PROG CH AB

Bits D[7:4]

Bits D[6:3]

Always write '0'

CLOCKOUT DELAY PROG CH AB

These bits program the clock out delay for channels A and B, see Table 5.

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Register Address ACh (Default = 00h)

D7

0

D6

D5

D4

D3

D2

0

D1

0

D0

ALWAYS

WRITE 1

CLOCKOUT DELAY PROG CH CD

Bit D7

Always write '0'

CLOCKOUT DELAY PROG CH CD

Bits D[7:4]

These bits program the clock out delay for channels C and D, as shown in Table 5.

Bits D[2:1]

Bit D[0]

Always write '0'

Always write '1'

This bit is set to 0 by default. User must set it to 1 after reset or power-up.

Table 5. Clock Out Delay Programmability for All Channels

CLOCKOUT DELAY PROG CHxx

DELAY (ps)

0 (default)

–30

0000 (default)

0001

0010

70

0011

30

0100

–150

–180

–70

0101

0110

0111

–110

270

1000

1001

230

1010

340

1011

300

1100

140

1101

110

1110

200

1111

170

Register Address C3h (Default = 00h)

D7

D6

D5

D4

D3

D2

D1

D0

FAST OVR THRESH PROG

Bits D[7:0]

FAST OVR THRESH PROG

The ADS4449 has a fast OVR mode that indicates an overload condition at the ADC

input. The input voltage level at which the overload is detected is referred to as the

threshold and is programmable using the FAST OVR THRESH PROG bits.

FAST OVR is triggered seven output clock cycles after the overload condition occurs. To

enable the FAST OVR programmability, enable the EN FAST OVR THRESH register bit.

The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the

FAST OVR THRESH PROG bits] / 255).

After reset, when EN FAST OVR THRESH PROG is set, the default value of the FAST

OVR THRESH PROG bits is 230 (decimal).

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Register Address C4h (Default = 00h)

D7

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

EN FAST OVR THRESH

Bit D7

EN FAST OVR THRESH

This bit enables the ADS4449 to be programmed to select the fast OVR threshold.

Bits D[6:0]

Always write '0'

Register Address CFh (Default = 00h)

D7

0

D6

0

D5

0

D4

0

D3

D2

0

D1

0

D0

0

OFFSET CORR EN2

Bits D[7:4]

Bit D3

Always write '0'

OFFSET CORR EN2

This bit must be set to ‘1’ when the OFFSET CORR EN1 bit is selected.

Bits D[2:0]

Always write '0'

Register Address D6h (Default = 00h)

D7

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

ALWAYS

WRITE 1

Bits D[7]

Always write '1'

This bit is set to 0 by default. User must set it to 1 after reset or power-up.

Bits D[6:0]

Always write '0'

Register Address D7h (Default = 00h)

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

0

D0

0

ALWAYS

WRITE 1

ALWAYS WRITE 1

Bits D[7:4], Bits

D[1:0]

Always write '0'

Bits D[3]

Always write '1'

This bit is set to 0 by default. User must set it to 1 after reset or power-up.

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Register Address F1h (Default = 00h)

D7

0

D6

0

D5

D4

0

D3

0

D2

D1

D0

HIGH FREQ MODE

ENABLE LVDS SWING PROG

Bits D[7:6]

Bit D5

Always write '0'

HIGH FREQ MODE

0 = Default (default)

1 = Use for input frequencies > 125 MHz

Bits D[4:3]

Bits D[2:0]

Always write '0'

ENABLE LVDS SWING PROG

This bit enables the LVDS swing control with the LVDS SWING bits.

00 = LVDS swing control disabled (default)

01 = Do not use

10 = Do not use

11 = LVDS swing control enabled

Register Address 58h (Default = 00h)

D7

0

D6

0

D5

D4

0

D3

0

D2

0

D1

0

D0

0

HIGH SNR

MODE CH A

Bits D[7:6], Bits

D[4:0]

Always write '0'

Bit D5

HIGH SNR MODE CH A

See the Using High SNR MODE Register Settings section.

Register Address 59h (Default = 00h)

D7

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

ALWAYS

WRITE 1

Bits D[7]

Always write '1'

This bit is set to 0 by default. User must set it to 1 after reset or power-up.

Bits D[6:0]

Always write '0'

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Register Address 70h (Default = 00h)

D7

0

D6

0

D5

D4

0

D3

0

D2

0

D1

0

D0

0

HIGH SNR

MODE CH B

Bits D[7:6], Bits

D[4:0]

Always write '0'

Bit D5

HIGH SNR MODE CH B

See the Using High SNR MODE Register Settings section.

Register Address 71h (Default = 00h)

D7

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

ALWAYS

WRITE 1

Bits D[7]

Always write '1'

This bit is set to 0 by default. User must set it to 1 after reset or power-up.

Bits D[6:0]

Always write '0'

Register Address 88h (Default = 00h)

D7

0

D6

0

D5

D4

0

D3

0

D2

0

D1

0

D0

0

HIGH SNR

MODE CH D

Bits D[7:6], Bits

D[4:0]

Always write '0'

Bit D5

HIGH SNR MODE CH D

See the Using High SNR MODE Register Settings section.

Register Address 89h (Default = 00h)

D7

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

ALWAYS

WRITE 1

Bits D[7]

Always write '1'

This bit is set to 0 by default. User must set it to 1 after reset or power-up.

Bits D[6:0]

Always write '0'

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Register Address A0h (Default = 00h)

D7

0

D6

0

D5

D4

0

D3

0

D2

0

D1

0

D0

0

HIGH SNR

MODE CH C

Bits D[7:6], Bits

D[4:0]

Always write '0'

Bit D5

HIGH SNR MODE CH C

See the Using High SNR MODE Register Settings section.

Register Address A1h (Default = 00h)

D7

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

ALWAYS

WRITE 1

Bits D[7]

Always write '1'

This bit is set to 0 by default. User must set it to 1 after reset or power-up.

Bits D[6:0]

Always write '0'

Register Address FEh (Default = 00h)

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

PDN CH D

PDN CH C

PDN CH A

PDN CH B

Bits D[7:4]

Bit D3

Always write '0'

PDN CH D: Power-down channel D

Channel D is powered down.

Bit D2

Bit D1

Bit D0

PDN CH C: Power-down channel C

Channel C is powered down.

PDN CH B: Power-down channel B

Channel B is powered down.

PDN CH A: Power-down channel A

Channel A is powered down.

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APPLICATION INFORMATION

THEORY OF OPERATION

The ADS4449 is a quad-channel, 14-bit, analog-to-digital converter (ADC) with sampling rates up to

250 MSPS. At every falling edge of the input clock, the analog input signal for each channel is sampled

simultaneously. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each

stage, the sampled-and-held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference

(residue) between the stage input and quantized equivalent is gained and propagates to the next stage. At every

clock, each subsequent stage resolves the sampled input with greater accuracy. The digital outputs from all

stages are combined in a digital correction logic block and are digitally processed to create the final code, after a

data latency of 10 clock cycles. The digital output is available in a double data rate (DDR) low-voltage differential

signaling (LVDS) interface and is coded in binary twos complement format.

ENABLING 14-BIT RESOLUTION

By default after reset, the ADS4449 outputs 11-bit data on the Dxx13P, Dxx13M and Dxx3P, Dxx3M pins and

OVR information on the Dxx0P, Dxx0M pins. When the ALWAYS WRITE 1 bits are set, the ADC outputs 13-bit

data on the Dxx13P, Dxx13M and Dxx1P, Dxx1M pins and OVR information on the Dxx0P, Dxx0M pins. To

enable 14-bit resolution, the DIS OVR ON LSB register bit must be set to '1' as indicated in Table 6.

Table 6. ADC configuration

DATA ON ADC PINS

ALWAYS WRITE 1 = 1

DIS OVR ON LSB = 1

ADC PIN NAMES

AFTER RESET

ALWAYS WRITE 1 = 1

Dxx13

—

D13

—

D13

—

D13

—

Dxx3

Dxx2

Dxx1

Dxx0

D3

D2

D1

D0

Logic 0

Logic 1

OVR

D2

D1

OVR

11-bit data (D[13:3]) and OVR come

on ADC output pins

13-bit data (D[13:1]) and OVR come

on ADC output pins

14-bit data comes on ADC output

pins

Comments

ANALOG INPUT

The analog input consists of a switched-capacitor-based differential sample-and-hold architecture. This

differential topology results in very good ac performance even for high input frequencies at high sampling rates.

The INP and INM pins must be externally biased around a common-mode voltage of 1.15 V, available on the

VCM pin. For a full-scale differential input, each input pin (INP, INM) must swing symmetrically between VCM +

0.5 V and VCM – 0.5 V, resulting in a 2-V_PPdifferential input swing.

The input sampling circuit has a high 3-dB bandwidth that extends up to 500 MHz when a 50-Ω source drives the

ADC analog inputs.

Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This configuration improves the

common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each

input pin is recommended to damp out ringing caused by package parasitics.

Spurious-free dynamic range (SFDR) performance can be limited because of several reasons (such as the effect

of sampling glitches, sampling circuit nonlinearity, and quantizer nonlinearity that follows the sampling circuit).

Depending on the input frequency, sampling rate, and input amplitude, one of these metrics plays a dominant

part in limiting performance. At very high input frequencies, SFDR is determined largely by the device sampling

circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity typically limits performance.

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Glitches are caused by opening and closing the sampling switches. The driving circuit should present a low

source impedance to absorb these glitches, otherwise these glitches may limit performance. A low impedance

path between the analog input pins and VCM is required from the common-mode switching currents perspective

as well. This impedance can be achieved by using two resistors from each input terminated to the common-mode

voltage (VCM).

The ADS4449 includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the

sampling glitches inside the device itself. The R-C component values are also optimized to support high input

bandwidth (up to 500 MHz). However, using an external R-LC-R filter (refer to Figure 48, Figure 49, Figure 50,

Figure 51, and Figure 55) improves glitch filtering, thus further resulting in better performance.

In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency

range and matched source impedance. In doing so, the ADC input impedance must be considered. Figure 45,

Figure 46, and Figure 47 show the impedance (Z_IN= R_IN|| C_IN) at the ADC input pins.

XINP⁽¹⁾

(2)

R_IN

C_IN

Z_IN

XINM⁽¹⁾

(1) X = A, B, C, or D.

(2) Z_IN= R_IN|| (1 / jωC_IN).

Figure 45. ADC Equivalent Input Impedance

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

6

5

4

3

2

1

100

200

300

400

500

0

100

200

300

400

500

Frequency (MHz)

G037

Frequency (MHz)

G038

Figure 46. ADC Analog Input Resistance (R_IN) vs

Frequency

Figure 47. ADC Analog Input Capacitance (C_IN) vs

Frequency

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Driving Circuit

Two example driving circuits with a 50-Ω source impedance are shown in Figure 48 and Figure 49. The driving

circuit in Figure 48 is optimized for input frequencies in the second Nyquist zone (centered at 185 MHz), whereas

the circuit in Figure 49 is optimized for input frequencies in third Nyquist zone (centered at 310 MHz).

Note that both drive circuits are terminated by 50 Ω near the ADC side. This termination is accomplished with a

25-Ω resistor from each input to the 1.15-V common-mode (VCM) from the device. This architecture allows the

analog inputs to be biased around the required common-mode voltage.

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order

harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and

good performance is obtained for high-frequency input signals.

T1

T2

0.1 mF

50 W

10 W

INP

25 W

Band-Pass Filter

Centered at

f₀= 185 MHz

R_IN

82 nH

C_IN

10 pF

0.1 mF

BW = 125 MHz

25 W

INM

10 W

0.1 mF

1:1

VCM

Device

Figure 48. Driving Circuit for a 50-Ω Source Impedance and Input Frequencies

in the Second Nyquist Zone

T1

T2

0.1 mF

50 W

10 W

INP

25 W

Band-Pass Filter

Centered at

f₀= 310 MHz

R_IN

27 nH

C_IN

10 pF

0.1 mF

BW = 125 MHz

25 W

INM

10 W

0.1 mF

1:1

VCM

Device

Figure 49. Driving Circuit for a 50-Ω Source Impedance and Input Frequencies

in the Third Nyquist Zone

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TI recommends terminating the drive circuit by a 50-Ω (or lower) impedance near the ADC for best performance.

However, in some applications higher impedances be required to terminate the drive circuit. Two example driving

circuits with 100-Ω differential termination are shown in Figure 50 and Figure 51. In these example circuits, the

1:2 transformer (T1) is used to transform the 50-Ω source impedance into a differential 100 Ω at the input of the

band-pass filter. In Figure 50, the parallel combination of two 68-Ω resistors and one 120-nH inductor and two

100-Ω resistors is used (100 Ω is the effective impedance in pass-band) for better performance.

T1

0.1 mF

T2

50 W

10 W

INP

68 W

25 W

100 W

Band-Pass Filter

Centered at

f₀= 185 MHz

120 nH

R_IN

82 nH

C_IN

10 pF

0.1 mF

BW = 125 MHz

68 W

25 W

10 W

INM

0.1 mF

1:2

1:1

VCM

Device

Figure 50. Driving Circuit for a 100-Ω Source Impedance and Input Frequencies

in the Second Nyquist Zone

T1

0.1 mF

T2

50 W

10 W

INP

25 W

50 W

Band-Pass Filter

Centered at

f₀= 310 MHz

R_IN

27 nH

C_IN

10 pF

0.1 mF

BW = 125 MHz

25 W

10 W

INM

0.1 mF

1:2

1:1

VCM

Device

Figure 51. Driving Circuit for a 100-Ω Source Impedance and Input Frequencies

in the Third Nyquist Zone

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Using High SNR Mode Register Settings

The HIGH SNR MODE register settings can be used to further improve the SNR. However, there is a trade off

between improved SNR and degraded THD when these settings are used. These settings shut down the internal

spectrum-cleaning algorithm, resulting in THD performance degradation. Figure 52 and Figure 53 show the effect

of using HIGH SNR MODE. SNR improves by approximately 1 dB and THD degrades by 3 dB.

0

F_IN= 170 MHz

SFDR = 93 dBc

SNR = 69.1 dBFS

SINAD = 69 dBFS

THD = 89 dBc

SFDR = 89 dBc

SNR = 70.1 dBFS

SINAD = 70 dBFS

THD = 86 dBc

−20

−40

−60

−80

−100

−120

−100

−120

0

25

50

75

100

125

0

25

50

75

100

125

Frequency (MHz)

G036

G037

Figure 52. FFT (Default) at 170 MHz

Figure 53. FFT with High SNR Mode at 170 MHz

Figure 54 shows SNR versus input frequency with and without these settings.

72

Default

HIGH SNR MODE Enable

71

70

69

68

67

66

65

64

40

90

140 190 240 290 340 390 440 490

Input Frequency (MHz)

G038

Figure 54. SNR vs Input Frequency with High SNR Mode

To obtain best performance, TI recommends keeping termination impedance between INP and INM low (for

instance, at 50 Ω differential). This setting helps absorb the kickback noise component of the spectrum-cleaning

algorithm. However, when higher termination impedances (such as 100 Ω) are required, shutting down the

spectrum-cleaning algorithm by using the HIGH SNR MODE register settings can be helpful.

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Input Common Mode

To ensure a low-noise, common-mode reference, the VCM pin should be filtered with a 0.1-µF, low-inductance

capacitor connected to ground. The VCM pin is designed to directly bias the ADC inputs (refer to Figure 48 to

Figure 51).

Each ADC input pin sinks a common-mode current of approximately 1.5 µA per MSPS of clock frequency. When

a differential amplifier is used to drive the ADC (with dc-coupling), ensure that the output common-mode of the

amplifier is within the acceptable input common-mode range of the ADC inputs (VCM ± 25 mV).

Clock Input

The ADS4449 clock inputs can be driven differentially with a sine, LVPECL, or LVDS source with little or no

difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using

internal 5-kΩ resistors, as shown in Figure 55. This setting allows the use of transformer-coupled drive circuits for

sine-wave clock or ac-coupling for LVPECL, LVDS, and LVCMOS clock sources (see Figure 56, Figure 57, and

Figure 58).

For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to common-

mode noise. TI recommends keeping the differential voltage between clock inputs less than 1.8 V_PPto obtain

best performance. A clock source with very low jitter is recommended for high input frequency sampling. Band-

pass filtering of the clock source can help reduce the effects of jitter. With a non-50% duty cycle clock input,

performance does not change.

Clock Buffer

L_PKG

~ 2 nH

20 Ω

CLKP

C_BOND

~ 1 pF

C_EQ

5 kΩ

R

ESR

~ 100 Ω

0.95V

5 kΩ

L

PKG

~ 2 nH

20 Ω

CLKM

C_BOND

~ 1 pF

R

ESR

~ 100 Ω

NOTE: C_EQis 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 55. Internal Clock Buffer

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0.1 mF

Z_O

0.1 mF

CLKP

Differential

Sine-Wave

Clock Input

R_T

0.1 mF

Typical LVDS

Clock Input

100 W

0.1 mF

Z_O

CLKM

(1) R_Tis the termination resistor (optional).

Figure 58. LVDS Clock Driving Circuit

Figure 56. Differential Sine-Wave Clock Driving

Circuit

0.1 mF

CLKP

0.1 mF

Z_O

CLKP

CMOS

Clock Input

150 W

VCM

Typical LVPECL

Clock Input

100 W

0.1 mF

CLKM

Z_O

CLKM

150 W

Figure 59. Typical LVCMOS Clock Driving Circuit

Figure 57. LVPECL Clock Driving Circuit

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Overrange Indication (OVRxx)

After reset, all serial interface register ALWAYS WRITE 1 bits must be set to '1'. Afterwards, 13-bit data are

output on the Dxx13P, Dxx13M to Dxx1P, Dxx1M pins and overrange information is output on the Dxx0P and

Dxx0M pins (where xx = channels A and B or channels C and D).

When the DIS OVR ON LSB bit is set to '1', 14-bit data are output on the Dxx13P, Dxx13M to Dxx0P, Dxx0M

pins without overrange information on the LSB bits.

The OVR timing diagram (13-bit data with OVR) is shown in Figure 60. In 14-bit mode, OVR is disabled by

setting the DIS OVR ON LSB bit to '1', as shown in Figure 61.

Register bits ALWAYS WRITE 1=1 & DIS OVR ON LSB=0

CLKOUTM

CLKOUTP

DA[13:1]P/M

DB[13:1]P/M

13-BIT OUTPUT

DA[13:1]P/M

OVR A

DB[13:1]P/M

OVR B

DA[13:1]P/M

OVR A

DB[13:1]P/M

OVR B

OVER-RANGE

INDICATOR

DAB0P, DAB0M

Sample N

Sample N+1

Figure 60. 13-Bit Data With OVR

Register bits ALWAYS WRITE 1=1 & DIS OVR ON LSB=1

CLKOUTM

CLKOUTP

DA[13:0]P/M

DB[13:0]P/M

14-BIT OUTPUT

DA[13:0]P/M

DB[13:0]P/M

DA[13:0]P/M

DB[13:0]P/M

Sample N

Sample N+1

Figure 61. 14-Bit Mode

Normal overrange indication (OVR) shows the event of the ADS4449 digital output being saturated when the

input signal exceeds the ADC full-scale range. Normal OVR has the same latency as digital output data.

However, an overrange event can be indicated earlier (than normal latency) by using the fast OVR mode. The

fast OVR mode (enabled by default) is triggered seven clock cycles after the overrange condition that occurred at

the ADC input. The fast OVR thresholds are programmable with the FAST OVR THRESH PROG bits (refer to

Table 4, register address C3h). At any time, either normal or fast OVR mode can be programmed on the Dxx0P

and Dxx0M pins.

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GAIN FOR SFDR AND SNR TRADE-OFF

The ADS4449 includes gain settings that can be used to obtain improved SFDR performance. The gain is

programmable from 0 dB to 6 dB (in 0.5-dB steps) using the DIGITAL GAIN CH X register bits. For each gain

setting, the analog input full-scale range scales proportionally, as shown in Table 7.

Table 7. Full-Scale Range Across Gains

GAIN (dB)

TYPE

FULL-SCALE (V_PP)

0

1

2

3

4

5

6

Default after reset

Fine, programmable

2

1.78

1.59

1.42

1.26

1.12

1

SFDR improvement is achieved at the expense of SNR; for each gain setting, SNR degrades by approximately

0.5 dB to 1 dB. SNR degradation is diminished at high input frequencies. As a result, fine gain is very useful at

high input frequencies because SFDR improvement is significant with marginal degradation in SNR. Therefore,

fine gain can be used to trade-off between SFDR and SNR.

After a reset, the gain function is disabled. To use fine gain:

•

First, program the DIGITAL ENABLE bits to enable digital functions.

This setting enables the gain for all four channels and places the device in a 0-dB gain mode.

For other gain settings, program the DIGITAL GAIN CH X register bits.

DIGITAL OUTPUT INFORMATION

The ADS4449 provides 14-bit digital data for each channel and two output clocks in LVDS mode. Output pins are

shared by a pair of channels that are accompanied by one dedicated output clock.

DDR LVDS Outputs

In the LVDS interface mode, the data bits and clock are output using LVDS levels. The data bits of two channels

are multiplexed and output on each LVDS differential pair of pins; see Figure 62 and Figure 63.

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CLKOUTxxP,

CLKOUTxxM

Dxx0P,

Dxx0M

Dxx1P,

Dxx1M

Dxx2P,

Dxx2M

14-Bit Output

Dxx12P,

Dxx12M

Dxx13P,

Dxx13M

Device

NOTE: xx = channels A and B or C and D.

Figure 62. DDR LVDS Interface

CLKOUTABM

CLKOUTABP

DAB[13:0]P,

DAB[13:0]M

DA[13:0]P,

DA[13:0]M

DB[13:0]P,

DB[13:0]M

DA[13:0]P,

DA[13:0]M

DB[13:0]P,

DB[13:0]M

DA[13:0]P,

DA[13:0]M

DB[13:0]P,

DB[13:0]M

Sample N

Sample N + 1

Sample N + 2

CLKOUTCDM

CLKOUTCDP

DCD[13:0]P,

DCD[13:0]M

DC[13:0]P,

DC[13:0]M

DD[13:0]P,

DD[13:0]M

DC[13:0]P,

DC[13:0]M

DD[13:0]P,

DD[13:0]M

DC[13:0]P,

DC[13:0]M

DD[13:0]P,

DD[13:0]M

Sample N

Sample N + 1

Sample N + 2

Figure 63. DDR LVDS Interface Timing Diagram

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LVDS Output Data and Clock Buffers

The equivalent circuit of each LVDS output buffer is shown in Figure 64. After reset, the buffer presents an

output impedance of 100 Ω to match with the external 100-Ω termination.

The V_DIFFvoltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.

The V_DIFFvoltage is programmable using the LVDS SWING register bits (refer to Table 4, register address 01h).

The buffer output impedance behaves similar to a source-side series termination. By absorbing reflections from

the receiver end, the source-side termination helps improve signal integrity.

V_DIFF(high)

High

Low

OUTP

OUTM

External

100-W Load

1.1 V

R_OUT

V_DIFF(low)

High

Low

Figure 64. LVDS Buffer Equivalent Circuit

Output Data Format

The ADS4449 transmits data in binary twos complement format. In the event of an input voltage overdrive, the

digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 3FFh. For a

negative input overdrive, the output code is 400h.

BOARD DESIGN CONSIDERATIONS

For evaluation module (EVM) board information, refer to the ADS4449 EVM User's Guide (SLAU455).

Grounding

A single ground plane is sufficient to provide good performance, as long as the analog, digital, and clock sections

of the board are cleanly partitioned. See the ADS4449 EVM User's Guide (SLAU455) for details on layout and

grounding.

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DEFINITION OF SPECIFICATIONS

Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with

respect to the low-frequency value.

Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at

which the sampling occurs. This delay is different across channels. The maximum variation is specified as an

aperture delay variation (channel-to-channel).

Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay.

Clock Pulse Width and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal

remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a

percentage. A perfect differential sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric

testing is performed at this sampling rate, unless otherwise noted.

Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1

LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.

Integral Nonlinearity (INL): INL is the deviation of the ADC transfer function from a best-fit line determined by a

least-squares curve fit of that transfer function, measured in units of LSBs.

Gain Error: Gain error is the deviation of the ADC actual input full-scale range from the ideal value. Gain error is

given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of

reference inaccuracy and error as a result of the channel. Both errors are specified independently as E_GREFand

E_GCHAN

To a first-order approximation, the total gain error of E_TOTALis approximately E_GREF+ E_GCHAN

For example, if E_TOTAL= ±0.5%, the full-scale input varies from (1 – 0.5 / 100) × f_{S ideal}to (1 + 0.5 / 100) × f_{S ideal}

.

Offset Error: Offset error is the difference, given in number of LSBs, between the ADC actual average idle

channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.

Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the

change per degree Celsius of the parameter from T_MINto T_MAX. The coefficient is calculated by dividing the

maximum deviation of the parameter across the T_MINto T_MAXrange by the difference of T_MAX– T_MIN

.

Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (P_S) to the noise floor power

(P_N), excluding the power at dc and the first nine harmonics.

P_S

SNR = 10Log¹⁰

P_N

(1)

SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-

scale range.

Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (P_S) to the power

of all other spectral components, including noise (P_N) and distortion (P_D) but excluding dc.

P_S

SINAD = 10Log¹⁰

P_N+ P_D

(2)

SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-

scale range.

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型号：	ADS4449IZCRT
厂家：	TEXAS INSTRUMENTS
描述：	Quad-Channel, 14-Bit, 250-MSPS, Low-Power ADC 四通道， 14位， 250 MSPS ，低功耗ADC
文件：	总54页 (文件大小：1544K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS4449IZCRT [TI]

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