ADS5272IPFPT [TI]
8-Channel, 12-Bit, 65MSPS ADC;![ADS5272IPFPT](http://pdffile.icpdf.com/pdf2/p00232/img/icpdf/ADS5272IPFPT_1363774_icpdf.jpg)
型号: | ADS5272IPFPT |
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描述: | 8-Channel, 12-Bit, 65MSPS ADC 转换器 |
文件: | 总32页 (文件大小:1501K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ADS5272
www.ti.com ...................................................................................................................................................... SBAS324C–JUNE 2004–REVISED JANUARY 2009
8-Channel, 12-Bit, 65MSPS ADC
with Serial LVDS Interface
An integrated phase lock loop (PLL) multiplies the
incoming ADC sampling clock by a factor of 12. This
1
FEATURES
23
•
Maximum Sample Rate: 65MSPS
high-frequency LVDS clock is used in the data
serialization and transmission process. The word
output of each internal ADC is serialized and
transmitted either MSB or LSB first. In addition to the
eight data outputs, a bit clock and a word clock are
also transmitted. The bit clock is at 6x the speed of
the sampling clock, whereas the word clock is at the
same speed of the sampling clock.
•
12-Bit Resolution
•
•
No Missing Codes
Total Power Dissipation:
Internal Reference: 983mW
External Reference: 917mW
•
•
•
•
•
•
•
•
•
•
CMOS Technology
Simultaneous Sample-and-Hold
71.1dBFS SNR at 5MHz IF
The ADS5272 provides internal references, or can
optionally be driven with external references. Best
performance is achieved through the internal
reference mode.
3.3V Digital/Analog Supply
Serialized LVDS Outputs
The device is available in a TQFP-80 PowerPAD
package and is specified over a –40°C to +85°C
operating range.
Integrated Frame and Bit Patterns
Option to Double LVDS Clock Output Currents
Four Current Modes for LVDS
Pin- and Format-Compatible Family
TQFP-80 PowerPAD™ Package
LCL KP
6x ADCLK
LCL KN
12x ADCL K
PLL
ADCLK P
ADCLK N
1x ADCLK
ADCLK
APPLICATIONS
IN1P
IN1N
OUT1P
OUT1N
12−Bit
ADC
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S erializer
S erializer
S erializer
S erializer
S erializer
S erializer
S erializer
•
•
•
•
Portable Ultrasound Systems
Tape Drives
Test Equipment
Optical Networking
IN2P
IN2N
OUT2P
OUT2N
12−Bit
ADC
IN3P
IN3N
OUT3P
OUT3N
12−Bit
ADC
DESCRIPTION
IN4P
IN4N
OUT4P
OUT4N
12−Bit
ADC
The ADS5272 is
a high-performance, 65MSPS,
IN5P
IN5N
OUT5P
OUT5N
8-channel analog-to-digital converter (ADC). Internal
references are provided, simplifying system design
requirements. Low power consumption allows for the
highest of system integration densities. Serial LVDS
(low-voltage differential signaling) outputs reduce the
number of interface lines and package size.
12−Bit
ADC
IN6P
IN6N
OUT6P
OUT6N
12−Bit
ADC
IN7P
IN7N
OUT7P
OUT7N
12−Bit
ADC
IN8P
IN8N
OUT8P
OUT8N
12−Bit
ADC
S erializer
Con trol
RELATED PRODUCTS
RESOLUTION
(BITS)
SAMPLE
RATE (MSPS) CHANNELS
Registers
Referen ce
IN T/EXT
MODEL
ADS5270
ADS5271
ADS5273
ADS5277
12
12
12
10
40
50
70
65
8
8
8
8
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2009, Texas Instruments Incorporated
ADS5272
SBAS324C–JUNE 2004–REVISED JANUARY 2009...................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT PACKAGE-LEAD(2)
ADS5272 HTQFP-80
ADS5272IPFP
Tray, 96
PFP
–40°C to +85°C
ADS5272IPFP
ADS5272IPFPT Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Thermal pad size: 4.69mm × 4.69mm (min), 6.20mm × 6.20mm (max).
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage Range, AVDD
–0.3V to +3.8V
–0.3V to +3.8V
Supply Voltage Range, LVDD
Voltage Between AVSS and LVSS
Voltage Between AVDD and LVDD
Voltage Applied to External REF Pins
All LVDS Data and Clock Outputs
Analog Input Pins(2)
–0.3V to +0.3V
–0.3V to +0.3V
–0.3V to +2.4V
–0.3V to +2.4V
–0.3V to min. [3.3V, (AVDD + 0.3V)]
–0.3V to min. [3.9V, (AVDD + 0.3V)](3)
–0.3V to min. [3.9V, (LVDD + 0.3V)](3)
–40°C to +85°C
Digital Input Pins, Set 1 (pins 69, 76-78)
Digital Input Pins, Set 2 (pins 16, 45)
Operating Free-Air Temperature Range, TA
Lead Temperature, 1.6mm (1/16" from case for 10s)
Junction Temperature
+260°C
+105°C
Storage Temperature Range
–65°C to +150°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) The dc voltage applied on the input pins should not go below –0.3V. Also, the dc voltage should be limited to the lower of either 3.3V or
(AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25Ω should be added in series with each
of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either
as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and
+3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed
1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
(3) It is recommended that a series resistor of 1kΩ or greater be used if the digital input pins are tied to AVDD or LVDD.
2
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Product Folder Link(s): ADS5272
ADS5272
www.ti.com ...................................................................................................................................................... SBAS324C–JUNE 2004–REVISED JANUARY 2009
RECOMMENDED OPERATING CONDITIONS
ADS5272
PARAMETER
MIN
TYP
MAX
UNITS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
REFT — External Reference Mode
REFB — External Reference Mode
REFCM = (REFT + REFB)/2 – External Reference Mode(1)
Reference = (REFT – REFB) – External Reference Mode
Analog Input Common-Mode Range(1)
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
ADCLK Duty Cycle
3.0
3.0
3.3
3.3
3.6
3.6
V
V
V
V
V
V
V
1.825
0.9
1.95
2.0
0.95
1.075
VCM ± 50mV
1.0
0.75
1.1
VCM ± 50mV
20
45
65
55
MSPS
%
Low-Level Voltage Clock Input
High-Level Voltage Clock Input
ADCLKP and ADCLKN Outputs (LVDS)
LCLKP and LCLKN Outputs (LVDS)(2)
Operating Free-Air Temperature, TA
Thermal Characteristics:
0.6
V
2.2
20
V
65
MHz
MHz
°C
120
–40
390
+85
θJA
19.4
4.2
°C/W
°C/W
θJC
(1) These voltages need to be set to 1.45V ± 50mV if they are derived independent of VCM
.
(2) 6 × ADCLK.
Copyright © 2004–2009, Texas Instruments Incorporated
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ADS5272
SBAS324C–JUNE 2004–REVISED JANUARY 2009...................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted. All values are applicable after the device has been reset.
ADS5272
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
No Missing Codes
Tested
±0.31
±0.41
DNL Differential Nonlinearity
INL Integral Nonlinearity
fIN = 5MHz
fIN = 5MHz
–0.95
–2.5
+1.0
+2.5
LSB
LSB
Offset Error(1)
–0.75
+0.75
%FS
ppm/°C
%FS
dB
Offset Temperature Coefficient
Fixed Attenuation in Channel(2)
Fixed Attenuation Matching Across Channels
Gain Error/Reference Error(3)
Gain Error Temperature Coefficient
POWER REQUIREMENTS(4)
Internal Reference
±6
1.5
0.01
±1.0
±20
0.2
VREFT – VREFB
–2.5
+2.5
%FS
ppm/°C
Power Dissipation
Analog Only (AVDD)
Output Driver (LVDD)
785
198
983
848
224
mW
mW
mW
Total Power Dissipation
External Reference
1072
Power Dissipation
Analog Only (AVDD)
Output Driver (LVDD)
719
198
917
94
mW
mW
mW
mW
Total Power Dissipation
Total Power-Down
Clock Running
149
REFERENCE VOLTAGES
VREFT Reference Top (internal)
VREFB Reference Bottom (internal)
VCM Common-Mode Voltage
VCM Output Current(5)
1.9
0.9
1.4
1.95
0.95
2.0
1.0
1.5
V
V
1.45
V
±50mV Change in Voltage
±2.0
mA
V
VREFT Reference Top (external)
VREFB Reference Bottom (external)
External Reference Common-Mode
External Reference Input Current(6)
1.825
0.9
1.95
2.0
0.95
1.075
V
VCM ± 50mV
1.0
V
mA
(1) Offset error is the deviation of the average code from mid-code with –1dBFS sinusoid from ideal mid-code (2048). Offset error is
expressed in terms of % of full-scale.
(2) Fixed attenuation in the channel arises due to a fixed attenuation in the sample-and-hold amplifier. When the differential voltage at the
analog input pins are changed from –VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code
(4096LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (REFT – REFB).
(3) The reference voltages are trimmed at production so that (VREFT – VREFB) is within ± 25mV of the ideal value of 1V. This specification
does not include fixed attenuation.
(4) Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.
(5) VCM provides the common-mode current for the inputs of all eight channels when the inputs are ac-coupled. The VCM output current
specified is the additional drive of the VCM buffer if loaded externally.
(6) Average current drawn from the reference pins in the external reference mode.
4
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ADS5272
www.ti.com ...................................................................................................................................................... SBAS324C–JUNE 2004–REVISED JANUARY 2009
ELECTRICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted. All values are applicable after the device has been reset.
ADS5272
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Differential Input Capacitance
4.0
VCM ± 50
2.03
pF
mV
Analog Input Common-Mode Range
Differential Full-Scale Input Voltage Range
Internal Reference
External Reference
VPP
2.03 × (VREFT – VREFB)
3.0
VPP
Voltage Overhead Recovery Time(7)
Input Bandwidth
CLK Cycles
–3dBFS, 25Ω Series
300
MHz
Resistances
DIGITAL DATA INPUTS
VIH High-Level Input Voltage
VIL Low-Level Input Voltage
CIN Input Capacitance
DIGITAL DATA OUTPUTS
Data Format
2.2
0.6
3.0
V
V
pF
Straight Offset Binary
Data Bit Rate
240
780
Mbps
MHz
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
20
(7) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the
full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the
ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value
when the pulse is switched from ON (high) to OFF (low).
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
Internal Reference; FSR = 2.03VPP
1
Default with internal pull-up.
Internal reference is powered down. The common-mode voltage of
the external reference should be within 50mV of VCM. VCM is
derived from the internal bandgap voltage.
External Reference; FSR = 2.03x (REFT – REFB)
0
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AC CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted.
ADS5272
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 5MHz
90
89
dBc
dBc
77
SFDR Spurious-Free Dynamic Range
HD2 2nd-Order Harmonic Distortion
HD3 3rd-Order Harmonic Distortion
SNR Signal-to-Noise Ratio
87
dBc
86
dBc
99
dBc
84
77
69
93
dBc
92
dBc
86
dBc
92
dBc
89
dBc
87
dBc
86
dBc
71.2
71.1
70.8
70
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
71.1
71
68.5
11.1
SINAD Signal-to-Noise and Distortion
70.7
69.9
11.5
ENOB Effective Number of Bits
Crosstalk
5MHz Full-Scale Signal Applied to 7 Channels;
Measurement Taken on the Channel with No Input Signal
–89
96
dBc
f1 = 9.5MHz at –7dBFS
f2 = 10.2MHz at –7dBFS
Two-Tone, Third-Order
IMD3
dBFS
Intermodulation Distortion
6
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ADS5272
www.ti.com ...................................................................................................................................................... SBAS324C–JUNE 2004–REVISED JANUARY 2009
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100Ω, CLOAD = 6pF, and 50% duty cycle. IO refers to the current setting for the LVDS buffer. RLOAD is
the differential load resistance between the differential LVDS pair. CLOAD is the effective single-ended load capacitance between each of the
LVDS pins and ground. CLOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are done with a 1-inch
transmission line of 100Ω characteristic impedance between the device and the load. All LVDS specifications are characterized, but not
parametrically tested at production. LCLKOUT refers to (LCLKP – LCLKN); ADCLKOUT refers to (ADCLKP – ADCLKN); DATA OUT refers to
(OUTP – OUTN); and ADCLK refers to the input sampling clock.
PARAMETER
DC SPECIFICATIONS(1)
CONDITIONS
MIN
TYP
MAX
UNITS
VOH Output Voltage High, OUTP or OUTN
VOL Output Voltage Low, OUTP or OUTN
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8
RLOAD = 100Ω ± 1%
1265
940
275
1.1
1365
1040
325
1.2
13
1465
1140
375
mV
mV
mV
V
|VOD
|
Output Differential Voltage
RLOAD = 100Ω ± 1%
VOS Output Offset Voltage(2)
RO Output Impedance, Differential
RO Output Impedance, Differential
CO Output Capacitance(3)
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8
Normal Operation
1.3
kΩ
kΩ
pF
Power-Down
20
4
|ΔVOD
|
Change in |VOD| Between 0 and 1
RLOAD = 100Ω ± 1%
RLOAD = 100Ω ± 1%
10
25
40
12
mV
mV
mA
mA
ΔVOS Change Between 0 and 1
ISOUT Output Short-Circuit Current
ISOUTNP Output Current
Drivers Shorted to Ground
Drivers Shorted Together
DRIVER AC SPECIFICATIONS
ADCLKOUT Clock Duty Cycle(4)
LCLKOUT Duty Cycle(4)
45
40
50
50
55
60
%
%
Data Setup Time(5)(6)
Data Hold Time(6)(7)
LVDS Outputs Rise/Fall Time(8)
0.4
0.25
ns
ns
ps
ps
ps
ps
ns
ns
ns
IO = 2.5mA
IO = 3.5mA
IO = 4.5mA
IO = 6.0mA
400
300
230
180
0.64
0.64
0
180
500
LCLKOUT Rising Edge to ADCLKOUT Rising Edge(9)
ADCLKOUT Rising Edge to LCLKOUT Falling Edge(9)
ADCLKOUT Rising Edge to DATA OUT Transition(9)
0.37
0.37
–0.3
0.9
0.9
+0.3
(1) The dc specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
(2) VOS refers to the common-mode of OUTP and OUTN.
(3) Output capacitance inside the device, from either OUTP or OUTN to ground.
(4) Measured between zero crossings.
(5) DATA OUT (OUTP – OUTN) crossing zero to LCLKOUT (LCLKP – LCLKN) crossing zero.
(6) Data setup and hold time accounts for data-dependent skews, channel-to-channel mismatches, as well as effects of clock jitter within
the device.
(7) LCLKOUT crossing zero to DATA OUT crossing zero.
(8) Measured from –100mV to +100mV on the differential output for rise time, and +100mV to –100mV for fall time.
(9) Measured between zero crossings.
SWITCHING CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
PARAMETER
SWITCHING SPECIFICATIONS
CONDITIONS
MIN
TYP
MAX
UNITS
tSAMPLE
tD(A) Aperture Delay(1)
15.4
2
50
ns
ns
4
6.5
Aperture Jitter (uncertainty)
tD(pipeline) Latency
tPROP Propagation Delay(2)
1
ps
6.5
4.8
Cycles
ns
3
6.5
(1) Rising edge of ADCLK to actual instant when data is sampled within the ADC.
(2) Falling edge of ADCLK to zero-crossing of rising edge of ADCLKOUT.
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LVDS TIMING DIAGRAM (PER ADC CHANNEL)
Sample n
Sample n + 6
Input
1
tSAMPLE
ADCLK
tS
2
LCLKP
6X ADCLK
LCLKN
OUTP
D10 D11
D0 D1
SERIAL DATA
OUTN
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Sample n data
ADCLKP
1X ADCLK
ADCLKN
tD(A)
tPROP
6.5 Clock Cycles
NOTE: Serial data bit format shown in LSB first mode.
RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING
AVDD (3V to 3.6V)
t1
AVDD
LVDD (3V to 3.6V)
t2
LVDD
Device Ready
For ADC Operation
t3
t4
t7
t5
t6
RESET
CS
Device Ready
For Serial Register Write
Device Ready
Start of Clock
For ADC Operation
ADCLK
t8
NOTE: 10 s < t1 < 50ms; 10 s < t2 < 50ms; 10ms < t3 < 10ms; t4 > 10ms; t5 > 100ns; t6 > 100ns; t7 > 10ms; and t8 > 100 s.
µ
µ
−
µ
8
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ADS5272
www.ti.com ...................................................................................................................................................... SBAS324C–JUNE 2004–REVISED JANUARY 2009
POWER-DOWN TIMING
µ
1 s
µ
500 s
PD
Device Fully
Powers Down
Device Fully
Powers Up
µ
NOTE: The shown power−up time is based on 1 F bypass capacitors on the reference pins.
See the Theory of Operation section for details.
SERIAL INTERFACE TIMING
Outputs change on
next rising clock edge
after CS goes high.
ADCLK
CS
Start Sequence
t6
t1
t7
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
D7
(MSB)
SDATA
D6
D5
D4
D3
D2
D1
D0
t4
t5
NOTE: Data is shifted in MSB first.
PARAMETER
DESCRIPTION
Serial CLK Period
Serial SLK High Time
Serial CLK Low Time
Data Setup Time
MIN
50
20
20
5
TYP
MAX
UNIT
ns
t1
t2
t3
t4
t5
t6
t7
ns
ns
ns
Data Hold Time
5
ns
CS Fall to SCLK Rise
8
ns
SCLK Rise to CS Rise
8
ns
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SERIAL INTERFACE REGISTERS
ADDRESS
DATA
DESCRIPTION
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
LVDS BUFFERS (Register 0)
Normal ADC Output
All Data Outputs
0
0
1
1
0
1
0
1
(default after reset)
Deskew Pattern
Sync Pattern
See Test Patterns
Custom Pattern
0
0
1
1
0
1
0
1
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
CLOCK CURRENT (Register 1)
Default LVDS Clock Output Current
2X LVDS Clock Output Current(1)
LSB/MSB MODE (Register 1)
LSB First Mode
(default after reset)
0
0
0
0
0
0
0
0
1
1
1
0
0
0
X
X
X
X
0
1
IOUT = 3.5mA (default)
IOUT = 7.0mA
0
0
0
1
X
X
X
X
(default after reset)
MSB First Mode
POWER-DOWN ADC CHANNELS
(Register 2)
X
X
X
X
X
X
X
X
Example: 1010 Powers Down
Channels 4 and 2 and
Keeps Channels 1 and 3 Active
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
0
0
1
1
POWER-DOWN ADC CHANNELS
(Register 3)
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
CUSTOM PATTERN (Registers 4–6)
D3
X
D2
X
D1
X
D0
X
Bits for Custom Pattern
See Test Patterns
0
0
0
1
1
1
0
0
1
0
1
0
X
X
X
X
X
X
X
X
(1) Output current drive for the two clock LVDS buffers (LCLKP and LCLKN and ADCLKP and ADCLKN) is double the output current setting
programmed in register 0. The current drive of the data buffers remains the same as the setting in register 0.
TEST PATTERNS
Serial Output(1)
ADC Output(2)
Deskew Pattern
Sync Pattern
LSB
D0
MSB
D11
0
D1
0
D2
1
D3
0
D4
1
D5
0
D6
1
D7
0
D8
1
D9
0
D10
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Custom Pattern(3)
D0(4)
D1(4)
D2(4)
D3(4)
D0(5)
D1(5)
D2(5)
D3(5)
D0(6)
D1(6)
D2(6)
D3(6)
(1) The serial output stream comes out LSB first by default.
(2) D11...D0 represent the 12 output bits from the ADC.
(3) D0(4) represents the content of bit D0 of register 4, D3(6) represents the content of bit D3 of register 6, etc.
10
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PIN CONFIGURATION
Top View
HTQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
1
2
AVDD
AVDD
IN1P
59 IN8N
58
57
3
IN8P
IN1N
4
AVSS
AVSS
IN2P
56 IN7N
55 IN7P
54 AVDD
5
IN2N
6
AVDD
AVSS
IN3P
7
53
52
51
8
AVSS
IN6N
IN6P
9
10
IN3N
ADS5272
50 AVSS
AVSS 11
49
48
12
13
IN5N
IN5P
IN4P
IN4N
47 AVDD
46 LVSS
45 RESET
AVDD 14
LVSS 15
PD 16
44
43
42
17
18
19
LVSS
LVSS
LVSS
LVSS
ADCLKN
LCLKP
41 ADCLKP
LCLKN 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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PIN DESCRIPTIONS
NAME
ADCLK
ADCLKN
ADCLKP
AVDD
AVSS
CS
PIN #
I/O DESCRIPTION
71
I
O
O
I
Data Converter Clock Input
42
Negative LVDS ADC Clock Output
Positive LVDS ADC Clock Output
41
1, 7, 14, 47, 54, 60, 63, 70, 75
Analog Power Supply
4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80
I
Analog Ground
76
I
Chip Select; 0 = Select, 1 = No Select
LVDS Power Supply
LVDD
LVSS
IN1N
25, 35
I
15, 17, 18, 26, 36, 43, 44, 46
I
LVDS Ground
3
I
Channel 1 Differential Analog Input Low
Channel 1 Differential Analog Input High
Channel 2 Differential Analog Input Low
Channel 2 Differential Analog Input High
Channel 3 Differential Analog Input Low
Channel 3 Differential Analog Input High
Channel 4 Differential Analog Input Low
Channel 4 Differential Analog Input High
Channel 5 Differential Analog Input Low
Channel 5 Differential Analog Input High
Channel 6 Differential Analog Input Low
Channel 6 Differential Analog Input High
Channel 7 Differential Analog Input Low
Channel 7 Differential Analog Input High
Channel 8 Differential Analog Input Low
Channel 8 Differential Analog Input High
Internal/External Reference Select; 0 = External, 1 = Internal. Weak pull-up to supply.
IN1P
2
I
IN2N
6
I
IN2P
5
I
IN3N
10
9
I
IN3P
I
IN4N
13
12
49
48
52
51
56
55
59
58
69
64
20
19
22
21
24
23
28
27
30
29
32
31
34
33
38
37
40
39
16
66
67
45
78
77
65
I
IN4P
I
IN5N
I
IN5P
I
IN6N
I
IN6P
I
IN7N
I
IN7P
I
IN8N
I
IN8P
I
INT/EXT
ISET
I
I/O Bias Current Setting Resistor of 56.2kΩ to Ground
LCLKN
LCLKP
OUT1N
OUT1P
OUT2N
OUT2P
OUT3N
OUT3P
OUT4N
OUT4P
OUT5N
OUT5P
OUT6N
OUT6P
OUT7N
OUT7P
OUT8N
OUT8P
PD
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Negative LVDS Clock
Positive LVDS Clock
Channel 1 Negative LVDS Data Output
Channel 1 Positive LVDS Data Output
Channel 2 Negative LVDS Data Output
Channel 2 Positive LVDS Data Output
Channel 3 Negative LVDS Data Output
Channel 3 Positive LVDS Data Output
Channel 4 Negative LVDS Data Output
Channel 4 Positive LVDS Data Output
Channel 5 Negative LVDS Data Output
Channel 5 Positive LVDS Data Output
Channel 6 Negative LVDS Data Output
Channel 6 Positive LVDS Data Output
Channel 7 Negative LVDS Data Output
Channel 7 Positive LVDS Data Output
Channel 8 Negative LVDS Data Output
Channel 8 Positive LVDS Data Output
Power-Down; 0 = Normal, 1 = Power-Down. Weak pull-down to ground.
REFB
REFT
RESET
SCLK
SDA
I/O Reference Bottom Voltage (2Ω resistor in series with a capacitor ≥ 0.1µF capacitor to ground)
I/O Reference Top Voltage (2Ω resistor in series with a capacitor ≥ 0.1µF capacitor to ground)
I
I
Reset to Default; 0 = Reset, 1 = Normal. Weak pull-down to ground.
Serial Data Clock
I
Serial Data input
VCM
O
Common-Mode Output Voltage
12
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
Minimum Conversion Rate
The analog input frequency at which the spectral
power of the fundamental frequency (as determined
by FFT analysis) is reduced by 3dB.
This is the minimum sampling rate where the ADC
still works.
Signal-to-Noise and Distortion (SINAD)
Aperture Delay
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but not
including dc.
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
PS
SINAD + 10Log
10 PN ) PD
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Clock Duty Cycle
Pulse width high is the minimum amount of time that
the ADCLK pulse should be left in logic ‘1’ state to
achieve rated performance. Pulse width low is the
minimum time that the ADCLK pulse should be left in
a low state (logic ‘0’). At a given clock rate, these
specifications define an acceptable clock duty cycle.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first eight harmonics.
PS
SNR + 10Log
10 PN
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are
exactly 1 LSB apart. DNL is the deviation of any
single LSB transition at the digital output from an
ideal 1 LSB step at the analog input. If a device
claims to have no missing codes, it means that all
possible codes (for a 12-bit converter, 4096 codes)
are present over the full operating range.
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Effective Number of Bits (ENOB)
Spurious-Free Dynamic Range
The ENOB is a measure of converter performance as
compared to the theoretical limit based on
quantization noise.
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier).
SINAD * 1.76
ENOB +
6.02
Two-Tone, Third-Order Intermodulation
Distortion
Integral Nonlinearity (INL)
INL is the deviation of the transfer function from a
reference line measured in fractions of 1 LSB using a
best straight line or best fit determined by a least
square curve fit. INL is independent from effects of
offset, gain or quantization errors.
Two-tone IMD3 is the ratio of power of the
fundamental (at frequencies f1 and f2) to the power of
the worst spectral component of third-order
intermodulation distortion at either frequency 2f1 – f2
or 2f2 – f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full-scale)
when the power of the fundamental is extrapolated to
the full-scale range of the converter.
Maximum Conversion Rate
The encode rate at which parametric testing is
performed. This is the maximum sampling rate where
certified operation is given.
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TYPICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per
channel, 16kFFT, and 8 averages, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
−
−
fIN = 1MHz, 1dBFS
SNR = 71.2dBFS
SINAD = 71.1dBFS
SFDR = 90dBc
fIN = 5MHz, 1dBFS
SNR = 71.1dBFS
SINAD = 70dBFS
SFDR = 88.5dBc
16 Averages
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
16 Averages
−
−
−
−
−
−
100
110
120
100
110
120
0
0
0
5
10
15
20
25
30 32.5
0
0
0
5
10
15
20
25
30 32.5
Input Frequency (MHz)
Input Frequency (MHz)
Figure 1.
Figure 2.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
−
fIN = 10MHz, 1dBFS
SNR = 70.8dBFS
SINAD = 70.7dBFS
SFDR = 87dBc
fIN = 20MHz
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
10
20
30
40
50
60
70
80
90
SNR = 70dBFS
SINAD = 69.9dBFS
SFDR = 86dBc
16 Averages
16 Averages
−
−
100
110
120
100
110
120
−
−
−
−
5
10
15
20
25
30 32.5
5
10
15
20
25
30 32.5
Input Frequency (MHz)
Input Frequency (MHz)
Figure 3.
Figure 4.
INTERMODULATION DISTORTION
f1 = 9.5MHz
CROSSTALK
0
0
fIN = 5MHz
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
10
20
30
40
50
60
70
80
90
f2 = 10.2MHz
IMD3 = 96dBFS
16 Averages
Crosstalk = 90dBFS
16 Averages
−
−
100
110
120
100
110
120
−
−
−
−
5
10
15
20
25
30 32.5
5
10
15
20
25
30 32.5
Input Frequency (MHz)
Input Frequency (MHz)
Figure 5.
Figure 6.
14
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per
channel, 16kFFT, and 8 averages, unless otherwise noted.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
0.60
0.45
0.30
0.15
0
0.45
0.30
0.15
0
fIN = 5MHz
fIN = 5MHz
−
−
−
−
0.15
0.30
0.45
0.60
−
−
−
0.15
0.30
0.45
0
512 1024 1536 2048 2560 3072 3584 4096
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Code
Figure 7.
Figure 8.
SNR vs INPUT FREQUENCY
SINAD vs INPUT FREQUENCY
80
75
70
65
60
55
80
75
70
65
60
55
50
External Reference
REFT = 1.95V
External Reference
REFT = 1.95V
REFB = 0.95V
REFB = 0.95V
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
Input Frequency (MHz)
Input Frequency (MHz)
Figure 9.
Figure 10.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
Internal Reference
100
95
90
85
80
75
70
80
75
70
65
60
55
External Reference
REFT = 1.95V
REFB = 0.95V
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
Input Frequency (MHz)
Input Frequency (MHz)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per
channel, 16kFFT, and 8 averages, unless otherwise noted.
SINAD vs INPUT FREQUENCY
Internal Reference
SFDR vs INPUT FREQUENCY
100
95
90
85
80
75
70
80
75
70
65
60
55
50
Internal Reference
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
Input Frequency (MHz)
Input Frequency (MHz)
Figure 13.
Figure 14.
SWEPT POWER — SNR
dBFS
SWEPT POWER — SFDR
120
100
80
60
40
20
0
80
70
60
50
40
30
20
10
0
dBFS
dBc
dBc
fIN = 10MHz
fIN = 10MHz
−
−
−
−
−
−
10
−
−
−
−
−
−
60
50
40
30
20
0
60
50
40
30
20
10
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 15.
Figure 16.
SWEPT POWER — SINAD
SWEPT POWER — SNR
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
dBFS
dBFS
dBc
dBc
fIN = 10MHz
fIN = 5MHz
−
−
−
−
−
−
−
−
−
−
−
−
10
60
50
40
30
20
10
0
60
50
40
30
20
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 17.
Figure 18.
16
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per
channel, 16kFFT, and 8 averages, unless otherwise noted.
SWEPT POWER — SINAD
dBFS
SWEPT POWER — SFDR
120
100
80
60
40
20
0
80
70
60
50
40
30
20
10
0
dBFS
dBc
dBc
fIN = 5MHz
fIN = 5MHz
−
−
−
−
−
−
10
−
−
−
−
−
−
60
50
40
30
20
0
65
65
60
50
40
30
20
10
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 19.
Figure 20.
SNR vs DUTY CYCLE
SINAD vs DUTY CYCLE
76
74
72
70
68
66
64
76
74
72
70
68
66
64
fIN = 5MHz
fIN = 5MHz
35
40
45
50
55
60
35
40
45
50
55
60
65
Duty Cycle (%)
Duty Cycle (%)
Figure 21.
Figure 22.
SFDR vs DUTY CYCLE
SNR vs SAMPLE RATE
95
90
85
80
75
70
65
80
76
72
68
64
60
fIN = 5MHz
fIN = 5MHz
35
40
45
50
55
60
65
20
25
30
35
40
45
50
55
60
Duty Cycle (%)
Sample Rate (MSPS)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per
channel, 16kFFT, and 8 averages, unless otherwise noted.
SINAD vs SAMPLE RATE
SFDR vs SAMPLE RATE
80
76
72
68
64
60
94
90
86
82
78
74
fIN = 5MHz
fIN = 5MHz
20
20
10
25
30
35
40
45
50
55
60
65
20
25
30
35
40
45
50
55
60
65
Sample Rate (MSPS)
Sample Rate (MSPS)
Figure 25.
Figure 26.
SINAD vs SAMPLE RATE
SFDR vs SAMPLE RATE
74
72
70
68
66
64
74
72
70
68
66
64
fIN = 10MHz
fIN = 10MHz
25
30
35
40
45
50
55
60
65
20
25
30
35
40
45
50
55
60
65
Sample Rate (MSPS)
Sample Rate (MSPS)
Figure 27.
Figure 28.
CURRENT vs SAMPLE RATE
TOTAL POWER vs SAMPLE RATE
300
250
200
150
100
50
1050
1000
950
900
850
800
750
700
IAVDD
ILVDD
0
20
30
40
50
60
70
10
20
30
40
50
60
70
Sample Rate (MSPS)
Sample Rate (MSPS)
Figure 29.
Figure 30.
18
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per
channel, 16kFFT, and 8 averages, unless otherwise noted.
TOTAL POWER vs TEMPERATURE
SNR vs TEMPERATURE
1050
1025
1000
975
76
74
72
70
68
66
64
950
925
900
−
−
15
40
+10
+35
+60
+85
−
−
15
40
+10
+35
+60
+85
_
Temperature ( C)
_
Temperature ( C)
Figure 31.
Figure 32.
SINAD vs TEMPERATURE
76
74
72
70
68
66
64
−
−
15
40
+10
+35
+60
+85
_
Temperature ( C)
Figure 33.
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THEORY OF OPERATION
data externally has multiple advantages, such as a
reduced number of output pins (saving routing space
on the board), reduced power consumption, and
reduced effects of digital noise coupling to the analog
circuit inside the ADS5272.
OVERVIEW
The ADS5272 is an 8-channel, high-speed, CMOS
ADC.
It
consists
of
a
high-performance
sample-and-hold circuit at the input, followed by a
12-bit ADC. The 12 bits given out by each channel
are serialized and sent out on a single pair of pins in
LVDS format. All eight channels of the ADS5272
operate from a single clock referred to as ADCLK.
The sampling clocks for each of the eight channels
are generated from the input clock using a carefully
matched clock buffer tree. The 12x clock required for
the serializer is generated internally from ADCLK
using a phase lock loop (PLL). A 6x and a 1x clock
are also output in LVDS format along with the data to
enable easy data capture. The ADS5272 operates
from internally generated reference voltages that are
trimmed to ensure matching across multiple devices
on a board. This feature eliminates the need for
external routing of reference lines and also improves
matching of the gain across devices. The nominal
values of REFT and REFB are 1.95V and 0.95V,
respectively. These values imply that a differential
input of –1V corresponds to the zero code of the
ADC, and a differential input of +1V corresponds to
the full-scale code (4095 LSB). VCM (common-mode
voltage of REFT and REFB) is also made available
externally through a pin, and is nominally 1.45V.
The ADS5272 operates from two sets of supplies and
grounds. The analog supply/ground set is denoted as
AVDD/AVSS, while the digital set is denoted by
LVDD/LVSS.
DRIVING THE ANALOG INPUTS
The analog input biasing is shown in Figure 34. The
inputs are biased internally using two 600Ω resistors
to enable ac-coupling. A resistor greater than 20Ω is
recommended in series with each input pin.
A 4pF sampling capacitor is used to sample the
inputs. The choice of the external ac-coupling
capacitor is dictated by the attenuation at the lowest
desired input frequency of operation. The attenuation
resulting from using a 10nF ac-coupling capacitor is
0.04%.
ADS5272
IN+
Ω
Ω
600
Input
Circuitry
The ADC employs a pipelined converter architecture
consisting of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the
digital error correction logic, ensuring excellent
differential linearity and no missing codes at the
12-bit level. The pipeline architecture results in a data
latency of 6.5 clock cycles.
600
−
IN
Internal
Voltage
VCM
Reference
CM Buffer
The output of the ADC goes to a serializer that
operates from a 12x clock generated by the PLL. The
12 data bits from each channel are serialized and
sent LSB first. In addition to serializing the data, the
serializer also generates a 1x clock and a 6x clock.
These clocks are generated in the same way the
serialized data is generated, so these clocks maintain
perfect synchronization with the data. The data and
clock outputs of the serializer are buffered externally
using LVDS buffers. Using LVDS buffers to transmit
NOTE: Dashed area denotes one of eight channels.
Figure 34. Analog Input Bias Circuitry
If the input is dc-coupled, then the output
common-mode voltage of the circuit driving the
ADS5272 should match the VCM (which is provided as
an output pin) to within ±50mV. It is recommended
that the output common-mode of the driving circuit be
derived from VCM provided by the device.
20
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Figure 35 shows a detailed RLC model of the
sample-and-hold circuit. The circuit operates in two
phases. In the sample phase, the input is sampled on
two capacitors that are nominally 4pF. The sampling
circuit consists of a low-pass RC filter at the input to
filter out noise components that might be differentially
coupled on the input pins. The next phase is the hold
phase wherein the voltage sampled on the capacitors
is transferred (using the amplifier) to a subsequent
pipeline ADC stage.
over-voltage pulse input of twice the amplitude of a
full-scale pulse is expected to be within three clock
cycles when the input switches from overload to zero
signal. All of the amplifiers in the SHA and ADC are
specially designed for excellent recovery from an
overload signal.
In most applications, the ADC inputs are driven with
differential sinusoidal inputs. While the pulse-type
signal remains at peak overload conditions
throughout its HIGH state, the sinusoid signal only
attains peak overload intermittently, at its minima and
maxima. This condition is much less severe for the
ADC input and the recovery of the ADC output (to 1%
of full-scale around the expected code). This typically
happens within the second clock when the input is
driven with a sinusoid of amplitude equal to twice that
of the ADC differential full-scale range.
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale range supported by the
ADS5272 is nominally 2.03V. The ADS5272 is
specially designed to handle an over-voltage
condition where the differential peak-to-peak voltage
can exceed up to twice the ADC full-scale range. If
the input common-mode is not considerably off from
VCM during overload (less than 300mV around the
nominal value of 1.45V), recovery from an
IN
OUT
5nH
to 9nH
INP
1.5pF to
2.5pF
3.2pF
to 4.8pF
Ω
Ω
Ω
60
Ω
to 120
15
15
Ω
to 25
Ω
to 25
Ω
1
IN
OUT
IN
OUT
Ω
500
Ω
to 720
OUT
OUTP
OUTN
1.5pF
to 1.9pF
IN
Ω
500
Ω
Ω
to 720
Ω
Ω
15 to 35
3.2pF
to 4.8pF
Ω
15
Ω
Ω
60
Ω
to 120
15
Ω
to 25
to 25
IN
OUT
IN
OUT
5nH
to 9nH
INN
1.5pF to
2.5pF
Switches that are ON
in SAMPLE phase.
Ω
1
Switches that are ON
in HOLD phase.
IN
OUT
Figure 35. Overall Structure of the Sample-and-Hold Circuit
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REFERENCE CIRCUIT DESIGN
reference voltages. This mode involves forcing REFT
and REFB externally. In this mode, the internal
reference buffer is tri-stated. Since the switching
current for the eight ADCs come from the externally
forced references, it is possible for the performance
to be slightly less than when the internal references
are used. It should be noted that in this mode, VCM
and ISET continue to be generated from the internal
bandgap voltage, as in the internal reference mode. It
is therefore important to ensure that the
common-mode voltage of the externally forced
The digital beam-forming algorithm relies heavily on
gain matching across all receiver channels. A typical
system would have about 12 octal ADCs on the
board. In such a case, it is critical to ensure that the
gain is matched, essentially requiring the reference
voltages seen by all the ADCs to be the same.
Matching references within the eight channels of a
chip is done by using a single internal reference
voltage buffer. Trimming the reference voltages on
each chip during production ensures the reference
voltages are well matched across different chips.
reference voltages matches to within 50mV of VCM
.
The state of the reference voltages during various
combinations of PD and INT/EXT is shown in
Table 1.
All bias currents required for the internal operation of
the device are set using an external resistor to
ground at pin ISET. Using a 56.2kΩ resistor on ISET
generates an internal reference current of 20µA. This
current is mirrored internally to generate the bias
current for the internal blocks. Using a larger external
resistor at ISET reduces the reference bias current and
thereby scales down the device operating power.
However, it is recommended that the external resistor
be within 10% of the specified value of 56.2kΩ so
that the internal bias margins for the various blocks
are proper.
Table 1. State of Reference Voltages for Various
Combinations of PD and INT/EXT
PD
INT/EXT
REFT
REFB
VCM
0
0
1
1
0
1
0
1
Tri-State
Tri-State
1.45V
1.95V
0.95V
1.45V
Tri-State
Tri-State
Tri-State(1) Tri-State(1)
Tri-State
Tri-State
(1) Weak pull-down (approximately 5kΩ) to ground.
Buffering the internal bandgap voltage also generates
a voltage called VCM, which is set to the midlevel of
REFT and REFB, and is accessible on a pin. It is
meant as a reference voltage to derive the input
common-mode in case the input is directly coupled. It
can also be used to derive the reference
common-mode voltage in the external reference
mode.
CLOCKING
The eight channels on the chip operate from a single
ADCLK input. To ensure that the aperture delay and
jitter are same for all the channels, a clock tree
network is used to generate individual sampling
clocks to each channel. The clock paths for all the
channels are matched from the source point all the
way to the sample-and-hold amplifier. This ensures
that the performance and timing for all the channels
are identical. The use of the clock tree for matching
introduces an aperture delay, which is defined as the
delay between the rising edge of ADCLK and the
actual instant of sampling. The aperture delays for all
the channels are matched to the best possible extent.
However, a mismatch of ±20ps (±3σ) could exist
between the aperture instants of the eight ADCs
within the same chip. However, the aperture delays of
ADCs across two different chips can be several
hundred picoseconds apart. Another critical
specification is the aperture jitter that is defined as
the uncertainty of the sampling instant. The gates in
the clock path are designed to provide an rms jitter of
approximately 1ps.
When using the internal reference mode, a 2Ω
resistor should be added between the reference pins
(REFT and REFB) and the decoupling capacitor, as
shown in Figure 36. If the device is used in the
external reference mode, this 2Ω resistor is not
required.
ADS5272
REFT
REFB
Ω
> 2
Ω
> 2
µ
0.1
µ
µ
2.2
µ
0.1 F
F
2.2 F
F
Ideally, the input ADCLK should have a 50% duty
cycle. However, while routing ADCLK to different
components onboard, the duty cycle of the ADCLK
reaching the ADS5272 could deviate from 50%. A
smaller (or larger) duty cycle reduces the time
available for sample or hold phases of each circuit,
and is therefore not optimal. For this reason, the
internal PLL is used to generate an internal clock that
Figure 36. Internal Reference Mode
The device also supports the use of external
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has 50% duty cycle. The input sampling instant,
however, is determined by the rising edge of the
external clock and is not affected by jitter in the PLL.
In addition to generating a 50% duty cycle clock for
the ADC, the PLL also generates a 12x clock that is
used by the serializer to convert the parallel data from
the ADC to a serial stream of bits.
takes the output data from each channel and
serializes it into a single data stream. For a clock
frequency of 65MHz, the data rate output of the
serializer is 780Mbps. The data comes out LSB first,
with a register programmability that allows it to revert
to MSB first. The serializer also transmits a 1x clock
and
a
6x clock. The 6x clock (denoted as
LCLKP/LCLKN) is meant to synchronize the capture of
the LVDS data.
The use of the PLL automatically dictates the
minimum sample rate to be about 20MSPS. The PLL
also requires the input clock to be free-running. If the
input clock is momentarily stopped (for a duration of
less than 300ns) then the PLL would require
approximately 10µs to lock back to the input clock
frequency.
Deskew mode can be enabled as well, using a
register setting. This mode gives out a data stream of
alternate 0s and 1s and can be used determine the
relative delay between the 6x clock and the output
data for optimum capture. A 1x clock is also
generated by the serializer and transmitted through
the LVDS buffer. The 1x clock (referred to as
ADCLKP/ADCLKN) is used to determine the start of
the 12-bit data frame. Sync mode (enabled through a
register setting) gives out a data of six 0s followed by
six 1s. Using this mode, the 1x clock can be used to
determine the start of the data frame. In addition to
the deskew mode pattern and the sync mode pattern,
a custom pattern can be defined by the user and
output from the LVDS buffer. The LVDS buffers are
tri-stated in the power-down mode. The LVDS outputs
are weakly forced to 1.2V through 10kΩ resistors
(from each output pin to 1.2V).
LVDS BUFFERS
The LVDS buffer has two current sources, as shown
in Figure 37. OUTP and OUTN are loaded externally
by a resistive load that is ideally about 100Ω.
Depending on whether the data is 0 or 1, the currents
are directed in one direction or the other through the
resistor. The LVDS buffer has four current settings.
The default current setting is 3.5mA, and provides a
differential drop of about ±350mV across the 100Ω
resistor.
The single-ended output impedance of the LVDS
drivers is very high because they are current-source
driven. If there are excessive reflections from the
receiver, it might be necessary to place a 100Ω
termination resistor across the outputs of the LVDS
drivers to minimize the effect of reflections. In such a
situation, the output current of the LVDS drivers can
be increased to regain the output swing.
NOISE COUPLING ISSUES
High-speed mixed signals are sensitive to various
types of noise coupling. One of the main sources of
noise is the switching noise from the serializer and
the output buffers. Maximum care is taken to isolate
these noise sources from the sensitive analog blocks.
As a starting point, the analog and digital domains of
the chip are clearly demarcated. AVDD and AVSS
are used to denote the supplies for the analog
sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there
is minimal interaction between the supply sets within
the device. The extent of noise coupled and
transmitted from the digital to the analog sections
depends on the following:
External
Termination
Resistor
High
Low
OUTP
OUTN
1. The effective inductances of each of the
supply/ground sets.
Low
High
2. The isolation between the digital and analog
supply/ground sets.
Smaller effective inductance of the supply/ground
pins leads to better suppression of the noise. For this
reason, multiple pins are used to drive each
supply/ground. It is also critical to ensure that the
impedances of the supply and ground lines on board
are kept to the minimum possible values. Use of
ground planes in the board as well as large
decoupling capacitors between the supply and
ground lines are necessary to get the best possible
SNR from the device.
Figure 37. LVDS Buffer
The LVDS buffer receives data from a serializer that
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It is recommended that the isolation be maintained on
board by using separate supplies to drive AVDD and
LVDD, as well as separate ground planes for AVSS
and LVSS.
RESET
After the supplies have stabilized, it is necessary to
give the device an active RESET pulse. This results
in all internal registers resetting to their default value
of 0 (inactive). Without a reset, it is possible that
some registers may be in their non-default state on
power-up. This may cause the device to malfunction.
When a reset is active, the device outputs ‘0’ code on
all channels. However, the LVDS output clocks are
unaffected by reset.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The
current in the LVDS buffer is independent of the
direction of switching. Also, the low output swing as
well as the differential nature of the LVDS buffer
results in low-noise coupling.
POWER-DOWN MODE
LAYOUT OF PCB WITH PowerPAD
THERMALLY-ENHANCED PACKAGES
The ADS5272 has a power-down pin, referred to as
PD. Pulling PD high causes the device to enter the
power-down mode. In this mode, the reference and
clock circuitry, as well as all the channels, are
powered down. Device power consumption drops to
less than 100mW in this mode. In power-down mode,
the internal buffers driving REFT and REFB are
tri-stated and their outputs are forced to a voltage
roughly equal to half of the voltage on AVDD. Speed
of recovery from power-down mode depends on the
value of the external capacitance on the REFT and
REFB pins. For capacitances on REFT and REFB less
than 1µF, the reference voltages settle to within 1%
of their steady-state values in less than 500µs.
Individual channels can also be selectively powered
down by programming registers.
The ADS5272 is housed in an 80-lead PowerPAD
thermally-enhanced package. To make optimum use
of the thermal efficiencies designed into the
PowerPAD package, the printed circuit board (PCB)
must be designed with this technology in mind.
Please refer to SLMA004 PowerPAD brief PowerPAD
Made Easy (refer to our web site at www.ti.com),
which addresses the specific considerations required
when integrating a PowerPAD package into a PCB
design. For more detailed information, including
thermal modeling and repair procedures, please see
the
technical
brief
SLMA002,
PowerPAD
Thermally-Enhanced Package (www.ti.com).
Interfacing High-Speed LVDS Outputs (SBOA104),
an application report discussing the design of a
simple deserializer that can deserialize LVDS outputs
up to 840Mbps, can also be found on the TI web site
(www.ti.com).
The ADS5272 also has an internal circuit that
monitors the state of stopped clocks. If ADCLK is
stopped for longer than 300ns (or if it runs at a speed
less than 3MHz), this monitoring circuit generates a
logic signal that puts the device in
power-down state. As result, the power
consumption of the device is reduced when ADCLK is
stopped. The recovery from such partial
power-down takes ap- proximately 100µs; this is
described in Table 2.
a partial
CONNECTING HIGH-SPEED,
a
MULTI-CHANNEL ADCs TO XILINX FPGAs
A separate application note (XAPP774) describing
how to connect TI's high-speed, multi-channel ADCs
with serial LVDS outputs to Xilinx FPGAs can be
downloaded directly from the Xilinx web site
(http://www.xilinx.com).
a
Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION
TYP
500µs
10µs
REMARKS
Recovery from power-down mode (PD = 1 to PD = 0).
Recovery from momentary clock stoppage ( < 300ns).
Recovery from extended clock stoppage ( > 300ns).
Capacitors on REFT and REFB less than 1µF.
100µs
24
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Product Folder Link(s): ADS5272
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Revision History
Changes from Revision B (September 2005) to Revision C .......................................................................................... Page
•
Updated Absolute Maximum Ratings table: added entries for Digital Input Pins, Set 1 and Set 2 and added footnote 3.... 2
Changes from Revision A (August 2005) to Revision B ................................................................................................ Page
•
•
•
•
•
•
•
•
Changed title to spell out ADC to match rest of family.......................................................................................................... 1
Changed Synch to Bit in 10th bullet of Features section....................................................................................................... 1
Deleted parallel from first paragraph of Description section.................................................................................................. 1
Changed front page figure. .................................................................................................................................................... 1
Changed unit values in Lead Temperature and Storage Temperature rows of Absolute Maximum table............................ 2
Deleted condition value of CO row in LVDS table.................................................................................................................. 7
Deleted Figure 27 (SNR vs Sample Rate)........................................................................................................................... 18
Changed 2.0ps to 20ps and added (±3σ) to seventh sentence of first paragraph of Clocking section in Theory of
Operation. ............................................................................................................................................................................ 22
Copyright © 2004–2009, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS5272IPFP
ADS5272IPFPG4
ADS5272IPFPT
ADS5272IPFPTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTQFP
HTQFP
HTQFP
HTQFP
PFP
PFP
PFP
PFP
80
80
80
80
96
96
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
250
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS5272IPFPT
HTQFP
PFP
80
250
330.0
24.4
15.0
15.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PFP 80
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
ADS5272IPFPT
250
Pack Materials-Page 2
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ADS5272IPFPTG4
Eight-Channel, 12-Bit, 65-MSPS Analog-to-Digital Converter (ADC) 80-HTQFP -40 to 85
TI
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ADS5273IPFPTG4
8-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQFP80, GREEN, PLASTIC, HTQFP-80
TI
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