ADS5287IRGCTG4_技术文档

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

10-Bit, Octal-Channel ADC Up to 65MSPS

Check for Samples: ADS5287

1

FEATURES

DESCRIPTION

The ADS5287 is a high-performance, low-power,

octal channel analog-to-digital converter (ADC).

Available in a 9mm × 9mm QFN package, with

serialized low-voltage differential signaling (LVDS)

outputs and a wide variety of programmable features,

the ADS5287 is highly customizable for a wide range

of applications and offers an unprecedented level of

system integration. An application note, XAPP774

(available at www.xilinx.com), describes how to

interface the serial LVDS outputs of TI's ADCs to

Xilinx^®field-programmable gate arrays (FPGAs). The

ADS5287 is specified over the industrial temperature

range of –40°C to +85°C.

234

•

Speed and Resolution Grades:

10-bit, 65MSPS

Power Dissipation:

–

•

–

46mW/Channel at 30MSPS

53mW/Channel at 40MSPS

62mW/Channel at 50MSPS

74mW/Channel at 65MSPS

•

61.7dBFS SNR at 10MHz IF

Analog Input Full-Scale Range: 2V_PP

Low-Frequency Noise Suppression Mode

6dB Overload Recovery in One Clock

External and Internal (Trimmed) Reference

3.3V Analog Supply, 1.8V Digital Supply

Single-Ended or Differential Clock:

LCLK_P

6x ADCLK

Clock

Buffer

LCLK_N

–

Clock Duty Cycle Correction Circuit (DCC)

12x ADCLK

PLL

1x ADCLK

•

Programmable Digital Gain: 0dB to 12dB

Serialized DDR LVDS Output

ADCLK_P

ADCLK_N

Programmable LVDS Current Drive, Internal

Termination

IN1_P

IN1_N

OUT1_P

OUT1_N

10-Bit

ADC

Digital

Serializer

•

Test Patterns for Enabling Output Capture

Channels

2 to 7

Straight Offset Binary or Two's Complement

Output

IN8_P

IN8_N

OUT8_P

OUT8_N

10-Bit

ADC

•

Package Options:

Digital

Serializer

–

9mm × 9mm QFN-64

APPLICATIONS

•

Medical Imaging

Wireless Base-Station Infrastructure

Test and Measurement Instrumentation

Power-

Down

ADC

Control

Registers

Reference

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

PowerPAD is a trademark of Texas Instruments, Inc.

Xilinx is a registered trademark of Xilinx, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

RELATED PRODUCTS

MODEL

ADS5281

ADS5282

ADS5287

ADS5270

ADS5271

ADS5272

ADS5273

ADS5242

RESOLUTION (BITS)

SAMPLE RATE (MSPS)

CHANNELS

12

10

12

50

65

40

50

65

70

65

8

4

Table 1. ORDERING INFORMATION^{(1) (2)}

SPECIFIED

PACKAGE

DESIGNATOR

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

PRODUCT

PACKAGE-LEAD

QFN-64

MEDIA, QUANTITY⁽³⁾

Tape and Reel

ADS5287IRGCT

ADS5287IRGCR

ADS5287

RGC

–40°C to +85°C

AZ5287

Tape and Reel

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) These devices meet the following planned eco-friendly classification:

Green (RoHS and No Sb/Br): Texas Instruments defines Green to mean Pb-free (RoHS compatible) and free of bromine (Br)- and

antimony (Sb)-based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more information. These devices

have a Cu NiPdAu lead/ball finish.

(3) Refer to the Package Option Addendum at the end of this document for specific transport media and quantity information.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

ADS5287

UNIT

V

Supply voltage range, AVDD

Supply voltage range, LVDD

Voltage between AVSS and LVSS

External voltage applied to REF_Tpin

External voltage applied to REF_Bpin

Voltage applied to analog input pins

Voltage applied to digital input pins

Peak solder temperature

–0.3 to +3.9

–0.3 to +2.2

V

–0.3 to +0.3

V

–0.3 to +3

V

–0.3 to +2

V

–0.3 to minimum [3.6, (AVDD + 0.3)]

V

–0.3 to minimum [3.9, (AVDD + 0.3)]

V

+260

+125

°C

Junction temperature

Storage temperature range

–65 to +150

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not supported.

2

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

RECOMMENDED OPERATING CONDITIONS

ADS5287

PARAMETER

MIN

TYP

MAX

UNIT

SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES

AVDD

LVDD

Analog supply voltage

3.0

1.7

3.3

3.6

1.9

V

Digital supply voltage

1.8

Differential input voltage range

Input common-mode voltage

External reference mode

2

V_CM± 0.05

2.5

V_PP

V

REF_T

REF_B

V

0.5

V

CLOCK INPUTS

ADCLK input sample rate 1/ t_C

10

50, 65

MSPS

Input clock amplitude differential (V_CLKP–V_CLKN) peak-to-peak

Sine wave, ac-coupled

3.0

1.6

0.7

V_PP

LVPECL, ac-coupled

LVDS, ac-coupled

Input clock CMOS, single-ended (V_CLKP

)

V_IL

0.6

V

V_IH

2.2

Input clock duty cycle

50

%

DIGITAL OUTPUTS

ADCLK_Pand ADCLK_Noutputs (LVDS)

LCLK_Pand LCLK_Noutputs (LVDS)

10

60

1x (sample rate)

50, 65

MHz

pF

6x (sample rate)

300, 390

C_LOAD

R_LOAD

T_A

Maximum external capacitance from each pin to LVSS

Differential load resistance between the LVDS output pairs

Operating free-air temperature

5

100

Ω

–40

+85

°C

INITIALIZATION REGISTERS

If the analog input is ac-coupled, the following registers must be written to in the order listed below.

ADDRESS (hex)

DATA (hex)

0010

Initialization Register 1

Initialization Register 5

01

E2

00C0

To disable the PLL configuration switching (especially useful in systems where a system-level timing calibration is done once

after power-up), the following registers must be written to in the order listed below. Also, see section PLL Operation Across

Sampling Frequency.

ADDRESS (hex)

DATA (hex)

0060

(1)

For 10 ≤ Fs ≤ 25

E3

(1)

For 15 ≤ Fs = ≤ 45

00A0

(1) where Fs = sampling clock frequency

3

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

DIGITAL CHARACTERISTICS

DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level

'0' or '1'. At C_LOAD= 5pF⁽¹⁾, I_OUT= 3.5mA⁽²⁾, R_LOAD= 100Ω⁽²⁾, and no internal termination, unless otherwise noted.

ADS5287

PARAMETER

DIGITAL INPUTS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

1.4

V

0.3

V

33

–33

3

μA

pF

LVDS OUTPUTS

High-level output voltage

Low-level output voltage

Output differential voltage, |V_OD

V_OSoutput offset voltage

1375

1025

350

mV

|

Common-mode voltage of OUT_Pand OUT_N

1200

Output capacitance inside the device,

from either output to ground

Output capacitance

2

pF

(1) C_LOADis the effective external single-ended load capacitance between each output pin and ground.

(2) I_OUTrefers to the LVDS buffer current setting; R_LOADis the differential load resistance between the LVDS output pair.

4

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

ELECTRICAL CHARACTERISTICS

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

ADS5287

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL REFERENCE VOLTAGES

V_REFB

V_REFT

Reference bottom

Reference top

0.5

2.5

2.0

1.5

±2

V

V_REFT– V_REFB

1.95

2.05

V

V_CM

Common-mode voltage (internal)

V_CMoutput current

1.425

1.575

V

mA

EXTERNAL REFERENCE VOLTAGES

V_REFB

V_REFT

Reference bottom

Reference top

V_REFT– V_REFB

0.4

2.4

1.9

0.5

2.5

2.0

0.6

2.6

2.1

V

ANALOG INPUT

Differential input voltage range

2.0

3

V_PP

pF

Differential input capacitance

Analog input bandwidth

520

MHz

V

Analog input common-mode range

DC-coupled input

V_CM± 0.05

Per input pin per MSPS of sampling

speed

μA/MHz

per pin

Analog input common-mode current

Voltage overload recovery time

2.5

1

Recovery from 6dB overload to within 1%

accuracy

Clock cycle

LSB

Standard deviation seen on a periodic

first data within full-scale range in a 6dB

overloaded sine wave

Voltage overload recovery repeatability

1

DC ACCURACY

Offset error

Offset error temperature coefficient⁽¹⁾

–1.25

±0.2

±5

+1.25

%FS

ppm/°C

%FS

Channel gain error

Excludes error in internal reference

–0.8

Channel gain error temperature

coefficient

Excludes temperature coefficient of

internal reference

±10

ppm/°C

Internal reference error temperature

coefficient⁽²⁾

DC power-supply rejection ratio⁽³⁾

±15

1.5

ppm/°C

mV/V

DC PSRR

POWER-DOWN MODES

Power in complete power-down mode

45

135

88

mW

Power in partial power-down mode

Power with no clock

Clock at 65MSPS

DYNAMIC PERFORMANCE

5MHz full-scale signal applied to seven

channels, measurement taken on channel

with no input signal

Crosstalk

–90

–92

dBc

Two-tone, third-order intermodulation

distortion

f₁= 9.5MHz at –7dBFs

f₂= 10.2MHz at –7dBFs

dBFS

DC ACCURACY

No missing codes

Assured

±0.1

DNL

INL

Differential nonlinearity

Integral nonlinearity

–0.55

–1

+0.55

+1

LSB

±0.1

POWER SUPPLY—INTERNAL REFERENCE MODE

(1) The offset temperature coefficient in ppm/°C is defined as (O₁– O₂) × 10⁶/(T₁– T₂)/1024, where O₁and O₂are the offset codes in LSB

at the two extreme temperatures, T₁and T₂.

(2) The internal reference temperature coefficient is defined as (REF₁– REF₂) × 10⁶/(T₁– T₂)/2, where REF₁and REF₂are the internal

reference voltages (V_REFT– V_REFB) at the two extreme temperatures, T₁and T₂.

(3) DC PSRR is defined as the ratio of the change in the ADC output (expressed in mV) to the change in supply voltage (in volts).

5

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

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ELECTRICAL CHARACTERISTICS (continued)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

ADS5287

PARAMETER

Analog supply current

Digital current

TEST CONDITIONS

MIN

TYP

139

87

MAX

165

UNIT

mA

IAVDD

ILVDD

Zero input to all channels

97

mA

Total power

615

719.1

mW

Obtained on powering down one channel

at a time

Incremental power saving

61

mW

POWER SUPPLY—EXTERNAL REFERENCE MODE

IAVDD

ILVDD

Analog supply current

Digital current

132

87

mA

mW

Zero input to all channels

Total power

592

Obtained on powering down one channel

at a time

Incremental power saving

59

mW

EXTERNAL REFERENCE LOADING

Switching current

Current drawn by the eight ADCs from the

external reference voltages; sourcing for

REF_T, sinking for REF_B.

3.5

mA

DYNAMIC CHARACTERISTICS

f_IN= 5MHz, single-ended clock

f_IN= 30MHz, differential clock

f_IN= 5MHz, single-ended clock

f_IN= 30MHz, differential clock

f_IN= 5MHz, single-ended clock

f_IN= 30MHz, differential clock

f_IN= 5MHz, single-ended clock

f_IN= 30MHz, differential clock

f_IN= 5MHz, single-ended clock

f_IN= 30MHz, differential clock

f_IN= 5MHz, single-ended clock

f_IN= 30MHz, differential clock

72

85

80

dBc

SFDR

HD2

Spurious-free dynamic range

Magnitude of second harmonic

Magnitude of third harmonic

Total harmonic distortion

Signal-to-noise ratio

85

82

72

85

HD3

80

70

80

THD

78

60.5

60.4

61.7

61.6

SNR

SINAD

Signal-to-noise and distortion

6

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

PIN CONFIGURATION

QFN-64 PowerPAD™

TOP VIEW

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

IN1_P

IN1_N

IN8_N

IN8_P

3

AVSS

IN2_P

AVSS

IN7_N

4

5

IN2_N

IN7_P

6

AVSS

IN3_P

AVSS

IN6_N

7

8

IN3_N

IN6_P

ADS5287

9

AVSS

IN4_P

AVSS

IN5_N

10

11

12

13

14

15

16

IN4_N

IN5_P

LVSS

PD

AVSS

LVSS

LVDD

OUT8_N

OUT8_P

LVSS

OUT1_P

OUT1_N

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Table 2. PIN DESCRIPTIONS: QFN-64

PIN NAME

DESCRIPTION

PIN NUMBER

# OF PINS

ADCLK_N

ADCLK_P

AVDD

LVDS frame clock (1X)—negative output

LVDS frame clock (1X)—positive output

Analog power supply, 3.3V

Analog ground

24

23

1

4

7

49, 50, 57, 60

AVSS

3, 6, 9, 37, 40, 43, 46

Negative differential clock input

Tie CLK_Nto 0V for a single-ended clock

CLK_N

59

1

CLK_P

CS

Positive differential clock input

58

61

2

1

Serial enable chip select—active low digital input

Negative differential input signal, channel 1

Positive differential input signal, channel 1

Negative differential input signal, channel 2

Positive differential input signal, channel 2

Negative differential input signal, channel 3

Positive differential input signal, channel 3

Negative differential input signal, channel 4

Positive differential input signal, channel 4

IN1_N

IN1_P

IN2_N

IN2_P

IN3_N

IN3_P

IN4_N

IN4_P

1

5

4

8

7

11

10

7

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

Table 2. PIN DESCRIPTIONS: QFN-64 (continued)

PIN NAME

IN5_N

DESCRIPTION

PIN NUMBER

# OF PINS

Negative differential input signal, channel 5

Positive differential input signal, channel 5

Negative differential input signal, channel 6

Positive differential input signal, channel 6

Negative differential input signal, channel 7

Positive differential input signal, channel 7

Negative differential input signal, channel 8

Positive differential input signal, channel 8

Internal/external reference mode select input

Bias pin—56.2kΩ to ground

39

38

1

3

1

IN5_P

IN6_N

42

IN6_P

41

IN7_N

45

IN7_P

44

IN8_N

48

IN8_P

47

INT/EXT

I_SET

56

51

LCLK_N

LCLK_P

LVDD

LVSS

OUT1_N

OUT1_P

OUT2_N

OUT2_P

OUT3_N

OUT3_P

OUT4_N

OUT4_P

OUT5_N

OUT5_P

OUT6_N

OUT6_P

OUT7_N

OUT7_P

OUT8_N

OUT8_P

PD

LVDS bit clock (6X)—negative output

LVDS bit clock (6X)—positive output

Digital and I/O power supply, 1.8V

Digital ground

26

25

35

12, 14, 36

16

LVDS channel 1—negative output

LVDS channel 1—positive output

LVDS channel 2—negative output

LVDS channel 2—positive output

LVDS channel 3—negative output

LVDS channel 3—positive output

LVDS channel 4—negative output

LVDS channel 4—positive output

LVDS channel 5—negative output

LVDS channel 5—positive output

LVDS channel 6—negative output

LVDS channel 6—positive output

LVDS channel 7—negative output

LVDS channel 7—positive output

LVDS channel 8—negative output

LVDS channel 8—positive output

Power-down input

15

18

17

20

19

22

21

28

27

30

29

32

31

34

33

13

REF_B

Negative reference input/output

Positive reference input/output

Active low RESET input

54

REF_T

55

RESET

SCLK

SDATA

TP

64

Serial clock input

63

Serial data input

62

Test pin, do not use

52

V_CM

Common-mode output pin, 1.5V output

53

8

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

FUNCTIONAL BLOCK DIAGRAM

LCLK_P

LCLK_N

6x ADCLK

Clock

Buffer

12x ADCLK

1x ADCLK

PLL

ADCLK_P

ADCLK_N

IN1_P

IN1_N

OUT1_P

OUT1_N

10-Bit

ADC

Digital

Serializer

IN2_P

IN2_N

OUT2_P

OUT2_N

10-Bit

ADC

IN3_P

IN3_N

OUT3_P

OUT3_N

10-Bit

ADC

IN4_P

IN4_N

OUT4_P

OUT4_N

10-Bit

ADC

IN5_P

IN5_N

OUT5_P

OUT5_N

10-Bit

ADC

IN6_P

IN6_N

OUT6_P

OUT6_N

10-Bit

ADC

IN7_P

IN7_N

OUT7_P

OUT7_N

10-Bit

ADC

IN8_P

IN8_N

OUT8_P

OUT8_N

10-Bit

ADC

Power-

Down

ADC

Control

Registers

Reference

9

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

LVDS TIMING DIAGRAM

Sample n

Sample n + 12

Analog Input

t_D(A)

Sample n + 13

Clock Input

t_SAMPLE

12 clocks latency

LCLK_N

6X ADCLK

LCLK_P

OUT_P

0

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

0

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

0

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

SERIAL DATA

OUT_N

ADCLK_N

1X ADCLK

ADCLK_P

t_PROP

DEFINITION OF SETUP AND HOLD TIMES

LCLK_N

LCLK_P

OUT_N

OUT_P

t_H1

t_SU1t_H2

t_SU2

t_SU= min(t_SU1, t_SU2

)

t_H= min(t_H1, t_H2

)

TIMING CHARACTERISTICS⁽¹⁾

ADS5287

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ns

t_A

Aperture delay

1.5

4.5

Aperture delay variation Channel-to-channel within the same device (3σ)

±20

400

ps

t_J

Aperture jitter

fs

Time to valid data after coming out of

COMPLETE POWER-DOWN mode

50

μs

Time to valid data after coming out of PARTIAL

POWER-DOWN mode (with clock continuing to

run during power-down)

t_WAKE

Wake-up time

2

Time to valid data after stopping and restarting

the input clock

40

12

Clock

cycles

Data latency

(1) Timing parameters are ensured by design and characterization; not production tested.

10

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

LVDS OUTPUT TIMING CHARACTERISTICS⁽¹⁾

Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of T_MIN= –40°C to T_MAX

=

+85°C, sampling frequency = as specified, C_LOAD= 5pF⁽²⁾, I_OUT= 3.5mA, R_LOAD= 100Ω⁽³⁾, and no internal termination, unless otherwise

noted.

ADS5287

40MSPS

TYP

50MSPS

TYP

65MSPS

TYP

PARAMETER

TEST CONDITIONS⁽⁴⁾

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Data valid⁽⁶⁾to zero-crossing of

LCLK_P

t_SU

t_H

Data setup time⁽⁵⁾

0.67

0.47

0.27

ns

Zero-crossing of LCLK_Pto data

becoming invalid⁽⁶⁾

Data hold time⁽⁵⁾

0.85

10

0.65

10

0.4

9.7

41

ns

Input clock (ADCLK) rising edge

cross-over to output clock (ADCLK_P)

rising edge cross-over

t_PROP

Clock propagation delay

LVDS bit clock duty cycle

14

16.6

53

12.5

14.1

53.5

11.5

14

57

Duty cycle of differential clock,

(LCLK_P– LCLK_N)

45.5

50

250

150

0.2

45

50

250

150

0.2

50

250

150

0.2

Bit clock cycle-to-cycle

jitter

ps, pp

ns

Frame clock cycle-to-cycle

jitter

t_RISE

t_FALL

,

Data rise time, data fall

time

Rise time is from –100mV to +100mV

Fall time is from +100mV to –100mV

0.09

0.4

0.09

0.4

0.09

0.4

t_CLKRISE

t_CLKFALL

,

Output clock rise time,

output clock fall time

Rise time is from –100mV to +100mV

Fall time is from +100mV to –100mV

ns

(1) Timing parameters are ensured by design and characterization; not production tested.

(2) C_LOADis the effective external single-ended load capacitance between each output pin and ground.

(3) I_OUTrefers to the LVDS buffer current setting; R_LOADis the differential load resistance between the LVDS output pair.

(4) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.

(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(6) Data valid refers to a logic high of +100mV and a logic low of –100mV.

LVDS OUTPUT TIMING CHARACTERISTICS⁽¹⁾

Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of T_MIN= –40°C to T_MAX

=

+85°C, sampling frequency = as specified, C_LOAD= 5pF⁽²⁾, I_OUT= 3.5mA, R_LOAD= 100Ω⁽³⁾, and no internal termination, unless otherwise

noted.

ADS5287

30MSPS

TYP

20MSPS

TYP

10MSPS

TYP

PARAMETER

TEST CONDITIONS⁽⁴⁾

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Data valid⁽⁶⁾to zero-crossing of

LCLK_P

t_SU

t_H

Data setup time⁽⁵⁾

0.8

1.5

3.7

ns

Zero-crossing of LCLK_Pto data

becoming invalid⁽⁶⁾

Data hold time⁽⁵⁾

1.2

9.5

1.9

9.5

48

3.9

10

49

ns

Input clock (ADCLK) rising edge

cross-over to output clock (ADCLK_P)

rising edge cross-over

t_PROP

Clock propagation delay

LVDS bit clock duty cycle

13.5

17.3

52

14.5

17.3

51

14.7

17.1

51

Duty cycle of differential clock,

(LCLK_P– LCLK_N)

46.5

50

250

150

0.2

50

250

150

0.2

50

750

500

0.2

Bit clock cycle-to-cycle

jitter

ps, pp

ns

Frame clock cycle-to-cycle

jitter

t_RISE

t_FALL

,

Data rise time, data fall

time

Rise time is from –100mV to +100mV

Fall time is from +100mV to –100mV

0.09

0.4

0.09

0.4

0.09

0.4

t_CLKRISE

t_CLKFALL

,

Output clock rise time,

output clock fall time

Rise time is from –100mV to +100mV

Fall time is from +100mV to –100mV

ns

(1) Timing parameters are ensured by design and characterization; not production tested.

(2) C_LOADis the effective external single-ended load capacitance between each output pin and ground.

(3) I_OUTrefers to the LVDS buffer current setting; R_LOADis the differential load resistance between the LVDS output pair.

(4) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.

(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(6) Data valid refers to a logic high of +100mV and a logic low of –100mV.

11

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LVDS OUTPUT TIMING CHARACTERISTICS

TIMINGS WHEN USING REGISTER 0xE3⁽²⁾

PARAMETER⁽¹⁾

TEST CONDITIONS

At 40 MSPS

MIN

0.60

0.92

TYP

MAX

Data setup time

Data valid⁽³⁾to zero-crossing of LCLKp

Data hold time

Zero-crossing of LCLKP to data becoming invalid⁽³⁾

Input clock (ADCLK) rising edge cross-over to output clock (ADCLK) rising edge

crossover

Clock propagation delay

8

12

14.6

(1) Only the setup time, hold time and clock propagation delay parameters are affected. Rest of the parameters are same as given in

previous two tables.

(2) Only timing specifications for 40MSPS are affected when using register 0xE3 (as specified in the recommended operating table section).

The timing specifications for other clock frequencies are same as given in previous two tables.

(3) Data valid refers to logic high of +100mV and logic low of –100mV.

RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING

t₁

AVDD (3V to 3.6V)

AVDD

t₂

LVDD (1.7V to 1.9V)

t₃

LVDD

t₄

t₇

High-Level RESET

(1.4V to 3.6V)

t₅

RESET

t₆

Device Ready for

Serial Register Write⁽²⁾

High-Level CS

(1.4V to 3.6V)

CS

Device Ready for

Data Conversion

Start of Clock

ADCLK

t₈

10μs < t₁< 50ms, 10μs < t₂< 50ms, –10ms < t₃< 10ms, t₄> 10ms, t₅> 100ns, t₆> 100ns, t₇> 10ms, and t₈> 100μs.

(1) The AVDD and LVDD power-on sequence does not matter as long as –10ms < t₃< 10ms. Similar considerations apply while shutting

down the device.

(2) Write initialization registers listed in the Initialization Registers table.

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ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

POWER-DOWN TIMING

1ms

t_WAKE

PD

Device Fully

Powers Down

Device Fully

Powers Up

Power-up time shown is based on 1μF bypass capacitors on the reference pins. t_WAKEis the time it takes for the device to wake up

completely from power-down mode. The ADS5287 has two power-down modes: complete power-down mode and partial power-down mode.

The device can be configured in partial power-down mode through a register setting.

t_WAKE< 50μs for complete power-down mode.

t_WAKE< 2μs for partial power-down mode (provided the clock is not shut off during power-down).

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SERIAL INTERFACE

The ADS5287 has a set of internal registers that can be accessed through the serial interface formed by pins CS

(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the

following actions occur:

•

Serial shift of bits into the device is enabled

SDATA (serial data) is latched at every rising edge of SCLK

SDATA is loaded into the register at every 24th SCLK rising edge

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16

bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds

(a few hertz) and also with a non-50% SCLK duty cycle.

Register Initialization

After power-up, the internal registers must be initialized to the respective default values. Initialization can be

done in one of two ways:

1. Through a hardware reset, by applying a low-going pulse on the RESET pin; or

2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the

internal registers to the respective default values and then self-resets the RST bit low. In this case, the

RESET pin stays high (inactive).

SERIAL INTERFACE TIMING

Start Sequence

End Sequence

CS

t₆

t₁

t₇

t₂

Data latched on rising edge of SCLK

SCLK

t₃

D15 D14 D13 D12 D11 D10 D9

SDATA

A7 A6 A5 A4 A3 A2 A1 A0

D8 D7 D6 D5 D4 D3 D2 D1 D0

t₄

t₅

ADS5287

PARAMETER

DESCRIPTION

SCLK period

MIN

TYP

MAX

UNIT

ns

t₁

t₂

t₃

t₄

t₅

t₆

t₇

50

20

5

SCLK high time

SCLK low time

Data setup time

Data hold time

CS fall to SCLK rise

ns

5

ns

8

ns

Time between last SCLK rising edge to CS rising edge

8

ns

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ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

SERIAL REGISTER MAP

Table 3. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE^{(1) (2) (3) (4)}

ADDRESS

IN HEX

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NAME

DESCRIPTION

DEFAULT

00

X

RST

Self-clearing software RESET.

Inactive

Channel-specific ADC power-

down mode.

X

PDN_CH<8:1>

PDN_PARTIAL

PDN_COMPLETE

PDN_PIN_CFG

Inactive

Partial power-down mode (fast

recovery from power-down).

X

0F

Register mode for complete

power-down (slower recovery).

X

Configures the PD pin for partial

power-down mode.

Complete

power-down

X

LVDS current drive

X

ILVDS_LCLK<2:0> programmability for LCLK_Nand

LCLK_Ppins.

3.5mA drive

LVDS current drive

ILVDS_FRAME

11

X

programmability for ADCLK_Nand 3.5mA drive

ADCLK_Ppins.

<2:0>

LVDS current drive

X

ILVDS_DAT<2:0> programmability for OUT_Nand

OUT_Ppins.

3.5mA drive

Enables internal termination for

EN_LVDS_TERM

Termination

disabled

X

1

LVDS buffers.

Programmable termination for

TERM_LCLK<2:0>

Termination

disabled

X

LCLK_Nand LCLK_Pbuffers.

12

TERM_FRAME

<2:0>

Programmable termination for

ADCLK_Nand ADCLK_Pbuffers.

Termination

disabled

X

Programmable termination for

OUT_Nand OUT_Pbuffers.

Termination

disabled

X

TERM_DAT<2:0>

LFNS_CH<8:1>

Channel-specific, low-frequency

noise suppression mode enable.

14

24

X

0

X

0

X

0

X

Inactive

IN_Pis

positive

input

Swaps the polarity of the analog

input pins electrically.

INVERT_CH<8:1>

EN_RAMP

Enables a repeating full-scale

ramp pattern on the outputs.

Inactive

Enables the mode wherein the

output toggles between two

defined codes.

DUALCUSTOM_

PAT

X

Enables the mode wherein the

output is a constant specified

code.

SINGLE_CUSTOM

_PAT

0

X

Inactive

25

2MSBs for a single custom

pattern (and for the first code of

the dual custom pattern). <9> is

the MSB.

BITS_CUSTOM1

<9:8>

X

Inactive

BITS_CUSTOM2

<9:8>

2MSBs for the second code of

the dual custom pattern.

X

8 lower bits for the single custom

pattern (and for the first code of

the dual custom pattern). <0> is

the LSB.

BITS_CUSTOM1

<7:0>

26

27

X

BITS_CUSTOM2

<7:0>

8 lower bits for the second code

of the dual custom pattern.

X

GAIN_CH1<3:0>

GAIN_CH2<3:0>

GAIN_CH3<3:0>

GAIN_CH4<3:0>

GAIN_CH5<3:0>

GAIN_CH6<3:0>

GAIN_CH7<3:0>

GAIN_CH8<3:0>

Programmable gain channel 1.

Programmable gain channel 2.

Programmable gain channel 3.

Programmable gain channel 4.

Programmable gain channel 5.

Programmable gain channel 6.

Programmable gain channel 7.

Programmable gain channel 8.

0dB gain

X

2A

2B

X

(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.

(2) X = Register bit referenced by the corresponding name and description (default is 0).

(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.

(4) Multiple functions in a register should be programmed in a single write operation.

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Table 3. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE^{(1) (2) (3) (4)}(continued)

ADDRESS

IN HEX

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NAME

DESCRIPTION

DEFAULT

Single-

ended clock

1

X

DIFF_CLK

Differential clock mode.

Enables the duty-cycle correction

circuit.

X

EN_DCC

Disabled

External

reference

drives REF_T

and REF_B

42

Drives the external reference

mode through the V_CMpin.

1

X

EXT_REF_VCM

PHASE_DDR<1:0>

Controls the phase of LCLK

output relative to data.

X

90 degrees

0

X

0

PAT_DESKEW

PAT_SYNC

Enables deskew pattern mode.

Enables sync pattern mode.

Inactive

45

46

X

Binary two's complement format

for ADC output.

Straight

offset binary

1

X

BTC_MODE

MSB_FIRST

Serialized ADC output comes

out MSB-first.

LSB-first

output

X

Enables SDR output mode

(LCLK becomes a 12x input

clock).

DDR output

mode

1

X

1

EN_SDR

Controls whether the LCLK rising Rising edge

or falling edge comes in the

middle of the data window when

operating in SDR output mode.

of LCLK in

middle of

data window

X

FALL_SDR

SUMMARY OF FEATURES

POWER IMPACT (relative to default)

AT f_S= 65MSPS

FEATURES

DEFAULT

SELECTION

ANALOG FEATURES

Internal or external reference

(driven on the REF_Tand REF_Bpins)

Internal reference mode takes approximately 23mW more power on

AVDD

N/A

External reference driven on the V_CMpin

Duty cycle correction circuit

Off

Register 42

Approximately 9mW less power on AVDD

Approximately 7mW more power on AVDD

With zero input to the ADC, low-frequency noise suppression causes

digital switching at f_S/2, thereby increasing LVDD power by

approximately 7mW/channel

Low-frequency noise suppression

Off

Register 14

Register 42

Differential clock mode takes approximately 7mW more power on

AVDD

Single-ended or differential clock

Power-down mode

Single-ended

Off

Refer to the Power-Down Modes section in the Electrical

Characteristics table

Pin and register 0F

DIGITAL FEATURES

Programmable digital gain (0dB to 12dB)

Straight offset or BTC output

Swap polarity of analog input pins

LVDS OUTPUT PHYSICAL LAYER

LVDS internal termination

0dB

Straight offset

Off

Registers 2A and 2B No difference

Register 46

Register 24

No difference

Off

Register 12

Register 11

Approximately 7mW more power on AVDD

LVDS current programmability

LVDS OUTPUT TIMING

3.5mA

As per LVDS clock and data buffer current setting

LSB- or MSB-first output

LSB-first

DDR

Register 46

Register 42

No difference

SDR mode takes approximately 2mW more power on LVDD

(at f_S= 30MSPS)

DDR or SDR output

LCLK phase relative to data output

Refer to Figure 1

No difference

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ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

DESCRIPTION OF SERIAL REGISTERS

SOFTWARE RESET

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

00

X

RST

Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears

to '0'.

POWER-DOWN MODES

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

X

PDN_CH<8:1>

PDN_PARTIAL

PDN_COMPLETE

PDN_PIN_CFG

X

0F

0

X

0

X

Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for

the ADC channel <N>.

In addition to channel-specific power-down, the ADS5287 also has two global power-down modes—partial

power-down mode and complete power-down mode. Partial power-down mode partially powers down the chip;

recovery from this mode is much quicker, provided that the clock has been running for at least 50μs before

exiting this mode. Complete power-down mode, on the other hand, completely powers down the chip, and

involves a much longer recovery time.

In addition to programming the device for either of these two power-down modes (through either the

PDN_PARTIAL or PDN_COMPLETE bits, respectively), the PD pin itself can be configured as either a partial

power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when the

PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when the PD pin

is high, the device enters partial power-down mode.

LVDS DRIVE PROGRAMMABILITY

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

X

ILVDS_LCLK<2:0>

ILVDS_FRAME<2:0>

ILVDS_DAT<2:0>

11

X

The LVDS drive strength of the bit clock (LCLK_Por LCLK_N) and the frame clock (ADCLK_Por ADCLK_N) can be

individually programmed. The LVDS drive strengths of all the data outputs OUT_Pand OUT_Ncan also be

programmed to the same value.

17

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

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All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 4

shows an example of how the drive strength of the bit clock is programmed (the method is similar for the frame

clock and data drive strengths).

Table 4. Bit Clock Drive Strength⁽¹⁾

ILVDS_LCLK<2>

ILVDS_LCLK<1>

ILVDS_LCLK<0>

LVDS DRIVE STRENGTH FOR LCLK_PAND LCLK_N

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3.5mA (default)

2.5mA

1.5mA

0.5mA

7.5mA

6.5mA

5.5mA

4.5mA

(1) Current settings lower than 1.5mA are not recommended.

LVDS INTERNAL TERMINATION PROGRAMMABILITY

ADDRESS

IN HEX

D15

D14

X

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

EN_LVDS_TERM

TERM_LCLK<2:0>

TERM_FRAME<2:0>

TERM_DAT<2:0>

1

X

12

1

X

1

X

The LVDS buffers have high-impedance current sources driving the outputs. When driving traces whose

characteristic impedance is not perfectly matched with the termination impedance on the receiver side, there may

be reflections back to the LVDS output pins of the ADS5287 that cause degraded signal integrity. By enabling an

internal termination (between the positive and negative outputs) for the LVDS buffers, the signal integrity can be

significantly improved in such scenarios. To set the internal termination mode, the EN_LVDS_TERM bit should

be set to '1'. Once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers

can be independently programmed using sets of three bits. Table 5 shows an example of how the internal

termination of the LVDS buffer driving the bit clock is programmed (the method is similar for the frame clock and

data buffers). These termination values are only typical values and can vary by up to ±20% across temperature

and from device to device.

Table 5. Bit Clock Drive Strengths

INTERNAL TERMINATION BETWEEN

TERM_LCLK<2>

TERM_LCLK<1>

TERM_LCLK<0>

LCLK_PAND LCLK_NIN Ω

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

260

150

94

125

80

66

55

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ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

LOW-FREQUENCY NOISE SUPPRESSION MODE

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

14

X

LFNS_CH<8:1>

The low-frequency noise suppression mode is specifically useful in applications where good noise performance is

desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of

the ADS5287 to approximately f_S/2, thereby moving the noise floor around dc to a much lower value.

LFNS_CH<8:1> enables this mode individually for each channel.

ANALOG INPUT INVERT

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

24

X

INVERT_CH<8:1>

Normally, the IN_Ppin represents the positive analog input pin, and IN_Nrepresents the complementary negative

input. Setting the bits marked INVERT_CH<8:1> (individual control for each channel) causes the inputs to be

swapped. IN_Nnow represents the positive input, and IN_Pthe negative input.

LVDS TEST PATTERNS

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

X

D5

0

D4

0

D3

D2

D1

D0

NAME

EN_RAMP

0

X

0

DUALCUSTOM_PAT

SINGLE_CUSTOM_PAT

BITS_CUSTOM1<9:8>

BITS_CUSTOM2<9:8>

BITS_CUSTOM1<7:0>

BITS_CUSTOM2<7:0>

PAT_DESKEW

25

0

X

26

27

X

0

X

0

45

X

PAT_SYNC

The ADS5287 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal

ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern.

The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the full-

scale code, it returns back to zero code and ramps again.

The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and

programming the desired code in BITS_CUSTOM1<9:0>. In this mode, BITS_CUSTOM1<9:0> take the place of

the 10-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as

normal ADC data are.

The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT

to '1'. The two codes are represented by the contents of BITS_CUSTOM1<9:0> and BITS_CUSTOM2<9:0>.

In addition to custom patterns, the device may also be made to output two preset patterns:

1. Deskew patten: Set using PAT_DESKEW, this mode causes the 12 serial bits to come out as

010101010101 (the rightmost bit representing the first bit in the LSB-first mode)

2. Sync pattern: Set using PAT_SYNC, this mode causes the 12 serial bits to come out as 111111000000 (the

rightmost bit representing the first bit in the LSB-first mode)

Note that only one of the above patterns should be active at any given instant.

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ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

PROGRAMMABLE GAIN

ADDRESS

www.ti.com

IN HEX

D15

D14

D13

D12

D11

D10

X

D9

X

D8

X

D7

D6

D5

D4

D3

D2

D1

D0

NAME

X

GAIN_CH1<3:0>

GAIN_CH2<3:0>

GAIN_CH3<3:0>

GAIN_CH4<3:0>

GAIN_CH5<3:0>

GAIN_CH6<3:0>

GAIN_CH7<3:0>

GAIN_CH8<3:0>

X

2A

X

2B

X

In applications where the full-scale swing of the analog input signal is much less than the 2V_PPrange supported

by the ADS5287, a programmable gain can be set to achieve the full-scale output code even with a lower analog

input swing. The programmable gain not only fills the output code range of the ADC, but also enhances the SNR

of the device by utilizing quantization information from some extra internal bits. The programmable gain for each

channel can be individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain

setting is coded in binary from 0dB to 12dB, as shown in Table 6.

Table 6. Gain Setting for Channel 1

GAIN_CH1<3>

GAIN_CH1<2>

GAIN_CH1<1>

GAIN_CH1<0>

CHANNEL 1 GAIN SETTING

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

Do not use

20

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

CLOCK, REFERENCE, AND DATA OUTPUT MODES

ADDRESS

IN HEX

D15

1

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

X

D2

D1

D0

NAME

DIFF_CLK

X

1

X

EN_DCC

42

1

EXT_REF_VCM

PHASE_DDR<1:0>

BTC_MODE

MSB_FIRST

EN_SDR

1

X

1

X

1

X

46

1

X

1

X

FALL_SDR

INPUT CLOCK

The ADS5287 is configured by default to operate with a single-ended input clock—CLK_Pis driven by a CMOS

clock and CLK_Nis tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a

differential input clock on CLK_Pand CLK_N. Operating with a low-jitter differential clock usually gives better SNR

performance, especially at input frequencies greater than 30MHz.

In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable

an internal duty cycle correction circuit. This enabling is done by setting the EN_DCC bit to '1'.

EXTERNAL REFERENCE

The ADS5287 can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,

the REF_Tand REF_Bpins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have

enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The

advantage of using the external reference mode is that multiple ADS5287 units can be made to operate with the

same external reference, thereby improving parameters such as gain matching across devices. However, in

applications that do not have an available high drive, differential external reference, the ADS5287 can still be

driven with a single external reference voltage on the V_CMpin. When EXT_REF_VCM is set as '1' (and the

INT/EXT pin is set to '0'), the V_CMpin is configured as an input pin, and the voltages on REF_Tand REF_Bare

generated as shown in Equation 1 and Equation 2.

V_CM

VREF_T= 1.5V +

1.5V

(1)

V_CM

VREF_B= 1.5V -

1.5V

(2)

21

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

BIT CLOCK PROGRAMMABILITY

The output interface of the ADS5287 is normally a DDR interface, with the LCLK rising edge and falling edge

transitions in the middle of alternate data windows. Figure 1 shows this default phase.

ADCLK_P

LCLK_P

OUT_P

Figure 1. Default Phase of LCLK

The phase of LCLK can be programmed relative to the output frame clock and data using bits

PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 2.

PHASE_DDR<1:0> = '00'

PHASE_DDR<1:0> = '10'

ADCLK_P

LCLK_P

OUT_P

PHASE_DDR<1:0> = '01'

PHASE_DDR<1:0> = '11'

ADCLK_P

LCLK_P

OUT_P

Figure 2. Phase Programmability Modes for LCLK

22

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR

mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12x times the input clock, or

twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two

manners shown in Figure 3. As shown in Figure 3, only the LCLK rising (or falling) edge is used to capture the

output data in SDR mode.

EN_SDR = '1', FALL_SDR = '0'

ADCLK_P

LCLK_P

OUT_P

EN_SDR = '1', FALL_SDR = '1'

ADCLK_P

LCLK_P

OUT_P

Figure 3. SDR Interface Modes

The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.

DATA OUTPUT FORMAT MODES

The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the

MSB, and the output becomes binary two's complement mode.

Also by default, the first two bits of the frame (following the rising edge of ADCLK_P) are zeroes, followed by the

LSB of the ADC output. Programming the MSB_FIRST mode inverts the bit order in the word. Thus, in the

MSB_FIRST mode, the MSB is output as the first bit following the ADCLK_Prising edge. The two zeroes come

after the LSB at the end of the word.

23

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

TYPICAL CHARACTERISTICS

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

SPECTRAL PERFORMANCE

(f_S= 40MHz, f_IN= 10MHz)

SPECTRAL PERFORMANCE

(f_S= 40MHz, f_IN= 25MHz)

0

-20

0

SFDR = 82.5dBc

SNR = 61.76dBFS

SINAD = 61.72dBFS

SFDR = 84.8dBc

-20

SNR = 61.8dBFS

SINAD = 61.79dBFS

THD = 87.6dBc

-40

-40 THD = 80.9dBc

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

Input Frequency (MHz)

Figure 4.

Figure 5.

SPECTRAL PERFORMANCE

(f_S= 50MHz, f_IN= 10MHz)

SPECTRAL PERFORMANCE

(f_S= 50MHz, f_IN= 25MHz)

0

-20

0

-20

SFDR = 84.7dBc

SNR = 61.78dBFS

SINAD = 61.77dBFS

THD = 86.5dBc

SFDR = 85.5dBc

SNR = 61.75dBFS

SINAD = 61.72dBFS

THD = 83.1dBc

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

0

5

10

15

20

25

0

5

10

15

20

25

Input Frequency (MHz)

Figure 6.

Figure 7.

24

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

TYPICAL CHARACTERISTICS (continued)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

SPECTRAL PERFORMANCE

(f_S= 65MHz, f_IN= 10MHz)

SPECTRAL PERFORMANCE

(f_S= 65MHz, f_IN= 25MHz)

0

-20

0

-20

SFDR = 86.9dBc

SFDR = 85.9dBc

SNR = 62.02dBFS

SNR = 61.73dBFS

SINAD = 61.72dBFS

THD = 86.5dBc

SNR (0MHz to 1MHz) = 76.5dBFS

SINAD = 62dBFS

THD = 84.1dBc

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

0

5

10

15

20

25

30 33

0

5

10

15

20

25

30 33

Input Frequency (MHz)

Figure 8.

Figure 9.

SPECTRAL PERFORMANCE, LOW-FREQUENCY NOISE

SUPPRESSION MODE ENABLED

DYNAMIC PERFORMANCE

vs

(f_S= 65MHz, f_IN= 25MHz)

INPUT FREQUENCY

0

90

85

80

75

70

65

60

SFDR = 85.8dBc

SNR = 62.1dBFS

-20

-40

SNR (0MHz to 1MHz) = 77dBFS

SINAD = 62dBFS

THD = 84.6dBc

SFDR (dBc)

-60

-80

f_S= 40MHz

-100

-120

-140

-160

SNR (dBFS)

15

0

5

10

15

20

25

30 33

5

10

20

25

30

Input Frequency (MHz)

Figure 10.

Figure 11.

25

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

DYNAMIC PERFORMANCE

vs

DYNAMIC PERFORMANCE

vs

INPUT FREQUENCY

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

SFDR (dBc)

f_S= 65MHz

f_S= 50MHz

SNR (dBFS)

20

SNR (dBFS)

20

5

10

15

25

30

5

10

15

25

30

Input Frequency (MHz)

Figure 12.

Figure 13.

DYNAMIC PERFORMANCE

vs

DIGITAL GAIN

AVDD

93

88

83

78

73

68

63

58

90

85

80

75

70

65

60

Output amplitude adjusted to -1dBFS for each gain setting.

SFDR (dBc)

f_S= 65MHz

f_IN= 10MHz

f_S= 65MHz

f_IN= 10MHz

SNR (dBFS)

0

2

4

6

8

10

12

3.0

3.1

3.2

3.3

3.4

3.5

3.6

Digital Gain (dB)

AVDD (V)

Figure 14.

Figure 15.

26

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

TYPICAL CHARACTERISTICS (continued)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

DYNAMIC PERFORMANCE

vs

DYNAMIC PERFORMANCE

vs

INPUT AMPLITUDE

CLOCK AMPLITUDE

90

85

80

75

70

65

60

90

80

70

60

50

40

30

20

10

SFDR (dBc)

SNR (dBFS)

f_S= 65MHz

f_IN= 10MHz

SFDR (dBc)

f_S= 65MHz

f_IN= 10MHz

SNR (dBFS)

0.1

0.6

1.1

1.6

2.1 2.3

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5

0

Clock Amplitude (V_PPDifferential)

Input Amplitude (dBFS)

Figure 16.

Figure 17.

DYNAMIC PERFORMANCE

vs

ANALOG INPUT COMMON-MODE VOLTAGE

EXTERNAL REFERENCE DIFFERENTIAL VOLTAGE

90

85

80

75

70

65

60

90

SFDR (dBc)

85

80

75

70

65

60

f_S= 65MHz

f_IN= 10MHz

f_S= 65MHz

f_IN= 10MHz

External reference common-mode voltage

maintained at 1.5V.

SNR (dBFS)

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70

External Reference Differential Voltage, REF_T- REF_B(V)

Analog Input Common-Mode Voltage (V)

Figure 18.

Figure 19.

27

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

DYNAMIC PERFORMANCE

vs

EXTERNAL REFERENCE COMMON-MODE VOLTAGE

EXTERNAL REFERENCE FORCED THROUGH V_CM

90

85

80

75

70

65

60

SFDR (dBc)

85

80

75

70

65

60

f_S= 65MHz

f_IN= 10MHz

f_S= 65MHz

f_IN= 10MHz

External reference differential voltage maintained at 2V.

SNR (dBFS)

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.35

1.40

1.45

1.50

1.55

1.60

1.65

External Reference Common-Mode Voltage, (REF_T+ REF_B)/2 (V)

Voltage on V_CM(V)

Figure 20.

Figure 21.

DYNAMIC PERFORMANCE

vs

DYNAMIC PERFORMANCE

vs

CLOCK DUTY CYCLE

(DCC DISABLED)

(DCC ENABLED)

90

95

90

85

80

75

70

65

60

85

80

75

70

65

60

55

SFDR (dBc)

f_S= 65MHz

f_IN= 10MHz

f_S= 65MHz

f_IN= 10MHz

SNR (dBFS)

60

35

40

45

50

55

60

65

20

30

40

50

70

80

Clock Duty Cycle (%)

Figure 22.

Figure 23.

28

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

TYPICAL CHARACTERISTICS (continued)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

HISTOGRAM OF OUTPUT CODE FOR ZERO INPUT

INTERMODULATION DISTORTION

70

60

50

40

30

20

10

0

10

-10

f_S= 65MHz

61.1%

f_S= 65MSPS

f₁= 10MHz (-7dBFS)

f₂= 16.1MHz (-7dBFS)

IMD = -96dBFS

-30

38.9%

-50

-70

-90

-110

-130

-150

0%

512

513

514

0

2

4

6

8

10

12

14

16

18

20

511

Code Bin (LSB)

Input Frequency (MHz)

Figure 24.

Figure 25.

DIFFERENTIAL NONLINEARITY

(f_S= 65MSPS, f_IN= 5MHz)

INTEGRAL NONLINEARITY

0.20

0.15

0.10

0.05

0

0.10

0.08

0.06

0.04

0.02

0

-0.20

-0.40

-0.60

-0.80

-0.10

-0.05

-0.10

-0.15

-0.20

f_S= 65MSPS

f_IN= 5MHz

64

192

320

448

576

704

832

960

64

320

576

832

960

Code (LSB)

Figure 26.

Figure 27.

29

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of T_MIN

=

–40°C to T_MAX= +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, I_SETresistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted.Typical values at +25°C.

AVDD AND LVDD POWER-SUPPLY CURRENTS

vs

CLOCK FREQUENCY

OVERLOAD RECOVERY AT 65MSPS

0.6

0.5

0.4

0.3

0.2

0.1

0

170

150

130

110

90

Zero Input on All Channels

Internal Reference Mode

I_AVDD

Standard Deviation of

1st Point After Overload

Standard Deviation of

2nd Point After Overload

70

I_LVDD

50

f_S= 65MSPS

f_IN= 5MHz

30

5

15

25

35

45

55

65

75

0

1

2

3

4

5

6

Clock Frequency (MSPS)

Overload Signal Amplitude (dBFS)

Figure 28.

Figure 29.

16384 t_S(Group 1)

First point after overload (Set 1)

Second point after overload (Set 1)

+FS

Set 1, Point 1 (of 16)

Set 1, Point 2 (of 16)

t_S

Overload

Amplitude

-FS

Second point after overload (Set 2)

First point after overload (Set 2)

NOTES:

Input sine wave phase is repetitive over 16384 clock cycles.

16 such repetitive groups (of 16384 clock cycles) are captured–a total of 262,144 points.

Standard deviation of every set of first and second points after overload are analyzed over the 16 groups.

Worst case of all such standard deviations are plotted in the graphs.

Figure 30. Overload Recovery

30

ADS5287

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SBAS428D –JANUARY 2008–REVISED JUNE 2012

APPLICATION INFORMATION

The ADC output goes to a serializer that operates

from a 12x clock generated by the PLL. The 12 data

bits from each channel are serialized and sent LSB

first. In addition to serializing the data, the serializer

also generates a 1x clock and a 6x clock. These

clocks are generated in the same way the serialized

data are generated, so these clocks maintain perfect

synchronization with the data. The data and clock

outputs of the serializer are buffered externally using

LVDS buffers. Using LVDS buffers to transmit data

THEORY OF OPERATION

The ADS5287 is an 8-channel, high-speed, CMOS

ADC. Two zeroes are appended on the LSB side to

the 10 bits given out by each channel. The resulting

12 bits are serialized and sent out on a single pair of

pins in LVDS format. All eight channels of the

ADS5287 operate from a single clock (ADCLK). The

sampling clocks for each of the eight channels are

generated from the input clock using a carefully

matched clock buffer tree. The 12x clock required for

the serializer is generated internally from ADCLK

using a phase-locked loop (PLL). A 6x and a 1x clock

are also output in LVDS format, along with the data,

to enable easy data capture. The ADS5287 operates

from internally-generated reference voltages that are

trimmed to achieve a high level of accuracy. Trimmed

references improve the gain matching across

devices, and provide the option to operate the

devices without having to externally drive and route

reference lines. The nominal values of REF_Tand

REF_Bare 2.5V and 0.5V, respectively. The

references are internally scaled down differentially by

a factor of 2. This scaling results in a differential input

of –1V to correspond to the zero code of the ADC,

and a differential input of +1V to correspond to the

full-scale code (1023 LSB). V_CM(the common-mode

voltage of REF_Tand REF_B) is also made available

externally through a pin, and is nominally 1.5V.

externally has multiple advantages, such as

a

reduced number of output pins (saving routing space

on the board), reduced power consumption, and

reduced effects of digital noise coupling to the analog

circuit inside the ADS5287.

The ADS5287 operates from two sets of supplies and

grounds. The analog supply and ground set is

identified as AVDD and AVSS, while the digital set is

identified by LVDD and LVSS.

ANALOG INPUT

The analog input consists of a switched-capacitor

based, differential sample-and-hold architecture. This

differential topology results in very good ac

performance, even for high input frequencies at high

sampling rates. The IN_Nand IN_Ppins must be

externally biased around a common-mode voltage of

1.5V, available on V_CM. For a full-scale differential

input, each input pin (IN_Nand IN_P) must swing

symmetrically between V_CM+ 0.5V and V_CM– 0.5V,

resulting in a 2V_PPdifferential input swing. The

maximum input peak-to-peak differential swing is

determined to be the difference between the internal

reference voltages REF_T(2.5V nominal) and REF_B

(0.5V nominal). Figure 31 illustrates the model of the

input driving circuit.

The ADC employs a pipelined converter architecture

that consists of a combination of multi-bit and single-

bit internal stages. Each stage feeds its data into the

digital error correction logic, ensuring excellent

differential linearity and no missing codes at the 10-

bit level.

31

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

5nH to 9nH (TQFP-80)

2nH to 3nH (QFN-64)

IN

OUT

IN_P

1.5pF to

1.5pF

2.5pF

5W

15W

to 2.4pF

to 10W

to 25W

to 30W

1W

IN

OUT

IN

OUT

1000W

to 1440W

OUT

OUT_P

OUT_N

0.2pF

to 0.3pF

IN

1000W

to 1440W

16W to 32W

1.5pF

5W

15W

to 2.4pF

to 10W

to 25W

to 30W

IN

OUT

IN

OUT

5nH to 9nH (TQFP-80)

2nH to 3nH (QFN-64)

IN_N

1.5pF to

2.5pF

Switches that are ON

in SAMPLE phase.

IN

OUT

1W

Switches that are ON

in HOLD phase.

Figure 31. Analog Input Circuit Model

during ac-coupling by increasing V_CMby roughly

75mV. When operating above 50MSPS, it is

recommended that additional parallel resistors be

added externally to restore the input common-mode

to at least 1.4V, if the inputs are to be ac-coupled.

Input Common-Mode Current

The input stage of all eight ADCs together sinks a

common-mode current on the order of 2mA at

50MSPS. Equation 3 describes the dependency of

the common-mode current and the sampling

frequency.

ADS5287

(2mA) ´ f_S

IN_P

1.2kW

50MSPS

(3)

Input

Circuitry

If the driving stage is dc-coupled to the inputs, then

Equation 3 can be used to determine its common-

mode drive capability and impedance. The inputs can

also be ac-coupled to the IN_Nand IN_Ppins. In that

case, the input common-mode is set by two internal

1.2kΩ resistors connecting the input pins to V_CM. This

architecture is shown in Figure 32.

1.2kW

IN_N

Internal

V_CM

Voltage

Reference

CM Buffer

When the inputs are ac-coupled, there is a drop in

the voltages at IN_Pand IN_Nrelative to V_CM. This can

be computed from Equation 3. At 50MSPS, for

example, the drop at each of the 16 input pins is

150mV, which is not optimal for ADC operation.

Initialization Registers 1 and 5, described in the

Initialization Register table, can be used to partially

reduce the effect of this input common-mode drop

Dashed area denotes one of eight channels.

Figure 32. Common-Mode Biasing of Input Pins

32

ADS5287

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Driving Circuit

At high input frequencies, the mismatch in the

transformer parasitic capacitance (between the

windings) results in degraded even-order harmonic

For optimum performance, the analog inputs must be

driven differentially. This approach improves the

common-mode noise immunity and even-order

harmonic rejection. Input configurations using RF

transformers suitable for low and high input

frequencies are shown in Figure 33 and Figure 34,

respectively. The single-ended signal is fed to the

primary winding of the RF transformer. The

transformer is terminated by 50Ω resistor on the

secondary side. Placing the termination on the

secondary side helps to shield the kicks caused by

the input sampling capacitors from the RF

transformer leakage inductances. The termination is

accomplished by two 25Ω resistors, connected in

series, with the center point connected to the 1.5V

common-mode. The 4.7Ω resistor in series with each

input pin is required to damp the ringing caused by

the device package parasitics.

performance.

Connecting

two

identical

RF

transformers back-to-back helps to minimize this

mismatch, and good performance is obtained for

high-frequency

input

signals.

An

additional

termination resistor pair is required between the two

transformers, as shown in Figure 34. The center point

of this termination is connected to ground to improve

the balance between the positive and negative sides.

The values of the terminations between the

transformers and on the secondary side must be

chosen to achieve an overall 50Ω (in the case of 50Ω

source impedance).

4.7W

IN_P

0.1mF

1:1

25W

0.1mF

25W

4.7W

IN_N

V_CM

Figure 33. Drive Circuit at Low Input Frequencies

1:2

2:1

IN_P

0.1mF

200W

50W

0.1mF

IN_N

V_CM

Figure 34. Drive Circuit at High Input Frequencies

33

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

CLOCK INPUT

The eight channels on the device operate from a

single ADCLK input. To ensure that the aperture

delay and jitter are the same for all channels, a clock

tree network is used to generate individual sampling

clocks to each channel. The clock paths for all the

channels are matched from the source point to the

sampling circuit. This architecture ensures that the

performance and timing for all channels are identical.

The use of the clock tree for matching introduces an

aperture delay that is defined as the delay between

the rising edge of ADCLK and the actual instant of

sampling. The aperture delays for all the channels

are matched to the best possible extent. A mismatch

of ±20ps (±3σ) could exist between the aperture

instants of the eight ADCs within the same chip.

However, the aperture delays of ADCs across two

different chips can be several hundred picoseconds

apart.

V_CM

5kW

CLK_P

CLK_N

Figure 36. Internal Clock Buffer

0.1mF

CLK_P

The ADS5287 can be made to operate either in

CMOS single-ended clock mode (default is

DIFF_CLK = 0) or differential clock mode (SINE,

LVPECL, or LVDS). When operating in the single-

Differential Sine-Wave,

PECL, or LVDS Clock Input

0.1mF

CLK_N

ended clock mode, CLK_Nmust be forced to 0V_DC

,

and the single-ended CMOS applied on the CLK_Ppin.

This operation is shown in Figure 35.

Figure 37. Differential Clock Driving Circuit

(DIFF_CLK = 1)

CMOS Single-Ended

CLK_P

Clock

0.1mF

CMOS Clock Input

CLK_P

CLK_N

0V

CLK_N

0.1mF

Figure 35. Single-Ended Clock Driving Circuit

(DIFF_CLK = 0)

When configured to operate in the differential clock

mode (register bit DIFF_CLK = 1) the ADS5287 clock

inputs can be driven differentially (SINE, LVPECL, or

LVDS) with little or no difference in performance

between them, or with a single-ended (LVCMOS).

The common-mode voltage of the clock inputs is set

to V_CMusing internal 5kΩ resistors, as shown in

Figure 36. This method allows using transformer-

coupled drive circuits for a sine wave clock or ac-

coupling for LVPECL and LVDS clock sources, as

shown in Figure 37. When operating in the differential

clock mode, the single-ended CMOS clock can be ac-

coupled to the CLK_Pinput, with CLK_N(pin 11)

connected to ground with a 0.1μF capacitor, as

shown in Figure 38.

Figure 38. Single-Ended Clock Driving Circuit

When DIFF_CLK = 1

For best performance, the clock inputs must be

driven differentially in order to reduce susceptibility to

common-mode noise. For high input frequency

sampling, it is recommended to use a clock source

with very low jitter. Bandpass filtering of the clock

source can help reduce the effect of jitter. If the duty

cycle deviates from 50% by more than 2% or 3%, it is

recommended to enable the DCC through register bit

EN_DCC.

34

ADS5287

www.ti.com

SBAS428D –JANUARY 2008–REVISED JUNE 2012

PLL OPERATION ACROSS SAMPLING

FREQUENCY

Step 2: Disable the PLL automatic switch and set

the PLL configuration depending on the clock

frequency

The ADS528X uses a PLL for generating the high

speed bit clock (LCLK), the frame clock (ADCLK) &

internal clocks for the serializer operation.

SAMPLE CLOCK FREQUENCY

REGISTER SETTING (Hex)

RANGE (MSPS)

Min

10

Max

25

Address

E3

Data

0060

00A0

To enable operation across the entire frequency

range, the PLL is automatically configured to one of

four states, depending on the sampling clock

frequency range. The frequency range detection is

automatic and each time the sampling frequency

15

45

E3

With the above settings applied for the respective

frequency ranges, the part will continue to

operate as per the stated datasheet specifications

for all timing parameters at all specified

frequencies, EXCEPT for the timing specifications

at 40MSPS. At 40MSPS, the affected parameters

are – Data setup time, Data hold time and Clock

propagation delay (refer to LVDS Timing ).

crosses

a

threshold, the PLL changes its

configuration to a new state. To prevent unwanted

toggling of PLL state around a threshold, the circuit

has an inbuilt hysteresis. The ADS528x has three

thresholds – taking into account the hysteresis range

of each threshold, variation across devices and

temperature, the thresholds can span the sampling

clock frequency range from 10MHz to 45MHz.

2. For sampling clock frequency ≥ 45MSPS

Threshold 1

Threshold 2

Threshold 3

As there are no PLL thresholds beyond 45MHz,

no change in PLL configuration can occur as the

temperature in the system stabilizes. The

ADS528x can be used in the system without

using the above software fix.

INPUT OVER-VOLTAGE RECOVERY

The differential peak-to-peak full-scale range

supported by the ADS5287 is nominally 2.0V. The

ADS5287 is specially designed to handle an over-

voltage condition where the differential peak-to-peak

voltage can be up to twice the ADC full-scale range.

If the input common-mode is not considerably off

from V_CMduring overload (less than 300mV around

the nominal value of 1.5V), recovery from an over-

voltage pulse input of twice the amplitude of a full-

scale pulse is expected to be within one clock cycle

when the input switches from overload to zero signal.

45 MHz

65 MHz

10 MHz

Sampling Frequency

Figure 39. Variation of Thresholds Across

Sampling Frequency

Based on actual system clock frequency, there are

two scenarios:

1. For sampling clock frequency < 45MSPS

After system power up, depending on the

frequency of operation and the frequency

threshold for the given device, the frequency

range detection circuit may change state once. In

some applications where a timing calibration

might be done at the system level once after

power up, this subsequent change of the PLL

state might be undesirable as it can cause a loss

of alignment in the received data. A software fix

for eliminating this one-time change of PLL state

exists using the serial register interface:

REFERENCE CIRCUIT

The digital beam-forming algorithm in an ultrasound

system relies on gain matching across all receiver

channels. A typical system would have about 12 octal

ADCs on the board. In such a case, it is critical to

ensure that the gain is matched, essentially requiring

the reference voltages seen by all the ADCs to be the

same. Matching references within the eight channels

of a chip is done by using a single internal reference

voltage buffer. Trimming the reference voltages on

each chip during production ensures that the

reference voltages are well-matched across different

chips.

–

Disable the automatic switch of the PLL

configuration based on frequency detected.

In addition to disabling the switching, it is also

required to set the PLL to the correct

configuration, depending on the sample clock

frequency used in the system.

–

All bias currents required for the internal operation of

the device are set using an external resistor to

ground at the I_SETpin. Using a 56.2kΩ resistor on I_SET

generates an internal reference current of 20μA. This

current is mirrored internally to generate the bias

current for the internal blocks. Using a larger external

The following sequence of register writes must be

followed:

Step 1: Write Address = 0x01, Data = 0x0010

35

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

resistor at I_SETreduces the reference bias current and

thereby scales down the device operating power.

However, it is recommended that the external resistor

be within 10% of the specified value of 56.2kΩ so

that the internal bias margins for the various blocks

are proper.

The device also supports the use of external

reference voltages. There are two methods to force

the references externally. The first method involves

pulling INT/EXT low and forcing externally REF_Tand

REF_Bto 2.5V and 0.5V nominally, respectively. In this

mode, the internal reference buffer goes to a 3-state

output. The external reference driving circuit should

be designed to provide the required switching current

for the eight ADCs inside the chip. It should be noted

that in this mode, V_CMand I_SETcontinue to be

generated from the internal bandgap voltage, as in

the internal reference mode. It is therefore important

to ensure that the common-mode voltage of the

externally-forced reference voltages matches to

Buffering the internal bandgap voltage also generates

the common-mode voltage V_CM, which is set to the

midlevel of REF_Tand REF_B, and is accessible on pin

53. It is meant as a reference voltage to derive the

input common-mode if the input is directly coupled. It

can also be used to derive the reference common-

mode voltage in the external reference mode. The

suggested decoupling for the reference pins is shown

in Figure 40.

within 50mV of V_CM

.

The second method of forcing the reference voltages

externally can be accessed by pulling INT/EXT low,

and programming the serial interface to drive the

external reference mode through the V_CMpin (register

bit called EXT_REF_VCM). In this mode, V_CM

becomes configured as an input pin that can be

driven from external circuitry. The internal reference

buffers driving REF_Tand REF_Bare active in this

mode. Forcing 1.5V on the V_CMpin in the mode

results in REF_Tand REF_Bcoming to 2.5V and 0.5V,

respectively. In general, the voltages on REF_Tand

REF_Bin this mode are given by Equation 4 and

Equation 5, respectively:

ADS5287

I_SET

REF_T

REF_B

56.2kW

0W to

2W

0.1mF

2.2mF

0.1mF

V_CM

VREF_T= 1.5V +

1.5V

(4)

Figure 40. Suggested Decoupling on the

Reference Pins

V_CM

VREF_B= 1.5V -

1.5V

(5)

Table 7 describes the state of the reference voltage

internal buffers during various combinations of the

PD, INT/EXT, and EXT_REF_VCM register bits.

Table 7. State of Reference Voltages for Various Combinations of PD, INT/EXT, and EXT_REF_VCM

REGISTER BIT

PD

INTERNAL BUFFER STATE

0

1

0

1

0

1

0

1

INT/EXT

1

0

1

EXT_REF_VCM

REF_Tbuffer

REF_Bbuffer

V_CMpin

0

1

3-state

1.5V

2.5V

0.5V

1.5V

3-state

1.5V

2.5V⁽¹⁾

0.5V⁽¹⁾

1.5V

1.5V + V_CM/1.5V

1.5V – V_CM/1.5V

Force

Do not use

2.5V⁽¹⁾

0.5V⁽¹⁾

Force

Do not use

(1) Weakly forced with reduced strength.

sections, while LVDD and LVSS are used to denote

the digital supplies. Care is taken to ensure that there

is minimal interaction between the supply sets within

the device. The extent of noise coupled and

transmitted from the digital to the analog sections

depends on:

NOISE COUPLING ISSUES

High-speed mixed signals are sensitive to various

types of noise coupling. One primary source of noise

is the switching noise from the serializer and the

output buffers. Maximum care is taken to isolate

these noise sources from the sensitive analog blocks.

As a starting point, the analog and digital domains of

the device are clearly demarcated. AVDD and AVSS

are used to denote the supplies for the analog

1. The effective inductances of each of the supply

and ground sets.

2. The isolation between the digital and analog

supply and ground sets.

36

ADS5287

www.ti.com

SBAS428D –JANUARY 2008–REVISED JUNE 2012

Smaller effective inductance of the supply and ground

pins leads to better noise suppression. For this

reason, multiple pins are used to drive each supply

and ground. It is also critical to ensure that the

impedances of the supply and ground lines on the

board are kept to the minimum possible values. Use

of ground planes in the printed circuit board (PCB) as

well as large decoupling capacitors between the

supply and ground lines are necessary to obtain the

best possible SNR performance from the device.

It is recommended that the isolation be maintained on

the board by using separate supplies to drive AVDD

and LVDD, as well as separate ground planes for

AVSS and LVSS. The use of LVDS buffers reduces

the injected noise considerably, compared to CMOS

buffers. The current in the LVDS buffer is

independent of the direction of switching. Also, the

low output swing as well as the differential nature of

the LVDS buffer results in low-noise coupling.

37

ADS5287

SBAS428D –JANUARY 2008–REVISED JUNE 2012

www.ti.com

REVISION HISTORY

Changes from Revision B (March 2008) to Revision C

Page

•

Changed Initialization Registers section to include Initialization Register 1 ......................................................................... 3

In the Input Common-Mode Current section, changed Initialization Register 5 to Initialization Registers 1 and 5 to

reflect change in Initialization Registers table .................................................................................................................... 32

Changes from Revision C (March 2008) to Revision D

Page

•

Added table in the INITIALIZATION REGISTERS section ................................................................................................... 3

Added table in the LVDS OUTPUT TIMING CHARACTERISTICS section ....................................................................... 12

Added PLL OPERATION ACROSS SAMPLING FREQUENCY section ............................................................................ 35

38

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS5287IRGCR

ADS5287IRGCT

VQFN

RGC

64

2000

250

330.0

16.4

9.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS5287IRGCR

ADS5287IRGCT

VQFN

RGC

64

2000

250

336.6

28.6

Pack Materials-Page 2

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型号：	ADS5287IRGCTG4
厂家：	TEXAS INSTRUMENTS
描述：	10-Bit, Octal-Channel ADC Up to 65MSPS 10位，八通道ADC多达65MSPS
文件：	总42页 (文件大小：824K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS5287IRGCTG4 [TI]

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