ADS5295PFPR_技术文档

ADS5295

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SBAS595 –DECEMBER 2012

12-Bit, 100-MSPS, 8-Channel Analog-to-Digital Converter

Check for Samples: ADS5295

1

FEATURES

DESCRIPTION

The ADS5295 is a low-power, 12-bit, 100-MSPS, 8-

channel analog-to-digital converter (ADC). Low power

consumption and integration of multiple channels in a

compact package make the device attractive for very

high channel count data acquisition systems.

2

•

Maximum Sample Rate: 100 MSPS

Designed for Low Power:

–

80 mW per channel at 100 MSPS

•

SNR: 70.6 dBFS

SFDR: 85 dBc at 10 MHz, 100 MSPS

Serial LVDS ADC Data Outputs:

Serial low-voltage differential signaling (LVDS)

outputs reduce the number of interface lines and

enable high system integration. The ADC digital data

can be output over one or two wires of LVDS pins per

channel. At high sample rates, the two-wire interface

helps keep the serial data rate low, allowing low-cost

–

One- or Two-Wire Serialized LVDS Outputs

per Channel

One-Wire Interface:

Up to 80 MSPS Sample Rate

field-programmable

receivers to be used.

gate

array

(FPGA)-based

Two-Wire Interface:

Up to 100 MSPS Sample Rate

The device integrates an internal reference trimmed

to accurately match across devices. Best

performance is expected to be achieved through the

internal reference mode. However, the device can be

driven with external references as well.

•

Digital Processing Block:

–

Programmable FIR Decimation Filter and

Oversampling to Minimize Harmonic

Interference

Several digital functions that are commonly used in

systems are included in the device. These functions

include a low-frequency suppression mode, digital

filtering options, and programmable mapping.

–

Programmable IIR High-Pass Filter to

Minimize DC Offset

Programmable Digital Gain: 0 dB to 12 dB

•

Low-Frequency Noise Suppression Mode

For low input frequency applications, the low-

frequency noise suppression mode enables noise

suppression at low frequencies and improves signal-

to-noise ratio (SNR) in the 1-MHz band near dc by

approximately 3 dB. Digital filtering options include

low-pass, high-pass, and band-pass digital filters, as

well as dc offset removal filters. The device also

provides programmable mapping of the LVDS output

pins and analog input channels. For applications

where the 12-bit ADC SNR is not required, the

ADS5295 can be configured as an 8-channel, 10-bit

ADC with 10x LVDS serialization to reduce the output

data rate.

Programmable Mapping Between ADC Input

Channels and LVDS Output Pins

•

Channel Averaging Mode

Variety of LVDS Test Patterns to Verify

Data Capture by FPGA or Receiver

•

Package: 12-mm × 12-mm QFP-80

APPLICATIONS

•

Ultrasound Imaging

Communication Applications

Multichannel Data Acquisition

The device is available in a 12-mm × 12-mm QFP-80

package. The ADS5295 is specified over the –40°C

to +85°C operating temperature range.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS5295

SBAS595 –DECEMBER 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

SPECIFIED TEMPERATURE

PRODUCT

PACKAGE-LEAD

PACKAGE DESIGNATOR

RANGE

PACKAGE MARKING

ORDERING NUMBER

ADS5295

TQFP-80

PFP

–40°C to +85°C

ADS5295

ADS5295IPFP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

PARAMETER

AVDD

VALUE

–0.3 to 2.2

UNIT

V

Supply voltage range

Voltage between

LVDD

–0.3 to 2.2

V

AGND and LGND

–0.3 to 0.3

V

AVDD to LVDD (when AVDD leads LVDD)

LVDD to AVDD (when LVDD leads AVDD)

INP, INN

0 to 2.2

V

0 to 2.2

V

–0.3 to min (2.2, AVDD + 0.3)

V

RESET, SCLK, SDATA, CS, PD, SYNC,

CLKP, CLKN⁽²⁾

Voltage applied to

–0.3 to min (2.2, AVDD + 0.3)

V

Digital outputs

–0.3 to min (2.2, LVDD + 0.3)

V

Operating free-air, T_A

Operating junction, T_J

Storage, T_stg

–40 to +85

+105

°C

V

Temperature range

–55 to +150

2000

Electrostatic discharge (ESD) rating

Human body model (HBM)

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP and CLKN is less than |0.3 V|.

This setting prevents the ESD protection diodes at the clock input pins from turning on.

THERMAL INFORMATION

ADS5295

THERMAL METRIC⁽¹⁾

PFP (TQFP)

80 PINS

30.8

UNITS

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

6.3

8.3

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

8.2

θ_JCbot

0.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

UNIT

SUPPLIES

AVDD

Analog supply voltage

Digital supply voltage

1.7

1.8

1.9

V

LVDD

ANALOG INPUTS

V_ID

Differential input voltage range

Input common-mode voltage

External reference mode

2

VCM ± 0.05

1.45

V_PP

V

REFT

REFB

VCM

V

External reference mode

0.45

V

Common-mode voltage output

0.95

V

CLOCK INPUTS (ADCLK Input Sample Rate)

One-wire LVDS interface

Two-wire LVDS interface

Sine-wave, ac-coupled

LVPECL, ac-coupled

LVDS, ac-coupled

V_IL

10

80

MSPS

V_PP

V

ADCLK input sample rate (1 / t_C)

100

1.5

1.6

Input clock amplitude differential

(VCLKP – VCLKN)

0.7

< 0.3

> 1.5

50

Input clock CMOS single-ended

(VCLKP)

V_IH

V

Input clock duty cycle

35

65

%

DIGITAL OUTPUTS

1x

ADCLKP and ADCLKN outputs (LVDS), one-wire

(sample rate in

MSPS)

MHz

ADCLKP and ADCLKN outputs (LVDS), two-wire

0.5x

(sample rate in

MSPS)

6x

(sample rate in

MSPS)

12x serialization

LCLKP and LCLKN outputs

(LVDS), one-wire

5x

(sample rate in

MSPS)

10x serialization

12x serialization

3x

(sample rate in

MSPS)

LCLKP and LCLKN outputs

(LVDS), two-wire

2.5x

(sample rate in

MSPS)

10x serialization

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ELECTRICAL CHARACTERISTICS: General

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and

LVDD = 1.8 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

Resolution

ANALOG INPUTS

12

Bits

Differential input voltage range

Differential input resistance

Differential input capacitance

Analog input bandwidth

2.0

2

V_PP

kΩ

At dc

3.7

500

pF

MHz

Analog input common-mode current

(per input pin)

1

µA/MSPS

VCM

Common-mode output voltage

VCM output current capability

0.95

5

V

mA

DYNAMIC ACCURACY

E_O

Offset error

–20

20

mV

Resulting from internal

reference inaccuracy alone

E_GREF

E_GCHAN

–1.5

1.5

%FS

Gain error

Of channel itself

0.5

%FS

E_GCHANtemperature coefficient

POWER SUPPLY

< 0.01

Δ%FS/°C

IAVDD

ILVDD

AVDD

LVDD

Analog supply current

100 MSPS

206

150

225

163

mA

100 MSPS, two-wire LVDS interface, 350-mV

swing with 100-Ω external termination

Output buffer supply current

Analog power

100 MSPS

370.8

270

mW

100 MSPS, two-wire LVDS interface, 350-mV

swing with 100-Ω external termination

Digital power

100 MSPS, two-wire LVDS interface, 350-mV

swing with 100-Ω external termination

Total power

640.8

192

mW

Global power-down

Standby power

45

mW

4

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ELECTRICAL CHARACTERISTICS: Dynamic Performance

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, maximum rated sampling frequency, 50% clock duty cycle,

100 MSPS, two-wire LVDS interface, and –1-dBFS differential analog input, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and

LVDD = 1.8 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

70.6

70.4

69.7

70.4

70

MAX

UNIT

dBFS

dBc

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 70 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 70 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 70 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 70 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 70 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 70 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 70 MHz

67.5

SNR

Signal-to-noise ratio

66

72.5

71

SINAD

SFDR

THD

Signal-to-noise and distortion ratio

Spurious-free dynamic range

Total harmonic distortion

68.9

86

79

dBc

76.3

85

dBc

78.4

75.8

89.5

86

dBc

72.5

75

dBc

HD2

Second-harmonic distortion

Third-harmonic distortion

dBc

HD3

79

dBc

76.4

95

dBc

Worst spur

(other than second and third harmonics)

93

dBc

82.3

dBc

f₁= 8 MHz, f₂= 10 MHz,

each tone at –7 dBFS

IMD

Two-tone intermodulation distortion

Crosstalk

86

1

dBc

dB

10-MHz full-scale signal on aggressor channel;

5-MHz input signal applied on victim channel

Recovery to within 1% (of full-scale) for

6-dB overload with sine-wave input

Clock

cycle

Input overload recovery

For 50-mV_PPsignal on AVDD supply,

up to 10 MHz, no signal applied to analog

inputs

PSRR

AC power-supply rejection ratio

60

dB

ENOB

DNL

INL

Effective number of bits

Differential nonlinearity

Integrated nonlinearity

f_IN= 5 MHz

11.4

±0.05

0.4

LSBs

–0.82

0.82

1.1

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DIGITAL CHARACTERISTICS

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level '0' or '1'. AVDD = 1.8 V and DRVDD = 1.8 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (RESET, SCLK, SDATA, CS, SYNC, PDN)

All pins support 1.8-V and 3.3-V CMOS

logic levels

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.3

V

All pins support 1.8-V and 3.3-V CMOS

logic levels

0.4

I_IH

I_IL

High-level input current

Low-level input current

CS, SDATA, SCLK⁽¹⁾

V_HIGH= 1.8 V

V_LOW= 0 V

6

µA

0.1

DIGITAL OUTPUTS (CMOS INTERFACE: SDOUT)

V_OH

V_OL

High-level output voltage

Low-level output voltage

AVDD – 0.1

V

0.1

DIGITAL OUTPUTS (LVDS INTERFACE: OUT1A_P, OUT1A_N to OUT8A_P, OUT8A_N and OUT1B_P, OUT1B_N to OUT8B_P, OUT8B_N)

V_ODH

V_ODL

V_OCM

High-level output differential voltage⁽²⁾

Low-level output differential voltage⁽²⁾

Output common-mode voltage

300

-485

0.95

485

-300

1.35

mV

V

(1) CS, SDATA, and SCLK have an internal 220-kΩ pull-down resistor.

(2) With an external 100-Ω termination.

6

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TIMING REQUIREMENTS⁽¹⁾

Typical values are at +25°C, AVDD = 1.8 V, LVDD = 1.8 V, sampling frequency = 100 MSPS, sine-wave input clock, C_LOAD

=

5 pF, and R_LOAD= 100 Ω, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and

LVDD = 1.7 V to 1.9 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_A

Aperture delay

4

ns

Aperture delay matching

Variation of aperture delay

Aperture jitter

Between any two channels of the same device

±200

ps

Between two devices at the same temperature and

LVDD supply

±1

ns

t_J

Sample uncertainty

320

5

fs rms

µs

Time to valid data after coming out of standby

Wake-up time

ADC latency⁽²⁾

Time to valid data after coming out of global power-

down mode

100

µs

One-wire LVDS Output interface

Two-wire LVDS Output interface

12

16

Clock cycles

TWO-WIRE, 12x SERIALIZATION

t_SU

t_H

Data setup time

Data hold time

Data valid to zero-crossing of LCLKP

0.52

0.62

ns

Zero-crossing of LCLKP to data becoming invalid

t_PDI

(11/12)

× t_S

=

Input clock rising edge crossover to output clock

rising edge crossover

t_PDI

Clock propagation delay

ns

+

t_DELAY

Delay time

8.5

11

13.5

ns

%

Duty cycle of differential clock

(LCLKP – LCLKN)

LVDS bit clock duty cycle

50

ACROSS ALL SERIALIZATION MODES

Rise time measured from –100 mV to +100 mV,

10 MSPS ≤ sampling frequency ≤ 100 MSPS

t_FALL

Data fall time

0.11

ns

Rise time measured from –100 mV to +100 mV,

10 MSPS ≤ sampling frequency ≤ 100 MSPS

t_RISE

Data rise time

Rise time measured from –100 mV to +100 mV,

10 MSPS ≤ sampling frequency ≤ 100 MSPS

t_CLKRISE

t_CLKFALL

Output clock rise time

Output clock fall time

Rise time measured from –100 mV to +100 mV,

10 MSPS ≤ sampling frequency ≤ 100 MSPS

(1) Timing parameters are ensured by design and characterization, but are not tested in production.

(2) At higher frequencies, t_PDIis greater than one clock period and the overall latency = ADC latency + 1.

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Table 1. Two-Wire, 12x Serialization⁽¹⁾⁽²⁾

t_PDI= (11/12) × t_S+ t_DELAY

Where t_DELAYis specified as

below, ns

SETUP TIME (ns)

TYP

HOLD TIME (ns)

MIN TYP

SAMPLING

FREQUENCY (MSPS)

MIN

7.80

2.40

1.10

0.83

0.60

0.52

MAX

MIN

8.5

TYP

11

MAX

13.5

10

30

8.00

2.50

1.60

1.25

1.00

0.62

11

50

11

65

11

80

11

100

11

(1) All the timing specifications are taken with default output clock and data delay settings (0 ps).

(2) Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for output clock and data delay

options.

Table 2. One-Wire, 12x Serialization⁽¹⁾⁽²⁾

t_PDI= (9/12) × t_S+ t_DELAY

Where t_DELAYis specified as

SETUP TIME (ns)

MIN TYP

HOLD TIME (ns)

MIN TYP

below, ns

SAMPLING

FREQUENCY (MSPS)

MAX

MIN

8

TYP

10

MAX

12

10

30

50

65

80

3.90

1.00

0.60

0.40

0.22

4.00

1.30

0.57

0.34

0.24

8

10

12

8

10

12

8

10

12

8

10

12

(1) All the timing specifications are taken with default output clock and data delay settings (0 ps).

(2) Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for output clock and data delay

options.

Table 3. Two-Wire, 10x Serialization⁽¹⁾⁽²⁾

SETUP TIME (ns)

TYP

HOLD TIME (ns)

TYP

SAMPLING FREQUENCY

(MSPS)

MIN

1.00

0.74

0.44

MAX

MIN

1.50

1.20

1.00

MAX

65

80

100

(1) All the timing specifications are taken with default output clock and data delay settings (0 ps).

(2) Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for output clock and data delay

options.

Table 4. One-Wire, 10x Serialization⁽¹⁾⁽²⁾

SETUP TIME (ns)

TYP

HOLD TIME (ns)

TYP

SAMPLING FREQUENCY

(MSPS)

MIN

0.51

0.33

0.17

MAX

MIN

0.60

0.36

0.31

MAX

65

80

100

(1) All the timing specifications are taken with default output clock and data delay settings (0 ps).

(2) Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for output clock and data delay

options.

8

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PARAMETRIC MEASUREMENT INFORMATION

LATENCY TIMING

Figure 1 shows a timing diagram of the LVDS output voltage levels.

OUTP

Logic 0

V_ODL= -350 mV⁽¹⁾

Logic 1

V_ODH= +350 mV⁽¹⁾

OUTN

V_OCM

GND

(1) With an external 100-Ω termination.

Figure 1. LVDS Output Voltage Levels

Figure 2 shows a latency timing diagram.

Sample

N + 11

Sample

N + 12

Sample

N + 13

Sample

N

Input Signal

t_A

CLKN

CLKP

Input Clock

Frequency = f_S

Latency = 12 Clocks

t_PDI

LCLKP

LCLKN

Bit Clock

Frequency = 6x f_S

OUTP

OUTN

Output Data

Rate = 12x f_S

D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 D11 D10

D9

D8

D7

D6

D5

D4

D1

D0

D3

D2

D11 D10 D9 D8

Sample N-1

Sample N

ADCLKN

ADCLKP

Frame Clock

Frequency = 1x f_S

Figure 2. Latency Timing Diagram

LVDS OUTPUT TIMING

Figure 3 shows the output timing described in the Timing Requirements table.

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PARAMETRIC MEASUREMENT INFORMATION (continued)

CLKN

Input

Clock

CLKP

t_PDI

ADCLKN

Frame

Clock

ADCLKP

t_SU

t_H

LCLKP

LCLKN

Bit

Clock

t_SU

t_H

t_SU

t_H

OUT1, OUT2,

OUT3, OUT4,

OUT5, OUT6,

OUT7, OUT8

Output

Data

Dn⁽¹⁾

Dn+1⁽¹⁾

(1) n = 0 to 11.

Figure 3. LVDS Output Timing

10

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PIN DESCRIPTION

PFP PACKAGE

TQFP-80

(Top View)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

IN2P

IN2N

1

2

3

4

5

6

7

8

9

60 IN7N

59 IN7P

AGND

IN3P

58 AGND

57 IN6N

IN3N

56 IN6P

AGND

IN4P

55 AGND

54 IN5N

IN4N

53 IN5P

AVDD

52 AVDD

PD 10

LVDD 11

LGND 12

51 RESET

50 LGND

49 LVDD

OUT1A_P 13

OUT1A_N 14

OUT1B_P 15

OUT1B_N 16

OUT2A_P 17

OUT2A_N 18

OUT2B_P 19

OUT2B_N 20

48 OUT8A_N

47 OUT8A_P

46 OUT8B_N

45 OUT8B_P

44 OUT7A_N

43 OUT7A_P

42 OUT7B_N

41

OUT7B_P

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

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PIN DESCRIPTIONS

NAME

ADCLKN

ADCLKP

AGND

NO.

FUNCTION⁽¹⁾

DESCRIPTION

30

DO

G

Differential LVDS frame clock (1x), negative

Differential LVDS frame clock (1x), positive

Analog ground pin

29

3, 6, 55, 58, 61, 80

9, 52, 66, 71, 74

AVDD

S

Analog supply pin, 1.8 V

Differential clock input, negative

For a single-ended clock, tie CLKN to 0 V

CLKN

73

AI

CLKP

CS

72

75

79

78

2

AI

DI

Differential clock input, positive

Serial enable chip select; active low digital input

Differential analog input for channel 1, negative

Differential analog input for channel 1, positive

Differential analog input for channel 2, negative

Differential analog input for channel 2, positive

Differential analog input for channel 3, negative

Differential analog input for channel 3, positive

Differential analog input for channel 4, negative

Differential analog input for channel 4, positive

Differential analog input for channel 5, negative

Differential analog input for channel 5, positive

Differential analog input for channel 6, negative

Differential analog input for channel 6, positive

Differential analog input for channel 7, negative

Differential analog input for channel 7, positive

Differential analog input for channel 8, negative

Differential analog input for channel 8, positive

LVDS differential bit clock output pins (6x), negative

LVDS differential bit clock output pins (6x), positive

Digital ground pin

IN1N

AI

IN1P

AI

IN2N

AI

IN2P

1

AI

IN3N

5

AI

IN3P

4

AI

IN4N

8

AI

IN4P

7

AI

IN5N

54

53

57

56

60

59

63

62

32

31

12, 50

11, 49

67

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

AI

IN5P

AI

IN6N

AI

IN6P

AI

IN7N

AI

IN7P

AI

IN8N

AI

IN8P

AI

LCLKN

LCLKP

LGND

DO

G

LVDD

S

Digital and I/O power supply, 1.8 V

NC

—

Do not connect

OUT1A_N

OUT1A_P

OUT1B_N

OUT1B_P

OUT2A_N

OUT2A_P

OUT2B_N

OUT2B_P

OUT3A_N

OUT3A_P

OUT3B_N

OUT3B_P

OUT4A_N

OUT4A_P

OUT4B_N

OUT4B_P

DO

Channel 1 differential LVDS negative data output, one-wire

Channel 1 differential LVDS positive data output, one-wire

Channel 1 differential LVDS negative data output, two-wire

Channel 1 differential LVDS positive data output, two-wire

Channel 2 differential LVDS negative data output, one-wire

Channel 2 differential LVDS positive data output, one-wire

Channel 2 differential LVDS negative data output, two-wire

Channel 2 differential LVDS positive data output, two-wire

Channel 3 differential LVDS negative data output, one-wire

Channel 3 differential LVDS positive data output, one-wire

Channel 3 differential LVDS negative data output, two-wire

Channel 3 differential LVDS positive data output, two-wire

Channel 4 differential LVDS negative data output, one-wire

Channel 4 differential LVDS positive data output, one-wire

Channel 4 differential LVDS negative data output, two-wire

Channel 4 differential LVDS positive data output, two-wire

(1) Pin functionality: AI = analog input; DI = digital input; DO = digital output; G = ground; and S = supply.

12

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SBAS595 –DECEMBER 2012

PIN DESCRIPTIONS (continued)

NAME

NO.

34

33

36

35

38

37

40

39

42

41

44

43

46

45

48

47

10

69

70

51

77

76

64

65

68

FUNCTION⁽¹⁾

DO

DI

DESCRIPTION

OUT5B_N

OUT5B_P

OUT5A_N

OUT5A_P

OUT6B_N

OUT6B_P

OUT6A_N

OUT6A_P

OUT7B_N

OUT7B_P

OUT7A_N

OUT7A_P

OUT8B_N

OUT8B_P

OUT8A_N

OUT8A_P

PD

Channel 5 differential LVDS negative data output, two-wire

Channel 5 differential LVDS positive data output, two-wire

Channel 5 differential LVDS negative data output, one-wire

Channel 5 differential LVDS positive data output, one-wire

Channel 6 differential LVDS negative data output, two-wire

Channel 6 differential LVDS positive data output, two-wire

Channel 6 differential LVDS negative data output, one-wire

Channel 6 differential LVDS positive data output, one-wire

Channel 7 differential LVDS negative data output, two-wire

Channel 7 differential LVDS positive data output, two-wire

Channel 7 differential LVDS negative data output, one-wire

Channel 7 differential LVDS positive data output, one-wire

Channel 8 differential LVDS negative data output, two-wire

Channel 8 differential LVDS positive data output, two-wire

Channel 8 differential LVDS negative data output, one-wire

Channel 8 differential LVDS positive data output, one-wire

Power-down control input pin

REFB

AI

Negative reference input/output

REFT

AI

Positive reference input/output

RESET

DI

Active high RESET input

SCLK

DI

Serial clock input

SDATA

DI

Serial data input

SDOUT

DO

DI

Serial data output

SYNC

Synchronization input for reduced output data rate

Common-mode output pin, 0.95-V output

VCM

AI

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FUNCTIONAL BLOCK DIAGRAM

OUT1A_P

OUT1A_N

IN1P

IN1N

Sampling

Circuit

Digital Processing

Block

12-Bit ADC

Serializer

OUT1B_P

OUT1B_N

OUT2A_P

OUT2A_N

IN2P

IN2N

Sampling

Circuit

Digital Processing

Block

12-Bit ADC

Serializer

OUT2B_P

OUT2B_N

OUT3A_P

OUT3A_N

IN3P

IN3N

Sampling

Circuit

Digital Processing

Block

12-Bit ADC

Serializer

OUT3B_P

OUT3B_N

OUT4A_P

OUT4A_N

IN4P

IN4N

Sampling

Circuit

Digital Processing

Block

12-Bit ADC

Serializer

OUT4B_P

OUT4B_N

LCLKP

LCLKN

CLKP

CLKN

CLOCKGEN

PLL

ADCLKP

ADCLKN

SYNC

OUT5A_P

OUT5A_N

IN5P

IN5N

Sampling

Circuit

Digital Processing

Block

12-Bit ADC

Serializer

OUT5B_P

OUT5B_N

OUT6A_P

OUT6A_N

IN6P

IN6N

Sampling

Circuit

Digital Processing

Block

12-Bit ADC

Serializer

OUT6B_P

OUT6B_N

OUT7A_P

OUT7A_N

IN7P

IN7N

Sampling

Circuit

Digital Processing

Block

12-Bit ADC

Serializer

OUT7B_P

OUT7B_N

OUT8A_P

OUT8A_N

IN8P

IN8N

Sampling

Circuit

Digital Processing

Block

12-Bit ADC

Serializer

OUT8B_P

OUT8B_N

Control

Interface

Reference

SDOUT

Device

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TYPICAL CHARACTERISTICS: General

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

0

−10

0

−10

SNR = 70.8 dBFS

SINAD = 70.7 dBFS

SFDR = 91 dBc

SNR = 70.7 dBFS

SINAD = 70.4 dBFS

SFDR = 81.7 dBc

THD = 81.4 dBc

−20

THD = 87.3 dBc

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

10

20

30

40

50

0

10

20

30

40

50

Frequency (MHz)

G001

G002

Figure 4. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 100 MSPS)

Figure 5. FFT FOR 15-MHz INPUT SIGNAL

(Sample Rate = 100 MSPS)

0

−10

0

−10

SNR = 69.6 dBFS

SINAD = 68.9 dBFS

SFDR = 76.4 dBc

THD = 76.26 dBc

SNR = 70.9 dBFS

SINAD = 70.8 dBFS

SFDR = 88.4 dBc

THD = 87.9 dBc

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

10

20

30

40

50

0

5

10

15

20

25

Frequency (MHz)

G003

G004

Figure 6. FFT FOR 70-MHz INPUT SIGNAL

(Sample Rate = 100 MSPS)

Figure 7. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 50 MSPS)

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TYPICAL CHARACTERISTICS: General (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

0

SNR = 70.5 dBFS

SINAD = 70.4 dBFS

SFDR = 85.9 dBc

THD = 84.6 dBc

SNR = 67 dBFS

SINAD = 66.7 dBFS

SFDR = 75.6 dBc

THD = 77.2 dBc

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

G005

G006

Figure 8. FFT FOR 15-MHz INPUT SIGNAL

(Sample Rate = 50 MSPS)

Figure 9. FFT FOR 70-MHz INPUT SIGNAL

(Sample Rate = 50 MSPS)

0

−10

72

71.5

71

f_IN1= 8 MHz

f_IN2= 10 MHz

Each Tone at −7−dBFS Amplitude

Two−Tone IMD = −93.6 dBFS

−20

−30

−40

−50

70.5

70

−60

−70

−80

69.5

69

−90

−100

−110

−120

−130

−140

68.5

68

0

10

20

30

40

50

0

10

20

30

40

50

60

70

80

90 100

Frequency (MHz)

Input Signal Frequency (MHz)

G007

G008

Figure 10. FFT WITH TWO-TONE SIGNAL

Figure 11. SIGNAL-TO-NOISE RATIO vs

INPUT SIGNAL FREQUENCY

16

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TYPICAL CHARACTERISTICS: General (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

94

90

86

82

78

74

70

66

74

70

66

62

58

Input Frequency = 10 MHz

Input Frequency = 70 MHz

0

10

20

30

40

50

60

70

80

90 100

0

1

2

3

4

5

6

7

8

9

10 11 12

Input Signal Frequency (MHz)

Digital Gain (dB)

G009

G010

Figure 12. SPURIOUS-FREE DYNAMIC RANGE vs

INPUT SIGNAL FREQUENCY

Figure 13. SIGNAL-TO-NOISE RATIO vs

DIGITAL GAIN

120

110

100

90

73

90

SNR

SFDR (dBc)

SFDR (dBFS)

Input Frequency = 5 MHz

Input Frequency = 10MHz

Input Frequency = 70MHz

72.5

72

86

82

78

74

70

71.5

71

80

70

70.5

70

60

50

69.5

69

40

30

68.5

68

20

−50 −45 −40 −35 −30 −25 −20 −15 −10 −5

Input amplitude (dBFS)

0

1

2

3

4

5

6

7

8

9

10 11 12

G012

Digital Gain (dB)

G011

Figure 14. SPURIOUS-FREE DYNAMIC RANGE vs

DIGITAL GAIN

Figure 15. PERFORMANCE vs INPUT AMPLITUDE

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TYPICAL CHARACTERISTICS: General (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

90

89.5

89

72

84

83.5

83

72

Input Frequency = 5 MHz

SFDR

SNR

Input Frequency = 5 MHz

SFDR

SNR

71.5

71

71.5

71

88.5

88

70.5

70

82.5

82

70.5

70

87.5

87

69.5

69

81.5

81

69.5

69

86.5

68.5

80.5

80

68.5

68

86

68

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

35

40

45

50

55

60

65

Input Clock Duty Cycle (%)

Input Clock Amplitude, Differential (V_P-P

)

G013

G014

Figure 16. PERFORMANCE vs INPUT CLOCK AMPLITUDE

Figure 17. PERFORMANCE vs INPUT CLOCK DUTY CYCLE

92

90

88

86

84

82

80

78

76

74

72

73

72

71

70

69

68

72

Input Frequency = 5 MHz

SFDR

SNR

Input Frequency = 5 MHz

AVDD = 1.7 V

AVDD = 1.8 V

AVDD = 1.9 V

71.5

71

70.5

70

69.5

69

68.5

0.8

0.85

0.9

0.95

1

1.05

1.1

68

Analog Input Common−Mode Voltage (V)

−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85

Temperature (°C)

G015

G016

Figure 18. PERFORMANCE vs

INPUT COMMON-MODE VOLTAGE

Figure 19. SIGNAL-TO-NOISE RATIO vs

AVDD AND TEMPERATURE

18

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TYPICAL CHARACTERISTICS: General (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

90

88

86

84

82

80

78

110

105

100

95

Input Frequency = 5 MHz

AVDD = 1.7 V

AVDD = 1.8 V

AVDD = 1.9 V

Adjacent Channel

Near Channel

Far Channel

90

85

80

75

70

65

60

−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85

Temperature (°C)

10

20

30

40

50

60

70

Frequency of Aggressor Channel (MHz)

G017

G018

(1)

Figure 20. SPURIOUS-FREE DYNAMIC RANGE vs

AVDD AND TEMPERATURE

Figure 21. CROSSTALK vs FREQUENCY

0.2

0.4

0.3

0.1

0

0.2

0.1

0

−0.1

−0.2

−0.3

−0.1

−0.2

−0.3

−0.4

0

500 1000 1500 2000 2500 3000 3500 4000

0

500 1000 1500 2000 2500 3000 3500 4000

Output Codes (LSB)

G020

G021

Figure 22. INTEGRAL NONLINEARITY

Figure 23. DIFFERENTIAL NONLINEARITY

(1) Adjacent channel: Neighboring channels on the immediate left and right of the channel of interest.

Near channel: Channels on the same side of the package, except the immediate neighbors.

Far channel: Channels on the opposite side of the package.

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TYPICAL CHARACTERISTICS: Digital Processing

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

20

10

40

30

Low-Pass

High-Pass

Low-Pass

Band-Pass 1

Band-Pass 2

High-Pass

20

0

10

−10

−20

−30

−40

−50

−60

−70

−80

0

−10

−20

−30

−40

−50

−60

−70

−80

0

0.1

0.2

0.3

0.4

0.5

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (f_IN/f_S)

G024

G025

Figure 24. DIGITAL FILTER RESPONSE

(Decimate-by-2)

Figure 25. DIGITAL FILTER RESPONSE

(Decimate-by-4)

0

−10

0

−10

SNR = 73.9 dBFS

SINAD = 73.3 dBFS

SFDR = 82.1 dBc

THD = 81.1 dBc

SNR = 74.5 dBFS

SINAD = 73.82 dBFS

SFDR = 81.4 dBc

THD = 80.8 dBc

−20

−30

Decimate−by−2 Filter Enabled

2 Channels Averaged

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

5

10

15

20

25

0

10

20

30

40

50

Frequency (MHz)

G026

G027

Figure 26. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 100 MSPS, Decimation Filter = 2)

Figure 27. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 100 MSPS by Averaging Two Channels)

20

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TYPICAL CHARACTERISTICS: Digital Processing (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

0

SNR = 77.19 dBFS

SINAD = 77 dBFS

SFDR = 91.2 dBc

THD = 90.6 dBc

Decimate−by−4 Filter Enabled

SNR = 76.4 dBFS

SINAD = 72.9 dBFS

SFDR = 74.5 dBc

THD = 74.4 dBc

−10

−20

−30

4 Channels Averaged

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

5

10

12.5

0

10

20

30

40

50

Frequency (MHz)

G028

G029

Figure 28. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 100 MSPS, Decimation Filter = 4)

Figure 29. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 100 MSPS by Averaging Four Channels)

0

−10

3

0

SNR = 77 dBFS

SINAD = 77 dBFS

SFDR = 94.4 dBc

THD = 100.9 dBc

Decimate−by−8 Filter Enabled

−3

−20

−6

−30

−9

−40

−12

−15

−18

−21

−24

−50

−60

−70

−80

K = 2

K = 3

−27

−90

−30

−33

−36

−39

−42

−45

K= 4

−100

−110

−120

−130

−140

K = 5

K = 6

K = 7

K = 8

K = 9

K = 10

0

1

2

3

4

5

6

0.02

0.1

1

10 15

Frequency (MHz)

G030

G031

Figure 30. FFT FOR 5-MHz INPUT SIGNAL

USING CUSTOM DECIMATION-BY-8 FILTER

Figure 31. DIGITAL HIGH-PASS FILTER RESPONSE

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TYPICAL CHARACTERISTICS: Digital Processing (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

0

HPF_DISABLED

HPF_ENABLED (K = 2)

SNR = 70.7 dBFS

SINAD = 70.4 dBFS

SFDR = 82.9 dBc

THD = 82.1 dBc

−10

−20

−30

−40

−50

−60

−70

−60

−80

−70

−90

−80

−100

−110

−120

−130

−140

−90

−100

−110

−120

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

10

20

30

40

50

Frequency (MHz)

G032

G033

Figure 32. FFT WITH HPF ENABLED AND DISABLED

(No Signal)

Figure 33. FULL-BAND FFT, 5-MHz INPUT

(100-MHz FS with LFNS Enabled)

0

−10

LF Noise Suppression Enabled

LF Noise Suppression Disabled

LF Noise Suppression Enabled

LF Noise Suppression Disabled

−10

−20

−30

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Frequency (MHz)

1

49 49.1 49.2 49.3 49.4 49.5 49.6 49.7 49.8 49.9 50

Frequency (MHz)

G034

G035

Figure 34. 0-MHz to 1 MHz FFT, 5-MHz INPUT

(100-MHz FS with LFNS Enabled)

Figure 35. 49-MHz to 50-MHz FFT, 5-MHz INPUT

(100-MHz FS with LFNS Enabled)

22

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TYPICAL CHARACTERISTICS: Power Consumption

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

390

360

330

300

270

240

210

180

150

120

300

275

250

225

200

175

150

125

100

Two−Wire

One−Wire

One−Wire, Decimate−By−2

One−Wire, Decimate−By−4

10

20

30

40

50

60

70

80

90

100

10

20

30

40

50

60

70

80

90

100

Sampling Frequency (MHz)

G036

G037

Figure 36. ANALOG SUPPLY POWER

Figure 37. DIGITAL SUPPLY POWER

220

200

180

160

140

120

100

80

170

150

130

110

90

Two−Wire

One−Wire

One−Wire, Decimate−By−2

One−Wire, Decimate−By−4

70

50

10

20

30

40

50

60

70

80

90

100

10

20

30

40

50

60

70

80

90

100

Sampling Frequency (MHz)

G038

G039

Figure 38. ANALOG SUPPLY CURRENT

Figure 39. DIGITAL SUPPLY CURRENT

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TYPICAL CHARACTERISTICS: Power Consumption (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

85

Two−Wire

One−Wire

80

75

70

65

60

55

50

45

40

35

30

10

20

30

40

50

60

70

80

90

100

Sampling Frequency (MHz)

G040

Figure 40. TOTAL POWER PER CHANNEL

24

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TYPICAL CHARACTERISTICS: Contour

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

100

69

68.6

90

70.2

68.2

69.8

69.4

70.6

69

80

70

60

50

40

30

20

68.6

67

67.8

67.4

68.2

70.2

69.8

69.4

70.6

69

68.6

67.8

68.2

68.6

69.8

70.2

69.4

70.6

69

10

20

30

40

50

60

70

80

90

Input Frequency, MHz

67

67.5

68

68.5

69

69.5

70

70.5

Figure 41. SIGNAL-TO-NOISE RATIO vs INPUT AND SAMPLING FREQUENCIES

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TYPICAL CHARACTERISTICS: Contour (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, 100 MSPS, two-wire LVDS interface,

and –1-dBFS differential analog input, unless otherwise noted.

100

76

90

84

82

76

86

78

80

74

80

70

60

50

40

30

20

72

76

82

84

78

80

86

74

72

88

80

76

78

84 82

86

74

10

20

30

40

50

60

70

80

86

90

Input Frequency, MHz

72

74

76

78

80

82

84

88

Figure 42. SPURIOUS-FREE DYNAMIC RANGE vs INPUT AND SAMPLING FREQUENCIES

26

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DEVICE CONFIGURATION

SERIAL INTERFACE

The ADC has a set of internal registers that can be accessed by the serial interface formed by the CS (serial

interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serially shifting bits into

the device is enabled when CS is low. The serial data (on the SDATA pin) are latched at every SCLK falling

edge when CS is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when

CS is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded

in multiples of 24-bit words within a single active CS pulse. The first eight bits form the register address and the

remaining 16 bits are the register data. The interface can function with SCLK frequencies from 15 MHz down to

very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

Register Initialization

After power-up, the internal registers must be initialized to default values. This initialization can be accomplished

in one of two ways:

1. Either through a hardware reset by applying a high pulse on the RESET pin (of widths greater than 10 ns),

as shown in Figure 43; or

2. By applying a software reset. When using the serial interface, set the RESET bit (register 00h, bit D7) high.

This setting initializes the internal registers to default values and then self-resets the RESET bit low. In this

case, the RESET pin is kept low (inactive).

Register Address

Register Data

SDATA

SCLK

A7

A6

A5

A4

A3

A2

A1

A0

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

t_DSU

t_DH

t_SCLK

t_SLOADS

t_SLOADH

CS

RESET

Figure 43. Serial Interface Timing Diagram

Table 5. Timing Characteristics for Figure 43⁽¹⁾

PARAMETER

MIN

>dc

33

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

SCLK frequency (equal to 1 / t_SCLK

CS to SCLK setup time

SCLK to CS hold time

SDATA setup time

)

15

33

ns

33

ns

t_DH

SDATA hold time

33

ns

(1) Typical values are at T_A= +25°C, minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX

+85°C, unless otherwise noted.

=

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Reset Timing

Figure 44 shows a timing diagram for the reset function.

Power Supply

AVDD, LVDD

t₁

RESET

t₂

t₃

SEN

Figure 44. Reset Timing Diagram

Table 6. Timing Characteristics for Figure 44⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay from AVDD and LVDD power-up

to active RESET pulse

t₁

Power-on delay

1

ms

t₂

t₃

Reset pulse width

Pulse width of active RESET signal

50

ns

Register write delay

Delay from RESET disable to CS active

100

(1) Typical values are at T_A= +25°C, minimum and maximum values are across the full temperature range of T_MIN= –40°C to

T_MAX= +85°C, unless otherwise noted.

(2) A high pulse on the RESET pin is required when initialization is done via a hardware reset.

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Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back on the SDOUT pin.

This readback mode may be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC.

By default, the SDOUT pin is in 3-state after a device power-up or reset. When the readout mode is enabled

using the READOUT register bit, SDOUT serially outputs the contents of the selected register. The following

steps describe how to achieve this functionality:

1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode. This mode prevents

any further writes to the internal registers, except for at register 01h. Note that the READOUT bit is also

located in register 01h. The device can exit readout mode by setting the READOUT bit to '0'. Note that only

the contents of register 01h are unable to be read in register readout mode.

2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read.

3. The device serially outputs the contents (D[15:0]) of the selected register on the SDOUT pin.

4. The external controller can latch the contents at the SCLK rising edge.

To exit serial readout mode, reset the READOUT register bit to '0', which enables writes to all device registers. At

this point, the SDOUT pin is in 3-state. A detailed timing diagram for the serial readout mode is shown in

Figure 45.

Register Address (A[7:0]) = 01h

Register Data (D[15:0]) = 0001

SDATA

SCLK

0

1

0

1

The SDOUT pin becomes active and is forced low.

CS

SDOUT

The SDOUT Pin is in 3-State

a) Enable Serial Readout (READOUT = 1)

Register Address (A[7:0]) = 0Fh

Register Data (D[15:0]) = XXXX (don’t care)

SDATA

SCLK

A7

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CS

0

1

SDOUT

SDOUT outputs the contents of register 0Fh in the same cycle, MSB first.

b) Read contents of register 0Fh. This register is initialized with 0200 (the device was previously put in global power-down).

Figure 45. Serial Readout Timing Diagram

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DESCRIPTION OF SERIAL INTERFACE REGISTERS

Register 00h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

RST

Bits D[15:1]

Bit D0

Must write '0'

RST

0 = Normal operation (default)

1 = Self-clearing software RESET; after reset, this bit is set to '0'

Register 01h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

D3

0

D2

0

D1

0

D0

EN_HIGH_

ADDRS

EN_READOUT

Bits D[15:5]

Bit D4

Must write '0'

EN_HIGH_ADDRS

0 = Access to register F0h disabled (default)

1 = Access to register F0h enabled

Bits D[3:1]

Bit D0

Must write '0'

EN_READOUT

0 = Normal operation (default)

1 = READOUT of registers mode using the SDOUT pin enabled

Register 0Ah

D15

D14

D6

D13

D5

D12

RAMP_PAT_RESET_VAL

D4 D3

RAMP_PAT_RESET_VAL

D11

D10

D2

D9

D1

D8

D0

D7

Bits D[15:0]

RAMP_PAT_RESET_VAL

The starting value of digital ramp test pattern can be programmed using these register bits.

By default, after a reset, the starting value is 0000h.

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Register 0Fh

D15

0

D14

0

D13

0

D12

0

D11

0

D10

D9

D8

PDN_

COMPLETE

PDN_PIN_CFG

PDN_PARTIAL

D7

D6

D5

D4

D3

D2

D1

D0

PDN_CH[8:1]

All bits default to '0' after reset.

Bits D[15:11]

Bit D10

Must write '0'

PDN_PIN_CFG

0 = PD pin configured for complete power-down mode

1 = PD pin configured for partial power-down mode

Bit D9

PDN_COMPLETE

0 = Normal operation

1 = Register mode for complete power-down; slow recovery from power-down

Bit D8

PDN_PARTIAL

0 = Normal operation

1 = Partial power-down mode; fast recovery from power-down

Bits D[7:0]

PDN_CH[8:1]

0 = Normal operation

1 = Individual channel ADC power-down mode

Register 14h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

D6

D5

D4

D3

D2

D1

D0

LFNS_CH[8:1]

Bits D[15:8]

Bits D[7:0]

Must write '0'

LFNS_CH[8:1]

0 = LFNS disabled (default)

1 = Low-frequency noise suppression (LFNS) mode enabled for individual channels

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Register 1Ch

D15

0

D14

D13

0

D12

0

D11

D3

D10

D9

D1

D8

D0

EN_FRAME_

PAT

ADCLKOUT[11:0]

D7

D6

D5

D4

D2

ADCLKOUT[11:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

EN_FRAME_PAT

0 = Normal operation on frame clock (default)

1 = Enables output frame clock to be programmed through a pattern specified by

ADCCLKOUT register bits

Bits D[13:12]

Bits D[11:0]

Must write '0'

ADCLKOUT[11:0]

These bits create the 12-bit pattern for the frame clock on the ADCLKP, ADCLKN pins.

Register 23h

D15

D14

D6

D13

D5

D12

D11

D3

D10

D2

D9

D1

D8

D0

PRBS_SEED[15:0]

D7

D4

PRBS_SEED[15:0]

Bits D[15:0]

PRBS_SEED[15:0]

These bits are the lower 16 bits of the PRBS pattern starting seed value.

The starting seed value of the PRBS test pattern can be specified using these register bits

Register 24h

D15

D14

D6

D13

D5

D12

D11

D3

D10

D2

D9

D1

D8

0

PRBS_SEED[22:16]

D7

D4

D0

INVERT_CH[8:1]

All bits default to '0' after reset.

Bits D[15:9]

PRBS_SEED[22:16]

These bits are the seven upper bits of the PRBS seed starting value.

Bit D8

Must write '0'

Bits D[7:0]

INVERT_CH[8:1]

0 = Normal configuration

Normally, the INP pin represents the positive analog input pin and INN represents the

complementary negative input.

1 = The polarity of the analog input pins is electrically swapped

Setting the INVERT_CH[8:1] bits causes the inputs to be swapped. INN now represents the

positive input and INP represents the negative input.

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Register 25h

D15

SBAS595 –DECEMBER 2012

D14

D13

D12

D11

0

D10

0

D9

D8

TP_HARD_

SYNC

PRBS_SEED_

FROM_REG

PRBS_

MODE_2

TP_SOFT_

SYNC

PRBS_TP_EN

0

D7

0

D6

D5

D4

D3

D2

D1

D0

TEST_PATT[2:0]

BITS_CUSTOM2[11:10]

BITS_CUSTOM1[11:10]

All bits default to '0' after reset.

Bit D15

TP_HARD_SYNC

0 = Inactive

1 = The external SYNC feature is enabled for syncing test patterns

Bit D14

PRBS_SEED_FROM_REG

0 = Disabled

1 = The PRBS seed is now able to be chosen from registers 23h and 24h

Bit D13

Bit D12

PRBS_MODE_2

The PRBS 9-bit LFSR (23-bit LFSR) is the default mode.

PRBS_TP_EN

0 = PRBS test pattern disabled

1 = PRBS test pattern enabled

Bits D[11:9]

Bit D8

Must write '0'

TP_SOFT_SYNC

0 = No sync

1 = Software sync bit for the test patterns on all eight channels

Bit D7

Bit D6

Must write '0'

TEST_PATT2

0 = Normal operation

1 = A repeating full-scale ramp pattern is enabled on the outputs; ensure that bits D4 and

D5 are '0'

Bit D5

Bit D4

TEST_PATT1

0 = Normal operation

1 = Enables a mode where the output toggles between two defined codes; ensure that bits

D4 and D6 are '0'

TEST_PATT0

0 = Normal operation

1 = Enables a mode where the output is a constant specified code; ensure that bits D5 and

D6 are '0'

Bits D[3:2]

Bits D[1:0]

BITS_CUSTOM2[11:10]

These bits are the two MSBs for the second code of the dual custom patterns.

BITS_CUSTOM1[11:10]

These bits are the two MSBs for the single custom pattern (and for the first code of the dual

custom patterns).

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Register 26h

D15

D14

D13

D12

D11

D10

D9

D8

BITS_CUSTOM1[9:0]

D7

D6

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

BITS_CUSTOM1[9:0]

Bits D[15:6]

BITS_CUSTOM1[9:0]

These bits are the 10 lower bits for the single custom pattern (and for the first code of the

dual custom pattern).

Bits D[5:0]

Must write '0'

Register 27h

D15

D14

D6

D13

D12

D11

D10

D9

D8

BITS_CUSTOM2[9:0]

D7

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

BITS_CUSTOM2[9:0]

Bits D[15:6]

Bits D[5:0]

BITS_CUSTOM2[9:0]

These bits are the 10 lower bits for the second code of the dual custom pattern.

Must write '0'

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Register 28h

D15

SBAS595 –DECEMBER 2012

D14

0

D13

0

D12

0

D11

0

D10

0

D9

D8

EN_WORD_

BIT_WISE

0

EN_BIT_WISE

D7

D6

D5

D4

D3

D2

D1

D0

EN_WORDWISE_BY_CH[7:0]

All bits default to '0' after reset.

Bit D15

EN_WORD_BIT_WISE

This bit enables the bit order output in two-wire mode.

0 = Byte-wise

1 = Word-wise if D[7:0] = 1 (bit-wise if D8 = 1 and D[7:0] = 0)

Bits D[14:9]

Bit D8

Must write '0'

EN_BIT_WISE

1 = Bit-wise if D15 =1 and D[7:0] = 0

EN_WORDWISE_BY_CH[7:0]

Bits D[7:0]

0 = Bit-wise if D15 = 1 and D8 = 1

1 = Word-wise if D15 = 1

Register 29h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

D0

EN_DIG_

FILTER

EN_CHANNEL

_AVG

Bits D[15:2]

Bit D1

Must write '0'

EN_DIG_FILTER

0 = Global control digital filter disabled(default)

1 = Global control digital filter enabled

Bit D0

EN_CHANNEL_AVG

0 = Channel averaging is disabled (default)

1 = Channel averaging is enabled and specified by the AVG_OUTn register bits

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Register 2Ah

D15

D14

GAIN_CH4[3:0]

D6 D5

GAIN_CH2[3:0]

D13

D12

D4

D11

D3

D10

D9

D1

D8

D0

GAIN_CH3[3:0]

D7

D2

GAIN_CH1[3:0]

Bits D[15:12]

Bits D[11:8]

Bits D[7:4]

Bits D[3:0]

GAIN_CH4[3:0]

These bits set the programmable gain for channel 4.

GAIN_CH3[3:0]

These bits set the programmable gain for channel 3.

GAIN_CH2[3:0]

These bits set the programmable gain for channel 2.

GAIN_CH1[3:0]

These bits set the programmable gain for channel 1.

Register 2Bh

D15

D14

D13

D5

D12

D4

D11

D3

D10

D9

D1

D8

D0

GAIN_CH5[3:0]

GAIN_CH6[3:0]

D7

D6

D2

GAIN_CH8[3:0]

GAIN_CH7[3:0]

Bits D[15:12]

Bits D[11:8]

Bits D[7:4]

Bits D[3:0]

GAIN_CH5[3:0]

These bits set the programmable gain for channel 5.

GAIN_CH6[3:0]

These bits set the programmable gain for channel 6.

GAIN_CH7[3:0]

These bits set the programmable gain for channel 7.

GAIN_CH8[3:0]

These bits set the programmable gain for channel 8.

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Register 2Ch

D15

0

D14

0

D13

0

D12

0

D11

0

D10

D9

D8

0

AVG_OUT4[1:0]

D7

D6

D5

0

D4

D3

D2

0

D1

D0

AVG_OUT3[1:0]

AVG_OUT2[1:0]

AVG_OUT1[1:0]

Bits D[15:11]

Bits D[10:9]

Must write '0'

AVG_OUT4[1:0]

These bits set the averaging control for what is transmitted on the LVDS output OUT4.

Bit D8

Must write '0'

Bits D[7:6]

AVG_OUT3[1:0]

These bits set the averaging control for what is transmitted on the LVDS output OUT3.

Bit D5

Must write '0'

Bits D[4:3]

AVG_OUT2[1:0]

These bits set the averaging control for what is transmitted on the LVDS output OUT2.

Bit D2

Must write '0'

Bits D[1:0]

AVG_OUT1[1:0]

These bits set the averaging control for what is transmitted on the LVDS output OUT1.

Register 2Dh

D15

0

D14

0

D13

0

D12

0

D11

0

D10

D9

D1

D8

0

AVG_OUT8[1:0]

D7

D6

D5

0

D4

D3

D2

0

D0

AVG_OUT7[1:0]

AVG_OUT6[1:0]

AVG_OUT5[1:0]

Bits D[15:11]

Bits D[10:9]

Must write '0'

AVG_OUT8[1:0]

These bits set the averaging control for what is transmitted on the LVDS output OUT8.

Bit D8

Must write '0'

Bits D[7:6]

AVG_OUT7[1:0]

These bits set the averaging control for what is transmitted on the LVDS output OUT7.

Bit D5

Must write '0'

Bits D[4:3]

AVG_OUT6[1:0]

These bits set the averaging control for what is transmitted on the LVDS output OUT6.

Bit D2

Must write '0'

Bits D[1:0]

AVG_OUT5[1:0]

These bits set the averaging control for what is transmitted on the LVDS output OUT5.

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Register 2Eh

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH1

D6

HPF_CORNER _CH1[3:0]

FILTER_TYPE_CH1[2:0]

D7

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH1[2:0]

SEL_ODD_

TAP_CH1

USE_FILTER_

CH1

DEC_RATE_CH1[2:0]

Bit D15

Bit D14

Must write '0'

HPF_EN_CH1

This bit enables the HPF filter for channel 1.

HPF_CORNER _CH1[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 1.

FILTER_TYPE_CH1[2:0]

These bits select the type of filter on channel 1.

DEC_RATE_CH1[2:0]

These bits set the decimation factor for the filter on channel 1.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH1

This bit enables the odd tap filter for channel 1.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH1

This bit enables the filter for channel 1.

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Register 2Fh

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH2

HPF_CORNER _CH2[3:0]

FILTER_TYPE_CH2[2:0]

D7

D6

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH2[2:0]

SEL_ODD_

TAP_CH2

USE_FILTER_

CH2

DEC_RATE_CH2[2:0]

Bit D15

Bit D14

Must write '0'

HPF_EN_CH2

This bit enables the HPF filter for channel 2.

HPF_CORNER _CH2[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 2.

FILTER_TYPE_CH2[2:0]

These bits select the type of filter on channel 2.

DEC_RATE_CH2[2:0]

These bits set the decimation factor for the filter on channel 2.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH2

This bit enables the odd tap filter for channel 2.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH2

This bit enables the filter for channel 2.

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Register 30h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH3

D6

HPF_CORNER _CH3[3:0]

FILTER_TYPE_CH3[2:0]

D7

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH3[2:0]

SEL_ODD_

TAP_CH3

USE_FILTER_

CH3

DEC_RATE_CH3[2:0]

Bit D15

Bit D14

Must write '0'

HPF_EN_CH3

This bit enables the HPF filter for channel 3.

HPF_CORNER _CH3[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 3.

FILTER_TYPE_CH3[2:0]

These bits select the type of filter on channel 3.

DEC_RATE_CH3[2:0]

These bits set the decimation factor for the filter on channel 3.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH3

This bit enables the odd tap filter for channel 3.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH3

This bit enables the filter for channel 3.

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Register 31h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH4

HPF_CORNER _CH4[3:0]

FILTER_TYPE_CH4[2:0]

D7

D6

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH4[2:0]

SEL_ODD_

TAP_CH4

USE_FILTER_

CH4

DEC_RATE_CH4[2:0]

Bit D15

Bit D14

Must write '0'

HPF_EN_CH4

This bit enables the HPF filter for channel 4.

HPF_CORNER _CH4[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 4.

FILTER_TYPE_CH4[2:0]

These bits select the type of filter on channel 4.

DEC_RATE_CH4[2:0]

These bits set the decimation factor for the filter on channel 4.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH4

This bit enables the odd tap filter for channel 4.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH4

This bit enables the filter for channel 4.

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Register 32h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH5

D6

HPF_CORNER _CH5[3:0]

FILTER_TYPE_CH5[2:0]

D7

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH5[2:0]

SEL_ODD_

TAP_CH5

USE_FILTER_

CH5

DEC_RATE_CH5[2:0]

Bit D15

Bit D14

Must write '0'

HPF_EN_CH5

This bit enables the HPF filter for channel 5.

HPF_CORNER _CH5[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 5.

FILTER_TYPE_CH5[2:0]

These bits select the type of filter on channel 5.

DEC_RATE_CH5[2:0]

These bits set the decimation factor for the filter on channel 5.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH5

This bit enables the odd tap filter for channel 5.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH5

This bit enables the filter for channel 5.

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Register 33h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH6

HPF_CORNER _CH6[3:0]

FILTER_TYPE_CH6[2:0]

D7

D6

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH6[2:0]

SEL_ODD_

TAP_CH6

USE_FILTER_

CH6

DEC_RATE_CH6[2:0]

Bit D15

Bit D14

Must write '0'

HPF_EN_CH6

This bit enables the HPF filter for channel 6.

HPF_CORNER _CH6[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 6.

FILTER_TYPE_CH6[2:0]

These bits select the type of filter on channel 6.

DEC_RATE_CH6[2:0]

These bits set the decimation factor for the filter on channel 6.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH6

This bit enables the odd tap filter for channel 6.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH6

This bit enables the filter for channel 6.

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Register 34h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH7

D6

HPF_CORNER _CH7[3:0]

FILTER_TYPE_CH7[2:0]

D7

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH7[2:0]

SEL_ODD_

TAP_CH7

USE_FILTER_

CH7

DEC_RATE_CH7[2:0]

Bit D15

Bit D14

Must write '0'

HPF_EN_CH7

This bit enables the HPF filter for channel 7.

HPF_CORNER _CH7[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 7.

FILTER_TYPE_CH7[2:0]

These bits select the type of filter on channel 7.

DEC_RATE_CH7[2:0]

These bits set the decimation factor for the filter on channel 7.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH7

This bit enables the odd tap filter for channel 7.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH7

This bit enables the filter for channel 7.

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Register 35h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH8

HPF_CORNER _CH8[3:0]

FILTER_TYPE_CH8[2:0]

D7

D6

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH8[2:0]

SEL_ODD_

TAP_CH8

USE_FILTER_

CH8

DEC_RATE_CH8[2:0]

Bit D15

Bit D14

Must write '0'

HPF_EN_CH8

This bit enables the HPF filter for channel 8.

HPF_CORNER _CH8[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 8.

FILTER_TYPE_CH8[2:0]

These bits select the type of filter on channel 8.

DEC_RATE_CH8[2:0]

These bits set the decimation factor for the filter on channel 8.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH8

This bit enables the odd tap filter for channel 8.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH8

This bit enables the filter for channel 8.

Register 38h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

D0

DATA_RATE[1:0]

Bits D[15:2]

Bits D[1:0]

Must write '0'

DATA_RATE[1:0]

Bits D1 and D0 select the output data rate depending on the type of filter.

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Register 42h

D15

D14

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

EN_PHASE_

DDR

0

D7

0

D6

D5

D4

0

D3

0

D2

0

D1

0

D0

0

PHASE_DDR1 PHASE_DDR0

Bit D15

This bit enables LCLK phase programmability.

Must write '0'

Bits D[14:7]

Bits D[6:5]

PHASE_DDR[1:0]

These bits control the LCLK output phase relative to data.

Refer to the Programmable LCLK Phase section.

Bits D[4:0]

Must write '0'

Register 45h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

D0

PAT_DESKEW_SYNC[1:0]

Bits D[15:2]

Bit D1

Must write '0'

PAT_DESKEW_SYNC1

0 = Inactive

1 = Sync pattern mode enabled; ensure that D0 is '0'

Bit D0

PAT_DESKEW_SYNC0

0 = Inactive

1 = Deskew pattern mode enabled; ensure that D1 is '0'

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Register 46h

D15

D14

0

D13

D12

0

D11

D3

D10

D9

D8

ENABLE 46

FALL_SDR

BIT_SER_SEL

D7

0

D6

0

D5

0

D4

D2

D1

0

D0

EN_MSB_

FIRST

EN_SDR

BTC_MODE

EN_2WIRE

All bits default to '0' after reset. Note that bit D15 must be set to '1' to enable bits D[13:0].

Bit D15

ENABLE 46

This bit enables register 46h.

Must write '0'

Bit D14

Bit D13

FALL_SDR

0 = The LCLK rising or falling edge comes at the edge of the data window when operating in

SDR output mode

1 = The LCLK rising or falling edge comes in the middle of the data window when operating

in SDR output mode

Bit D12

Must write '0'

BIT_SER_SEL

Bits D[11:8]

0001 = 10-bit serialization mode enabled

0010 = 12-bit serialization mode enabled

0100 = 14-bit serialization mode enabled

1000 = 16-bit serialization mode enabled

Do not use any other bit combinations.

Bits D[7:5]

Bit D4

Must write '0'

EN_SDR

0 = DDR bit clock

1 = SDR bit clock

Bit D3

Bit D2

EN_MSB_FIRST

0 = LSB first

1 = MSB first

BTC_MODE

0 = Binary offset (ADC data output format)

1 = Twos complement (ADC data output format)

Bit D1

Bit D0

Must write '0'

EN_2WIRE

0 = One-wire LVDS output

1 = Two-wire LVDS output

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Programmable LVDS Mapping Mode Registers

Register 50h

D15

D14

0

D13

0

D12

0

D11

D3

D10

MAP_Ch1234_to_OUT2A

D2 D1

MAP_Ch1234_to_OUT1A

D9

D8

D0

ENABLE 50

D7

D6

D5

D4

MAP_Ch1234_to_OUT1B

Bit D15

ENABLE 50

This bit enables bits D[11:0] of register 50h.

Must write '0'

Bits D[14:12]

Bits D[11:8]

MAP_Ch1234_to_OUT2A

These bits set the OUT2A pin pair to the channel data mapping selection.

MAP_Ch1234_to_OUT1B

Bits D[7:4]

Bits D[3:0]

These bits set the OUT1B pin pair to the channel data mapping selection.

MAP_Ch1234_to_OUT1A

These bits set the OUT1A pin pair to the channel data mapping selection.

Register 51h

D15

D14

0

D13

0

D12

0

D11

D3

D10

MAP_Ch1234_to_OUT3B

D2 D1

MAP_Ch1234_to_OUT2B

D9

D8

D0

ENABLE 51

D7

D6

D5

D4

MAP_Ch1234_to_OUT3A

Bit D15

ENABLE 51

This bit enables bits D[11:0] of register 51h.

Must write '0'

Bits D[14:12]

Bits D[11:8]

MAP_Ch1234_to_OUT3B

These bits set the OUT3B pin pair to the channel data mapping selection.

MAP_Ch1234_to_OUT3A

Bits D[7:4]

Bits D[3:0]

These bits set the OUT3A pin pair to the channel data mapping selection.

MAP_Ch1234_to_OUT2B

These bits set the OUT2B pin pair to the channel data mapping selection.

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Register 52h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

D8

0

ENABLE 52

0

D7

D6

D5

D4

D3

D2

D1

D0

MAP_Ch1234_to_OUT4B

MAP_Ch1234_to_OUT4A

Bit D15

ENABLE 52

This bit enables bits D[7:0] of register 52h.

Must write '0'

Bits D[14:8]

Bits D[7:4]

MAP_Ch1234_to_OUT4B

These bits set the OUT4B pin pair to the channel data mapping selection.

MAP_Ch1234_to_OUT4A

Bits D[3:0]

These bits set the OUT4A pin pair to the channel data mapping selection.

Register 53h

D15

D14

0

D13

0

D12

0

D11

D3

D10

MAP_Ch5678_to_OUT6B

D2 D1

MAP_Ch5678_to_OUT5B

D9

D8

D0

ENABLE 53

D7

D6

D5

D4

MAP_Ch5678_to_OUT5A

Bit D15

ENABLE 53

This bit enables bits D[11:0] of register 53h.

Must write '0'

Bits D[14:12]

Bits D[11:8]

MAP_Ch5678_to_OUT6B

These bits set the OUT6B pin pair to the channel data mapping selection.

MAP_Ch5678_to_OUT5A

Bits D[7:4]

Bits D[3:0]

These bits set the OUT5A pin pair to the channel data mapping selection.

MAP_Ch5678_to_OUT5B

These bits set the OUT5B pin pair to the channel data mapping selection.

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Register 54h

D15

D14

D13

0

D12

0

D11

D3

D10

MAP_Ch5678_to_OUT7A

D2 D1

MAP_Ch5678_to_OUT6A

D9

D8

D0

ENABLE 54

0

D7

D6

D5

D4

MAP_Ch5678_to_OUT7B

Bit D15

ENABLE 54

This bit enables bits D[11:0] of register 54h.

Must write '0'

Bits D[14:12]

Bits D[11:8]

MAP_Ch5678_to_OUT7A

These bits set the OUT7A pin pair to the channel data mapping selection.

MAP_Ch5678_to_OUT7B

Bits D[7:4]

Bits D[3:0]

These bits set the OUT7B pin pair to the channel data mapping selection.

MAP_Ch5678_to_OUT6A

These bits set the OUT6A pin pair to the channel data mapping selection.

Register 55h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

ENABLE 55

D7

D6

D5

D4

D3

D2

D1

D0

MAP_Ch5678_to_OUT8A

MAP_Ch5678_to_OUT8B

Bit D15

ENABLE 55

This bit enables bits D[7:0] of register 55h.

Must write '0'

Bits D[14:8]

Bits D[7:4]

MAP_Ch5678_to_OUT8A

These bits set the OUT8A pin pair to the channel data mapping selection.

MAP_Ch5678_to_OUT8B

Bits D[3:0]

These bits set the OUT8B pin pair to the channel data mapping selection.

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Custom Coefficient Registers

Registers 5Ah to 65h⁽¹⁾

D15

D14

0

D13

0

D12

0

D11

D3

D10

D9

D8

D0

EN_CUSTOM_

FILT_CH1

COEFFn_SET_CH1[11:0]

D7

D6

D5

D4

D2

D1

COEFFn_SET_CH1[11:0]

(1) n = 0 to 11.

These registers are the custom coefficient registers for channel 1.

Bit D15

EN_CUSTOM_FILT_CH1

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH1[11:0]

These bits set the custom coefficient n for the channel 1 digital filter.

Registers 66h to 71h⁽¹⁾

D15

D14

0

D13

0

D12

0

D11

D10

COEFFn_SET_CH2[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH2

D7

D6

D5

D4

D3

COEFFn_SET_CH2[11:0]

(1) n = 0 to 11.

These registers are the custom coefficient registers for channel 2.

Bit D15

EN_CUSTOM_FILT_CH2

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH2[11:0]

These bits set the custom coefficient n for the channel 2 digital filter.

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Registers 72h to 7Dh⁽¹⁾

D15

D14

0

D13

0

D12

0

D11

D3

D10

COEFFn_SET_CH3[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH3

D7

D6

D5

D4

COEFFn_SET_CH3[11:0]

(1) n = 0 to 11.

These registers are the custom coefficient registers for channel 3.

Bit D15

EN_CUSTOM_FILT_CH3

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH3[11:0]

These bits set the custom coefficient n for the channel 3 digital filter.

Registers 7Eh to 89h⁽¹⁾

D15

D14

0

D13

0

D12

0

D11

D10

COEFFn_SET_CH4[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH4

D7

D6

D5

D4

D3

COEFFn_SET_CH4[11:0]

(1) n = 0 to 11.

These registers are the custom coefficient registers for channel 4.

Bit D15

EN_CUSTOM_FILT_CH4

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH1[11:0]

These bits set the custom coefficient n for the channel 4 digital filter.

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Registers 8Ah to 95h⁽¹⁾

D15

D14

0

D13

0

D12

0

D11

D3

D10

D9

D8

D0

EN_CUSTOM_

FILT_CH5

COEFFn_SET_CH5[11:0]

D7

D6

D5

D4

D2

D1

COEFFn_SET_CH5[11:0]

(1) n = 0 to 11.

These registers are the custom coefficient registers for channel 5.

Bit D15

EN_CUSTOM_FILT_CH5

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH5[11:0]

These bits set the custom coefficient n for the channel 5 digital filter.

Registers 96h to A1h⁽¹⁾

D15

D14

0

D13

0

D12

0

D11

D10

COEFFn_SET_CH6[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH6

D7

D6

D5

D4

D3

COEFFn_SET_CH6[11:0]

(1) n = 0 to 11.

These registers are the custom coefficient registers for channel 6.

Bit D15

EN_CUSTOM_FILT_CH6

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH6[11:0]

These bits set the custom coefficient n for the channel 6 digital filter.

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Registers A2h to ADh⁽¹⁾

D15

D14

0

D13

0

D12

0

D11

D3

D10

COEFFn_SET_CH7[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH7

D7

D6

D5

D4

COEFFn_SET_CH7[11:0]

(1) n = 0 to 11.

These registers are the custom coefficient registers for channel 7.

Bit D15

EN_CUSTOM_FILT_CH7

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH7[11:0]

These bits set the custom coefficient n for the channel 7 digital filter.

Registers AEh to B9h⁽¹⁾

D15

D14

0

D13

0

D12

0

D11

D10

COEFFn_SET_CH8[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH8

D7

D6

D5

D4

D3

COEFFn_SET_CH8[11:0]

(1) n = 0 to 11.

These registers are the custom coefficient registers for channel 8.

Bit D15

EN_CUSTOM_FILT_CH8

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH8[11:0]

These bits set the custom coefficient n for the channel 8 digital filter.

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Register BEh

D15

SBAS595 –DECEMBER 2012

D14

0

D13

0

D12

0

D11

0

D10

0

D9

D8

EN_LVDS_

PROG

DELAY_DATA_R[1:0]

D7

D6

D5

D4

D3

D2

D1

D0

DELAY_LCLK_R[2:0]

DELAY_DATA_F[1:0]

DELAY_LCLK_F[2:0]

Bit D15

This bit enables LVDS edge delay programmability.

Must write '0'

Bits D[14:10]

Bits D[9:8]

Bits D[7:5]

Bits D[4:3]

Bits D[2:0]

Refer Table 22 for settings.

Refer Table 23 for settings.

Refer Table 22 for settings.

Refer Table 23 for settings.

Register F0h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

EN_EXT_REF

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

The EN_HIGH_ADDRS register bit (register 01h, bit D4) must be set to '1' to allow access to this register.

Bit D15

EN_EXT_REF

0 = Internal reference mode (default)

1 = External reference mode enabled; apply the reference voltages on the REFT and REFB

pins

Bits D[14:0]

Must write '0'

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APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5295 is a low-power, 8-channel, 12-bit analog-to-digital converter (ADC) with sample rates up to

100 MSPS that run off of a single 1.8-V supply. All eight channels simultaneously sample the analog inputs at the

input clock rising edge. The sampled signal is sequentially converted by a series of small resolution stages, with

the outputs combined in a digital correction logic block. At every clock edge, the sample propagates through the

pipeline, resulting in a data latency of 12 clock cycles.

ANALOG INPUT

The analog input consists of a switched-capacitor-based, differential sample-and-hold architecture, as shown in

Figure 46. This differential topology results in very good ac performance even for high input frequencies at high

sampling rates. The INP and INM pins must be externally biased around a common-mode voltage of 0.95 V,

available on the VCM pin. For a full-scale differential input, each input pin (INP, INN) must swing symmetrically

between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-V_PPdifferential input swing. The input sampling circuit

has a high 3-dB bandwidth that extends up to 500 MHz (measured from the input pins to the sampled voltage).

S

SZ

R_ON

25 W

R_ON

C_PAR3

100 W

0.3 pF

Sampling

Switch

L_PKG

2 nH

S

Sampling

Capacitor

15 W

INP

R_ON

10 W

C_BOND

0.5 pF

C_PAR2

1 pF

C_SAMP

2.6 pF

1 kW

R_ESR

200 W

C_PAR1

1.5 pF

R_ON

40 W

VCM

L_PKG

2 nH

1 kW

C_SAMP

2.6 pF

R_ON

10 W

15 W

INN

C_BOND

0.5 pF

C_PAR2

1 pF

Sampling

Capacitor

S

R_ESR

Sampling

Switch

200 W

R_ON

25 W

100 W

C_PAR3

0.3 pF

S

SZ

Figure 46. Analog Input Equivalent Circuit

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Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This architecture improves the

common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with

each input pin is recommended to damp out ringing caused by package parasitics. The drive circuits in Figure 47

and Figure 48 show an R-C filter across the analog input pins. The purpose of the filter is to absorb the glitches

caused by the opening and closing of the sampling capacitors. Figure 49 and Figure 50 show the differential

input resistance and capacitance across frequency.

0.1 mF

5 ꢀ

10 W

INP

25 ꢀ

6.8 pF

25 ꢀ

VCM

25 ꢀ

Device

3.3 pF

INN

5 ꢀ

INN

10 W

0.1 mF

Figure 47. DC-Coupled Drive Circuit with RCR

Figure 48. AC-Coupled Drive Circuit

2

4

3.5

3

1.5

1

2.5

2

0.5

1.5

1

0

100 200 300 400 500 600 700 800 900 1000

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

G043

G044

Figure 49. ADC Differential Input Resistance (R_IN)

vs Frequency

Figure 50. ADC Differential Input Capacitance (C_IN)

vs Frequency

Large- and Small-Signal Input Bandwidth

The small-signal bandwidth of the analog input circuit is high, approximately 500 MHz. When using an amplifier

to drive the ADS5295, the total amplifier noise up to the small-signal bandwidth must be considered. The large-

signal bandwidth of the device depends on the amplitude of the input signal. The ADS5295 supports a 2-V_PP

amplitude for input signal frequencies up to 90 MHz. For higher frequencies, the amplitude of the input signal

must be decreased proportionally. For example, at 180 MHz, the device supports a maximum 1-V_PPsignal.

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CLOCK INPUT

The ADS5295 can operate with both single-ended (CMOS) and differential input clocks (such as sine wave,

LVPECL, and LVDS). Operating with a low-jitter differential clock is recommended for good SNR performance,

especially at input frequencies greater than 30 MHz. In the differential mode, the clock inputs are internally

biased to a 0.95-V common-mode voltage. While driving with an external LVPECL or LVDS driver, TI

recommends ac-coupling the clock signals so that the clock pins are correctly biased to the common-mode

voltage (0.95 V). To operate using a single-ended clock, connect a CMOS clock source to CLKP and tie CLKN to

GND. The device automatically detects the presence of a single-ended clock without requiring any configuration

and disables the internal biasing. Typical clock termination schemes are shown in Figure 51, Figure 52,

Figure 53, and Figure 54.

0.1 mF

CLKP

R_TERM

Differential

LVPECL

Clock Input

Differential

Sine-Wave

Clock Input

0.1 mF

CLKN

R_TERM

Figure 51. Differential Sine-Wave Clock Driving

Circuit

Figure 52. Differential LVPECL Clock Driving

Circuit

0.1 mF

CMOS

Clock Input

CLKP

Differential

LVDS

Clock Input

R_TERM

0.1 mF

CLKN

Figure 53. Differential LVDS Clock Driving Circuit

Figure 54. Single-Ended Clock Driving Circuit

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SBAS595 –DECEMBER 2012

EXTERNAL REFERENCE MODE OF OPERATION

For normal operation, the device requires two reference voltages (REFT and REFB) that are generated internally

by default, as shown in Figure 55. The value of the reference voltage determines the actual ADC full-scale input

voltage, as shown in Equation 1:

Full-Scale Input Voltage = 2 ´ (V_REFT- V_REFB

)

(1)

Device

INTREF/EXTREF

Internal

Reference

REFT

REFB

REF Amp

ADC

Figure 55. Reference Equivalent Circuit

Any error in the reference results in a deviation of the full-scale input range from its ideal value of 2.0 V_PP, as

shown in Equation 2:

Error in Full-Scale Voltage = 2x [Error in (V_REFT– V_REFB)]

(2)

The reference inaccuracy results in a gain error, which is defined as Equation 3:

100

Gain Error (%) = Error in Full-Scale Voltage ´

Ideal Full-Scale Voltage

100

= 2x [Error in (V_REFT- V_REFB)] ´

2.0

(3)

To minimize the gain error, the internal reference voltages are trimmed to an accuracy of ±1.5% (or ±30 mV).

To obtain even lower gain error, the ADS5295 supports an external reference mode of operation. In this mode,

the internal reference amplifiers are powered down and an external amplifier must force the reference voltages

on the REFT and REFB pins. For example, this mode can be used to ensure that multiple ADS5295 chips in the

system have nearly the same full-scale voltage.

To enable the external reference mode, set the register bits as shown in Table 8. These settings power down the

internal reference amplifier and the two reference voltages can be forced directly on the REFT and REFB pins as

V_REFT= 1.45 V and V_REFB= 0.45 V.

Table 8. External Reference Function

FUNCTION

EN_HIGH_ADDRS

EN_EXT_REF

External reference using the REFT, REFB pins

1

Because the internal reference amplifiers are powered down, the accuracy of the full-scale voltage is determined

by the accuracy of (V_REFT– V_REFB), where V_REFTis the voltage forced on REFT and V_REFBis the voltage forced

on REFB.

Note that although the nominal value of (V_REFT– V_REFB) = 1.0 V, ensure that:

[(V_REFT+ V_REFB) / 2 = 0.950 V ± 50 mV].

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Figure 56 shows an example of driving the reference pins. The 1-µF bypass capacitor helps provide the

switching current drawn by the REFT and REFB pins. The external amplifier must provide an average current of

5 mA or less at 100 MSPS. The performance in the external reference mode depends on the sampling speed. At

low sampling speeds (20 MSPS), the performance is the same as that of an internal reference. At higher speeds,

the performance degrades because of the effect of the parasitic bond-wire inductance of the REF pins. Figure 57

highlights the difference in SNR between the external and internal reference modes.

R_S

+

REFT

V_T

V_B

-

1 mF

Precision

Reference

Device

+

R_S

REFB

-

1 mF

Figure 56. Driving Reference Inputs in External Reference Mode

73

SNR in External Reference

SNR in Internal Reference

72

71

70

69

68

67

66

65

20

30

40

50

60

70

80

Sampling Frequency (MSPS)

G045

Figure 57. SNR in Internal and External Reference Mode

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LOW-FREQUENCY NOISE SUPPRESSION

The low-frequency noise suppression (LFNS) mode is particularly useful in applications where good noise

performance is desired in the low-frequency band of dc to 1 MHz. By setting this mode, the low-frequency noise

spectrum band around dc is shifted to a similar band around f_S/ 2 (or the Nyquist frequency). As a result, the

noise spectrum from dc to approximately 1 MHz improves significantly, as shown in Figure 58, Figure 59, and

Figure 60.

This function can be selectively enabled in each channel using the LFNS_CH register bits. Figure 58, Figure 59,

and Figure 60 show the effect of this mode on the spectrum.

0

−10

0

−10

SNR = 70.7 dBFS

SINAD = 70.4 dBFS

SFDR = 82.9 dBc

THD = 82.1 dBc

LF Noise Suppression Enabled

LF Noise Suppression Disabled

−20

−30

−40

−50

−60

−70

−80

−70

−90

−80

−100

−110

−120

−130

−140

−90

−100

−110

−120

0

10

20

30

40

50

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Frequency (MHz)

1

Frequency (MHz)

G033

G034

Figure 58. Full-Scale Input Amplitude

Figure 59. Spectrum (Zoomed) From DC to 1 MHz

0

−10

LF Noise Suppression Enabled

LF Noise Suppression Disabled

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

49 49.1 49.2 49.3 49.4 49.5 49.6 49.7 49.8 49.9 50

Frequency (MHz)

G035

Figure 60. Spectrum (Zoomed) in 1-MHz Band from 49 MHz to 50 MHz (f_S= 100 MSPS)

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DIGITAL PROCESSING BLOCKS

The ADS5295 integrates a set of commonly-used digital functions that can be used to ease system design.

These functions are shown in Figure 61 and are described in the following sections.

LVDS Outputs

Test

Patterns,

Ramp

Channel 1 ADC Data

12-Bit

ADC

Channel 1

OUT1A

OUT1B

Serializer

Wire 1

Average of

2 Channels

Built-In Coefficients

Serializer

Wire 2

Decimate

By 2 or 4

24-Tap Filter

(Even Tap)

ADC Data:

Channel 2

Channel 3

Channel 4

Channel 2

OUT2A

OUT2B

23-Tap Tilter

(Odd Tap)

Serializer

Wire 1

Average of

4 Channels

Serializer

Wire 2

Mapper

8:8

Multiplexer

Custom Coefficients

Decimate

By 2, 4,

or 8

24-Tap Filter

(Even Tap)

OUT3A

OUT3B

Channel 3

Serializer

Wire 1

Gain

(0 dB to 12 dB,

in 1-dB steps)

23-Tap Filter

(Odd Tap)

Serializer

Wire 2

12-Tap Filter

OUT4A

OUT4B

Channel 4

Serializer

Wire 1

Digital Processing Block for Channel 1

Digital Processing Block for Channel 2

Serializer

Wire 2

12-Bit

ADC

Channel 2 ADC Data

Channel 3 ADC Data

12-Bit

ADC

Digital Processing Block for Channel 3

Digital Processing Block for Channel 4

12-Bit

ADC

Channel 4 ADC Data

1/2 ADS5295

Figure 61. Digital Processing Block Diagram

Digital Gain

The ADS5295 includes programmable digital gain settings from 0 dB to 12 dB in 1-dB steps. The benefit of

digital gain is obtaining improved SFDR performance. However, SFDR improvement is achieved at the expense

of SNR; for each gain setting, SNR degrades by approximately 1 dB. Therefore, the gain can be used to trade-off

between SFDR and SNR.

For each gain setting, the supported analog input full-scale range scales proportionally, as shown in Table 9.

After reset, the device comes up in 0-dB gain mode. To use other gain settings, program the GAIN_CH[3:0]

register bits.

Table 9. Analog Full-Scale Range Across Gains

GAIN_CH[3:0]

DIGITAL GAIN (dB)

ANALOG FULL-SCALE INPUT (V_PP)

0000

0001

0

2

1

1.78

1.59

1.42

1.26

1.12

1

0010

2

0011

3

0100

4

0101

5

0110

6

0111

7

0.89

0.8

1000

8

1001

9

0.71

0.63

0.56

0.5

1010

10

11

1011

1100

12

Other combinations

Do not use

—

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Digital Filter

The digital processing block includes the option to filter and decimate the ADC data outputs digitally. Various

filters and decimation rates are supported: decimation rates of 2, 4, and 8, and low-pass, high-pass, and band-

pass filters are available.

The filters are internally implemented as 24-tap symmetric finite impulse response (FIR) filters (even-tap) using

the predefined coefficients of Equation 4:

y(n) =

1

2¹¹

´ [h0.x(n) + h1.x(n-1) + h2.x(n-2) + ... + h11.x(n-11) + h12.x(n-12) + ... + h1.x (n-22) + h0.x(n-23)]

(4)

Alternatively, some filters can be configured as 23-tap symmetric FIR filters (odd-tap), as described in

Equation 5:

y(n) =

1

2¹¹

´ [h0.x(n) + h1.x(n-1) + h2.x(n-2) + ... + h10.x(n-10) + h11.x(n-11) + h10.x(n-12) + ... + h1.x (n-21) + h0.x(n-22)]

(5)

In Equation 4 and Equation 5, h0 through h11 are 12-bit, signed, twos complement representations of the

coefficients (–2048 to +2047). x(n) is the filter input data sequence and y(n) is the filter output sequence.

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Details of the registers used for configuring the digital filters are described in the digital filter registers (registers

29h, 2Eh, 2Fh, 30h, 31h, and 38h) and Table 10. Table 10 gives a summary of the register bits to be used for

each filter type.

Table 10. Digital Filters

USE_

FILTER_

CHn

EN_

CUSTOM_

FILT_CHn

DATA_ DEC_RATE

RATE

FILTER_

TYPE_CHn

ODD_

TAP_CHn

EN_DIG_

FILTER

DECIMATION

TYPE OF FILTER

_CHn⁽¹⁾

Built-in, low-pass, odd-tap filter

(pass band = 0 to f_S/ 4)

01

000

001

010

011

1

0

1

0

1

Decimate-by-2

Built-in, high-pass, odd-tap filter

(pass band = 0 to f_S/ 4)

01

10

000

001

Built-in, low-pass, even-tap filter

(pass band = 0 to f_S/ 8)

Built-in, first band pass, even-tap filter

(pass band = f_S/ 8 to f_S/ 4)

Decimate-by-4

Built-in, second band pass,

even-tap filter

10

001

100

0

1

0

1

(pass band = f_S/ 4 to 3 f_S/ 8)

Built-in, high-pass, odd-tap filter

(pass band = 3 f_S/ 8 to f_S/ 2)

10

01

10

11

001

000

001

100

101

000

1

0

1

Custom filter

(user-programmable coefficients)

Decimate-by-2

Decimate-by-4

Decimate-by-8

0 or 1

Custom filter

(user-programmable coefficients)

Custom filter

(user-programmable coefficients)

12-tap filter

without

decimation

Custom filter

(user-programmable coefficients)

00

011

000

0

1

(1) The DEC_RATE_CHn value must be the same for all channels.

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Predefined Coefficients

The built-in filter types (low pass, high pass, and band pass) use predefined coefficients. The frequency

response of the built-in filters is shown in Figure 62 and Figure 63.

20

10

40

30

Low-Pass

High-Pass

Low-Pass

Band-Pass 1

Band-Pass 2

High-Pass

20

0

10

−10

−20

−30

−40

−50

−60

−70

−80

0

−10

−20

−30

−40

−50

−60

−70

−80

0

0.1

0.2

0.3

0.4

0.5

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (f_IN/f_S)

G024

G025

Figure 62. Filter Response (Decimate-by-2)

Figure 63. Filter Response (Decimate-by-4)

The predefined coefficients for the decimate-by-2 and decimate-by-4 filters are listed in Table 11 and Table 12,

respectively.

Table 11. Predefined Coefficients for Decimate-by-2 Filters

DECIMATE-BY-2

COEFFICIENTS

LOW-PASS FILTER

HIGH-PASS FILTER

h0

h1

3

0

–22

–65

–52

30

h2

5

h3

1

h4

–27

–2

66

h5

–35

–107

38

h6

73

h7

3

h8

–178

–4

202

–41

–644

1061

h9

h10

h11

636

1024

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Table 12. Predefined Coefficients for Decimate-by-4 Filters

DECIMATE-BY-4

COEFFICIENTS

LOW-PASS FILTER

1st BAND-PASS FILTER 2nd BAND-PASS FILTER

HIGH-PASS FILTER

h0

h1

–17

–50

71

–7

19

–34

–101

43

40

–15

–95

22

h2

–47

127

73

h3

46

h4

24

58

–8

h5

–42

–100

–97

8

0

–28

–5

–81

106

–62

–97

310

–501

575

h6

86

h7

117

–190

–464

–113

526

–179

294

86

h8

h9

202

414

554

h10

h11

–563

352

Custom Filter Coefficients

In addition to the built-in filters described in the Predefined Coefficients section, customers also have the option

of using their own custom, 12-bit, signed coefficients. Because of the symmetric FIR implementation of the filters,

only 12 coefficients can be specified with the configuration of Equation 4 or Equation 5. These coefficients (h0 to

h11) must be configured in the custom coefficient registers as shown in Equation 6:

Register Content = 12-Bit Signed Representation of (Real Coefficient Value × 2¹¹)

(6)

The 12 custom coefficients must be loaded into 12 separate registers for each channel (refer to the custom

coefficient registers, 5Ah to B9h). The MSB bit of each coefficient register determines whether the built-in filters

or custom filters are used. If the EN_CUSTOM_FILT MSB bit is reset to '0', then the built-in filter coefficients are

used. Otherwise, the custom coefficients are used.

Custom Filter without Decimation

Another mode is available that enables the use of the digital filter without decimation. In this mode, the filter

behaves similar to a 12-tap symmetric FIR filter, as shown in Equation 7:

y(n) =

1

2¹¹

´ [h6.x(n) + h7.x(n-1) + h8.x(n-2) + h9.x(n-3) + h10.x(n-4) + h11.x(n-5) +

+ h11.x(n-6) + h10.x(n-7) + h9.x(n-8) + h8.x(n-9) + h7.x(n-10) + h6.x (n-11)]

(7)

In Equation 7, h6 through h11 are 12-bit, signed, twos complement representations of the coefficients (–2048 to

+2047). x(n) is the filter input data sequence and y(n) is the filter output sequence.

In this mode, because the filter is implemented as a 12-tap symmetric FIR, only six custom coefficients must be

specified and loaded in registers h6 to h11 (refer to the custom coefficient registers, 5Ah to B9h). To enable this

mode, use the register setting specified in bit 15 of registers AEh to B9h.

Digital High-Pass Filter

In addition to the 12 tap filters described previously, the digital processing block also includes a separate high-

pass filter for each channel. The high-pass corner frequency can be programmed using bits D[14:10] in register

2Eh.

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Digital Averaging

The ADS5295 includes an averaging function where the ADC digital data from two (or four) channels can be

averaged. The averaged data are output on specific LVDS channels. Table 13 shows the combinations of the

input channels that can be averaged and the LVDS channels on which the averaged data are available.

Table 13. Using Channel Averaging

OUTPUT WHERE

AVERAGED CHANNELS AVERAGED DATA ARE

AVAILABLE AT

REGISTER SETTINGS

1, 2

OUT1A, OUT1B

OUT3A, OUT3B

OUT4A, OUT4B

OUT2A, OUT2B

OUT1A, OUT1B

OUT4A, OUT4B

OUT5A, OUT5B

OUT7A, OUT7B

OUT8A, OUT8B

OUT6A, OUT6B

OUT5A, OUT5B

OUT8A, OUT8B

Set AVG_OUT1 = 10 and EN_CHANNEL_AVG = 1

Set AVG_OUT3 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT4 = 10 and EN_CHANNEL_AVG = 1

Set AVG_OUT2 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT1 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT4 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT5 = 10 and EN_CHANNEL_AVG = 1

Set AVG_OUT7 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT8 = 10 and EN_CHANNEL_AVG = 1

Set AVG_OUT6 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT5 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT8 = 11 and EN_CHANNEL_AVG = 1

3, 4

1, 2, 3, 4

5, 6

7, 8

5, 6, 7, 8

Performance with Digital Processing Blocks

In applications where higher SNR performance is desired, digital processing blocks (such as averaging and

decimation filters) can be used advantageously to achieve this. Table 14 shows the improvement in SNR that

can be achieved compared to the default value, using these modes.

Table 14. SNR Improvement Using Digital Processing

TYPICAL IMPROVEMENT IN

MODE⁽¹⁾

TYPICAL SNR (dB)⁽²⁾

SNR (dB)

Default

70.6

NA

With decimate-by-2 filter enabled

74.64

76.13

77.04

77.43

76.14

79.27

4.04

With decimate-by-4 filter enabled

5.53

With decimate-by-8 filter enabled

6.44

With two channels averaged and decimate-by-4 filter enabled

With four channels averaged

6.83

5.54

With four channels averaged and decimate-by-4 filter enabled

8.67

(1) Custom coefficients are used for the decimate-by-8 filter.

(2) In all these modes (except the default one), 14x serialization is used to capture data.

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PROGRAMMABLE MAPPING BETWEEN INPUT CHANNELS AND OUTPUT PINS

The ADS5295 has 16 pairs of LVDS channel outputs. The mapping of ADC channels to LVDS output channels is

programmable to allow for flexibility in board layout. The control register mapping is shown in Table 15. The 16

LVDS channel outputs are split into two groups of eight LVDS pairs. Within each group, four ADC input channels

can be multiplexed to the eight LVDS pairs, depending on the mode of operation (one-wire mode or two-wire

mode).

Table 15. Mapping Control Registers

ADDRESS

(Hex)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

1

X

MAP_CH1234_TO_OUT1A

MAP_CH1234_TO_OUT1B

MAP_CH1234_TO_OUT2A

MAP_CH1234_TO_OUT2B

MAP_CH1234_TO_OUT3A

MAP_CH1234_TO_OUT3B

MAP_CH1234_TO_OUT4A

MAP_CH1234_TO_OUT4B

MAP_CH5678_TO_OUT5B

MAP_CH5678_TO_OUT5A

MAP_CH5678_TO_OUT6B

MAP_CH5678_TO_OUT6A

MAP_CH5678_TO_OUT7B

MAP_CH5678_TO_OUT7A

MAP_CH5678_TO_OUT8B

MAP_CH5678_TO_OUT8A

50

X

51

52

53

X

54

55

X

Input channels 1 to 4 can be mapped to any LVDS output (OUT1A, OUT1B to OUT4A, OUT4B) using the

MAP_CH1234_TO_OUTnA, MAP_CH1234_TO_OUTnB bits, as shown in Table 16.

Table 16. Multiplexing IN1 to IN4

MAP_CH1234_TO_OUTN[3:0]⁽¹⁾

MAPPING

USED IN ONE-WIRE MODE?

USED IN TWO-WIRE MODE?

0000

ADC input channel IN1 to OUTn

Y

Y (LSB byte)

ADC input channel IN1 to OUTn

(two-wire only)

0001

0010

0011

0100

0101

0110

0111

N

Y

N

Y

N

Y

N

Y (MSB byte)

Y (LSB byte)

Y (MSB byte)

Y (LSB byte)

Y (MSB byte)

Y (LSB byte)

Y (MSB byte)

ADC input channel IN2 to OUTn

(two-wire only)

ADC input channel IN3 to OUTn

(two-wire only)

ADC input channel IN4 to OUTn

(two-wire only)

LVDS output buffer OUTn

powered down

1xxx

—

(1) n = 1A, 1B, 2A, 2B, 3A, 3B, 4A, or 4B.

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Similarly, input channels 5 to 8 can be mapped to any LVDS output (OUT5A, OUT5B to OUT8A, OUT8B) using

the MAP_CH5678_TO_OUTnA, MAP_CH5678_TO_OUTnB bits, as shown in Table 17. Both multiplexing

options are controlled by registers 50h to 55h. Channel mapping block diagrams for one-wire mode and two-wire

mode are illustrated in Figure 64 and Figure 65, respectively.

Table 17. Multiplexing IN5 to IN8

MAP_CH5678_TO_OUTN[3:0]⁽¹⁾

MAPPING

USED IN ONE-WIRE MODE?

USED IN TWO-WIRE MODE?

0000

ADC input channel IN8 to OUTn

Y

Y (LSB byte)

ADC input channel IN8 to OUTn

(two-wire only)

0001

0010

0011

0100

0101

0110

0111

N

Y

N

Y

N

Y

N

Y (MSB byte)

Y (LSB byte)

Y (MSB byte)

Y (LSB byte)

Y (MSB byte)

Y (LSB byte)

Y (MSB byte)

ADC input channel IN7 to OUTn

(two-wire only)

ADC input channel IN6 to OUTn

(two-wire only)

ADC input channel IN5 to OUTn

(two-wire only)

LVDS output buffer OUTn

powered down

1xxx

—

(1) n = 5A, 5B, 6A, 6B, 7A, 7B, 8A, or 8B.

Channel 8 Data

MAP_CH5678_to_OUTn[3:0] = 0000

Channel 7 Data

MAP_CH5678_to_OUTn[3:0] = 0010

(1)

OUTn

Channel 6 Data

MAP_CH5678_to_OUTn[3:0] = 0100

MAP_CH5678_to_OUTn[3:0] = 1xxx,

the unused OUTn LVDS buffer is powered down.

Channel 5 Data

MAP_CH5678_to_OUTn[3:0] = 0110

Channel 4 Data

MAP_CH1234_to_OUTn[3:0] = 0110

Channel 3 Data

MAP_CH1234_to_OUTn[3:0] = 0100

(1)

OUTn

Channel 2 Data

MAP_CH1234_to_OUTn[3:0] = 0010

MAP_CH1234_to_OUTn[3:0] = 1xxx,

the unused OUTn LVDS buffer is powered down.

Channel 1 Data

MAP_CH1234_to_OUTn[3:0] = 0000

(1) For channels 1 to 4, n = 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B. For channels 5 to 8, n = 5A, 5B, 6A, 6B, 7A, 7B, 8A, and 8B.

Figure 64. One-Wire Channel Mapping Mode

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Channel 1 LSB Byte Data[7:0]

MAP_CH1234_to_OUTn[3:0] = 0000

Channel 1 MSB Byte Data[15:8]

MAP_CH1234_to_OUTn[3:0] = 0001

Channel 2 LSB Byte Data[7:0]

MAP_CH1234_to_OUTn[3:0] = 0010

Channel 2 MSB Byte Data[15:8]

MAP_CH1234_to_OUTn[3:0] = 0011

(1)

OUTn

Channel 3 LSB Byte Data[7:0]

MAP_CH1234_to_OUTn[3:0] = 0100

Channel 3 MSB Byte Data[15:8]

MAP_CH1234_to_OUTn[3:0] = 0101

MAP_CH1234_to_OUTn[3:0] = 1xxx,

the unused OUTn LVDS buffer is powered down.

Channel 4 LSB Byte Data[7:0]

MAP_CH1234_to_OUTn[3:0] = 0110

Channel 4 MSB Byte Data[15:8]

MAP_CH1234_to_OUTn[3:0] = 0111

Channel 8 LSB Byte Data[7:0]

MAP_CH5678_to_OUTn[3:0] = 0000

Channel 8 MSB Byte Data[15:8]

MAP_CH5678_to_OUTn[3:0] = 0001

Channel 7 LSB Byte Data[7:0]

MAP_CH5678_to_OUTn[3:0] = 0010

Channel 7 MSB Byte Data[15:8]

MAP_CH5678_to_OUTn[3:0] = 0011

(1)

OUTn

Channel 6 LSB Byte Data[7:0]

MAP_CH5678_to_OUTn[3:0] = 0100

Channel 6 MSB Byte Data[15:8]

MAP_CH5678_to_OUTn[3:0] = 0101

MAP_CH5678_to_OUTn[3:0] = 1xxx,

the unused OUTn LVDS buffer is powered down.

Channel 5 LSB Byte Data[7:0]

MAP_CH5678_to_OUTn[3:0] = 0110

Channel 5 MSB Byte Data[15:8]

MAP_CH5678_to_OUTn[3:0] = 0111

(1) For channels 1 to 4, n = 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B. For channels 5 to 8, n = 5A, 5B, 6A, 6B, 7A, 7B, 8A, and 8B.

Figure 65. Two-Wire Channel Mapping Mode

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The default mapping for the one-wire and two-wire modes is shown in Table 18 and Table 19, respectfully.

Table 18. Mapping for One-Wire Mode

ANALOG INPUT CHANNEL

Channel IN1

LVDS OUTPUT⁽¹⁾

OUT1A

Channel IN2

OUT2A

Channel IN3

OUT3A

Channel IN4

OUT4A

Channel IN5

OUT5A

Channel IN6

OUT6A

Channel IN7

OUT7A

Channel IN8

OUT8A

(1) ADC data are only available on OUTnA with default register settings.

Table 19. Mapping for Two-Wire Mode

ANALOG INPUT CHANNEL

Channel IN1

LVDS OUTPUT⁽¹⁾

OUT1A, OUT1B

OUT2A, OUT2B

OUT3A, OUT3B

OUT4A, OUT4B

OUT5A, OUT5B

OUT6A, OUT6B

OUT7A, OUT7B

OUT8A, OUT8B

Channel IN2

Channel IN3

Channel IN4

Channel IN5

Channel IN6

Channel IN7

Channel IN8

(1) ADC data are available on both OUTnA and OUTnB.

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SYNCHRONIZATION USING THE SYNC PIN

The SYNC pin can be used to synchronize the data output from channels within the same chip or from channels

across multiple chips when decimation filters are used with a reduced output data rate. When decimation filters

are used (if the decimate-by-2 filter is enabled, for example), then effectively, the device outputs one digital code

for every two analog input samples. If the SYNC pulse is not used, then the filters are not synchronized (even

within a chip). When the filters are not synchronized, one channel may be transmitting codes corresponding to

input samples N, N+1, and so on, while another channel may be transmitting codes corresponding to N+1, N+2,

and so on.

To achieve synchronization across multiple chips, the SYNC pulse must arrive at all ADS5295 chips at the same

time (as shown in Figure 66). The ADS5295 generates an internal synchronization signal that resets the internal

clock dividers used by the decimation filter. Using the SYNC signal in this way ensures that all channels output

digital codes corresponding to the same set of input samples.

Synchronizing the filters using the SYNC pin is enabled by default. No register bits are required to be written.

The TP_HARD_SYNC register bit must be reset to '0' for this mode to function properly. As shown in Figure 66,

the SYNC rising edge can be positioned anywhere within the window. SYNC width must be at least one clock

cycle.

In addition, SYNC can also be used to synchronize the RAMP test patterns across channels. In order to

synchronize the test patterns, TP_HARD_SYNC must be set to '1'. Setting TP_HARD_SYNC to '1' actually

disables the sync of the filters.

0 ns

t_CLK/ 2

ADC Input

Clock

-1 ns

t_CLK/ 2

t_D= -1 ns < t_D< t_CLK/ 2

SYNC

t_WIDTH³ 1 Clock Cycle

Figure 66. SYNC Timing Diagram

Synchronizing ADC Sampling Instants

Note that SYNC does not and cannot be used to synchronize the ADC sampling instants across chips. All

channels within a single chip sample the analog inputs simultaneously. To ensure that channels across two chips

sample the analog inputs simultaneously, the input clock must be routed to both chips with an identical length.

This layout ensures that the input clocks arrive at both chips at the same time. Therefore, the SYNC pin cannot

be used to synchronize the sampling instants because the input clock routing must be implemented during board

design.

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DIGITAL OUTPUT INTERFACE

SERIAL LVDS INTERFACE

The ADS5295 offers several flexible output options, making the device easy to interface to an application-specific

integrated circuit (ASIC) or a field-programmable gate array (FPGA). Each option can be easily programmed

using the serial interface. A summary of all available options is listed in Table 20 along with the default values

after power-up and reset. Following Table 20, each option is described in detail. Table 21 lists the two-wire

register settings for the LVDS interface.

Table 20. Summary of Output Interface Options

AVAILABLE IN:

DEFAULT AFTER

ONE-

WIRE

TWO-

WIRE

POWER-UP AND

RESET

FEATURE

OPTIONS

BRIEF DESCRIPTION

One-wire: ADC data are sent serially over one pair

of LVDS pins.

Two-wire: ADC data are split and sent serially over

two pairs of LVDS pins.

Wire interface

One- and two-wire

N

One-wire

12x

10x

Y

12x

To be used with digital processing functions, such

as averaging and decimation filers.

Serialization factor

14x

16x

Y

N

Y

N

Y

To be used with digital processing functions, such

as averaging and decimation filers.

Only available with one-wire interface for 12x, 10x,

14x, and 16x serialization factors, respectively.

6x, 5x, 7x, 8x

3x, 2.5x, 3.5x, 4x

6x

DDR bit clock frequency

Frame clock frequency

Only available with two-wire interface for 12x, 10x,

14x, and 16x serialization factors, respectively.

1x sample rate

Y

N

Y

1x

1/2x sample rate

Only available with the two-wire interface.

Byte-wise: the ADC data are split into upper and

lower bytes that are output on separate wires.

Byte-wise

Bit-wise

N

Y

Byte-wise

Only available with the two-wire interface.

Bit-wise: the ADC data are split into even and odd

bits that are output on separate wires.

Bit sequence

Only available with the two-wire interface.

Word-wise: successive ADC data samples are sent

over separate wires.

Word-wise

Table 21. Register Settings for Two-wire LVDS Interface

D[7:0]

D8 (EN_BIT_WISE)

D15 (EN_WORD_BIT_WISE)

LVDS OUTPUT

(EN_WORDWISE_BY_CH)

0

1

X

1

X

1

0

Byte-wise mode

Word-wise mode

Bit-wise mode

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One-Wire, 12x Serialization with DDR Bit Clock and 1x Frame Clock

The 12-bit ADC data are serialized and output over one LVDS pair per channel along with a 6x bit clock and a 1x

frame clock, as shown in Figure 67. The output data rate is a 12x sample rate; therefore, it is suited for low

sample rates.

Input Clock

(CLK Frequency = f_S)

Frame Clock

(ADCLK Frequency = 1x f_S)

Bit Clock

(LCLK Frequency = 6x f_S)

Output Data⁽¹⁾

(OUTA Data rate = 12x f_S)

D11

(D0)

D10

(D1)

D9

(D2)

D8

(D3)

D7

(D4)

D6

(D5)

D5

(D6)

D4

(D7)

D3

(D8)

D2

(D9)

D1

(D10)

D0

(D11)

D11

(D0)

D10

(D1)

Sample N

Sample N+1

(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.

Figure 67. LVDS Output Interface Timing Diagram (One-Wire, 12x Serialization)

One-Wire, 10x Serialization with DDR Bit Clock and 1x Frame Clock

The 10 upper bits of the 12-bit ADC data are serialized and output over one LVDS pair per channel along with a

5x bit clock and a 1x frame clock, as shown in Figure 68. The output data rate is a 10x sample rate; therefore, it

is suited for low sample rates, typically up to 65 MSPS.

Input Clock

(CLK Frequency = f_S)

Frame Clock

(ADCLK Frequency = 1x f_S)

Bit Clock

(LCLK Frequency = 5x f_S)

Output Data⁽¹⁾

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D9

D8

D7

(OUTA Data rate = 10x f_S)

(D0)

(D1)

(D2)

(D3)

(D4)

(D5)

(D6)

(D7)

(D8)

(D9)

(D0)

(D1)

(D2)

Sample N

Sample N+1

(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.

Figure 68. LVDS Output Interface Timing Diagram (One-Wire, 10x Serialization)

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Two-Wire, 12x Serialization with DDR Bit Clock and 1/2x Frame Clock

The 12-bit ADC data are serialized and output over two LVDS pairs per channel, as shown in Figure 69 and

Figure 70. The output data rate is a 12x sample rate with a 3x bit clock and a 1/2x frame clock. This interface

can be used up to the maximum sample rate of the device because the output data rate is half of the data rate in

the one-wire case.

Input Clock, CLK

Frequency = f_S

Frame Clock, ADCLK

Frequency = 1x f_S

Bit Clock, DDR LCLK

Frequency = 3x f_S

Output Data

OUT1B, OUT2B,

OUT3B, OUT4B

D9

(D2)

D8

(D3)

D7

(D4)

D6

(D5)

D11

(D0)

D10

(D1)

D9

(D2)

D8

(D3)

D7

(D4)

D6

(D5)

D11

(D0)

D10

(D1)

Output Data

OUT1A, OUT2A,

OUT3A, OUT4A

D5

(D6)

D4

(D7)

D3

(D8)

D2

(D9)

D1

(D10)

D0

(D11)

D5

(D6)

D4

(D7)

D3

(D8)

D2

(D9)

D1

(D10)

D0

(D11)

Output Data

OUT1B, OUT2B,

OUT3B, OUT4B

D6

(D5)

D4

(D7)

D2

(D9)

D0

(D11)

D10

(D1)

D8

(D3)

D6

(D5)

D4

(D7)

D2

(D9)

D0

(D11)

D10

(D1)

D8

(D3)

Output Data

OUT1A, OUT2A,

OUT3A, OUT4A

D11

(D0)

D9

(D2)

D7

(D4)

D5

(D6)

D3

(D8)

D1

(D10)

D11

(D0)

D9

(D2)

D7

(D4)

D5

(D6)

D3

(D8)

D1

(D10)

Data Rate = 6x f_S

White Cells = Sample N

Grey Cells = Sample N+1

Data Bit in MSB-First Mode

D5

(D0)

Data Bit in LSB-First Mode

(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.

(2) Shaded cells correspond to N+1 samples. Unshaded cells correspond to N samples.

Figure 69. LVDS Output Interface Timing Diagram

(Two-Wire, 12x Serialization, Byte-Wise and Bit-Wise Modes)

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Input Clock, CLK

Frequency = f_S

Frame Clock, ADCLK

Frequency = 1x f_S

Bit Clock, DDR LCLK

Frequency = 3x f_S

Output Data

OUT1A, OUT2A,

OUT3A, OUT4A

D6

(D5)

D7

(D4)

D8

(D3)

D9

(D2)

D10

(D1)

D11

(D0)

D2

(D9)

D3

(D8)

D4

(D7)

D5

(D6)

D0

(D11)

D1

(D10)

Output Data

OUT1B, OUT2B,

OUT3B, OUT4B

D6

(D5)

D7

(D4)

D8

(D3)

D9

(D2)

D10

(D1)

D11

(D0)

D2

(D9)

D3

(D8)

D4

(D7)

D5

(D6)

D0

(D11)

D1

(D10)

Data Rate = 6x f_S

White Cells = Sample N

Grey Cells = Sample N+1

Data Bit in LSB-First Mode

Data Bit in MSB-First Mode

D0

(D11)

Figure 70. LVDS Output Interface Timing Diagram (Two-Wire, 12x Serialization, Word-Wise Mode)

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Two-Wire, 10x Serialization with DDR Bit Clock and 1/2x Frame Clock

The 10 upper bits of the 12-bit ADC data are serialized and output over two LVDS pairs per channel, as shown in

Figure 71. The output data rate is a 5x sample rate per wire with a 2.5x bit clock and a 1/2x frame clock. This

interface can be used up to the maximum sample rate of the device because the output data rate is half of the

data rate in the one-wire case.

Input Clock, CLK

Frequency = f_S

Frame Clock, ADCLK

Frequency = 1x f_S

Bit Clock, DDR LCLK

Frequency = 2.5x f_S

Output Data

OUT1B, OUT2B,

OUT3B, OUT4B

D7

(D2)

D6

(D3)

D5

(D4)

D7

(D2)

D6

(D3)

D5

(D4)

D9

(D0)

D8

(D1)

D9

(D0)

D8

(D1)

Output Data

OUT1A, OUT2A,

OUT3A, OUT4A

D4

(D5)

D3

(D6)

D2

(D7)

D1

(D8)

D0

(D9)

D4

(D5)

D3

(D6)

D2

(D7)

D1

(D8)

D0

(D9)

Output Data

OUT1B, OUT2B,

OUT3B, OUT4B

D4

(D5)

D2

(D7)

D0

(D9)

D4

(D5)

D2

(D7)

D0

(D9)

D8

(D1)

D6

(D3)

D8

(D1)

D6

(D3)

Output Data

OUT1A, OUT2A,

OUT3A, OUT4A

D9

(D0)

D7

(D2)

D5

(D4)

D3

(D6)

D1

(D8)

D9

(D0)

D7

(D2)

D5

(D4)

D3

(D6)

D1

(D8)

Data Rate = 2.5x f_S

White Cells = Sample N

Grey Cells = Sample N+1

Data Bit in MSB-First Mode

D9

(D0)

Data Bit in LSB-First Mode

(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.

(2) Shaded cells correspond to N+1 samples. Unshaded cells correspond to N samples.

Figure 71. LVDS Output Interface Timing Diagram (Two-Wire, 10x Serialization)

When digital signal processing functions are used, the 14x and 16x serialization modes can also be used. These

modes are:

•

One-wire, 14x and 16x serialization with DDR bit clock and 1x frame clock mode, and

Two-wire, 14x with DDR bit clock and 1/2x frame clock mode.

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PROGRAMMABLE LCLK PHASE

The ADS5295 enables the edge of the output bit clock (LCLK) to be programmed with the PHASE_DDR register

bits. The default value of PHASE_DDR after reset is '10'. The default phase is shown in Figure 72.

ADCLKP

LCLKP

DATA

OUT

PHASE_DDR[1:0] = 10

Figure 72. Default LCLK Phase

The phase can also be changed by changing the value of the PHASE_DDR[1:0] bits, as shown in Figure 73.

ADCLKP

LCLKP

DATA

OUT

DATA

OUT

PHASE_DDR[1:0] = 10

PHASE_DDR[1:0] = 00

ADCLKP

LCLKP

ADCLKP

LCLKP

DATA

OUT

DATA

OUT

PHASE_DDR[1:0] = 11

PHASE_DDR[1:0] = 01

Figure 73. Programmable LCLK Phases

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PROGRAMMABLE LVDS OUTPUT CLOCK AND DATA EDGES

The ADS5295 enables the edges of the output data and output bit clock to be programmed with the

DELAY_DATA and DELAY_LCLK register bits.

Figure 74 details the timing of the output data and clock edge movements.Table 22 and Table 23 show the

register settings and corresponding delay values for the data and clock edge movements.

t_DF

DATA

t_DR

LCLKN

LCLKP

t_CR

t_CF

Figure 74. LVDS Interface Output Data and Clock Edge Movement

Table 22. LVDS Interface Output Data Delay Settings⁽¹⁾

DATA DELAY, RISING CLOCK

EDGE

DATA DELAY, FALLING CLOCK

EDGE

DELAY_DATA_R[1:0]

t_DR, Typical (ps)

DELAY_DATA_F[1:0]

t_DF, Typical (ps)

0

1

0

1

0

1

0

1

0

1

0

1

0

33

72

120

(1) Delay settings are the same for both 10x and 12x serialization modes.

Table 23. LVDS Interface Output Clock Delay Settings⁽¹⁾

CLOCK RISING EDGE DELAY

t_CR, Typical (ps)

CLOCK FALLING EDGE DELAY

DELAY_LCLK_R[2:0]

DELAY_LCLK_F[2:0]

t_CF, Typical (ps)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

33

72

120

106

159

202

244

120

106

159

202

244

(1) Delay settings are the same for both 10x and 12x serialization modes.

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LVDS OUTPUT DATA AND CLOCK BUFFERS

The equivalent circuit of each LVDS output buffer is shown in Figure 75. After reset, the buffer presents an

output impedance of 100 Ω to match with the external 100-Ω termination.

The V_DIFFvoltage is nominally 350 mV, resulting in an output swing of ±350 mV with a 100-Ω external

termination. The buffer output impedance behaves in the same way as a source-side series termination. By

absorbing reflections from the receiver end, this impedance helps improve signal integrity.

V_DIFF

High

Low

OUTP

OUTM

External

100-W Load

V_OCM

(1)

R_OUT

V_DIFF

High

Low

(1) R_OUT= 100 Ω.

Figure 75. LVDS Buffer Equivalent Circuit

OUTPUT DATA FORMAT

Two output data formats are supported: twos complement and offset binary. These formats can be selected by

the BTC_MODE serial interface register bit. In the event of an input voltage overdrive, the digital outputs go to

the appropriate full-scale level. For a positive overload, the 12-bit output data (D[11:0]) is FFFh in offset binary

output format and 7FFh in twos complement output format. For a negative input overload, the output data is 000h

in offset binary output format and 800h in twos complement output format.

BOARD DESIGN CONSIDERATIONS

Grounding

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of

the board are cleanly partitioned. See the EVM User Guide (ADS5295, 8-Channel ADC Evaluation Module,

SLAU442) for details on layout and grounding.

Supply Decoupling

Minimal external decoupling can be used without loss in performance because the ADS5295 already includes

internal decoupling. Note that decoupling capacitors can help filter external power-supply noise; thus, the

optimum number of capacitors would depend on the actual application. The decoupling capacitors should be

placed very close to the converter supply pins.

Exposed Pad

In addition to providing a path for heat dissipation, the pad is also electrically connected to the digital ground

internally. Therefore, the exposed pad must be soldered to the ground plane for best thermal and electrical

performance.

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DEFINITION OF SPECIFICATIONS

Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with

respect to the low-frequency value.

Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at

which the sampling occurs. This delay is different across channels. The maximum variation is specified as

aperture delay variation (channel-to-channel).

Aperture Uncertainty (jitter): The sample-to-sample variation in aperture delay.

Clock Pulse Width (duty cycle): The duty cycle of a clock signal is the ratio of the time that the clock signal

remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a

percentage. A perfect differential sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric

testing is performed at this sampling rate, unless otherwise noted.

Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly

1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.

Integral Nonlinearity (INL): INL is the deviation of the ADC transfer function from a best-fit line determined by a

least-squares curve fit of that transfer function, measured in units of LSBs.

Gain Error: Gain error is the deviation of the actual ADC input full-scale range from its ideal value. The gain

error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a

result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as

E_GREFand E_GCHAN, respectively. To a first-order approximation, the total gain error is (E_TOTAL~ E_GREF+ E_GCHAN).

For example, if E_TOTAL= ±0.5%, then the full-scale input varies from [(1 – 0.5 / 100) × FS_IDEAL] to [(1 + 0.5 / 100)

× FS_IDEAL].

Offset Error: Offset error is the difference, given in number of LSBs, between the actual average ADC idle

channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.

Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the

change per degree Celsius of the parameter from T_MINto T_MAX. Drift is calculated by dividing the maximum

deviation of the parameter across the T_MINto T_MAXrange by the difference of T_MAX– T_MIN

.

Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (P_S) to the noise floor power

(P_N), excluding the power at dc and the first nine harmonics. SNR is either given in units of dBc (dB to carrier)

when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power

of the fundamental is extrapolated to the converter full-scale range.

P_S

SNR = 10 Log¹⁰

P_N

(8)

Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (P_S) to the power

of all the other spectral components, including noise (P_N) and distortion (P_D), but excluding dc. SINAD is either

given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or

dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

P_S

SINAD = 10 Log¹⁰

P_N+ P_D

(9)

Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the

theoretical limit based on quantization noise.

SINAD - 1.76

ENOB =

6.02

(10)

Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (P_S) to the power of the first

nine harmonics (P_D). THD is typically given in units of dBc (dB to carrier).

P_S

THD = 10 Log¹⁰

P_N

(11)

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83

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ADS5295

SBAS595 –DECEMBER 2012

www.ti.com

Spurious-Free Dynamic Range (SFDR): SFDR is the ratio of power of the fundamental to the highest other

spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).

Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies

f₁and f₂) to the power of the worst spectral component at either frequency 2 f₁– f₂or 2 f₂– f₁. IMD3 is either

given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or

dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply

voltage by the ADC. If ΔV_SUPis the change in supply voltage and ΔV_OUTis the resultant change of the ADC

output code (referred to the input), then:

DV_OUT

PSRR = 20 Log¹⁰

(Expressed in dBc)

DV_SUP

(12)

Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an

overload on the analog inputs. This recovery is tested by separately applying a sine-wave signal with 6-dB

positive and negative overload. The deviation of the first few samples after the overload (from the expected

values) is noted.

Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input

common-mode by the ADC. If ΔV_{CM_IN}is the change in the common-mode voltage of the input pins and ΔV_OUTis

the resulting change of the ADC output code (referred to the input), then:

DV_OUT

CMRR = 20 Log¹⁰

(Expressed in dBc)

DV_CM

(13)

CROSSTALK: (only for multichannel ADCs) Crosstalk is a measure of the internal coupling of a signal from an

adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate

neighboring channel (near-channel) and for coupling from a channel across the package (far-channel). Crosstalk

is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of

the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the

adjacent channel input. Crosstalk is typically expressed in dBc.

84

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Product Folder Links: ADS5295

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS5295PFPR

ADS5295PFPT

HTQFP

PFP

80

1000

250

330.0

24.4

15.0

1.5

20.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS5295PFPR

ADS5295PFPT

HTQFP

PFP

80

1000

250

367.0

45.0

Pack Materials-Page 2

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型号：	ADS5295PFPR
厂家：	TEXAS INSTRUMENTS
描述：	八通道 12 位、100MSPS 高 SNR 低功耗 ADC \| PFP \| 80 \| -40 to 85 转换器模数转换器
文件：	总91页 (文件大小：2512K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS5295PFPR [TI]

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