ADS5294IPFPR [TI]

八通道、14 位、80MSPS 模数转换器 (ADC) | PFP | 80 | -40 to 85;


型号：	ADS5294IPFPR
厂家：	TEXAS INSTRUMENTS
描述：	八通道、14 位、80MSPS 模数转换器 (ADC) \| PFP \| 80 \| -40 to 85 转换器模数转换器
文件：	总67页 (文件大小：2460K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS5294

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SLAS776B –NOVEMBER 2011–REVISED JULY 2012

Octal Channel 14-Bit, 80 MSPS High-SNR and Low-Power ADC

Check for Samples: ADS5294

FEATURES

DESCRIPTION

Using CMOS process technology and innovative

circuit techniques, the ADS5294 is a low power

80MSPS 8-Channel ADC. Low power consumption,

high SNR, low SFDR, and consistent overload

recovery allow users to design high performance

systems.

•

Maximum Sample Rate: 80 MSPS/14-Bit

High Signal-to-Noise Ratio

–

75.5-dBFS SNR at 5 MHz/80 MSPS

78.2-dBFS SNR at 5 MHz/80 MSPS and

Decimation Filter Enabled

The ADS5294 has a digital processing block that

integrates several commonly used digital functions for

improving system performance. It includes a digital

filter module that has built-in decimation filters (with

low-pass, high-pass and band-pass characteristics).

The decimation rate is also programmable (by 2, by

4, or by 8). This makes it useful for narrow-band

applications, where the filters can be used

conveniently to improve SNR and knock-off

harmonics, while at the same time reducing the

output data rate. The device includes an averaging

mode where two channels (or even four channels)

can be averaged to improve SNR.

–

84-dBc SFDR at 5 MHz/80 MSPS

•

Low Power Consumption

–

58 mW/CH at 50 MSPS

77 mW/CH at 80 MSPS (2 LVDS Wire Per

Channel)

Digital Processing Block

–

Programmable FIR Decimation Filter and

Oversampling to Minimize Harmonic

Interference

–

Programmable IIR High Pass Filter to

Minimize DC Offset

Serial LVDS outputs reduce the number of interface

lines and enable the highest system integration. The

digital data from each channel ADC can be output

over one or two wires of LVDS output lines

depending on the ADC sampling rate. This 2-wire

interface helps keep the serial data rate low, allowing

low cost FPGA based receivers to be used even at

high sample rate. The ADC resolution can be

programmed to 12 bit or 14 bit through registers. A

very unique feature is the programmable mapping

module that allows flexible mapping between the

input channels and the LVDS output pins. This helps

greatly reduce the complexity of LVDS output routing

and can potentially result in cheaper system boards

by reducing the number of PCB layers.

–

Programmable Digital Gain: 0 dB to 12 dB

2- or 4- Channel Averaging

•

Flexible Serialized LVDS Outputs:

–

One or Two Wires of LVDS Output Lines

per Channel Depending on ADC Sampling

Rate

Programmable Mapping Between ADC

Input Channels and LVDS Output Pins-

Eases Board Design

Variety of Test Patterns to Verify Data

Capture by FPGA/Receiver

•

Internal and External References

1.8V Operation for Low Power Consumption

Low-Frequency Noise Suppression

The device integrates an internal reference trimmed

to accurately match across devices. Best

performance is expected to be achieved through the

internal reference mode. The device can be driven

with external references as well.

Recovery From 6-dB Overload within 1 Clock

Cycle

•

Package: 12-mm × 12-mm 80-Pin QFP

The device is available in a 12 mm × 12 mm 80-pin

QFP. It is specified over a –40°C to 85°C operating

temperature range. ADS5294 is completely pin-to-pin

and register compatible to ADS5292.

APPLICATIONS

•

Ultrasound Imaging

Communication Applications

Multi-channel Data Acquisition

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS5294

SLAS776B –NOVEMBER 2011–REVISED JULY 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Figure 1. Block Diagram

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PACKAGING/ORDERING INFORMATION⁽¹⁾

PRODUCT

PACKAGE TYPE

OPERATING

ORDERING NUMBER

TRANSPORT MEDIA, QUANTITY

Tray, 480 (MOQ)

ADS5294IPFP

ADS5294

PFP

–40°C to 85°C

ADS5294IPFPR

ADS5294IPFPT

Tape and Reel, 1000

Tape and Reel, 250

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

PIN CONFIGURATION

80-PIN TQFP WITH THERMAL PAD

PFP PACKAGE (TOP VIEW)

80 79 78 77 76

71 70 69 68 67 66 65 64 63 62 61

73 72

IN2p

IN2n

IN7n

IN7p

AGND

IN6n

Thermal Pad

IN3p

IN3n

IN6p

AGND

IN4p

AGND

IN5n

IN4n

IN5p

AVDD

RESET

LGND

ADS529X

80 TQFP

LVDD

LGND

LVDD

OUT8A_n

OUT1A_p

OUT1A_n

OUT8A_p

OUT8B_n

OUT8B_p

OUT7A_n

OUT7A_p

OUT1B_p

OUT1B_n

OUT2A_p

OUT2A_n

OUT2B_p

OUT2B_n

OUT7B_n

OUT7B_p

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PIN FUNCTIONS

NUMBER

OF PINS

DESCRIPTION

NAME

AVDD

AGND

VCM

NUMBER

9, 52, 66, 71, 74

Analog power supply, 1.8V

3, 6, 55, 58, 61, 80 Analog ground

Common-mode output pin, 0.95 V output. This pin can be configured as the external reference

voltage (1.5 V) input pin as well. See Reg 0x42.

CLKN

CLKP

Negative differential clock –Tie CLKN to GND for single-ended clock

Positive differential clock

IN1P, IN1N

IN2P, IN2N

IN3P, IN3N

78, 79

1, 2

4, 5

Differential input signal, Channel 1

Differential input signal, Channel 2

Differential input signal, Channel 3

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PIN FUNCTIONS (continued)

NUMBER

OF PINS

DESCRIPTION

NAME

NUMBER

7, 8

IN4P, IN4N

Differential input signal, Channel 4

Differential input signal, Channel 5

Differential input signal, Channel 6

Differential input signal, Channel 7

Differential input signal, Channel 8

Differential LVDS bit clock (7X)

Differential LVDS frame clock (1X)

IN5P, IN5N

53, 54

56, 57

59, 60

62, 63

31, 32

29, 30

13, 14

15, 16

17, 18

19, 20

21, 22

23, 24

25, 26

27, 28

35, 36

33, 34

39, 40

37, 38

43, 44

41, 42

47, 48

45, 46

IN6P, IN6N

IN7P, IN7N

IN8P, IN8N

LCLKP, LCLKN

ACLKP, ACLKN

OUT1A_P, OUT1A_N

OUT1B_P, OUT1B_N

OUT2A_P, OUT2A_N

OUT2B_P, OUT2B_N

OUT3A_P, OUT3A_N

OUT3B_P, OUT3B_N

OUT4A_P, OUT4A_N

OUT4B_P, OUT4B_N

OUT5A_P, OUT5A_N

OUT5B_P, OUT5B_N

OUT6A_P, OUT6A_N

OUT6B_P, OUT6B_N

OUT7A_P, OUT7A_N

OUT7B_P, OUT7B_N

OUT8A_P, OUT8A_N

OUT8B_P, OUT8B_N

Differential LVDS data output, wire 1, channel 1

Differential LVDS data output, wire 2, channel 1

Differential LVDS data output, wire 1, channel 2

Differential LVDS data output, wire 2, channel 2

Differential LVDS data output, wire 1, channel 3

Differential LVDS data output, wire 2, channel 3

Differential LVDS data output, wire 1, channel 4

Differential LVDS data output, wire 2, channel 4

Differential LVDS data output, wire 1, channel 5

Differential LVDS data output, wire 2, channel 5

Differential LVDS data output, wire 1, channel 6

Differential LVDS data output, wire 2, channel 6

Differential LVDS data output, wire 1, channel 7

Differential LVDS data output, wire 2, channel 7

Differential LVDS data output, wire 1, channel 8

Differential LVDS data output, wire 2, channel 8

Power down control input. Active High. The pin has an internal 220-kΩ pulldown resistor.

Negative reference input/ output

REFB

REFT

Positive reference input/ output

RESET

Active HIGH RESET input. The pin has an internal 220-kΩ pulldown resistor.

Serial clock input. The pin has an internal 220-kΩ pulldown resistor.

Serial data input. The pin has an internal 220-kΩ pulldown resistor.

SCLK

SDATA

SDOUT

Serial data readout. This pin is in the high-impedance state after reset. When the <READOUT> bit

is set, the SDOUT pin becomes active. This is a CMOS digital output running from the AVDD

supply.

CSZ

Serial enable chip select – active low digital input

SYNC

Input signal to synchronize channels and chips when used with reduced output data rates. If it is

not used, add a ≤ 10 KΩ pull-down resistor.

LVDD

LGND

11, 49

12, 50

Digital and I/O power supply, 1.8V

Digital ground

No Connection. Must leave floated

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

–0.3

MAX

2.2

Supply voltage AVDD

LVDD

2.2

between AGND and LGND

0.3

at analog inputs

at digital inputs, CLKN, CLKP⁽²⁾, RESET, SCLK, SDATA, CSZ

min[2.2, AVDD+0.3]

Voltage

min[2.2, AVDD+0.3]

at digital outputs

Maximum junction temperature (T_J), any condition

Storage temperature range

min[2.2,LVDD+0.3]

105

150

°C

–55

-40

Operating temperature range

Human Body Model (HBM)

ESD Ratings

2000

500

Charged Device Model (CDM)

(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.

(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKN is < |0.3V|. This

prevents the ESD protection diodes at the clock input pins from turning on.

THERMAL INFORMATION

ADS5294

THERMAL METRIC⁽¹⁾

UNITS

PFP (80 PINS)

θ_JA

Junction-to-ambient thermal resistance

30.8

6.3

8.3

0.2

8.2

0.3

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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UNIT

RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

SUPPLIES

AVDD Analog supply voltage

LVDD Digital supply voltage

ANALOG INPUTS/OUTPUTS

Differential input voltage range

Input common-mode voltage

REF_TExternal reference mode

REF_BExternal reference mode

1.7

1.8

1.9

0.95±0.05

1.45

V_PP

0.45

VCM

Common-mode voltage output

External Reference mode Input

0.95

1.5

(1)

Maximum Input Frequency

2 V_PPamplitude

MHz

CLOCK INPUTS

ADC Clock input sample rate

0.2

MSPS

V_PP

Sine wave, AC-coupled

LVPECL, AC-coupled

LVDS, AC-coupled

1.5

1.6

Input Clock amplitude differential (V_(CLKP)

V_(CLKN)) peak-to-peak

0.7

V_IL

V_IH

<0.3

>1.5

50%

Input Clock CMOS single-ended (V_(CLKP)

Input clock duty cycle

)

35%

65%

DIGITAL OUTPUTS

1x (sample

rate)

ACLKP and ACLKN outputs (LVDS), 1-wire interface

LCLKP and LCLKN outputs (LVDS), 1-wire interface

ACLKP and ACLKN outputs (LVDS), 2-wire interface

LCLKP and LCLKN outputs (LVDS), 2-wire interface

MSPS

7x (sample

rate)

0.5x (sample

rate)

3.5x (sample

rate)

Maximum data rate, 2-wire interface

560

700

Mbps

Maximum data rate, 1-wire interface

C_LOADMaximum external capacitance from each output pin to LGND

R_LOADDifferential load resistance between the LVDS output pairs

100

T_A

Operating free-air temperature

-40

°C

(1) See the Large and Small Signal Input Bandwidth section.

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SLAS776B –NOVEMBER 2011–REVISED JULY 2012

ELECTRICAL CHARACTERISTICS DYNAMIC PERFORMANCE

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, Sample

rate = 80 MSPS, ADC is configured in internal reference mode (unless otherwise noted). MIN and MAX values are across the

full temperature range T_MIN= –40°C to T_MAX= 85°C, AVDD = 1.8 V, LVDD = 1.8 V.

PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

AC PERFORMANCE

f_in= 10 MHz, 65 MSPS

f_in= 5 MHz, T_A= 25°C

75.6

75.5

dBFS

Bits

72.8

71.8

f_in= 5 MHz, Across temperatures

SNR

Signal-to-noise ratio

f_in= 5 MHz, -60 dBFS Input signal amplitude

77.3

78.2

74.2

71.7

74.8

73.4

f_in= 5 MHz, Decimation by two enabled

f_in= 30 MHz

f_in= 65 MHz

f_in= 5 MHz

SINAD

Signal-to-noise and distortion ratio

f_in= 30 MHz

f_in= 65 MHz

ENOB

DNL

INL

Effective number of bits

Differential nonlinearity

Integral nonlinearity

f_in= 5 MHz

12.2

±0.5

2.2

f_in= 5 MHz

–0.96

1.7

5.5

LSB

dBc

f_in= 5 MHz

SFDR

THD

HD2

HD3

Spurious-free dynamic range

Total harmonic distortion

f_in= 30 MHz

dBc

f_in= 65 MHz

dBc

f_in= 5 MHz

70.5

dBc

f_in= 30 MHz

dBc

f_in= 65 MHz

73.5

dBc

f_in= 5 MHz

dBc

Second-harmonic distortion

Third-harmonic distortion

f_in= 30 MHz

dBc

f_in= 65 MHz

dBc

f_in= 5 MHz

dBc

f_in= 30 MHz

dBc

f_in= 65 MHz

dBc

f_in= 5 MHz

dBc

Worse spur excluding HD2, HD3

f_in= 30 MHz

dBc

f_in= 65 MHz

dBc

IMD3

Intermodualtion distortion

Overload recovery

f_in= 8 MHz at –7 dBFS, f₂= 10 MHz at –7 dBFS

84.5

dBc

Recovery to within 1% of full-scale for 6-dB overload with

sine wave input

Clock Cycle

f_in= 10 MHz, -1 dBFS signal applied on

aggressor channel no signal applied on

victim channel

far channel

dBc

XTALK

Cross-talk

near channel

Phase noise

5 MHz, 1 kHz off carrier

–138

dBc/Hz

ANALOG INPUT / OUTPUT

Differential input voltage range

(0-dB gain)

V_PP

R_IN

C_IN

Differential Input Resistance

Differential Input Capacitance

Analog input bandwidth

At DC

3.2

kΩ

At DC

With a 50 Ωsource impedance

550

MHz

Analog input common-mode current

(per input pin)

1.6

µA/MSPS

VCM common-mode output voltage

VCM output current capability

0.95

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ELECTRICAL CHARACTERISTICS DYNAMIC PERFORMANCE (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, Sample

rate = 80 MSPS, ADC is configured in internal reference mode (unless otherwise noted). MIN and MAX values are across the

full temperature range T_MIN= –40°C to T_MAX= 85°C, AVDD = 1.8 V, LVDD = 1.8 V.

PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Offset error

Across devices and across channels within a device

–15

Temperature coefficient of offset error

<0.01

mV/ °C

Gain error due to internal reference

inaccuracy alone

E_(GREF)

Across devices

-2

%FS

E_(GCHAN)

Gain error of channel alone

0.5

%FS

Temperature coefficient of E_(GCHAN)

<0.01

%FS/ °C

POWER SUPPLY

80 MSPS, 14 Bit, 2-wire LVDS

50 MSPS, 1-wire LVDS

mW/CH

40 MSPS, 14 Bit, 1-wire LVDS

10 MSPS, 14 Bit, 1-wire LVDS

Power consumption

f_in= 10 MHz, 80 MSPS, 14 Bit,

Decimation filter = 2, 1-wire LVDS

100

mW/CH

14 Bit, 80 MSPS

230

200

155

111

265

122

AVDD

LVDD

14 Bit, 65 MSPS

14 Bit, 40 MSPS

80 MSPS, 14 Bit, 2-wire LVDS

50 MSPS, 14 Bit, 1-wire LVDS

40 MSPS, 14 Bit, 1-wire LVDS

80 MSPS, 1 Bit, Decimation filter = 2,

1-wire LVDS

210

175

Partial Power Down (80 MSPS, 2-wire)

Complete Power Down

Power-down power consumption

Power supply modulation ratio

Power supply rejection ratio

Carrier = 5 MHz, f_(PSRR)= 10 kHz, 50 mVpp on AVDD

AC power supply rejection ratio f = 10 kHz

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DIGITAL CHARACTERISTICS

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD = 1.8V, LVDD = 1.8V

PARAMETERS

CONDITION

MIN

TYP

MAX

UNITS

DIGITAL INPUTS/OUTPUTS

All digital inputs support 1.8-V and 3.3-V CMOS

logic levels.

V_IH

Logic high input voltage

1.3

V_IL

I_IH

Logic low input voltage

Logic high input current

Logic low input current

Logic high output voltage

Logic low output voltage

0.4

µA

V_HIGH= 1.8 V

V_LOW= 0 V

< 0.1

I_IL

V_OH

V_OL

AVDD - 0.1

0.2

LVDS OUTPUTS

High-level output differential

voltage

V_ODH

100 Ω external termination

245

350

405

Low-level output differential

voltage

V_ODL

V_OCM

–245

900

–350

1100

–405

1300

Output common-mode voltage

OUTP

Logic 0

V = +350 mV*

ODH

= -350 mV*

ODL

OUTM

OCM

GND

*With external 100-W termination

Figure 2. LVDS Output Voltage Levels

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TIMING REQUIREMENTS^(1)(2)(3)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8 V, sampling frequency = 80 MSPS, 14-bit, sine wave input clock = 1.5

Vpp clock amplitude, C_LOAD= 5 pF, R_LOAD= 100 Ω, unless otherwise noted. MIN and MAX values are across the full

temperature range T_MIN= –40°C to T_MAX= 85°C, AVDD = 1.8 V, LVDD = 1.7 V to 1.9 V

PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

The delay in time between the rising edge of the input

sampling clock and the actual time at which the sampling

occurs

t_a

Aperture delay

Aperture delay variation

Across channels within the same device

±175

2.5

Across devices at the same temperature and LVDD supply

t_j

Aperture jitter RMS

Data latency

320

fs rms

Clock

cycles

1-wire LVDS output interface

2-wire LVDS output interface

t_d

Clock

cycles

t_SU

t_H

Data setup time

Data hold time

80 MSPS, 2 wire LVDS, 7x serialization

0.34

0.55

0.57

0.8

Input clock rising edge(zero cross) to frame clock rising

edge(zero cross)

Clock propagation delay

See Table 1 and Table 2

t_PROP

Variation of t_PROP

LVDS bit clock duty cycle

Data rise time

Between two devices at same temperature and LVDD supply

±0.75

48%

0.24

0.20

t_RISE

Rise time is from -100 mV to + 100 mV, 10 ≤ Fs ≤ 80 MSPS

Fall time is from +100 mV to -100 mV, 10 ≤ Fs ≤ 80 MSPS

Rise time is from -100 mV to +100 mV, 10 ≤ Fs ≤ 80 MSPS

Fall time is from +100 mV to -100 mV, 10 ≤ Fs ≤ 80 MSPS

t_FALL

Data fall time

t_CLKRISE

t_CLKFALL

Output clock rise time

Output clock fall time

Time to valid data after coming out of COMPLETE POWER-

DOWN mode

t_WAKE

Wake-up Time

100

µs

Time to valid data after coming out of PARTIAL POWER-

DOWN mode (with clock continuing to run during power-

down)

(1) Timing parameters are ensured by design and characterization and not tested in production.

(2) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold

time specifications take into account the effect of jitter on the output data and clock.

(3) Data valid refers to logic HIGH of 100 mV and logic LOW of –100 mV.

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(1)

Table 1. LVDS Timing at Different Sampling Frequencies - 2 Wire Interface, 7x Serialization

LVDS Output Rate (MSPS)

Setup Time (t_su), ns

Hold Time (t_H), ns

t_PROG= (6/7) × T + t_delay, ns⁽²⁾

Zero-Crossing of LCLKP to

Data Becoming Invalid

Data Valid to Zero-

Crossing of LCLKP

(both edges)

t_PROG= delay from Input clock zero-cross

rising edge to frame clock zero cross (rising

edge)

Fs = 1/T

(both edges)

MIN

TYP

0.57

0.64

0.9

1.3

MAX

MIN

0.55

0.8

1.2

1.6

TYP

0.8

1.1

1.5

1.85

2.3

3.5

MAX

MIN

TYP

9.5

MAX

0.34

0.35

0.7

1.7

2.9

6.5

3.2

6.7

3.2

6.7

(1) Bit clock and Frame clock jitter has been included in the Setup and hold timing.

(2) Values below correspond to tdelay, NOT t_PROG

(1)

Table 2. LVDS Timing at Different Sampling Frequencies - 1 Wire Interface, 14x Serialization

LVDS Output Rate (MSPS)

Setup Time (t_su), ns

Hold Time (t_H), ns

t_PROG= (5/7) × T + t_delay, ns⁽²⁾

Zero-Crossing of LCLKP to

Data Becoming Invalid

Data Valid to Zero-

Crossing of LCLKP

(both edges)

t_PROG= delay from Input clock zero-cross

rising edge to frame clock zero cross (rising

edge)

Fs = 1/T

(both edges)

MIN

TYP

0.48

0.68

0.8

MAX

MIN

0.28

0.54

TYP

0.6

MAX

MIN

7.5

TYP

MAX

10.5

0.28

0.5

0.8

0.62

1.2

1.25

1.9

1.4

1.6

3.3

3.1

3.3

3.5

(1) Bit clock and Frame clock jitter has been included in the Setup and hold timing.

(2) Values below correspond to tdelay, NOT t_PROG

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LVDS TIMING DIAGRAM

Figure 3. 14-Bit 1 wire LVDS Timing Diagram

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Figure 4. Enlarged 1 wire LVDS Timing Diagram (14bit)

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Figure 5. 14-Bit 2 wire LVDS Timing Diagram

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Figure 6. Enlarged 2 wire LVDS Timing Diagram (14bit)

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Figure 7. Definition of Setup and Hold Times t_SU= min(t_SU1, t_SU2); t_H= min(t_H1, t_H2

)

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SLAS776B –NOVEMBER 2011–REVISED JULY 2012

TYPICAL CHARACTERISTICS

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

−10

SNR = 76.1 dBFS

SINAD = 75.7 dBFS

SFDR = 87 dBc

THD =84.7 dBc

SNR = 75.5 dBFS

SINAD = 74.4 dBFS

SFDR = 80.3 dBc

THD =79.7 dBc

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

Frequency (MHz)

Figure 8. FFT for 5 MHz Input Signal,

Sample Rate = 80 MSPS

Figure 9. FFT for 15 MHz Input Signal,

Sample Rate = 80 MSPS

−10

SNR = 70.7 dBFS

SNR = 76.5 dBFS

SINAD =69.5 dBFS

SFDR = 74.9 dBc

THD =74.55 dBc

SINAD = 76.5 dBFS

SFDR = 90.23 dBc

THD = 87 dBc

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

Frequency (MHz)

Figure 10. FFT for 65 MHz Input Signal,

Sample Rate = 80 MSPS

Figure 11. FFT for 5 MHz Input Signal,

Sample Rate = 40 MSPS

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TYPICAL CHARACTERISTICS (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

SNR = 76.5 dBFS

SINAD = 76.5 dBFS

SFDR = 88.4 dBc

THD = 87 dBc

fIN1 = 8 MHz

fIN2 = 10 MHz

Each Tone at −7dBFS Amplitude

Two Tone IMD = −91.4 dBFS

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

Frequency (MHz)

Figure 12. FFT for 15 MHz Input Signal,

Sample Rate = 40 MSPS

Figure 13. Two Tone Intermodulation

Input Signal frequency (MHz)

Figure 14. Signal -To-Noise Ratio vs. Input Signal

Frequency

Figure 15. Spurious-Free Dynamic Range vs. Input Signal

Frequency

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TYPICAL CHARACTERISTICS (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

Input frequency = 10 MHz

Input frequency = 70 MHz

Input frequency = 10 MHz

Input frequency = 70 MHz

10 11 12

Digital gain (dB)

G001

Figure 16. SNR vs. Digital Gain

Figure 17. SFDR vs. Digital Gain

120

110

100

SFDR

SNR

79.5

78.5

77.5

76.5

75.5

SNR

SFDR(dBc)

SFDR(dBFS)

74.5

−96 −86 −76 −66 −56 −46 −36 −26 −16 −6

Input amplitude (dBFS)

0.2 0.4 0.6 0.8

1.2 1.4 1.6 1.8

2.2 2.4

Input Clock Amplitude, differential (Vp−p)

Figure 18. Performance vs. Input Amplitude

Figure 19. Performance vs. Clock Input Amplitudes

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TYPICAL CHARACTERISTICS (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

85.5

SFDR

SNR

Fin = 5 MHz

SFDR

SNR

77.5

76.5

84.5

75.5

83.5

74.5

82.5

73.5

1.10

0.80

0.85

0.90

0.95

1.00

1.05

Input Clock Duty Cycle (%)

Analog Input Common−mode voltage (V)

Figure 20. Performance vs. Input Clock Duty Cycle

Figure 21. Performance vs. Input VCM

77.0

AVDD=1.65V

AVDD=1.7V

AVDD=1.8V

AVDD=1.9V

AVDD=1.95V

AVDD=1.65V

AVDD=1.7V

AVDD=1.8V

AVDD=1.9V

AVDD=1.95V

76.5

76.0

75.5

75.0

74.5

74.0

−40

−20

−40

−20

Temperature (°C)

Figure 22. Signal -To-Noise Ratio vs. Temperature

Figure 23. Spurious-Free Dynamic Range vs. Temperature

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TYPICAL CHARACTERISTICS (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

100

−110

−120

−130

−140

−150

−160

Far Channel

Near Channel

0.01

0.1

100

Frequency of Aggressor Channel (MHz)

Frequency Offset (kHz)

Figure 24. Crosstalk vs. Frequency

Figure 25. Phase Noise for 5 MHz Input Signal,

Sample Rate = 80 MSPS

0.8

0.7

0.3

0.2

0.6

0.5

0.4

0.3

0.1

0.2

0.1

0.0

−0.1

−0.2

−0.3

−0.4

−0.5

−0.6

−0.7

−0.8

−0.1

−0.2

−0.3

900

3900

6900

9900

12900

15900

900

3900

6900

9900

12900

15400

Output_codes (dB)

Output_codes (LSB)

Figure 26. Integral Non-Linearity

Figure 27. Differential Non-Linearity

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TYPICAL CHARACTERISTICS (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

With 50mVpp signal superimposed on input common−mode

45.5

Fin = 3 MHz

31.53

16.18

5.55

0.1

0.11

0.03

Frequency of CMRR signal (MHz)

Figure 28. Histogram of Output Code with Analog Inputs

Shorted

Figure 29. Common Mode Rejection Ratio vs. Frequency

−10

With 50mVpp signal

PSMR

PSRR

Low Pass

High pass

superimposed on AVDD supply

PSMR: 3MHz input signal applied

PSRR: No input signal applied

−20

−30

−40

−50

−60

−70

−80

−10

−20

−30

−40

−50

−60

−70

−80

0.01

0.1

0.0

0.1

0.2

0.3

0.4

0.5

Frequency of signal on supply (MHz)

Normalized Frequency (fin/fs)

Figure 30. Power Supply Rejection Ratio vs. Frequency

Figure 31. Filter Response, Decimate by 2

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SLAS776B –NOVEMBER 2011–REVISED JULY 2012

TYPICAL CHARACTERISTICS (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

Low Pass

SNR = 78.2 dBFS

SINAD = 78.2 dBFS

Decimate by 2 Filter Enabled

−10

Band−Pass1

Band−Pass2

High Pass

−20

−30

−40

−50

−10

−20

−30

−40

−50

−60

−70

−80

−60

−70

−80

−90

−100

−110

−120

−130

−140

0.0

0.1

0.2

0.3

0.4

0.5

Frequency (MHz)

Normalized frequency (fin/fs)

Figure 32. Filter Response, Decimate by 4

Figure 33. FFT for 5 MHz Input Signal, Sample

Rate = 80 MSPS with Decimation Filter = 2

−10

SNR = 77.9 dBFS

SINAD = 77.9 dBFS

SFDR = 93.13 dBc

THD = −96 dBc

−3

−20

−6

−30

2 Channels averaged

−9

−40

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−50

−60

−70

−80

K=2

K=3

K=4

K=5

K=6

K=7

K=8

K=9

K=10

−90

−100

−110

−120

−130

−140

0.02

0.1

10 15

Frequency (MHz)

Input Signal Frequency (MHz)

Figure 34. FFT for 5 MHz Input Signal, Sample

Rate = 80 MSPS by Averaging 2 Channels

Figure 35. Digital High-Pass Filter Response

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TYPICAL CHARACTERISTICS (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

−5

HPF_DISABLED

HPF_ENABLED

−10

−15

−25

−20

−30

−40

−35

−50

−45

−60

−55

−70

−65

−80

−90

−75

−100

−110

−120

−130

−140

−150

−85

−95

−105

−115

−125

0.5

1.5

2.5

3.5

4.5

Input Signal Frequency (MHz)

Frequency (MHz)

Figure 36. FFT with HPF Enabled and Disabled, No Signal

Figure 37. FFT (Full-Band) for 5 MHz Input Signal, Sample

Rate = 80MSPS with Low Frequency Noise Suppression

Enabled

LF noise suppression enabled

LF noise suppression disabled

LF noise suppression enabled

LF noise suppression disabled

−10

−20

−30

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Frequency (MHz)

39 39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 39.9 40

Frequency (MHz)

Figure 38. FFT (0 to 1 MHz) for 5 MHz Input Signal, Sample

Rate = 80 MSPS with Low Frequency Noise Suppression

Enabled

Figure 39. FFT (39 MHz to 40 MHz) for 5 MHz Input Signal,

Sample Rate = 80 MSPS with Low Frequency Noise

Suppression Enabled

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SLAS776B –NOVEMBER 2011–REVISED JULY 2012

TYPICAL CHARACTERISTICS (continued)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8V, 50% clock duty cycle, –1 dBFS differential analog input, 14 Bit/80

MSPS, ADC is configured in the internal reference mode, unless otherwise noted.

450

400

350

300

250

200

150

350

325

300

275

250

225

200

175

150

125

100

2−wire

1−wire

1−wire Decimate by 2

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Sampling Frequency (MSPS)

Figure 40. Power Consumption on Analog Supply

Figure 41. Power Consumption on Digital Supply

240

190

170

150

130

110

2−wire

1−wire

1−wire Decimate by 2

220

200

180

160

140

120

100

Sampling Frequency (MSPS)

Figure 42. Supply Current on Analog Supply

Figure 43. Supply Current on Digital Supply

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SERIAL INTERFACE

ADS5294 has a set of internal registers that can be accessed by the serial interface formed by pins CSZ (Serial

interface Enable – Active Low), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).

When CSZ is low,

•

Serial shift of bits into the device is enabled.

Serial data (SDATA) is latched at every rising edge of SCLK.

SDATA is loaded into the register at every 24^thSCLK rising edge

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CSZ pulse. The first eight bits form the register address and the remaining 16

bits the register data. The interface can work with SCLK frequencies from 15 MHz down to very low speeds (few

Hertz) and also with non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to the respective default values. Initialization can be done

in one of two ways:

1. Through a hardware reset, by applying a high pulse on the RESET pin; or

2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the

internal registers to the respective default values and then self-resets the bit low. In this case, the RESET pin

stays low (inactive).

SDATA

SCLK

D15 D14 D13 D12 D11 D10

DSU

SLOADH

SCLK

SLOADS

CSZ

RESET

Figure 44. Serial Interface Timing

SERIAL INTERFACE TIMING CHARACTERISTICS

Typical values at 25°C, MIN and MAX values across the full temperature range T_MIN= –40°C to T_MAX= 85°C, AVDD = 1.8 V,

LVDD = 1.8 V, unless otherwise noted.

PARAMETER

MIN

> DC

TYP MAX

UNIT

MHz

f_SCLK

t_SLOADS

t_SLOADH

t_DS

SCLK frequency (= 1/ t_SCLK

CS to SCLK setup time

SCLK to CS hold time

SDATA setup time

)

t_DH

SDATA hold time

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RESET TIMING

Typical values at 25°C, MIN and MAX values across the full temperature range T_MIN= –40°C to T_MAX= 85°C (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

Delay from power up of AVDD and LVDD to RESET pulse active

Pulse duration of active RESET signal

MIN TYP MAX UNIT

t₁

t₂

t₃

Power-on delay

Reset pulse duration

Delay from RESET disable to CSZ active

100

POWER SUPPLY

AVDD, LVDD

RESET

SEN

NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.

For parallel interface operation, RESET has to be tied permanently HIGH.

Figure 45. Reset Timing Diagram

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Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back on SDOUT pin. This

may be useful as a diagnostic check to verify the serial interface communication between the external controller

and the ADC.

By default, after power up and device reset, the SDOUT pin is in the high-impedance state. When the readout

mode is enabled using the register bit <READOUT>, SDOUT outputs the contents of the selected register

serially, described as follows.

•

Set register bit <READOUT> = 1 to put the device in serial readout mode. This disables any further writes

into the internal registers, EXCEPT the register at address 1. Note that the <READOUT> bit itself is also

located in register 1.

The device can exit readout mode by writing <READOUT> to 0.

Only the contents of register at address 1 cannot be read in the register readout mode.

•

Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content is to be read.

The device serially outputs the contents (D15–D0) of the selected register on the SDOUT pin.

The external controller can latch the contents at the rising edge of SCLK.

To exit the serial readout mode, reset register bit <READOUT> = 0, which enables writes into all registers of

the device. At this point, the SDOUT pin enters the high-impedance state.

A) Enable Serial Readout (<READOUT> = 1)

SDATA

SCLK

CSZ

Pin SDOUT Becomes

Active and Forces Low

Pin SDOUT is tri-stated

SDOUT

B) Read Contents of Register 0x0F.

This Register has been Initialized with 0x0200

(The Device was earlier put in global power down)

D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0

SDATA

SCLK

D13

D10

D15 D14

D12 D11

D7 D6

CSZ

SDOUT

SDOUT Output Contents of Register 0x0F in the same cycle, MSB first

Figure 46. Serial Readout Timing

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SLAS776B –NOVEMBER 2011–REVISED JULY 2012

DEFAULT STATES AFTER RESET

•

Device is in normal operation mode with 14-bit ADC enabled for all channels.

Output interface is 1-wire, 14× serialization with 7×bit clock and 1×frame clock frequency

Serial readout is disabled

PDN pin is configured as global power-down pin

Digital gain is set to 0 dB.

Digital modes such as LFNS, digital filters, and so on, are disabled.

(1)(2)(3)(4)

Table 3. Summary of Functions Supported by Serial Interface

ADDR.

(HEX)

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

1: Self-clearing software RESET; . After reset, this bit is set to 0

0: Normal operation.

RST

EN_READOUT

EN_HIGH_ADDRS

1: READOUT of registers mode;0: Normal operation

0 – Disable access to register at address 0xF0

1 – Enable access to register at address 0xF0

1:Enable SYNC feature to synchronize the test patterns;

0: Normal operation, SYNC feature is disabled for the test patterns.

Note: this bit needs to be set as 1 when software or hardware SYNC

feature is used. see Reg.0x25[8] and 0x25[15]

EN_SYNC

RAMP_PAT_RESET_VAL

PDN_CH<8:1>

Ramp pattern reset value

1:Channel-specific ADC power-down mode;

0: Normal operation

1:Partial power-down mode - fast recovery from power-down;

0: Normal operation

PDN_PARTIAL

PDN_COMPLETE

PDN_PIN_CFG

LFNS_CH<8:1>

EN_FRAME_PAT

1:Register mode for complete power-down - slower recovery;

0: Normal operation

1:Configures PD pin for partial power-down mode;

0:Configures PD pin for complete power-down mode

1: Channel-specific low frequency noise suppression mode enable;

0: LFNS disabled

1: Enables output frame clock to be programmed through a pattern;

0: Normal operation on frame clock

ADCLKOUT<13:0>

PRBS_SEED<15:0>

14-bit pattern for frame clock on ADCLKP/ADCLKN pins

PRBS pattern starting seed value lower 16 bits

1: Swaps the polarity of the analog input pins electrically;

0: Normal configuration

INVERT_CH<8:1>

PRBS_SEED<22:16>

PRBS seed starting value upper 7 bits

(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.

(2) X = Register bit referenced by the corresponding name and description

(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.

(4) Multiple functions in a register can be programmed in a single write operation.

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Table 3. Summary of Functions Supported by Serial Interface ^(1)(2)(3)(4)(continued)

ADDR.

(HEX)

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

1: Enables a repeating full scale ramp pattern on the outputs;

0: Normal operation

EN_RAMP

1:Enables mode wherein output toggles between 2 defined codes;

0: Normal operation

DUALCUSTOM_PAT

SINGLE_CUSTOM_PAT

1: Enables mode wherein output is a constant specified code;

0: Normal operation

2 MSBs for single custom pattern (and for the first code of the dual

custom patterns)

BITS_CUSTOM1<13:12>

BITS_CUSTOM2<13:12>

2 MSBs for second code of the dual custom patterns

1: Software sync bit for test patterns on all 8 CHs;

0: No sync. Note: in order to synchronize the digital filters using the

SYNC pin, this bit must be set as 0.

TP_SOFT_SYNC

1: PRBS test pattern enable bit;

0: PRBS test pattern disabled

PRBS_TP_EN

PRBS_MODE_2

PRBS 9 bit LFSR (23bit LFSR is default)

1: Enable PRBS seed to be chosen from register 0x23 and 0x24;

0: Disabled

PRBS_SEED_FROM_REG

1: Enable the external SYNC feature for syncing test patterns.

0: Inactive. Note: in order to synchronize the digital filters using the

SYNC pin, this bit must be set as 0.

TP_HARD_SYNC

12 lower bits for single custom pattern (and for the first code of the

dual custom pattern).

BITS_CUSTOM1<11:0>

BITS_CUSTOM2<11:0>

EN_BITORDER

12 lower bits for second code of the dual custom pattern

Enables the bit order output.

0 = Byte wise, 1 = Word wise

Selects between bytewise and bit wise

1: bit-wise, odd bits come out on one wire and even bits come out on

other wire

0: byte-wise, upper bits on one wire and lower bits on other wire

Note: D15 must be set to '0' for this mode

BIT_WISE

1: Output format is one sample on one LVDS wire and next sample

on other LVDS wire.

0: Data comes out in two-wire mode with upper set of bits on one

channel and lower set of bits on the other.

EN_WORDWISE__BY_CH<7:0>

Note: D15 must set '1' for this mode.

1: Enables filter blocks - global control;

0: Inactive

GLOBAL_EN_FILTER

EN_CHANNEL_AVG

1: Enables channel averaging mode;

0: Inactive

GAIN_CH1<3:0>

GAIN_CH2<3:0>

GAIN_CH3<3:0>

GAIN_CH4<3:0>

Programmable gain - Channel 1

Programmable gain - Channel 2

Programmable gain - Channel 3

Programmable gain - Channel 4

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Table 3. Summary of Functions Supported by Serial Interface ^(1)(2)(3)(4)(continued)

ADDR.

(HEX)

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

Programmable gain - Channel 5

GAIN_CH5<3:0>

GAIN_CH6<3:0>

Programmable gain - Channel 6

GAIN_CH7<3:0>

Programmable gain - Channel 7

GAIN_CH8<3:0>

Programmable gain - Channel 8

AVG_CTRL4<1:0>

AVG_CTRL3<1:0>

AVG_CTRL2<1:0>

AVG_CTRL1<1:0>

AVG_CTRL8<1:0>

AVG_CTRL7<1:0>

AVG_CTRL6<1:0>

AVG_CTRL5<1:0>

FILTER1_COEFF_SET<2:0>

FILTER1_RATE<2:0>

ODD_TAP1

1: Averaging control for what comes out on LVDS output OUT4

Averaging control for what comes out on LVDS output OUT3

Averaging control for what comes out on LVDS output OUT2

Averaging control for what comes out on LVDS output OUT1

Averaging control for what comes out on LVDS output OUT8

Averaging control for what comes out on LVDS output OUT7

Averaging control for what comes out on LVDS output OUT6

Averaging control for what comes out on LVDS output OUT5

Select stored coefficient set for filter 1

Set decimation factor for filter 1

Use odd tap filter 1

1: Enables filter for channel 1;

0: Disables

USE_FILTER1

HPF_CORNER _CH1

HPF_EN_CH1

HPF corner in values k from 2 to 10

1: HPF filter enable for the channel;

0: Disables

FILTER2_COEFF_SET<2:0>

FILTER2_RATE<2:0>

ODD_TAP2

Select stored coefficient set for filter 2

Set decimation factor for filter 2

Use odd tap filter 2

1: Enables filter for channel 2;

0: Disables

USE_FILTER2

HPF_CORNER _CH2

HPF_EN_CH2

HPF corner in values k from 2 to 10

1: HPF filter enabled for the channel;

0: Disabled

FILTER3_COEFF_SET<2:0>

FILTER3_RATE<2:0>

ODD_TAP3

Select stored coefficient set for filter 3

Set decimation factor for filter 3

Use odd tap filter 3

1: Enables filter for channel 3;

0: Disables

USE_FILTER3

HPF_CORNER _CH3

HPF_EN_CH3

HPF corner in values k from 2 to 10

1: HPF filter enabled for the channel;

0: Disabled

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Table 3. Summary of Functions Supported by Serial Interface ^(1)(2)(3)(4)(continued)

ADDR.

(HEX)

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

Select stored coefficient set for filter 4

FILTER4_COEFF_SET<2:0>

FILTER4_RATE<2:0>

ODD_TAP4

Set decimation factor for filter 4

Use odd tap filter 4

1: Enables filter for channel 4;

0: Disables

USE_FILTER4

HPF_CORNER _CH4

HPF_EN_CH4

HPF corner in values k from 2 to 10

1: HPF filter enabled for the channel;

0: Disabled

FILTER5_COEFF_SET<2:0>

FILTER5_RATE<2:0>

ODD_TAP5

Select stored coefficient set for filter 5

Set decimation factor for filter 5

Use odd tap filter 5

1: Enables filter for channel 5;

0: Disables

USE_FILTER5

HPF_CORNER _CH5

HPF_EN_CH5

HPF corner in values k from 2 to 10

1: HPF filter enabled for the channel;

0: Disabled

FILTER_TYPE6<2:0>

DECBY8_6

Select stored coefficient set for filter 6

Enables decimate by 8 filter 6

Set decimation factor for filter 6

Use odd tap filter 6

FILTER_MODE6<1:0>

ODD_TAP6

USE_FILTER6

Enables filter for channel 6

HPF_CORNER _CH6

HPF_EN_CH6

HPF corner in values k from 2 to 10

Hpf filter enable for the channel

Select stored coefficient set for filter 7

Enables decimate by 8 filter 7

Set decimation factor for filter 7

Use odd tap filter 7

FILTER_TYPE7<2:0>

DECBY8_7

FILTER_MODE7<1:0>

ODD_TAP7

USE_FILTER7

Enables filter for channel 7

HPF_CORNER _CH7

HPF_EN_CH7

HPF corner in values k from 2 to 10

Hpf filter enable for the channel

Select stored coefficient set for filter 8

Enables decimate by 8 filter 8

Set decimation factor for filter 8

Use odd tap filter 8

FILTER_TYPE8<2:0>

DECBY8_8

FILTER_MODE8<1:0>

ODD_TAP8

1: Enables filter for channel 8;

0: Disables

USE_FILTER8

HPF_CORNER_CH8

HPF_EN_CH8

HPF corner in values k from 2 to 10

1: HPF filter enable for the channel;

0: Disables

DATA_RATE<1:0>

Select output frame clock rate

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Table 3. Summary of Functions Supported by Serial Interface ^(1)(2)(3)(4)(continued)

ADDR.

(HEX)

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

Drive external reference mode through:

D15=D3=1: the VCM pin;

EXT_REF_VCM

D15=D3=0: REFT/REFB pins.

Note: 0xF[15] should be set as '1' to enable the external reference

mode

PHASE_DDR<1:0>

PAT_DESKEW

Controls phase of LCLK output relative to data

1: Enable deskew pattern mode;

0: Inactive

1: Enable sync pattern mode;

0: Inactive

PAT_SYNC

EN_2WIRE

BTC_MODE

MSB_FIRST

EN_SDR

1: 2 wire LVDS output;

0: 1 wire LVDS output

1: 2's complement; (ADC data output format)

0: Binary Offset (ADC data output format)

1: MSB First;

0: LSB First

1:SDR Bit Clock;

0: DDR Bit Clock

1: Enable 12 bit serialization mode;

0: Inactive

EN_12BIT

EN_14BIT

1: Enable 14 bit serialization mode;

0: Inactive

1: Enable 16 bit serialization mode;

0: Inactive

EN_16BIT

FALL_SDR

Note: 16 bit can be used when average mode or decimation mode is

enabled for better SNR.

1: Controls LCLK rising or falling edge comes in the middle of data

window when operating in SDR output mode; 0: At the edge of data

window.

MAP_Ch1234_to_OUT1A

MAP_Ch1234_to_OUT1B

MAP_Ch1234_to_OUT2A

MAP_Ch1234_to_OUT2B

MAP_Ch1234_to_OUT3A

MAP_Ch1234_to_OUT3B

MAP_Ch1234_to_OUT4A

MAP_Ch1234_to_OUT4B

MAP_Ch5678_to_OUT5B

MAP_Ch5678_to_OUT5A

MAP_Ch5678_to_OUT6B

MAP_Ch5678_to_OUT6A

MAP_Ch5678_to_OUT7B

MAP_Ch5678_to_OUT7A

OUT1A Pin pair to channel data mapping selection

OUT1B Pin pair to channel data mapping selection

OUT2A Pin pair to channel data mapping selection

OUT2B Pin pair to channel data mapping selection

OUT3A Pin pair to channel data mapping selection

OUT3B Pin pair to channel data mapping selection

OUT4A Pin pair to channel data mapping selection

OUT4B Pin pair to channel data mapping selection

OUT5B Pin pair to channel data mapping selection

OUT5A Pin pair to channel data mapping selection

OUT6B Pin pair to channel data mapping selection

OUT6A Pin pair to channel data mapping selection

OUT7B Pin pair to channel data mapping selection

OUT7A Pin pair to channel data mapping selection

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Table 3. Summary of Functions Supported by Serial Interface ^(1)(2)(3)(4)(continued)

ADDR.

(HEX)

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

MAP_Ch5678_to_OUT8B

MAP_Ch5678_to_OUT8A

OUT8B Pin pair to channel data mapping selection

OUT8A Pin pair to channel data mapping selection

1: Enable external reference mode. the voltage reference can be

applied on either REFP/B pins or VCM pin.

EN_EXT_REF

0: Default: internal reference mode.

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DESCRIPTION OF SERIAL REGISTERS

POWER-DOWN MODES

ADDR. D15 D14 D13 D12 D11 D10

(HEX)

NAME

PDN_CH<8:1>

PDN_PARTIAL

PDN_COMPLETE

PDN_PIN_CFG

Each of the 8 channels can be individually powered down. PDN_CH<N> controls the power-down mode for ADC

channel <N>. In addition to channel-specific power-down, the ADS5294 also has two global power-down modes:

1. The partial power-down mode. It partially powers down the chip; recovery time from the partial power-down

mode is about 10 µs provided that the clock has been running for at least 50 µs before exiting this mode.

2. The complete power-down mode. It completely powers down the chip, and involves a much longer recovery

time 100 µs.

In addition to programming the chip in either of these two power-down modes (through either the PDN_PARTIAL

or PDN_COMPLETE bits), the PD pin itself can be configured as either a partial power-down pin or a complete

power-down pin control. For example, if PDN_PIN_CFG=0 (default), when the PD pin is high, the device enters

complete power-down mode. However, if PDN_PIN_CFG=1, when the PD pin is high, the device enters partial

power-down mode.

LOW FREQUENCY NOISE SUPPRESSION MODE

ADDR. D15 D14 D13 D12 D11 D10

(HEX)

NAME

LFNS_CH<8:1>

The low frequency noise suppression mode is specifically useful in applications where good noise performance is

desired in the frequency band of 0 to 1 MHz (around DC). Setting this mode shifts the low-frequency noise of the

ADS5294 to approximately Fs/2, thereby, moving the noise floor around DC to a much lower value.

LFNS_CH<8:1> enables this mode individually for each channel. See Figure 38 and Figure 39.

ANALOG INPUT INVERT

ADDR. D15 D14 D13 D12 D11 D10

(HEX)

NAME

INVERT_CH<8:1>

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Normally, IN_Ppin represents the positive analog input pin, and INN represents the complementary negative input.

Setting the bits marked INVERT_CH<8:1> (individual control for each channel) causes the inputs to be swapped.

IN_Nnow represents the positive input, and IN_Pthe negative input.

LVDS TEST PATTERNS

ADDR.

(HEX)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NAME

PRBS_SEED<15:0>

PRBS_SEED<22:16>

EN_RAMP

DUALCUSTOM_PAT

SINGLE_CUSTOM_PAT

BITS_CUSTOM1<13:12>

BITS_CUSTOM2<13:12>

TP_SOFT_SYNC

PRBS_TP_EN

PRBS_MODE_2

PRBS_SEED_FROM_REG

TP_HARD_SYNC

BITS_CUSTOM1<11:0>

BITS_CUSTOM2<11:0>

PAT_DESKEW

PAT_SYNC

The ADS5294 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal

ADC data output. All these patterns can be synchronized across devices by the sync function either through the

hardware SYNC pin or the software sync bit TP_SOFT_SYNC bit in register 0x25. TP_HARD_SYNC bit when

set enables the Test patterns to be synchronized by the hardware SYNC Pin. When the software sync bit

TP_SOFT_SYNC bit is set, special timing is needed.

•

Setting EN_RAMP to 1 causes all the channels to output a repeating full-scale ramp pattern. The ramp

increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the full scale

code, it returns back to zero code and ramps again.

•

The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to 1, and

programming the desired code in BITS_CUSTOM1<13:0>. In this mode, BITS_CUSTOM1<13:0> take the

place of the 14-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes the same way

as normal ADC data are.

•

The device may also be made to toggle between two consecutive codes, by programming

DUAL_CUSTOM_PAT to 1. The two codes are represented by the contents of BITS_CUSTOM1<13:0> and

BITS_CUSTOM2<13:0>.

In addition to custom patterns, the device may also be made to output two preset patterns:

–

Deskew patten – Set using PAT_DESKEW, this mode replaces the 14-bit ADC output D<13:0> with the

0101010101010101 word.

Sync pattern – Set using PAT_SYNC, the normal ADC word is replaced by a fixed 11111110000000

word.

PRBS patterns: The device can give 9 bit or 23 bit LFSR Pseudo random pattern on the channel outputs

that are controlled by the register 0x25. To enable the PRBS pattern PRBS_TP_EN bit in the register

0x25 needs to be set. Default is the 23 bit LFSR but 9 bit LFSR can be chosen by setting

PRBS_MODE_2 bit. The seed value for the PRBS patterns can be chosen by enabling the

PRBS_SEED_FROM_REG bit to 1 and the value written to the PRBS_SEED registers in 0x24 and 0x23.

Note that only one of the above patterns should be active at any given instant.

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BIT-BYTE-WORD WISE OUTPUT

ADDR. D15 D14 D13 D12 D11 D10 D9

(HEX)

NAME

EN_BITORDER

BIT_WISE

EN_WORDWISE_B

Y_CH<7:>

Figure 47 and Figure 48 illustrate the details.

Figure 47. 12-Bit Word Wise

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Figure 48. 14-Bit Word Wise

DIGITAL PROCESSING BLOCKS

The ADS5294 integrates a set of commonly useful digital functions that can be used to ease system design.

These functions are shown in the digital block diagram of Figure 49 and described in the following sections.

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LVDS OUTPUTS

Test Patterns

Channel 1 ADC Data

Channel

14-BIT

Ramp

OUT 1A

OUT 1B

Serializer

Wire

Serializer

Wire

Average of 2

channels

Built-in Coefficients

24-tap filter

(Even Tap)

Decimation

by or

Channel

OUT 2A

OUT 2B

23-tap filter

(Odd Tap)

Serializer

Channel 2 ADC Data

Channel 3 ADC Data

Channel 4 ADC Data

Wire

Serializer

Wire

Average of 4

channels

Custom Coefficients

MAPPER

Decimation

24-tap filter

(Even Tap)

MULTIPLEXER

8 : 8

OUT 3A

OUT 3B

23-tap filter

(Odd Tap)

Channel

Serializer

GAIN

Wire

Serializer

Wire

(0 to 12 dB ,

dB steps )

12-tap filter

OUT 4A

OUT 4B

Channel

Serializer

Wire

Serializer

Wire

DIGITAL PROCESSING BLOCK for CHANNEL 1

½ ADS529x

Figure 49. Digital Processing Block Diagram

PROGRAMMABLE DIGITAL GAIN

ADDR.

D15 D14 D13 D12 D11 D10 D9

(HEX)

NAME

GAIN_CH1<3:0>

GAIN_CH2<3:0>

GAIN_CH3<3:0>

GAIN_CH4<3:0>

GAIN_CH5<3:0>

GAIN_CH6<3:0>

GAIN_CH7<3:0>

GAIN_CH8<3:0>

In applications where the full scale swing of the analog input signal is much less than the 2 V_PPrange supported

by the ADS5294, a programmable gain can be set to achieve the full-scale output code even with a lower analog

input swing. The programmable gain for each channel can be individually set using a set of four bits, indicated as

GAIN_CHN<3:0> for Channel N. The gain setting is coded in binary from 0-12 dB as shown in Table 4.

Table 4. Gain Setting for Channel N

GAIN_CHN<3>

GAIN_CHN<2>

GAIN_CHN<1>

GAIN_CHN<0>

CHANNEL N GAIN SETTING

0 dB

1 dB

2 dB

3 dB

4 dB

5 dB

6 dB

7 dB

8 dB

9 dB

10 dB

11 dB

12 dB

Do not use

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CHANNEL AVERAGING

ADDR.

D15 D14 D13 D12 D11 D10 D9

(HEX)

NAME

EN_CHANNEL_AVG

AVG_CTRL4<1:0>

AVG_CTRL3<1:0>

AVG_CTRL2<1:0>

AVG_CTRL1<1:0>

AVG_CTRL8<1:0>

AVG_CTRL7<1:0>

AVG_CTRL6<1:0>

AVG_CTRL5<1:0>

In the default mode of operation, the LVDS outputs <8..1> contain the data of the ADC Channels <8..1>. By

setting the EN_CHANNEL_AVG bit to ‘1’, the outputs from multiple channels can be averaged. The resulting

outputs from the Channel averaging block (which is bypassed in the default mode) are referred to as Bins. The

contents of the Bins <8..1> come out on the LVDS outputs <8..1>. The contents of each of the 8 bins are

determined by the register bits marked AVG_CTRLn<1:0> where n stands for the Bin number. The different

settings are shown below:

AVG_CTRL1<1>

AVG_CTRL1<0>

Contents of Bin 1

Zero

ADC Channel 1

Average of ADC Channel 1, 2

Average of ADC Channel 1, 2, 3, 4

Contents of Bin 2

Zero

AVG_CTRL2<1>

AVG_CTRL2<0>

ADC Channel 2

ADC Channel 3

Average of ADC Channel 3, 4

Contents of Bin 3

Zero

AVG_CTRL3<1>

AVG_CTRL3<0>

ADC Channel 3

ADC Channel 2

Average of ADC Channel 1, 2

Contents of Bin 4

Zero

AVG_CTRL4<1>

AVG_CTRL4<0>

ADC Channel 4

Average of ADC Channel 3, 4

Average of ADC Channel 1, 2, 3, 4

Contents of Bin 5

Zero

AVG_CTRL5<1>

AVG_CTRL5<0>

ADC Channel 5

Average of ADC Channel 5, 6

Average of ADC Channel 5, 6, 7, 8

Contents of Bin 6

Zero

AVG_CTRL6<1>

AVG_CTRL6<0>

ADC Channel 6

ADC Channel 7

Average of ADC Channel 7, 8

Contents of Bin 7

Zero

AVG_CTRL7<1>

AVG_CTRL7<0>

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AVG_CTRL1<1>

AVG_CTRL1<0>

Contents of Bin 1

ADC Channel 7

ADC Channel 6

Average of ADC Channel 6, 5

Contents of Bin 8

AVG_CTRL8<1>

AVG_CTRL8<0>

Zero

ADC Channel 8

Average of ADC Channel 7, 8

Average of ADC Channel 5, 6, 7, 8

When the contents of a particular bin is set to Zero, then the LVDS buffer corresponding to that bin gets

automatically powered down.

DECIMATION FILTER

ADDR.

(HEX)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NAME

GLOBAL_EN_FILTER

FILTER1_COEFF_SET<2:0>

FILTER1_RATE<2:0>

ODD_TAP1

USE_FILTER1

FILTER2_COEFF_SET<2:0>

FILTER2_RATE<2:0>

ODD_TAP2

USE_FILTER2

FILTER3_COEFF_SET<2:0>

FILTER3_RATE<2:0>

ODD_TAP3

USE_FILTER3

FILTER4_COEFF_SET<2:0>

FILTER4_RATE<2:0>

ODD_TAP4

USE_FILTER4

FILTER5_COEFF_SET<2:0>

FILTER5_RATE<2:0>

ODD_TAP5

USE_FILTER5

FILTER6_COEFF_SET<2:0>

FILTER6_RATE<2:0>

ODD_TAP6

USE_FILTER6

FILTER7_COEFF_SET<2:0>

FILTER7_RATE<2:0>

ODD_TAP7

USE_FILTER7

FILTER8_COEFF_SET<2:0>

FILTER8_RATE<2:0>

ODD_TAP8

USE_FILTER8

The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit

signed). The filter equation is:

æ 1 ö

y(n) =

´ (h ´ x(n)+h ´ x(n -1)+h ´ x(n - 2)+...+h ´ x(n -11)+h ´ x(n -12)...+h ´ x(n - 22)+h ´ x(n - 23)

é ù

0 1 2 11 11 1 0

è 2

(1)

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By setting the register bit <ODD_TAPn> = 1, a 23-tap FIR is implemented:

y(n)=

´é(h ´x(n)+h ´x(n-1)+h ´x(n-2)+...+h ´x(n-10)+h ´x(n -11)+h ´x(n-12)...+h ´x(n-21)+h ´x(n -22)ù

(2)

In Equation 1 and Equation 2, h0, h1 …h₁₁are 12 bit signed representation of the coefficients, x(n) is the input

data sequence to the filter and y(n) is the filter output sequence.

A decimation filter can be introduced at the output of each channel. To enable this feature, the

GLOBAL_EN_FILTER should be set to ‘1’. Setting this bit to ‘1’ increases the overall latency of each channel to

20 clock cycles irrespective of whether the filter for that particular channel has been chosen or not (using the

USE_FILTER bit). The bits marked FILTERn_COEFF_SET<2:0>, FILTERn_RATE<2:0>, ODD_TAPn and

USE_FILTERn represent the controls for the filter for Channel n. Note that these bits are functional only when

the GLOBAL_EN_FILTER gets set to ‘1’. For illustration, the controls for channel 1 are listed in Table 5:

The USE_FILTER1 bit determines whether the filter for Channel 1 is used or not. When this bit is set to ‘1’, the

filter for channel 1 is enabled. When this bit is set to ‘0’, the filter for channel 1 is disabled but the channel data

passes through a dummy delay so that the overall latency of channel 1 is 20 clock cycles. With the

USE_FILTER1 bit set to ‘1’, the characteristics of the filter can be set by using the other sets of bits.

The ADS5294 has 6 sets of filter coefficients stored in memory. Each of these sets define a unique pass band in

the frequency domain and contain 12 coefficients (each coefficient is 12-bit long). These 12 coefficients are used

to implement either a symmetric 24-tap (even-tap) filter, or a symmetric 23-tap (odd-tap) filter. Setting the register

bit ODD_TAP1 to ‘1’ enables the odd-tap configuration (the default is even tap with this bit set to ‘0’) for Channel

1. The bits FILTER1_COEFF_SET<2:0> can be used to choose the required set of coefficients for Channel 1.

The passbands corresponding to of each of these filter coefficient sets is shown in Figure 50

Set 1

Set 2

H(f)

0.2*Fs

0.3*Fs

0.2*Fs

0.3*Fs

0.5*Fs

Set 3

Set 4

H(f)

0.1*Fs

0.15*Fs

0.075*Fs

0.275*Fs

0.225*Fs

0.125*Fs

Set 5

Set 6

H(f)

0.275*Fs

0.4*Fs 0.5*Fs

0.375*Fs

0.225*Fs

0.35*Fs

Figure 50. Filter Types

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Coefficient Sets 1 and 2 are the most appropriate when Decimation by a factor of 2 is required, whereas

Coefficient Sets 3,4,5,6 are appropriate when Decimation by a factor of 4 is desired. The computation rate of the

filter output can be independently set using the bits FILTERn_RATE<2:0>. The settings are shown in Table 5.

Table 5. Digital Filters

<USE

FILTER

CHn>

<DATA

RATE>

FILTERn

RATE>

<FILTERn

COEFF SET>

<EN CUSTOM

FILT>

DECIMATION

TYPE OF FILTER

Built-in low-pass odd-tap filter (pass band = 0 to f_S/4)

Built-in high-pass odd-tap filter (pass band = 0 to f_S/4)

Built-in low-pass even-tap filter (pass band = 0 to f_S/8)

Built-in first band pass even tap filter(pass band = f_S/8 to f_S/4)

001

010

000

001

000

001

010

011

Decimate by 2

Decimate by 4

Built-in second band pass even tap filter(pass band = f_S/4 to 3

f_S/8)

010

001

100

Built-in high pass odd tap filter (pass band = 3 f_S/8 to f_S/2)

Custom filter (user programmablecoefficients)

010

001

010

011

001

000

001

100

101

000

Decimate by 2

Decimate by 4

Decimate by 8

Bypass decimation

0 and 1

The choice of the odd/even tap setting, filter coefficient set and the filter rate uniquely determines the filter to be

used. In addition to the preset filter coefficients, the coefficients for each of the eight filter channels can be

programmed by the user. Each of the eight channels has 12 programmable coefficients, each 12-bit long. The 96

registers with addresses from 5A (Hex) to B9 (Hex) are used to program these 8 sets of 12 programmable

coefficients. Registers 5A to 65 are used to program the 1^stfilter, with the 1^stcoefficient occupying the bits

D11..D0 of register 5A, the 2^ndcoefficient occupying the bits D11..D0 of register 5B, and so on. Similarly

registers 66(Hex) to 71(Hex) are used to program the 2^ndfilter, and so on.

When programming the filter coefficients, the D15 bit of each of the 12 registers corresponding to that filter

should be set to ‘1’. If the D15 bit of these 12 registers is set to ‘0’, then the preset coefficient (as programmed by

FILTERn_COEFF_SET<2:0>) is used even if the bits D11..D0 get programmed. By setting or not setting the D15

bits of individual filter channels to ‘1’, some filters can be made to operate with preset coefficient sets, and some

others can be made to simultaneously operate with programmed coefficient sets.

HIGH PASS FILTER

ADDR.

D15 D14 D13 D12 D11 D10

NAME

(HEX)

HPF_corner_CH1

HPF_EN_CH1

HPF_corner_CH2

HPF_EN_CH2

HPF_corner_CH3

HPF_EN_CH3

HPF_corner_CH4

HPF_EN_CH4

HPF_corner_CH5

HPF_EN_CH5

HPF_corner_CH6

HPF_EN_CH6

HPF_corner_CH7

HPF_EN_CH7

HPF_corner_CH8

HPF_EN_CH8

This group of registers controls the characteristics of a digital high pass transfer function applied to the output

data, useing Equation 3:

2^k

2^k+1

y(n) =

[x(n) - x(n -1)+y(n -1)]

(3)

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Where k is set as described by the HPF_corner registers (one for each channel). Also the HPF_EN bit in each

BIT CLOCK PROGRAMMABILITY

ADDR.

(HEX)

D15 D14 D13 D12 D11 D10 D9

NAME

PHASE_DDR<1:0>

EN_SDR

FALL_SDR

The output interface of the ADS5294 is normally a DDR interface, with the LCLK rising edge and falling edge

transitions in the middle of alternate data windows. This default phase is shown in Figure 51.

PHASE_DDR<1:0> = 10

ADCLKp

LCLKp

OUTp

Figure 51. Default Phase of LCLK

The phase of LCLK can be programmed relative to the output frame clock and data using bits

PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 52.

PHASE_DDR<1:0> = 00

PHASE_DDR<1:0> = 10

ADCLKp

LCLKp

OUTp

LCLKp

OUTp

PHASE_DDR<1:0> = 01

PHASE_DDR<1:0> = 11

ADCLKp

LCLKp

OUTp

ADCLKp

LCLKp

OUTp

Figure 52. Phase Programmability Modes for LCLK

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In addition to programming the phase of the LCLK in the DDR mode, the device can also be made to operate in

SDR mode by setting bit EN_SDR to 1. In the mode, the bit clock (LCLK) is output at 14X times the input clock,

or twice the rate as in DDR mode. Depending on the state of FALL_SDR, the LCLK may be output in either of

the two manners shown in Figure 53. As can be seen in Figure 53, only the LCLK rising (or falling edge) is used

to capture the output data in SDR mode. The SDR mode does not work well beyond 40 MSPS because the

LCLK frequency will become very high.

EN_SDR = 1, FALL_SDR = 0

ADCLKp

LCLKp

OUTp

EN_SDR = 1, FALL_SDR = 1

ADCLKp

LCLKp

OUTp

Figure 53. SDR Interface Modes

OUTPUT DATA RATE CONTROL

ADDR. D15 D14 D13 D12 D11 D10 D9

(HEX)

DATA_RATE<1> DATA_RATE<0>

In the default mode of operation, the data rate at the output of the ADS5294 is at the sampling rate of the ADC.

This is true even when the custom pattern generator is enabled. In addition, both output data rate and sampling

rate can also be configured to a sub-multiple of the input clock rate.

With the DATA_RATE<1:0> control, the output data rate can be programmed to be a sub-multiple of the ADC

sampling rate. This feature can be used to lower the output data rate, for example when the decimation filter is

used. Without enabling the decimation filter, the sub-multiple ADC sampling rate feature still can be used.

The different settings are listed below:

DATA_RATE<1>

DATA_RATE<0>

Output data rate

Same as ADC sampling rate

1/2 of ADC sampling rate

1/4 of ADC sampling rate

1/8 of ADC sampling rate

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SYNCHRONIZATION PULSE

ADDR.

(HEX)

D15

D14

D13

D12 D11 D10

TP_HARD_SYNC

EN_SYNC

The SYNC pin can be used to synchronize the data output from channels within the same chip or from channels

across chips when decimation filters are used with reduced output data rate.

When the decimation filters are used (for example, the decimate by two filter is enabled), then, effectively, the

device outputs one digital code for every two analog input samples. If the SYNC function is not enabled, then the

filters are not synchronized (even within a chip) – this means that one channel may be sending out codes

corresponding to input samples N, N+1 and so on, while another may be sending out code corresponding to

N+1, N+2 and so on.

To achieve synchronization, the SYNC pulse must arrive at all the ADS529x chips at the same time instant (as

shown in the timing diagram of Figure 54

The ADS5294 generates an internal synchronization signal which is used to reset the internal clock dividers used

by the decimation filter.

Using the SYNC signal in this way ensures that all channels will output digital codes corresponding to the same

set of input samples.

SYNC Timings:

Synchronizing the filters using the SYNC pin is enabled by default. No register bits are required to be

written. Even EN_SYNC bit is not required.It is important for register bit TP_HARD_SYNC to be 0 for

this mode to work. As shown by Figure 54, the SYNC rising edge can be positioned anywhere within the

window. The width of the SYNC must be at least one clock cycle.

0ns

ADC Input

Clock

t_CLK/2

-1ns

t_CLK/2

t : -1ns< t < t_CLK/2

SYNC

width

1clock cycle

Figure 54. Synchronization Pulse Timing

Note that the SYNC DOES NOT synchronize the sampling instants of the ADC across chips. All channels within

a single chip sample their analog inputs simultaneously. To ensure that channels across two chips will sample

their analog inputs simultaneously, the input clock needs to be routed to both chips with identical length. This

ensuring that the input clocks arrive at both the chips at the same time. This needs to be taken care of in the

board design and routing. The SYNC pin cannot be used to synchronize the sampling instants.

In addition to the above, the SYNC can also be used to synchronize the RAMP test patterns across channels. In

order to synchronize the test patterns, TP_HARD_SYNC must be set as 1. Setting TP_HARD_SYNC =1 actually

disables the sync of the filters.

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External Reference Mode of Operation

The ADS5294 supports an external reference mode of operation in one of two ways:

a. By forcing the reference voltages on the REFT and REFB pins.

b. By applying the reference voltage on VCM pin.

This mode can be used to operate multiple ADS5294 chips with the same (externally applied) reference voltage.

Using the REF pins:

For normal operation, the device requires two reference voltages, REFT and REFB. By default, the device

generates these two voltages internally. To enable the external reference mode, set the register bits as shown in

Table 6 . This powers down the internal reference amplifier and the two reference voltages can be forced directly

on the REFT and REFB pins as VREFT = 1.45V ± 50mV and VREFB = 0.45 V ±50 mV.

Note that the relation between the ADC full-scale input voltage and the applied reference voltages is

Full-scale input voltage = 2 x (VREFT – VREFB)

(4)

Using the VCM pin:

In this mode, an external reference voltage VREFIN can be applied to the VCM pin such that

Full-scale input voltage = 2 x VREFIN

(5)

To enable this mode, set the register bits as shown in Table 6. This changes the function of the VCM pin to an

external reference input pin. The voltage applied on VCM must be 1.5 V ±50 mV.

Table 6. External reference function

Function

EN_HIGH_ADDRS

EN_EXT_REF

EXT_REF_VCM

External reference using REFT/REFB pins

External reference using VCM pin

DATA OUTPUT FORMAT MODES

ADDR.

D15 D14 D13 D12 D11 D10

(HEX)

NAME

BTC_MODE

MSB_FIRST

The ADC output, by default, is in Straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the

MSB, and the output becomes Binary 2’s complement mode. Also, by default, the first bit of the frame (following

the rising edge of CLKP) is the LSB of the ADC output. Programming the MSB_FIRST mode inverts the bit order

in the word, and the MSB is output as the first bit following CLKP rising edge.

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PROGRAMMABLE MAPPING BETWEEN INPUT CHANNELS AND OUTPUT PINS

ADDR.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

(HEX)

NAME

MAP_CH1234_TO_OUT1A

MAP_CH1234_TO_OUT1B

MAP_CH1234_TO_OUT2A

MAP_CH1234_TO_OUT2B

MAP_CH1234_TO_OUT3A

MAP_CH1234_TO_OUT3B

MAP_CH1234_TO_OUT4A

MAP_CH1234_TO_OUT4B

MAP_CH5678_TO_OUT5B

MAP_CH5678_TO_OUT5A

MAP_CH5678_TO_OUT6B

MAP_CH5678_TO_OUT6A

MAP_CH5678_TO_OUT7B

MAP_CH5678_TO_OUT7A

MAP_CH5678_TO_OUT8B

MAP_CH5678_TO_OUT8A

The ADS5294 has 16 pairs of LVDS channel outputs. The mapping of ADC channels to LVDS output channels is

programmable to allow for flexibility in board layout. The 16 LVDS channel outputs are split in to 2 groups of 8

LVDS pairs. Within each group 4 ADC input channels can be multiplexed in to the 8 LVDS pairs depending on

the modes of operation whether it is 1 wire mode or 2 wire mode.

Input channels 1 to 4 can be mapped to any of the LVDS outputs OUT1A/B to OUT4A/B (using the

MAP_CH1234_TO_OUTnA/B). Similarly, input channels 5 to 8 can be mapped to any of the LVDS outputs

OUT5A/B to OUT8A/B (using the MAP_CH5678_TO_OUTnA/B). The block diagram of the mapping is listed in

Figure 55.

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Channel 8 data

MAP_CH5678_to_OUTn<3:0> = 0000

n = 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B

Channel 7 data

MAP_CH5678_to_OUTn<3:0> = 0010

OUTn

Channel 6 data

MAP_CH5678_to_OUTn<3:0> = 0100

MAP_CH5678_to_OUTn<3:0> = 1xxx, the

unused OUTn LVDS buffer is powered down.

Channel 5 data

MAP_CH5678_to_OUTn<3:0> = 0110

Channel 4 data

MAP_CH1234_to_OUTn<3:0> = 0110

Channel 3 data

MAP_CH1234_to_OUTn<3:0> = 0100

OUTn

Channel 2 data

MAP_CH1234_to_OUTn<3:0> = 0010

MAP_CH1234_to_OUTn<3:0> = 1xxx, the

unused OUTn LVDS buffer is powered down.

Channel 1 data

MAP_CH1234_to_OUTn<3:0> = 0000

(a) 1-wire mode

Channel 1 LSB Byte data<7:0>

MAP_CH1234_to_OUTn<3:0> = 0000

Channel 1 MSB Byte data<15:8>

MAP_CH1234_to_OUTn<3:0> = 0001

Channel 2 LSB Byte data<7:0>

MAP_CH1234_to_OUTn<3:0> = 0010

n = 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B

OUTn

Channel 2 MSB Byte data<15:8>

MAP_CH1234_to_OUTn<3:0> = 0011

Channel 3 LSB Byte data<7:0>

MAP_CH1234_to_OUTn<3:0> = 0100

MAP_CH1234_to_OUTn<3:0> = 1xxx, the

unused OUTn LVDS buffer is powered down.

Channel 3 MSB Byte data<15:8>

MAP_CH1234_to_OUTn<3:0> = 0101

Channel 4 LSB Byte data<7:0>

MAP_CH1234_to_OUTn<3:0> = 0110

Channel 4 MSB Byte data<15:8>

MAP_CH1234_to_OUTn<3:0> = 0011

Channel 8 LSB Byte data<7:0>

MAP_CH5678_to_OUTn<3:0> = 0000

Channel 8 MSB Byte data<15:8>

MAP_CH5678_to_OUTn<3:0> = 0001

Channel 7 LSB Byte data<7:0>

MAP_CH5678_to_OUTn<3:0> = 0010

n = 5A, 5B, 6A, 6B, 7A, 7B, 7A, 7B

OUTn

Channel 7 MSB Byte data<15:8>

MAP_CH5678_to_OUTn<3:0> = 0011

Channel 6 LSB Byte data<7:0>

MAP_CH5678_to_OUTn<3:0> = 0100

MAP_CH5678_to_OUTn<3:0> = 1xxx, the

unused OUTn LVDS buffer is powered down.

Channel 6 MSB Byte data<15:8>

MAP_CH5678_to_OUTn<3:0> = 0101

Channel 5 LSB Byte data<7:0>

MAP_CH5678_to_OUTn<3:0> = 0110

Channel 5 MSB Byte data<15:8>

MAP_CH5678_to_OUTn<3:0> = 0011

(b) 2-wire mode

Figure 55. Input and Output Channel Mapping

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Registers 0x50 to 0x55 control the multiplexing options as below:

MAP_CH1234_to_OUTn<3:0>

Mapping

Used in 1-wire mode?

Used in 2-wire mode?

0000

0001

ADC input channel IN1 to OUTn

Y, for LSB byte

Y, for MSB byte

ADC input channel IN1 to OUTn (2-

wire only)

0010

0011

ADC input channel IN2 to OUTn

Y, for LSB byte

Y, for MSB byte

ADC input channel IN2 to OUTn (2-

wire only)

0100

0101

ADC input channel IN3 to OUTn

Y, for LSB byte

Y, for MSB byte

ADC input channel IN3 to OUTn (2-

wire only)

0110

0111

ADC input channel IN4 to OUTn

Y, for LSB byte

Y, for MSB byte

ADC input channel IN4 to OUTn (2-

wire only)

1xxx

LVDS output buffer OUTn is powered

down

MAP_CH5678_to_OUTn<3:0> Mapping

Used in 1-wire mode?

Used in 2-wire mode?

Y, for LSB byte

0000

0001

ADC input channel IN8 to OUTn

ADC input channel IN8 to OUTn (2-

wire only)

Y, for MSB byte

0010

0011

ADC input channel IN7 to OUTn

Y, for LSB byte

Y, for MSB byte

ADC input channel IN7 to OUTn (2-

wire only)

0100

0101

ADC input channel IN6 to OUTn

Y, for LSB byte

Y, for MSB byte

ADC input channel IN6 to OUTn (2-

wire only)

0110

0111

ADC input channel IN5 to OUTn

Y, for LSB byte

Y, for MSB byte

ADC input channel IN5 to OUTn (2-

wire only)

1xxx

LVDS output buffer OUTn is powered

down

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The default mapping for 1-wire and 2-wire modes is:

Table 7. Mapping for 1-wire Mode

Analog Input channel

Channel IN1

Channel IN2

Channel IN3

Channel IN4

Channel IN5

Channel IN6

Channel IN7

Channel IN8

LVDS Output

OUT1A

OUT2A

OUT3A

OUT4A

OUT5A

OUT6A

OUT7A

OUT8A

Note: In the single wire mode with default register settings, ADC data is available only on OUTnA.

Table 8. Mapping for 2-wire Mode

Analog Input channel

Channel IN1

Channel IN2

Channel IN3

Channel IN4

Channel IN5

Channel IN6

Channel IN7

Channel IN8

LVDS Output

OUT1A, OUT1B

OUT2A, OUT2B

OUT3A, OUT3B

OUT4A, OUT4B

OUT5A, OUT5B

OUT6A, OUT6B

OUT7A, OUT7B

OUT8A, OUT8B

Note: In the 2-wire mode, the ADC data is available on both OUTnA and OUTnB.

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APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5294 is an octal channel, 14-bit high-speed ADC with sample rate up to 80 MSPS that runs off a single

1.8 V supply. All eight channels of the ADS5294 simultaneously sample their analog inputs at the rising edge of

the input clock. The sampled signal is sequentially converted by a series of small resolution stages, with the

outputs combined in a digital correction logic block. At every clock, edge the sample propagates through the

pipeline resulting in a data latency of 11 clock cycles.

The 14 data bits of each channel are serialized and sent out in either 1-wire (one pair of LVDS pins are used) or

2-wire (two pairs of LVDS pins are used) mode, depending on the LVDS output rate. When the data is output in

the 2-wire mode, it can reduce the serial data rate of the outputs, especially at higher sampling rates. Hence, low

cost FPGAs can be used to capture 80 MSPS/14bit data. Alternately, at lower sample rates, the 14-bit data can

be output as a single data stream over one pair of LVDS pins (1-wire mode). The device outputs a bit clock at 7x

and frame clock at 1x times the sample frequency in the 14-bit mode.

This 14-bit ADC achieves approximately 76 dBFS SNR at 80 MSPS. Its output resolution can be configured as

12-bit and 10-bit if necessary. 70 dBFS and 61 dBFS SNRs are achieved when the ADS5294’s output resolution

is 12-bit and 10-bit respectively.

ANALOG INPUT

The analog inputs consist of a switched-capacitor based, differential sample and hold architecture. This

differential topology results in very good AC performance even for high input frequencies at high sampling rates.

The INP and INM pins are internally biased around a common-mode voltage of Vcm (0.95 V). For a full-scale

differential input, each input pin (INP and INM) must swing symmetrically between Vcm + 0.5V and Vcm - 0.5V,

resulting in a 2 V_PPdifferential input swing. Figure 56 illustrates the equivalent circuit of the input sampling circuit.

Figure 56. Analog Input Circuit Model

DRIVE CIRCUIT

For optimum performance, the analog inputs must be driven differentially. This improves the common-mode

noise immunity and even order harmonic rejection. A 5 Ω to 15 Ω resistor in series with each input pin is

recommended to damp out ringing caused by package parasitic.

The drive circuit shows an R-C filter across the analog input pins. The purpose of the filter is to absorb the

glitches caused by the opening and closing of the sampling capacitors.

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0.1 mF

10 W

INP

Differential

Input

2 pF

INM

ADS259x

10 W

0.1 mF

Figure 57. Analog Input Drive Circuit

Large and Small Signal Input Bandwidth

The small signal bandwidth of the analog input circuit is high, around 550 MHz. When using an amplifier to drive

the ADS5294, the total noise of the amplifier up to the small signal bandwidth must be considered. The large

signal bandwidth of the device depends on the amplitude of the input signal. The ADS5294 supports 2 V_PP

amplitude for input signal frequency up to 80 MHz. For higher frequencies (80 MHz), the amplitude of the input

signal must be decreased proportionally. For example, at 160 MHz, the device supports a maximum of 1 V_PP

signal.

INPUT CLOCK

The ADS5294 is configured by default to operate with a single-ended input clock – CLKP is driven by a CMOS

clock and CLKM is tied to GND. The device can automatically detect a single-ended or differential clock. If CLKM

is grounded, the device treats clock as a single-ended clock. Operating with a low-jitter differential clock usually

gives better SNR performance, especially at input frequencies greater than 30 MHz. Typical clock termination

structures are listed in Figure 58 andFigure 59.

Clock buffer

Lpkg

~ 2 nH

5 Ω

CLKP

Cbond

~ 0.5 pF

Ceq

6 pF

5 kΩ

Resr

~ 200 Ω

VCM

5 kΩ

Lpkg

~ 2 nH

5 Ω

CLKM

Cbond

~ 0.5 pF

Resr

~ 200 Ω

Ceq is approximately 1 to 3 pF, equivalent input capacitance of clock buffer.

Figure 58. Equivalent Circut of the Input Clock Circuit

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SINGLE-ENDED CLOCK CONNECTIONS

CMOS

CLOCK IN

CLKP

VCM

CLKM

ADS529x

Figure 59. Single-Ended Clock Drive Circuit

DIFFERENTIAL CLOCK CONNECTIONS

0.1 mF

CLKP

CLKM

CLKP

CLKM

Differential

LVPECL

term

Differential sine-

wave clock input

clock input

0.1 mF

ADS529x

0.1 mF

ADS529x

term

0.1 mF

CLKP

Differential

LVDS

term

clock input

CLKM

0.1 mF

ADS529x

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DIGITAL HIGH PASS IIR FILTER

DC offset is often observed at ADC input signals. For example, in ultrasound applications, the DC offset from

VGA (variable Gain amplifier) varies at different gains. Such a variable offset can introduce artifacts in ultrasound

images especially in Doppler modes. Analog filter between ADC and VGA can be used with added noise and

power. Digital filter achieves the same performance as analog filters and has more flexibility in fine tuning

multiple characteristics.

ADS5294 includes optional 1^storder digital high-pass IIR filter. Its block diagram is shown in Figure 60 as well as

its transfer function

2^k

2^k+1

y(n) =

[x(n) - x(n -1)+y(n -1)]

(6)

Figure 60. HP Filter Block Diagram

Figure 61 shows its characteristics at k=2 to 10.

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

K=2

K=3

K=4

K=5

K=6

K=7

K=8

K=9

K=10

−45

0.02

0.1

10 15

Input Signal Frequency (MHz)

Figure 61. HP Filter Amplitude Response at K = 2 to 10

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DECIMATION FILTER

ADS5294 includes an option to decimate the ADC output data using filters. Once the decimation is enabled, the

decimation rate, frequency band of the filter can be programmed. In addition, the user can select either the pre-

defined or custom coefficients.

Table 9. Digital Filters

<USE

FILTER

CHn>

<DATA

RATE>

FILTERn

RATE>

<FILTERn

COEFF SET>

<EN CUSTOM

FILT>

DECIMATION

TYPE OF FILTER

Built-in low-pass odd-tap filter (pass band = 0 to f_S/4)

Built-in high-pass odd-tap filter (pass band = 0 to f_S/4)

Built-in low-pass even-tap filter (pass band = 0 to f_S/8)

Built-in first band pass even tap filter(pass band = f_S/8 to f_S/4)

001

010

000

001

000

001

010

011

Decimate by 2

Decimate by 4

Built-in second band pass even tap filter(pass band = f_S/4 to 3

f_S/8)

010

001

100

Built-in high pass odd tap filter (pass band = 3 f_S/8 to f_S/2)

Custom filter (user programmablecoefficients)

010

001

010

011

001

000

001

100

101

000

Decimate by 2

Decimate by 4

Decimate by 8

Bypass decimation

0 and 1

DECIMATION FILTER EQUATION

In the default setting, the decimation filter is implemented as a 24-tap FIR filter with symmetrical coefficients

(each coefficient is 12-bit signed). By setting the register bit <ODD TAPn> = 1, a 23-tap FIR is implemented

Pre-defined Coefficients

The build-in filters (low pass, high pass an band pass) use pre-defined coefficients. The frequency responses of

the build-in decimation filters with different decimation factors are shown in Figure 62.

Low Pass

High pass

Low Pass

Band−Pass1

Band−Pass2

High Pass

−10

−20

−30

−40

−50

−60

−70

−80

−10

−20

−30

−40

−50

−60

−70

−80

0.0

0.1

0.2

0.3

0.4

0.5

0.0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (fin/fs)

Normalized frequency (fin/fs)

Figure 62. Decimation Filter Responses

(Decimate by 2)

Figure 63. Decimation Filter Responses

(Decimate by 4)

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Custom Filter Coefficients

The filter coefficients can also be programmed by the user (customized). For custom coefficients, set the register

bit <FILTER COEFF SELECT> and load the coefficients (h₀to h₁₁) in registers 0x5A to 0xB9, using the serial

interface as:

Board Design Considerations

Grounding

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of

the board are cleanly partitioned. See ADS5294VM Evaluation Module (SLAU355) for placement of components,

routing and grounding.

Supply Decoupling

Because the ADS5294 already includes internal decoupling, minimal external decoupling can be used without

loss in performance. For example, the ADS5294EVM uses a single 0.1 µF decoupling capacitor for each supply,

placed close to the device supply pins.

Packaging

Exposed Pad

The exposed pad at the bottom of the package is the main path for heat dissipation. Therefore, the pad must be

soldered to a ground plane on the PCB for best thermal performance. The pad must be connected to the ground

plane through the optimum number of vias.

Also, visit TI’s thermal website at www.ti.com/thermal.

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DEFINITION OF SPECIFICATIONS

Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with

respect to the low-frequency value.

Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at

which the sampling occurs. This delay is different across channels. The maximum variation is specified as

aperture delay variation (channel-to-channel).

Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains

at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a

percentage. A perfect differential sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric

testing is performed at this sampling rate unless otherwise noted.

Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly

1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.

Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined

by a least squares curve fit of that transfer function, measured in units of LSBs.

Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain

error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a

result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as

E_GREFand E_GCHAN

To a first-order approximation, the total gain error is E_TOTAL~ E_GREF+ E_GCHAN

For example, if E_TOTAL= ±0.5%, the full-scale input varies from (1 – 0.5/100) x FS_idealto (1 + 0.5/100) x FS_ideal

Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle

channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.

Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the

change per degree Celsius of the parameter from T_MINto T_MAX. It is calculated by dividing the maximum deviation

of the parameter across the T_MINto T_MAXrange by the difference T_MAX– T_MIN

Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (P_S) to the noise floor power (P_N),

excluding the power at dc and the first nine harmonics.

P_S

SNR = 10Log¹⁰

P_N

(7)

SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-

scale range.

Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (P_S) to the power

of all the other spectral components including noise (P_N) and distortion (P_D), but excluding dc.

P_S

SINAD = 10Log¹⁰

P_N+ P_D

(8)

SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-

scale range.

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SLAS776B –NOVEMBER 2011–REVISED JULY 2012

Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the

theoretical limit based on quantization noise.

SINAD - 1.76

ENOB =

6.02

(9)

Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (P_S) to the power of the

first nine harmonics (P_D).

P_S

THD = 10Log¹⁰

P_N

(10)

THD is typically given in units of dBc (dB to carrier).

Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other

spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).

Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f₁

and f₂) to the power of the worst spectral component at either frequency 2f₁– f₂or 2f₂– f₁. IMD3 is either given

in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB

to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change

in analog supply voltage. The dc PSRR is typically given in units of mV/V.

AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the

supply voltage by the ADC. If ΔV_SUPis the change in supply voltage and ΔV_OUTis the resultant change of the

ADC output code (referred to the input), then:

DV_OUT

PSRR = 20Log¹⁰

(Expressed in dBc)

DV_SUP

(11)

Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an

overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and

negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.

Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input

common-mode by the ADC. If ΔV_{CM_IN}is the change in the common-mode voltage of the input pins and ΔV_OUTis

the resulting change of the ADC output code (referred to the input), then:

DV_OUT

CMRR = 20Log

(Expressed in dBc)

DV_CM

(12)

Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an

adjacent channel into the channel of interest. It is specified separately for coupling from the immediate

neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually

measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the

coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the

adjacent channel input. It is typically expressed in dBc.

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SLAS776B –NOVEMBER 2011–REVISED JULY 2012

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REVISION HISTORY

Changes from Original (November 2011) to Revision A

Page

•

Changed From: Product Preview To: Production ................................................................................................................. 1

Changes from Revision A (November 2011) to Revision B

Page

•

Changed the location of OUT A and OUT B in Figure 5 and Figure 6 ............................................................................... 14

Added EN_HIGH_ADDRS to Table 3 ................................................................................................................................. 29

Moved EN_EXT_REF From: 0x0F To: 0xF0 in Table 3 ..................................................................................................... 34

Added the section BIT-BYTE-WORD WISE OUTPUT. Added Figure 47 and Figure 48. .................................................. 37

Added section DIGITAL PROCESSING BLOCKS ............................................................................................................. 38

Replaced Table 5 and Table 6 with new Table 5 - Digital Filters ....................................................................................... 43

Changed the SYNCHRONIZATION PULSE section .......................................................................................................... 46

Added the External Reference Mode of Operation section ................................................................................................ 47

Added Figure 58 ................................................................................................................................................................. 53

Replaced Table 9 (Decimation Filter Modes) with new Table 9 - Digital Filters ................................................................. 56

Deleted section: Synchronization Pulse ............................................................................................................................. 57

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PACKAGE OPTION ADDENDUM

www.ti.com

25-Feb-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

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ACTIVE

HTQFP

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& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

1000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

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SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

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PACKAGE MATERIALS INFORMATION

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14-Jul-2012

*All dimensions are nominal

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