ADS5287 [TI]
10-Bit, Octal-Channel ADC Up to 65MSPS; 10位，八通道ADC多达65MSPS
| 型号： | ADS5287 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-Bit, Octal-Channel ADC Up to 65MSPS |
| 文件： | 总31页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5287
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SBAS428–JANUARY 2008
10-Bit, Octal-Channel ADC Up to 65MSPS
1
FEATURES
DESCRIPTION
23
•
Speed and Resolution Grades:
10-bit, 65MSPS
Power Dissipation:
The ADS5287 is a high-performance, low-power,
octal channel analog-to-digital converter (ADC).
Available in a 9mm × 9mm QFN package, with
serialized low-voltage differential signaling (LVDS)
outputs and a wide variety of programmable features,
the ADS5287 is highly customizable for a diversity of
applications and offers an unprecedented level of
system integration. An application note, XAPP774
(available at www.xilinx.com) describes how to
interface the serial LVDS outputs of TI's ADCs to
Xilinx® field-programmable gate arrays (FPGAs). The
ADS5287 is specified over the industrial temperature
range of –40°C to +85°C.
–
•
–
–
–
–
46mW/Channel at 30MSPS
53mW/Channel at 40MSPS
62mW/Channel at 50MSPS
74mW/Channel at 65MSPS
•
•
•
•
•
•
•
61.7dBFS SNR at 10MHz IF
Analog Input Full-Scale Range: 2VPP
Low-Frequency Noise Suppression Mode
6dB Overload Recovery in One Clock
External and Internal (Trimmed) Reference
3.3V Analog Supply, 1.8V Digital Supply
Single-Ended or Differential Clock:
LCLKP
LCLKN
6x ADCLK
12x ADCLK
1x ADCLK
Clock
Buffer
–
Clock Duty Cycle Correction Circuit (DCC)
•
•
•
Programmable Digital Gain: 0dB to 12dB
Serialized DDR LVDS Output
PLL
ADCLKP
ADCLKN
Programmable LVDS Current Drive, Internal
Termination
IN1P
IN1N
OUT1P
OUT1N
10-Bit
ADC
Digital
Serializer
•
•
Test Patterns for Enabling Output Capture
Channels
2 to 7
Straight Offset Binary or Two's Complement
Output
•
Package Options:
IN8P
IN8N
OUT8P
OUT8N
10-Bit
ADC
Digital
Serializer
–
9mm × 9mm QFN-64
APPLICATIONS
•
•
•
Medical Imaging
Wireless Base-Station Infrastructure
Test and Measurement Instrumentation
Power-
Down
ADC
Control
Registers
Reference
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Xilinx is a registered trademark of Xilinx, Inc.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2008, Texas Instruments Incorporated
ADS5287
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SBAS428–JANUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
RELATED PRODUCTS
MODEL
ADS5281
ADS5282
ADS5287
ADS5270
ADS5271
ADS5272
ADS5273
ADS5242
RESOLUTION (BITS)
SAMPLE RATE (MSPS)
CHANNELS
12
12
10
12
12
12
12
12
50
65
65
40
50
65
70
65
8
8
8
8
8
8
8
4
ORDERING INFORMATION(1)(2)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
PRODUCT
PACKAGE-LEAD
QFN-64
MEDIA, QUANTITY
Tape and Reel, 250
Tape and Reel, 2000
ADS5287IRGCT
ADS5287IRGCR
ADS5287
RGC
–40°C to +85°C
AZ5287
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) These devices meet the following planned eco-friendly classification:
Green (RoHS and No Sb/Br): Texas Instruments defines Green to mean Pb-free (RoHS compatible) and free of bromine (Br)- and
antimony (Sb)-based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more information. These devices
have a Cu NiPdAu lead/ball finish.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
ADS5287
UNIT
V
Supply voltage range, AVDD
Supply voltage range, LVDD
Voltage between AVSS and LVSS
External voltage applied to REFT pin
External voltage applied to REFB pin
Voltage applied to analog input pins
Voltage applied to digital input pins
Peak solder temperature
–0.3 to +3.9
–0.3 to +2.2
V
–0.3 to +0.3
V
–0.3 to +3
V
–0.3 to +2
V
–0.3 to minimum [3.6, (AVDD + 0.3)]
V
–0.3 to minimum [3.9, (AVDD + 0.3)]
V
+260
+125
°C
°C
°C
Junction temperature
Storage temperature range
–65 to +150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
2
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RECOMMENDED OPERATING CONDITIONS
ADS5287
TYP
PARAMETER
MIN
MAX
UNIT
SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES
AVDD
LVDD
Analog supply voltage
3.0
1.7
3.3
3.6
1.9
V
V
Digital supply voltage
1.8
Differential input voltage range
Input common-mode voltage
External reference mode
External reference mode
2
VCM ± 0.05
2.5
VPP
V
REFT
REFB
V
0.5
V
CLOCK INPUTS
ADCLK input sample rate 1/ tC
10
50, 65
MSPS
Input clock amplitude differential (VCLKP–VCLKN) peak-to-peak
Sine wave, ac-coupled
3.0
1.6
0.7
VPP
VPP
VPP
LVPECL, ac-coupled
LVDS, ac-coupled
Input clock CMOS, single-ended (VCLKP
)
VIL
0.6
V
V
VIH
2.2
Input clock duty cycle
50
%
DIGITAL OUTPUTS
ADCLKP and ADCLKN outputs (LVDS)
LCLKP and LCLKN outputs (LVDS)
10
60
1x (sample rate)
50, 65
MHz
MHz
pF
6x (sample rate)
300, 390
CLOAD
RLOAD
TA
Maximum external capacitance from each pin to LVSS
Differential load resistance between the LVDS output pairs
Operating free-air temperature
5
100
Ω
–40
+85
°C
INITIALIZATION REGISTERS
After the device has been powered up, the following registers must be written to (in the exact order listed) through the serial
interface as part of an initialization sequence.
ADDRESS (hex)
DATA (hex)
0002
Initialization register 1
Initialization register 2
Initialization register 3
Initialization register 4
03
01
0010
C7
DE
8001
01C0
If the analog input is ac-coupled, register 5 must be be written to.
ADDRESS (hex)
E2
DATA (hex)
Initialization register 5
00C0
Initializing these registers configures the device for the most optimum mode of operation.
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DIGITAL CHARACTERISTICS
DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level
'0' or '1'. At CLOAD = 5pF(1), IOUT = 3.5mA(2), RLOAD = 100Ω(2), and no internal termination, unless otherwise noted.
ADS5287
PARAMETER
DIGITAL INPUTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
1.4
V
0.3
V
33
–33
3
µA
µA
pF
LVDS OUTPUTS
High-level output voltage
Low-level output voltage
Output differential voltage, |VOD
VOS output offset voltage
1375
1025
350
mV
mV
mV
mV
|
Common-mode voltage of OUTP and OUTN
1200
Output capacitance inside the device,
from either output to ground
Output capacitance
2
pF
(1) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(2) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
4
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ELECTRICAL CHARACTERISTICS
Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN
=
–40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS
differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless
otherwise noted.Typical values at +25°C.
ADS5287
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE VOLTAGES
VREFB
VREFT
Reference bottom
Reference top
0.5
2.5
2.0
1.5
±2
V
V
VREFT – VREFB
1.95
2.05
V
VCM
Common-mode voltage (internal)
VCM output current
1.425
1.575
V
mA
EXTERNAL REFERENCE VOLTAGES
VREFB
VREFT
Reference bottom
Reference top
VREFT – VREFB
0.4
2.4
1.9
0.5
2.5
2.0
0.6
2.6
2.1
V
V
V
ANALOG INPUT
Differential input voltage range
2.0
3
VPP
pF
Differential input capacitance
Analog input bandwidth
520
MHz
V
Analog input common-mode range
DC-coupled input
VCM ± 0.05
Per input pin per MSPS of sampling
speed
µA/MHz
per pin
Analog input common-mode current
Voltage overload recovery time
2.5
1
Recovery from 6dB overload to within 1%
accuracy
Clock cycle
LSB
Standard deviation seen on a periodic
first data within full-scale range in a 6dB
overloaded sine wave
Voltage overload recovery repeatability
1
DC ACCURACY
Offset error
Offset error temperature coefficient(1)
–1.25
±0.2
±5
+1.25
%FS
ppm/°C
%FS
Channel gain error
Excludes error in internal reference
–0.8
Channel gain error temperature
coefficient
Excludes temperature coefficient of
internal reference
±10
ppm/°C
Internal reference error temperature
coefficient(2)
DC power-supply rejection ratio(3)
±15
1.5
ppm/°C
DC PSRR
mV/V
POWER-DOWN MODES
Power in complete power-down mode
45
135
88
mW
mW
mW
Power in partial power-down mode
Power with no clock
Clock at 65MSPS
DYNAMIC PERFORMANCE
5MHz full-scale signal applied to seven
channels, measurement taken on channel
with no input signal
Crosstalk
–90
–92
dBc
Two-tone, third-order intermodulation
distortion
f1 = 9.5MHz at –7dBFs
f2 = 10.2MHz at –7dBFs
dBFS
DC ACCURACY
No missing codes
Assured
±0.1
DNL
INL
Differential nonlinearity
Integral nonlinearity
–0.5
–1
+0.5
+1
LSB
LSB
±0.1
(1) The offset temperature coefficient in ppm/°C is defined as (O1 – O2) × 106/(T1 – T2)/1024, where O1 and O2 are the offset codes in LSB
at the two extreme temperatures, T1 and T2.
(2) The internal reference temperature coefficient is defined as (REF1 – REF2) × 106/(T1 – T2)/2, where REF1 and REF2 are the internal
reference voltages (REFT – REFB) at the two extreme temperatures, T1 and T2.
(3) DC PSRR is defined as the ratio of the change in the ADC output (expressed in mV) to the change in supply voltage (in volts).
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN
=
–40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS
differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless
otherwise noted.Typical values at +25°C.
ADS5287
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY—INTERNAL REFERENCE MODE
IAVDD
ILVDD
Analog supply current
Digital current
139
87
TBD
TBD
TBD
mA
mA
mW
Zero input to all channels
Total power
615
Obtained on powering down one channel
at a time
Incremental power saving
61
mW
POWER SUPPLY—EXTERNAL REFERENCE MODE
IAVDD
ILVDD
Analog supply current
Digital current
132
87
mA
mA
mW
Zero input to all channels
Total power
592
Obtained on powering down one channel
at a time
Incremental power saving
59
mW
EXTERNAL REFERENCE LOADING
Switching current
Current drawn by the eight ADCs from the
external reference voltages; sourcing for
REFT, sinking for REFB.
3.5
mA
DYNAMIC CHARACTERISTICS
fIN = 5MHz, single-ended clock
fIN = 30MHz, differential clock
fIN = 5MHz, single-ended clock
fIN = 30MHz, differential clock
fIN = 5MHz, single-ended clock
fIN = 30MHz, differential clock
fIN = 5MHz, single-ended clock
fIN = 30MHz, differential clock
fIN = 5MHz, single-ended clock
fIN = 30MHz, differential clock
fIN = 5MHz, single-ended clock
fIN = 30MHz, differential clock
73
73
85
80
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
SFDR
HD2
Spurious-free dynamic range
Magnitude of second harmonic
Magnitude of third harmonic
Total harmonic distortion
Signal-to-noise ratio
85
82
73
85
HD3
80
70
80
THD
78
60.5
60.4
61.7
61.7
61.6
61.6
SNR
SINAD
Signal-to-noise and distortion
6
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PIN CONFIGURATION
QFN-64 PowerPAD
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IN1P
IN1N
IN8N
IN8P
3
AVSS
IN2P
AVSS
IN7N
4
5
IN2N
IN7P
6
AVSS
IN3P
AVSS
IN6N
7
8
IN3N
IN6P
ADS5287
9
AVSS
IN4P
AVSS
IN5N
10
11
12
13
14
15
16
IN4N
IN5P
LVSS
PD
AVSS
LVSS
LVDD
OUT8N
OUT8P
LVSS
OUT1P
OUT1N
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Table 1. PIN DESCRIPTIONS: QFN-64
PIN NAME
ADCLKN
ADCLKP
AVDD
DESCRIPTION
PIN NUMBER
# OF PINS
LVDS frame clock (1X)—negative output
LVDS frame clock (1X)—positive output
Analog power supply, 3.3V
Analog ground
24
23
1
1
4
7
49, 50, 57, 60
AVSS
3, 6, 9, 37, 40, 43, 46
Negative differential clock input
Tie CLKN to 0V for a single-ended clock
CLKN
59
1
CLKP
CS
Positive differential clock input
58
61
2
1
1
1
1
1
1
1
1
1
1
Serial enable chip select—active low digital input
Negative differential input signal, channel 1
Positive differential input signal, channel 1
Negative differential input signal, channel 2
Positive differential input signal, channel 2
Negative differential input signal, channel 3
Positive differential input signal, channel 3
Negative differential input signal, channel 4
Positive differential input signal, channel 4
IN1N
IN1P
IN2N
IN2P
IN3N
IN3P
IN4N
IN4P
1
5
4
8
7
11
10
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Table 1. PIN DESCRIPTIONS: QFN-64 (continued)
PIN NAME
IN5N
DESCRIPTION
PIN NUMBER
# OF PINS
Negative differential input signal, channel 5
Positive differential input signal, channel 5
Negative differential input signal, channel 6
Positive differential input signal, channel 6
Negative differential input signal, channel 7
Positive differential input signal, channel 7
Negative differential input signal, channel 8
Positive differential input signal, channel 8
Internal/external reference mode select input
Bias pin—56.2kΩ to ground
39
38
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IN5P
IN6N
42
IN6P
41
IN7N
45
IN7P
44
IN8N
48
IN8P
47
INT/EXT
ISET
56
51
LCLKN
LCLKP
LVDD
LVSS
OUT1N
OUT1P
OUT2N
OUT2P
OUT3N
OUT3P
OUT4N
OUT4P
OUT5N
OUT5P
OUT6N
OUT6P
OUT7N
OUT7P
OUT8N
OUT8P
PD
LVDS bit clock (6X)—negative output
LVDS bit clock (6X)—positive output
Digital and I/O power supply, 1.8V
Digital ground
26
25
35
12, 14, 36
16
LVDS channel 1—negative output
LVDS channel 1—positive output
LVDS channel 2—negative output
LVDS channel 2—positive output
LVDS channel 3—negative output
LVDS channel 3—positive output
LVDS channel 4—negative output
LVDS channel 4—positive output
LVDS channel 5—negative output
LVDS channel 5—positive output
LVDS channel 6—negative output
LVDS channel 6—positive output
LVDS channel 7—negative output
LVDS channel 7—positive output
LVDS channel 8—negative output
LVDS channel 8—positive output
Power-down input
15
18
17
20
19
22
21
28
27
30
29
32
31
34
33
13
REFB
Negative reference input/output
Positive reference input/output
Active low RESET input
54
REFT
55
RESET
SCLK
SDATA
TP
64
Serial clock input
63
Serial data input
62
Test pin, do not use
52
VCM
Common-mode output pin, 1.5V output
53
8
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FUNCTIONAL BLOCK DIAGRAM
LCLKP
LCLKN
6x ADCLK
Clock
Buffer
12x ADCLK
1x ADCLK
PLL
ADCLKP
ADCLKN
IN1P
IN1N
OUT1P
OUT1N
10-Bit
ADC
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
IN2P
IN2N
OUT2P
OUT2N
10-Bit
ADC
IN3P
IN3N
OUT3P
OUT3N
10-Bit
ADC
IN4P
IN4N
OUT4P
OUT4N
10-Bit
ADC
IN5P
IN5N
OUT5P
OUT5N
10-Bit
ADC
IN6P
IN6N
OUT6P
OUT6N
10-Bit
ADC
IN7P
IN7N
OUT7P
OUT7N
10-Bit
ADC
IN8P
IN8N
OUT8P
OUT8N
10-Bit
ADC
Power-
Down
ADC
Control
Registers
Reference
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LVDS TIMING DIAGRAM
Sample n
tD(A)
Sample n + 12
Analog Input
Clock Input
Sample n + 13
tSAMPLE
12 clocks latency
LCLKN
6X ADCLK
LCLKP
OUTP
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
SERIAL DATA
OUTN
ADCLKN
1X ADCLK
ADCLKP
tPROP
DEFINITION OF SETUP AND HOLD TIMES
LCLKN
LCLKP
OUTN
OUTP
tH1
tSU1 tH2
tSU2
tSU = min(tSU1, tSU2
)
tH = min(tH1, tH2
)
TIMING CHARACTERISTICS(1)
ADS5287
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
tA
Aperture delay
1.5
4.5
Aperture delay variation Channel-to-channel within the same device (3σ)
±20
400
ps
tJ
Aperture jitter
fs
Time to valid data after coming out of
COMPLETE POWER-DOWN mode
50
µs
µs
µs
Time to valid data after coming out of PARTIAL
POWER-DOWN mode (with clock continuing to
run during power-down)
tWAKE
Wake-up time
2
Time to valid data after stopping and restarting
the input clock
40
12
Clock
cycles
Data latency
(1) Timing parameters are ensured by design and characterization; not production tested.
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LVDS OUTPUT TIMING CHARACTERISTICS(1)
Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX
=
+85°C, sampling frequency = as specified, CLOAD = 5pF(2), IOUT = 3.5mA, RLOAD = 100Ω(3), and no internal termination, unless otherwise
noted.
ADS5287
40MSPS
TYP
50MSPS
TYP
65MSPS
TYP
PARAMETER
TEST CONDITIONS(4)
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Data valid(6) to zero-crossing of
LCLKP
tSU
tH
Data setup time(5)
0.67
0.47
0.27
ns
Zero-crossing of LCLKP to data
becoming invalid(6)
Data hold time(5)
0.85
10
0.65
10
0.4
9.7
41
ns
ns
Input clock (ADCLK) rising edge
cross-over to output clock (ADCLKP)
rising edge cross-over
tPROP
Clock propagation delay
LVDS bit clock duty cycle
14
16.6
53
12.5
14.1
53.5
11.5
14
57
Duty cycle of differential clock,
(LCLKP – LCLKN)
45.5
50
250
150
0.2
0.2
45
50
250
150
0.2
0.2
50
250
150
0.2
0.2
Bit clock cycle-to-cycle
jitter
ps, pp
ps, pp
ns
Frame clock cycle-to-cycle
jitter
tRISE
tFALL
,
Data rise time, data fall
time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
0.09
0.09
0.4
0.4
0.09
0.09
0.4
0.4
0.09
0.09
0.4
0.4
tCLKRISE
tCLKFALL
,
Output clock rise time,
output clock fall time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
ns
(1) Timing parameters are ensured by design and characterization; not production tested.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
(6) Data valid refers to a logic high of +100mV and a logic low of –100mV.
LVDS OUTPUT TIMING CHARACTERISTICS(1)
Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX
=
+85°C, sampling frequency = as specified, CLOAD = 5pF(2), IOUT = 3.5mA, RLOAD = 100Ω(3), and no internal termination, unless otherwise
noted.
ADS5287
30MSPS
TYP
20MSPS
TYP
10MSPS
TYP
PARAMETER
TEST CONDITIONS(4)
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Data valid(6) to zero-crossing of
LCLKP
tSU
tH
Data setup time(5)
0.8
1.5
3.7
ns
Zero-crossing of LCLKP to data
becoming invalid(6)
Data hold time(5)
1.2
9.5
1.9
9.5
48
3.9
10
49
ns
ns
Input clock (ADCLK) rising edge
cross-over to output clock (ADCLKP)
rising edge cross-over
tPROP
Clock propagation delay
LVDS bit clock duty cycle
13.5
17.3
52
14.5
17.3
51
14.7
17.1
51
Duty cycle of differential clock,
(LCLKP – LCLKN)
46.5
50
250
150
0.2
0.2
50
250
150
0.2
0.2
50
750
500
0.2
0.2
Bit clock cycle-to-cycle
jitter
ps, pp
ps, pp
ns
Frame clock cycle-to-cycle
jitter
tRISE
tFALL
,
Data rise time, data fall
time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
0.09
0.09
0.4
0.4
0.09
0.09
0.4
0.4
0.09
0.09
0.4
0.4
tCLKRISE
tCLKFALL
,
Output clock rise time,
output clock fall time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
ns
(1) Timing parameters are ensured by design and characterization; not production tested.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
(6) Data valid refers to a logic high of +100mV and a logic low of –100mV.
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RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING(1)
t1
AVDD (3V to 3.6V)
AVDD
t2
LVDD (1.7V to 1.9V)
t3
LVDD
t4
t7
High-Level RESET
(1.4V to 3.6V)
t5
RESET
t6
Device Ready for
Serial Register Write(2)
High-Level CS
(1.4V to 3.6V)
CS
Device Ready for
Data Conversion
Start of Clock
ADCLK
t8
10µs < t1 < 50ms, 10µs < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100µs.
(1) The AVDD and LVDD power-on sequence does not matter as long as –10ms < t3 < 10ms. Similar considerations apply while shutting
down the device.
(2) Write initialization registers listed in the Initialization Registers table.
POWER-DOWN TIMING
1ms
tWAKE
PD
Device Fully
Powers Down
Device Fully
Powers Up
Power-up time shown is based on 1µF bypass capacitors on the reference pins. tWAKE is the time it takes for the device to wake up
completely from power-down mode. The ADS5287 has two power-down modes: complete power-down mode and partial power-down mode.
The device can be configured in partial power-down mode through a register setting.
tWAKE < 50µs for complete power-down mode.
tWAKE < 2µs for partial power-down mode (provided the clock is not shut off during power-down).
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SERIAL INTERFACE
The ADS5287 has a set of internal registers that can be accessed through the serial interface formed by pins CS
(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the
following actions occur:
•
•
•
Serial shift of bits into the device is enabled
SDATA (serial data) is latched at every rising edge of SCLK
SDATA is loaded into the register at every 24th SCLK rising edge
If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of
24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16
bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds
(a few hertz) and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the respective default values. Initialization can be
done in one of two ways:
1. Through a hardware reset, by applying a low-going pulse on the RESET pin; or
2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the
internal registers to the respective default values and then self-resets the RST bit low. In this case, the
RESET pin stays high (inactive).
After all registers have been initialized to the respective default values through a RESET operation, the registers
detailed in the Initialization Registers table must be written into. The write process must be done after every
hardware or software RESET operation in order to configure the device for the best mode of operation.
SERIAL INTERFACE TIMING
Start Sequence
End Sequence
CS
t6
t1
t7
t2
Data latched on rising edge of SCLK
SCLK
t3
D15 D14 D13 D12 D11 D10 D9
SDATA
A7 A6 A5 A4 A3 A2 A1 A0
D8 D7 D6 D5 D4 D3 D2 D1 D0
t4
t5
ADS5287
PARAMETER
DESCRIPTION
SCLK period
MIN
TYP
MAX
UNIT
ns
t1
t2
t3
t4
t5
t6
t7
50
20
20
5
SCLK high time
SCLK low time
Data setup time
Data hold time
CS fall to SCLK rise
ns
ns
ns
5
ns
8
ns
Time between last SCLK rising edge to CS rising edge
8
ns
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SERIAL REGISTER MAP
Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1)(2)(3)(4)
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
DESCRIPTION
DEFAULT
00
X
RST
Self-clearing software RESET.
Inactive
Channel-specific ADC
power-down mode.
X
X
X
X
X
X
X
X
PDN_CH<8:1>
PDN_PARTIAL
PDN_COMPLETE
PDN_PIN_CFG
Inactive
Inactive
Inactive
Partial power-down mode (fast
recovery from power-down).
X
0F
Register mode for complete
power-down (slower recovery).
X
Configures the PD pin for partial
power-down mode.
Complete
power-down
X
LVDS current drive
X
X
X
ILVDS_LCLK<2:0> programmability for LCLKN and
LCLKP pins.
3.5mA drive
LVDS current drive
ILVDS_FRAME
11
X
X
X
programmability for ADCLKN and 3.5mA drive
ADCLKP pins.
<2:0>
LVDS current drive
X
X
X
ILVDS_DAT<2:0> programmability for OUTN and
OUTP pins.
3.5mA drive
Enables internal termination for
EN_LVDS_TERM
Termination
disabled
X
1
1
1
LVDS buffers.
Programmable termination for
TERM_LCLK<2:0>
Termination
disabled
X
X
X
LCLKN and LCLKP buffers.
12
TERM_FRAME
<2:0>
Programmable termination for
ADCLKN and ADCLKP buffers.
Termination
disabled
X
X
X
Programmable termination for
OUTN and OUTP buffers.
Termination
disabled
X
X
X
TERM_DAT<2:0>
LFNS_CH<8:1>
Channel-specific, low-frequency
noise suppression mode enable.
14
24
X
X
X
X
X
0
X
X
0
X
X
0
0
X
X
X
X
X
X
X
X
Inactive
INP is
positive
input
Swaps the polarity of the analog
input pins electrically.
INVERT_CH<8:1>
EN_RAMP
Enables a repeating full-scale
ramp pattern on the outputs.
Inactive
Inactive
Enables the mode wherein the
output toggles between two
defined codes.
DUALCUSTOM_
PAT
X
Enables the mode wherein the
output is a constant specified
code.
SINGLE_CUSTOM
_PAT
0
0
X
Inactive
25
2MSBs for a single custom
pattern (and for the first code of
the dual custom pattern). <9> is
the MSB.
BITS_CUSTOM1
<9:8>
X
X
Inactive
Inactive
Inactive
Inactive
BITS_CUSTOM2
<9:8>
2MSBs for the second code of
the dual custom pattern.
X
X
8 lower bits for the single custom
pattern (and for the first code of
the dual custom pattern). <0> is
the LSB.
BITS_CUSTOM1
<7:0>
26
27
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BITS_CUSTOM2
<7:0>
8 lower bits for the second code
of the dual custom pattern.
X
X
X
X
GAIN_CH1<3:0>
GAIN_CH2<3:0>
GAIN_CH3<3:0>
GAIN_CH4<3:0>
GAIN_CH5<3:0>
GAIN_CH6<3:0>
GAIN_CH7<3:0>
GAIN_CH8<3:0>
Programmable gain channel 1.
Programmable gain channel 2.
Programmable gain channel 3.
Programmable gain channel 4.
Programmable gain channel 5.
Programmable gain channel 6.
Programmable gain channel 7.
Programmable gain channel 8.
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
X
X
X
X
X
X
X
X
2A
2B
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.
(2) X = Register bit referenced by the corresponding name and description (default is 0).
(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.
(4) Multiple functions in a register should be programmed in a single write operation.
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Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (continued)
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
DESCRIPTION
DEFAULT
Single-
ended clock
1
1
X
DIFF_CLK
Differential clock mode.
Enables the duty-cycle correction
circuit.
X
EN_DCC
Disabled
External
reference
drives REFT
and REFB
42
Drives the external reference
mode through the VCM pin.
1
1
X
EXT_REF_VCM
PHASE_DDR<1:0>
Controls the phase of LCLK
output relative to data.
X
X
90 degrees
0
X
0
PAT_DESKEW
PAT_SYNC
Enables deskew pattern mode.
Enables sync pattern mode.
Inactive
Inactive
45
46
X
Binary two's complement format
for ADC output.
Straight
offset binary
1
1
1
1
X
BTC_MODE
MSB_FIRST
Serialized ADC output comes
out MSB-first.
LSB-first
output
X
Enables SDR output mode
(LCLK becomes a 12x input
clock).
DDR output
mode
1
1
1
1
X
1
EN_SDR
Controls whether the LCLK rising Rising edge
or falling edge comes in the
middle of the data window when
operating in SDR output mode.
of LCLK in
middle of
data window
X
FALL_SDR
SUMMARY OF FEATURES
POWER IMPACT (relative to default)
AT fS = 65MSPS
FEATURES
DEFAULT
SELECTION
ANALOG FEATURES
Internal or external reference
(driven on the REFT and REFB pins)
Internal reference mode takes approximately 23mW more power on
AVDD
N/A
Pin
External reference driven on the VCM pin
Duty cycle correction circuit
Off
Off
Register 42
Register 42
Approximately 9mW less power on AVDD
Approximately 7mW more power on AVDD
With zero input to the ADC, low-frequency noise suppression causes
digital switching at fS/2, thereby increasing LVDD power by
approximately 7mW/channel
Low-frequency noise suppression
Off
Register 14
Register 42
Differential clock mode takes approximately 7mW more power on
AVDD
Single-ended or differential clock
Power-down mode
Single-ended
Off
Refer to the Power-Down Modes section in the Electrical
Characteristics table
Pin and register 0F
DIGITAL FEATURES
Programmable digital gain (0dB to 12dB)
Straight offset or BTC output
Swap polarity of analog input pins
LVDS OUTPUT PHYSICAL LAYER
LVDS internal termination
0dB
Straight offset
Off
Registers 2A and 2B No difference
Register 46
Register 24
No difference
No difference
Off
Register 12
Register 11
Approximately 7mW more power on AVDD
LVDS current programmability
LVDS OUTPUT TIMING
3.5mA
As per LVDS clock and data buffer current setting
LSB- or MSB-first output
LSB-first
DDR
Register 46
Register 46
Register 42
No difference
SDR mode takes approximately 2mW more power on LVDD
(at fS = 30MSPS)
DDR or SDR output
LCLK phase relative to data output
Refer to Figure 1
No difference
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DESCRIPTION OF SERIAL REGISTERS
SOFTWARE RESET
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
RST
00
X
Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears
to '0'.
POWER-DOWN MODES
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
X
X
X
X
X
X
X
PDN_CH<8:1>
PDN_PARTIAL
PDN_COMPLETE
PDN_PIN_CFG
X
0F
0
X
0
X
Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for
the ADC channel <N>.
In addition to channel-specific power-down, the ADS5287 also has two global power-down modes—partial
power-down mode and complete power-down mode. Partial power-down mode partially powers down the chip;
recovery from this mode is much quicker, provided that the clock has been running for at least 50µs before
exiting this mode. Complete power-down mode, on the other hand, completely powers down the chip, and
involves a much longer recovery time.
In addition to programming the device for either of these two power-down modes (through either the
PDN_PARTIAL or PDN_COMPLETE bits, respectively), the PD pin itself can be configured as either a partial
power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when the
PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when the PD pin
is high, the device enters partial power-down mode.
LVDS DRIVE PROGRAMMABILITY
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
X
X
ILVDS_LCLK<2:0>
ILVDS_FRAME<2:0>
ILVDS_DAT<2:0>
11
X
X
X
X
X
X
The LVDS drive strength of the bit clock (LCLKP or LCLKN) and the frame clock (ADCLKP or ADCLKN) can be
individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTN can also be
programmed to the same value.
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All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 3
shows an example of how the drive strength of the bit clock is programmed (the method is similar for the frame
clock and data drive strengths).
Table 3. Bit Clock Drive Strength(1)
ILVDS_LCLK<2>
ILVDS_LCLK<1>
ILVDS_LCLK<0>
LVDS DRIVE STRENGTH FOR LCLKP AND LCLKN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.5mA (default)
2.5mA
1.5mA
0.5mA
7.5mA
6.5mA
5.5mA
4.5mA
(1) Current settings lower than 1.5mA are not recommended.
LVDS INTERNAL TERMINATION PROGRAMMABILITY
ADDRESS
IN HEX
D15
D14
X
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
EN_LVDS_TERM
TERM_LCLK<2:0>
TERM_FRAME<2:0>
TERM_DAT<2:0>
1
X
X
X
12
1
X
X
X
1
X
X
X
The LVDS buffers have high-impedance current sources driving the outputs. When driving traces whose
characteristic impedance is not perfectly matched with the termination impedance on the receiver side, there may
be reflections back to the LVDS output pins of the ADS5287 that cause degraded signal integrity. By enabling an
internal termination (between the positive and negative outputs) for the LVDS buffers, the signal integrity can be
significantly improved in such scenarios. To set the internal termination mode, the EN_LVDS_TERM bit should
be set to '1'. Once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers
can be independently programmed using sets of three bits. Table 4 shows an example of how the internal
termination of the LVDS buffer driving the bit clock is programmed (the method is similar for the frame clock and
data drive strengths). These termination values are only typical values and can vary by up to ±20% across
temperature and from device to device.
Table 4. Bit Clock Drive Strengths
INTERNAL TERMINATION BETWEEN
TERM_LCLK<2>
TERM_LCLK<1>
TERM_LCLK<0>
LCLKP AND LCLKN IN Ω
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
260
150
94
125
80
66
55
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LOW-FREQUENCY NOISE SUPPRESSION MODE
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
LFNS_CH<8:1>
14
X
X
X
X
X
X
X
X
The low-frequency noise suppression mode is specifically useful in applications where good noise performance is
desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of
the ADS5287 to approximately fS/2, thereby moving the noise floor around dc to a much lower value.
LFNS_CH<8:1> enables this mode individually for each channel.
ANALOG INPUT INVERT
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
24
X
X
X
X
X
X
X
X
INVERT_CH<8:1>
Normally, the INP pin represents the positive analog input pin, and INN represents the complementary negative
input. Setting the bits marked INVERT_CH<8:1> (individual control for each channel) causes the inputs to be
swapped. INN now represents the positive input, and INP the negative input.
LVDS TEST PATTERNS
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
X
D5
0
D4
0
D3
D2
D1
D0
NAME
EN_RAMP
0
X
0
DUALCUSTOM_PAT
SINGLE_CUSTOM_PAT
BITS_CUSTOM1<9:8>
BITS_CUSTOM2<9:8>
BITS_CUSTOM1<7:0>
BITS_CUSTOM2<7:0>
PAT_DESKEW
25
0
0
X
X
X
X
X
26
27
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
0
45
X
PAT_SYNC
The ADS5287 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal
ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern.
The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the
full-scale code, it returns back to zero code and ramps again.
The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and
programming the desired code in BITS_CUSTOM1<9:0>. In this mode, BITS_CUSTOM<9:0> take the place of
the 10-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as
normal ADC data are.
The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT
to '1'. The two codes are represented by the contents of BITS_CUSTOM1<9:0> and BITS_CUSTOM2<9:0>.
In addition to custom patterns, the device may also be made to output two preset patterns:
1. Deskew patten: Set using PAT_DESKEW, this mode causes the 12 serial bits to come out as
010101010101 (the rightmost bit representing the first bit in the LSB-first mode)
2. Sync pattern: Set using PAT_SYNC, this mode causes the 12 serial bits to come out as 111111000000 (the
rightmost bit representing the first bit in the LSB-first mode)
Note that only one of the above patterns should be active at any given instant.
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PROGRAMMABLE GAIN
ADDRESS
IN HEX
D15
D14
D13
D12
D11
X
D10
X
D9
X
D8
X
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
X
X
X
GAIN_CH1<3:0>
GAIN_CH2<3:0>
GAIN_CH3<3:0>
GAIN_CH4<3:0>
GAIN_CH5<3:0>
GAIN_CH6<3:0>
GAIN_CH7<3:0>
GAIN_CH8<3:0>
X
X
X
X
2A
X
X
X
X
X
X
X
X
X
X
X
X
2B
X
X
X
X
X
X
X
X
In applications where the full-scale swing of the analog input signal is much less than the 2VPP range supported
by the ADS5287, a programmable gain can be set to achieve the full-scale output code even with a lower analog
input swing. The programmable gain not only fills the output code range of the ADC, but also enhances the SNR
of the device by utilizing quantization information from some extra internal bits. The programmable gain for each
channel can be individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain
setting is coded in binary from 0dB to 12dB, as shown in Table 5.
Table 5. Gain Setting for Channel 1
GAIN_CH1<3>
GAIN_CH1<2>
GAIN_CH1<1>
GAIN_CH1<0>
CHANNEL 1 GAIN SETTING
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
Do not use
Do not use
Do not use
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CLOCK, REFERENCE, AND DATA OUTPUT MODES
ADDRESS
IN HEX
D15
1
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
X
D2
D1
D0
NAME
X
DIFF_CLK
EN_DCC
1
X
42
1
EXT_REF_VCM
PHASE_DDR<1:0>
BTC_MODE
MSB_FIRST
EN_SDR
1
X
X
1
1
1
1
1
X
1
X
46
1
X
1
1
X
FALL_SDR
INPUT CLOCK
The ADS5287 is configured by default to operate with a single-ended input clock—CLKP is driven by a CMOS
clock and CLKN is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a
differential input clock on CLKP and CLKN. Operating with a low-jitter differential clock usually gives better SNR
performance, especially at input frequencies greater than 30MHz.
In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable
an internal duty cycle correction circuit. This enabling is done by setting the EN_DCC bit to '1'.
EXTERNAL REFERENCE
The ADS5287 can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,
the REFT and REFB pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have
enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The
advantage of using the external reference mode is that multiple ADS5287 units can be made to operate with the
same external reference, thereby improving parameters such as gain matching across devices. However, in
applications that do not have an available high drive, differential external reference, the ADS5287 can still be
driven with a single external reference voltage on the VCM pin. When EXT_REF_VCM is set as '1' (and the
INT/EXT pin is set to '0'), the VCM pin is configured as an input pin, and the voltages on REFT and REFB are
generated as shown in Equation 1 and Equation 2.
VCM
VREFT = 1.5V +
1.5V
(1)
(2)
VCM
VREFB = 1.5V -
1.5V
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BIT CLOCK PROGRAMMABILITY
The output interface of the ADS5287 is normally a DDR interface, with the LCLK rising edge and falling edge
transitions in the middle of alternate data windows. Figure 1 shows this default phase.
ADCLKP
LCLKP
OUTP
Figure 1. Default Phase of LCLK
The phase of LCLK can be programmed relative to the output frame clock and data using bits
PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 2.
PHASE_DDR<1:0> = '00'
PHASE_DDR<1:0> = '10'
ADCLKP
ADCLKP
LCLKP
OUTP
LCLKP
OUTP
PHASE_DDR<1:0> = '01'
PHASE_DDR<1:0> = '11'
ADCLKP
ADCLKP
LCLKP
OUTP
LCLKP
OUTP
Figure 2. Phase Programmability Modes for LCLK
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In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR
mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12x times the input clock, or
twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two
manners shown in Figure 3. As shown in Figure 3, only the LCLK rising (or falling) edge is used to capture the
output data in SDR mode.
EN_SDR = '1', FALL_SDR = '0'
ADCLKP
LCLKP
OUTP
EN_SDR = '1', FALL_SDR = '1'
ADCLKP
LCLKP
OUTP
Figure 3. SDR Interface Modes
The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.
DATA OUTPUT FORMAT MODES
The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the
MSB, and the output becomes binary two's complement mode.
Also by default, the first two bits of the frame (following the rising edge of ADCLKP) are zeroes, followed by the
LSB of the ADC output. Programming the MSB_FIRST mode inverts the bit order in the word. Thus, in the
MSB_FIRST mode, the MSB is output as the first bit following the ADCLKP rising edge. The two zeroes come
after the LSB at the end of the word.
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APPLICATION INFORMATION
The ADC output goes to a serializer that operates
from a 12x clock generated by the PLL. The 12 data
bits from each channel are serialized and sent LSB
first. In addition to serializing the data, the serializer
also generates a 1x clock and a 6x clock. These
clocks are generated in the same way the serialized
data are generated, so these clocks maintain perfect
synchronization with the data. The data and clock
outputs of the serializer are buffered externally using
LVDS buffers. Using LVDS buffers to transmit data
THEORY OF OPERATION
The ADS5287 is an 8-channel, high-speed, CMOS
ADC. Two zeroes are appended on the LSB side to
the 10 bits given out by each channel. The resulting
12 bits are serialized and sent out on a single pair of
pins in LVDS format. All eight channels of the
ADS5287 operate from a single clock (ADCLK). The
sampling clocks for each of the eight channels are
generated from the input clock using a carefully
matched clock buffer tree. The 12x clock required for
the serializer is generated internally from ADCLK
using a phase-locked loop (PLL). A 6x and a 1x clock
are also output in LVDS format, along with the data,
to enable easy data capture. The ADS5287 operates
from internally-generated reference voltages that are
trimmed to achieve a high level of accuracy. Trimmed
references improve the gain matching across
devices, and provide the option to operate the
devices without having to externally drive and route
reference lines. The nominal values of REFT and
REFB are 2.5V and 0.5V, respectively. The
references are internally scaled down differentially by
a factor of 2. This scaling results in a differential input
of –1V to correspond to the zero code of the ADC,
and a differential input of +1V to correspond to the
full-scale code (1023 LSB). VCM (the common-mode
voltage of REFT and REFB) is also made available
externally through a pin, and is nominally 1.5V.
externally has multiple advantages, such as
a
reduced number of output pins (saving routing space
on the board), reduced power consumption, and
reduced effects of digital noise coupling to the analog
circuit inside the ADS5287.
The ADS5287 operates from two sets of supplies and
grounds. The analog supply and ground set is
identified as AVDD and AVSS, while the digital set is
identified by LVDD and LVSS.
ANALOG INPUT
The analog input consists of a switched-capacitor
based, differential sample-and-hold architecture. This
differential topology results in very good ac
performance, even for high input frequencies at high
sampling rates. The INN and INP pins must be
externally biased around a common-mode voltage of
1.5V, available on VCM. For a full-scale differential
input, each input pin (INN and INP) must swing
symmetrically between VCM + 0.5V and VCM – 0.5V,
resulting in a 2VPP differential input swing. The
maximum input peak-to-peak differential swing is
determined to be the difference between the internal
reference voltages REFT (2.5V nominal) and REFB
(0.5V nominal). Figure 4 illustrates the model of the
input driving circuit.
The ADC employs a pipelined converter architecture
that consists of a combination of multi-bit and
single-bit internal stages. Each stage feeds its data
into the digital error correction logic, ensuring
excellent differential linearity and no missing codes at
the 10-bit level.
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5nH to 9nH (TQFP-80)
IN
OUT
2nH to 3nH (QFN-64)
INP
1.5pF to
2.5pF
1.5pF
5W
15W
15W
to 2.4pF
to 10W
to 25W
to 30W
1W
IN
OUT
IN
OUT
1000W
to 1440W
OUT
OUTP
OUTN
0.2pF
to 0.3pF
IN
1000W
to 1440W
16W to 32W
1.5pF
5W
15W
15W
to 2.4pF
to 10W
to 25W
to 30W
IN
OUT
IN
OUT
5nH to 9nH (TQFP-80)
2nH to 3nH (QFN-64)
INN
1.5pF to
2.5pF
Switches that are ON
in SAMPLE phase.
IN
OUT
1W
Switches that are ON
in HOLD phase.
Figure 4. Analog Input Circuit Model
ac-coupling by increasing VCM by roughly 75mV.
When operating above 50MSPS, it is recommended
that additional parallel resistors be added externally
to restore the input common-mode to at least 1.4V, if
the inputs are to be ac-coupled.
Input Common-Mode Current
The input stage of all eight ADCs together sinks a
common-mode current on the order of 2mA at
50MSPS. Equation 3 describes the dependency of
the common-mode current and the sampling
frequency.
ADS5287
(2mA) ´ fS
INP
1.2kW
50MSPS
(3)
Input
Circuitry
If the driving stage is dc-coupled to the inputs, then
1.2kW
Equation can be used to determine its
3
INN
common-mode drive capability and impedance. The
inputs can also be ac-coupled to the INN and INP
pins. In that case, the input common-mode is set by
two internal 1.2kΩ resistors connecting the input pins
to VCM. This architecture is shown in Figure 5.
Internal
VCM
Voltage
Reference
CM Buffer
When the inputs are ac-coupled, there is a drop in
the voltages at INP and INN relative to VCM. This can
be computed from Equation 3. At 50MSPS, for
example, the drop at each of the 16 input pins is
150mV, which is not optimal for ADC operation. The
initialization register 5 described in the Initialization
Registers table can be used to partially reduce the
effect of this input common-mode drop during
Dashed area denotes one of eight channels.
Figure 5. Common-Mode Biasing of Input Pins
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Driving Circuit
At high input frequencies, the mismatch in the
transformer parasitic capacitance (between the
windings) results in degraded even-order harmonic
For optimum performance, the analog inputs must be
driven differentially. This approach improves the
common-mode noise immunity and even-order
harmonic rejection. Input configurations using RF
transformers suitable for low and high input
frequencies are shown in Figure 6 and Figure 7,
respectively. The single-ended signal is fed to the
primary winding of the RF transformer. The
transformer is terminated by 50Ω resistor on the
secondary side. Placing the termination on the
secondary side helps to shield the kicks caused by
the input sampling capacitors from the RF
transformer leakage inductances. The termination is
accomplished by two 25Ω resistors, connected in
series, with the center point connected to the 1.5V
common-mode. The 4.7Ω resistor in series with each
input pin is required to damp the ringing caused by
the device package parasitics.
performance.
Connecting
two
identical
RF
transformers back-to-back helps to minimize this
mismatch, and good performance is obtained for
high-frequency
input
signals.
An
additional
termination resistor pair is required between the two
transformers, as shown in Figure 7. The center point
of this termination is connected to ground to improve
the balance between the positive and negative sides.
The values of the terminations between the
transformers and on the secondary side must be
chosen to achieve an overall 50Ω (in the case of 50Ω
source impedance).
4.7W
INP
0.1mF
1:1
25W
0.1mF
25W
4.7W
INN
VCM
Figure 6. Drive Circuit at Low Input Frequencies
1:2
2:1
INP
0.1mF
200W
200W
50W
50W
0.1mF
INN
VCM
Figure 7. Drive Circuit at High Input Frequencies
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CLOCK INPUT
The eight channels on the device operate from a
single ADCLK input. To ensure that the aperture
delay and jitter are the same for all channels, a clock
tree network is used to generate individual sampling
clocks to each channel. The clock paths for all the
channels are matched from the source point to the
sampling circuit. This architecture ensures that the
performance and timing for all channels are identical.
The use of the clock tree for matching introduces an
aperture delay that is defined as the delay between
the rising edge of ADCLK and the actual instant of
sampling. The aperture delays for all the channels
are matched to the best possible extent. A mismatch
of ±20ps (±3σ) could exist between the aperture
instants of the eight ADCs within the same chip.
However, the aperture delays of ADCs across two
different chips can be several hundred picoseconds
apart.
VCM
VCM
5kW
5kW
CLKP
CLKN
Figure 9. Internal Clock Buffer
0.1mF
CLKP
The ADS5287 can be made to operate either in
CMOS single-ended clock mode (default is
DIFF_CLK = 0) or differential clock mode (SINE,
LVPECL, or LVDS). When operating in the
single-ended clock mode, CLKN must be forced to
0VDC, and the single-ended CMOS applied on the
CLKP pin. This operation is shown in Figure 8.
Differential Sine-Wave,
PECL, or LVDS Clock Input
0.1mF
CLKN
Figure 10. Differential Clock Driving Circuit
(DIFF_CLK = 1)
CMOS Single-Ended
CLKP
Clock
0.1mF
CMOS Clock Input
CLKP
CLKN
0V
CLKN
0.1mF
Figure 8. Single-Ended Clock Driving Circuit
(DIFF_CLK = 0)
When configured to operate in the differential clock
mode (register bit DIFF_CLK = 1) the ADS5287 clock
inputs can be driven differentially (SINE, LVPECL, or
LVDS) with little or no difference in performance
between them, or with a single-ended (LVCMOS).
The common-mode voltage of the clock inputs is set
to VCM using internal 5kΩ resistors, as shown in
Figure 11. Single-Ended Clock Driving Circuit
When DIFF_CLK = 1
For best performance, the clock inputs must be
driven differentially, reducing susceptibility to
common-mode noise. For high input frequency
sampling, it is recommended to use a clock source
with very low jitter. Bandpass filtering of the clock
source can help reduce the effect of jitter. If the duty
cycle deviates from 50% by more than 2% or 3%, it is
recommended to enable the DCC through register bit
EN_DCC.
Figure
9.
This
method
allows
using
transformer-coupled drive circuits for a sine wave
clock or ac-coupling for LVPECL and LVDS clock
sources, as shown in Figure 10. When operating in
the differential clock mode, the single-ended CMOS
clock can be ac-coupled to the CLKP input, with CLKN
(pin 11) connected to ground with a 0.1µF capacitor,
as shown in Figure 11.
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INPUT OVER-VOLTAGE RECOVERY
ADS5287
The differential peak-to-peak full-scale range
supported by the ADS5287 is nominally 2.0V. The
ADS5287 is specially designed to handle an
over-voltage condition where the differential
peak-to-peak voltage can be up to twice the ADC
full-scale range. If the input common-mode is not
considerably off from VCM during overload (less than
300mV around the nominal value of 1.5V), recovery
from an over-voltage pulse input of twice the
amplitude of a full-scale pulse is expected to be
within one clock cycle when the input switches from
overload to zero signal.
ISET
REFB
REFT
56.2kW
0W to
0W to
2W
2W
0.1mF
2.2mF
2.2mF
0.1mF
Figure 12. Suggested Decoupling on the
Reference Pins
REFERENCE CIRCUIT
The digital beam-forming algorithm in an ultrasound
system relies on gain matching across all receiver
channels. A typical system would have about 12 octal
ADCs on the board. In such a case, it is critical to
ensure that the gain is matched, essentially requiring
the reference voltages seen by all the ADCs to be the
same. Matching references within the eight channels
of a chip is done by using a single internal reference
voltage buffer. Trimming the reference voltages on
each chip during production ensures that the
reference voltages are well-matched across different
chips.
The device also supports the use of external
reference voltages. There are two methods to force
the references externally. The first method involves
pulling INT/EXT low and forcing externally REFT and
REFB to 2.5V and 0.5V nominally, respectively. In
this mode, the internal reference buffer goes to a
3-state output. The external reference driving circuit
should be designed to provide the required switching
current for the eight ADCs inside the chip. It should
be noted that in this mode, VCM and ISET continue to
be generated from the internal bandgap voltage, as in
the internal reference mode. It is therefore important
to ensure that the common-mode voltage of the
externally-forced reference voltages matches to
All bias currents required for the internal operation of
the device are set using an external resistor to
ground at the ISET pin. Using a 56.2kΩ resistor on ISET
generates an internal reference current of 20µA. This
current is mirrored internally to generate the bias
current for the internal blocks. Using a larger external
resistor at ISET reduces the reference bias current and
thereby scales down the device operating power.
However, it is recommended that the external resistor
be within 10% of the specified value of 56.2kΩ so
that the internal bias margins for the various blocks
are proper.
within 50mV of VCM
.
The second method of forcing the reference voltages
externally can be accessed by pulling INT/EXT low,
and programming the serial interface to drive the
external reference mode through the VCM pin (register
bit called EXT_REF_VCM). In this mode, VCM
becomes configured as an input pin that can be
driven from external circuitry. The internal reference
buffers driving REFT and REFB are active in this
mode. Forcing 1.5V on the VCM pin in the mode
results in REFT and REFB coming to 2.5V and 0.5V,
respectively. In general, the voltages on REFT and
REFB in this mode are given by Equation 4 and
Equation 5, respectively:
Buffering the internal bandgap voltage also generates
the common-mode voltage VCM, which is set to the
midlevel of REFT and REFB, and is accessible on pin
53. It is meant as a reference voltage to derive the
input common-mode if the input is directly coupled. It
can also be used to derive the reference
common-mode voltage in the external reference
mode. The suggested decoupling for the reference
pins is shown in Figure 12.
VCM
VREFT = 1.5V +
1.5V
(4)
VCM
VREFB = 1.5V -
1.5V
(5)
Table 6 describes the state of the reference voltage
internal buffers during various combinations of the
PD, INT/EXT, and EXT_REF_VCM register bits.
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Table 6. State of Reference Voltages for Various Combinations of PD and INT/EXT
REGISTER BIT
PD
INTERNAL BUFFER STATE
0
0
0
1
0
1
0
0
1
0
1
1
1
INT/EXT
1
1
0
1
1
EXT_REF_VCM
REFT buffer
REFB buffer
VCM pin
0
0
0
0
1
1
3-state
3-state
1.5V
2.5V
0.5V
1.5V
3-state
3-state
1.5V
2.5V(1)
0.5V(1)
1.5V
1.5V + VCM/1.5V
1.5V – VCM/1.5V
Force
Do not use
Do not use
Do not use
2.5V(1)
0.5V(1)
Force
Do not use
Do not use
Do not use
(1) Weakly forced with reduced strength.
Smaller effective inductance of the supply and ground
pins leads to better noise suppression. For this
reason, multiple pins are used to drive each supply
and ground. It is also critical to ensure that the
impedances of the supply and ground lines on the
board are kept to the minimum possible values. Use
of ground planes in the printed circuit board (PCB) as
well as large decoupling capacitors between the
supply and ground lines are necessary to obtain the
best possible SNR performance from the device.
NOISE COUPLING ISSUES
High-speed mixed signals are sensitive to various
types of noise coupling. One primary source of noise
is the switching noise from the serializer and the
output buffers. Maximum care is taken to isolate
these noise sources from the sensitive analog blocks.
As a starting point, the analog and digital domains of
the device are clearly demarcated. AVDD and AVSS
are used to denote the supplies for the analog
sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there
is minimal interaction between the supply sets within
the device. The extent of noise coupled and
transmitted from the digital to the analog sections
depends on:
It is recommended that the isolation be maintained
onboard by using separate supplies to drive AVDD
and LVDD, as well as separate ground planes for
AVSS and LVSS. The use of LVDS buffers reduces
the injected noise considerably, compared to CMOS
buffers. The current in the LVDS buffer is
independent of the direction of switching. Also, the
low output swing as well as the differential nature of
the LVDS buffer results in low-noise coupling.
1. The effective inductances of each of the supply
and ground sets.
2. The isolation between the digital and analog
supply and ground sets.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
QFN
QFN
Drawing
ADS5287IRGCR
ADS5287IRGCT
PREVIEW
PREVIEW
RGC
64
64
2000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
RGC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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