ADS5444-EP_13 [TI]
13-BIT 250-MSPS ANALOG-TO-DIGITAL CONVERTER;
| 型号： | ADS5444-EP_13 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 13-BIT 250-MSPS ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总29页 (文件大小：760K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
13-BIT 250-MSPS ANALOG-TO-DIGITAL CONVERTER
FEATURES
•
•
TQFP-80 PowerPAD™ Package
•
Controlled Baseline
Pin Compatible With the ADS5440
– One Assembly
•
Military Temperature Range = –55°C to 125°C
(1)
– One Test Site
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
– One Fabrication Site
•
•
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Enhanced Product-Change Notification
Qualification Pedigree(1)
APPLICATIONS
•
•
•
•
•
Test and Measurement
Software-Defined Radio
Multichannel Base Station Receivers
Base Station Tx Digital Predistortion
Communications Instrumentation
13-Bit Resolution
250-MSPS Sample Rate
SNR = 69 dBc at 100-MHz IF and 250 MSPS
SFDR = 76 dBc at 100-MHz IF and 250 MSPS
SNR = 67.7 dBc at 230-MHz IF and 250 MSPS
SFDR = 77 dBc at 230-MHz IF and 250 MSPS
2.2-VPP Differential Input Voltage
Fully Buffered Analog Inputs
RELATED PRODUCTS
•
•
•
ADS5424 - 14-Bit, 105 MSPS ADC
ADS5423 - 14-Bit, 80 MSPS ADC
ADS5440 - 13-Bit, 210 MSPS ADC
5-V Analog Supply Voltage
LVDS Compatible Outputs
Total Power Dissipation: 2 W
Offset Binary Output Format
DESCRIPTION
The ADS5444 is a 13-bit 250-MSPS analog-to-digital converter (ADC) that operates from a 5-V supply, while
providing LVDS-compatible digital outputs from a 3.3-V supply. The ADS5444 input buffer isolates the internal
switching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generator
is also provided to further simplify the system design. The ADS5444 has outstanding low noise and linearity over
input frequency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
AV
DD
DV
DD
AIN
AIN
+
+
Σ
Σ
A1
TH1
TH2
A2
TH3
A3
ADC3
−
−
ADC1
DAC1
ADC2
DAC2
VREF
Reference
5
5
5
Digital Error Correction
CLK
CLK
Timing
OVR
OVR
DRY
DRY
D[12:0]
GND
B0061-01
The ADS5444 is available in an 80-pin TQFP PowerPAD™ package. The ADS5444 is built on a state-of-the-art
Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full military temperature
range (–55°C to 125°C).
2
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION(1)
Product
Package-
Lead
Package
Designator
Specified
Temperature
Range
Package
Marking
Ordering
Number
Transport
Media,
Quantity
(1)
HTQFP-80(2)
PowerPAD
ADS5444
PFP
–55°C to 125°C
ADS5444M-EP
ADS5444MPFPEP
Tray, 96
(1) For the most current product and ordering information, see the Package Option Addendum located at the end of this document, or see
the TI website at www.ti.com.
(2) Thermal pad size: 7,5 mm x 7,5 mm (typ)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE / UNIT
AVDD to GND
6 V
5 V
Supply voltage
DRVDD to GND
Analog input to GND
Clock input to GND
CLK to CLK
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
±2.5 V
Digital data output to GND
–0.3 V to DRVDD + 0.3 V
–55°C to 125°C
150°C
Operating temperature range
Maximum junction temperature
Storage temperature range
ESD Human Body Model (HBM)
–65°C to 150°C
2.5 kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
TYP
21.7
15.4
50
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
Soldered slug, no airflow
Soldered slug, 250-LFPM airflow
Unsoldered slug, no airflow
Unsoldered slug, 250-LFPM airflow
Bottom of package (heatslug)
θJA
43.4
2.99
θJC
(1) Using 36 thermal vias (6 x 6 array). See the Application Section.
3
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
1000
100
10
Wirebond Voiding Fail Mode
Electromigration Fail Mode
1
0.1
120
130
140
150
160
170
180
Continuous TJ − 5C
Figure 1. ADS5444MPFPEP Operating Life Derating Chart
4
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
4.75
3
5
5.25
3.6
V
V
DRVDD
Output driver supply voltage
3.3
ANALOG INPUT
Differential input range
Input common mode
CLOCK INPUT
1/tC ADCLK input sample rate (sine wave)
2.2
2.4
VPP
V
VCM
10
250 MSPS
VPP
Clock amplitude, differential sine wave
Clock duty cycle
3
50%
TA
Open free-air temperature
–55
125
°C
ELECTRICAL CHARACTERISTICS
Min, Typ, and Max values at TA = 25°C, full temperature range is TMIN = –55°C to TMAX = 125°C, sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise
noted)
PARAMETER
Resolution
ANALOG INPUTS
Differential input range
TEST CONDITIONS
MIN
TYP
MAX UNIT
13
Bits
2.2
1
Vpp
kΩ
Differential input resistance (DC)
Differential input capacitance
1.5
800
pF
Analog input bandwidth
MHz
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
2.4
V
DYNAMIC ACCURACY
No missing codes
DNL
Assured
±0.4
fIN = 10 MHz
fIN = 10 MHz
TA = 25°C
–1
–1
1
Differential linearity error
LSB
2
Full temp range
TA = 25°C
±0.4
INL
–2.2
–4.3
–11
±0.9
2.2
Integral linearity error
LSB
4.3
Full temp range
±2.7
Offset error
11
5
mV
Offset temperature coefficient
Gain error
0.0005
mV/°C
%FS
–5
Gain temperature coefficient
PSRR
–0.02
1
∆%/°C
mV/V
fIN = 100 MHz
POWER SUPPLY
IAVDD
Analog supply current
340
80
2
430
100
mA
mA
W
VIN = full scale, fIN = 100 MHz, FS = 250
MSPS
IDRVDD Output buffer supply current
Power dissipation
2.37
5
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
ELECTRICAL CHARACTERISTICS (continued)
Min, Typ, and Max values at TA = 25°C, full temperature range is TMIN = –55°C to TMAX = 125°C, sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
fIN = 70 MHz
69.3
69
69
69
68.3
67.7
67
66
85
77
77
77
74
77
70
64
87
77
80
74
78
70
64
86
82
79
80
91
80
69
90
95
82
80
83
86
85
fIN = 100 MHz
TA = 25°C
67
Full temp range
64.25
SNR
Signal-to-noise ratio
dBc
fIN = 170 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
fIN = 10 MHz
fIN = 70 MHz
TA = 25°C
70
64
fIN = 100 MHz
Full temp range
SFDR
Spurious free dynamic range
dBc
fIN = 170 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
HD2
Second harmonic
dBc
dBc
dBc
HD3
Third harmonic
Worst other harmonic/spur (other than
HD2 and HD3)
6
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
ELECTRICAL CHARACTERISTICS (continued)
Min, Typ, and Max values at TA = 25°C, full temperature range is TMIN = –55°C to TMAX = 125°C, sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
69
MAX UNIT
fIN = 10 MHz
fIN = 70 MHz
68
fIN = 100 MHz
67.6
66.5
67
SINAD
fIN = 170 MHz
dBc
fIN = 230 MHz
fIN = 300 MHz
65
fIN = 400 MHz
61
ENOB
Effective number of bits
RMS idle channel noise
fIN = 10 MHz
11.2
0.4
Bits
Inputs tied to common-mode
LSB
DIGITAL CHARACTERISTICS – LVDS DIGITAL OUTPUTS
Differential output voltage
0.247
1.125
0.452
1.25 1.375
V
V
Output offset voltage
7
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TIMING CHARACTERISTICS
t
A
N+3
N
AIN
N+1
N+2
N+4
t
t
t
CLKL
CLK
CLKH
CLK, CLK
N + 1
N + 2
N + 3
N + 4
N
t
t
t
h_c
C_DR
su_c
D[12:0],
OVR, OVR
N−3
N−2
N−1
t
N
t
f
t
t
r
h_DR
su_DR
DRY, DRY
t
DR
T0073-01
Figure 2. Timing Diagram
TIMING CHARACTERISTICS
Min, Typ, Max over full temperature range, 50% clock duty cycle, sampling rate = 250 MSPS, AVDD = 5 V, DRVDD = 3.3 V
PARAMETER
Aperture delay
TEST CONDITIONS
MIN
TYP
500
200
4
MAX UNIT
ps
tA
tJ
Clock slope independent aperture uncertainty (jitter)
Latency
fs RMS
cycles
Clock Input
tCLK
Clock period
4
2
2
ns
ns
ns
tCLKH
Clock pulse width high
Clock pulse width low
tCLKL
Clock to DataReady (DRY)
tDR
Clock rising to DataReady falling
Clock rising to DataReady rising
1.1
3.1
ns
(1)
tC_DR
Clock duty cycle = 50%
2.7
3.5
ns
Clock to DATA, OVR(2)
tr
Data rise time (20% to 80%)
0.6
0.6
3.1
0.2
ns
ns
ns
ns
tf
Data fall time(80% to 20%)
tsu_c
th_c
Data valid to clock (setup time)
Clock to invalid Data (hold time)
DataReady (DRY)/DATA, OVR(2)
tsu(DR)
th(DR)
Data valid to DRY
DRY to invalid Data
1.7
0.9
2
ns
ns
1.3
(1) tC_DR = tDR + tCLKH for clock duty cycles other than 50%
(2) Data is updated with clock falling edge or DRY rising edge.
8
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
DEVICE INFORMATION
PFP PACKAGE
(TOP VIEW)
D4
D4
DVDD
GND
AVDD
NC
D3
D3
D2
NC
D2
D1
VREF
GND
AVDD
GND
CLK
D1
GND
DVDD
D0
GND
CLK
D0
GND
AVDD
AVDD
GND
AIN
NC
NC
NC
NC
NC
NC
OVR
OVR
AIN
GND
AVDD
GND
P0027-01
9
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
AVDD
DVDD
GND
NO.
3, 8, 13, 14, 19, 21,
23, 25, 27, 31, 35, 37, Analog power supply
39
1, 51, 66
Output driver power supply
2, 7, 9, 12, 15, 18, 20,
22, 24, 26, 28, 30, 32, Ground
34, 36, 38, 40, 52, 65
VREF
CLK
CLK
AIN
6
Reference voltage
10
11
16
17
Differential input clock (positive). Conversion initiated on rising edge.
Differential input clock (negative)
Differential input signal (positive)
AIN
Differential input signal (negative)
Over range indicator LVDS output. A logic high signals an analog input in excess of the
full-scale range.
OVR, OVR
42, 41
D0, D0
50, 49
53–64
67–76
78, 77
80, 79
LVDS digital output pair, least-significant bit (LSB)
LVDS digital output pairs
D1–D6, D1–D6
D7–D11, D7–D11
D12, D12
LVDS digital output pairs
LVDS digital output pair, most-significant bit (MSB)
Data ready LVDS output pair
DRY, DRY
NC
4, 5, 29, 33, 43–48 No connect
DEFINITION OF SPECIFICATIONS
Analog BandwidthThe analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the
low frequency value.
Aperture DelayThe delay in time between the rising edge of the input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty CycleThe duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic
high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50% duty cycle.
Maximum Conversion RateThe maximum sampling rate at which certified operation is given. All parametric testing is
performed at this sampling rate unless otherwise noted.
Minimum Conversion RateThe minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL)An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart.
The DNL is the deviation of any single step from this ideal value, measured in units of LSB.
Integral Nonlinearity (INL)The INL is the deviation of the ADCs transfer function from a best fit line determined by a least
squares curve fit of that transfer function. The INL at each analog input value is the difference between the
actual transfer function and this best fit line, measured in units of LSB.
Gain Error
The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode.
Temperature DriftTemperature drift (with respect to gain error and offset error) specifies the change from the value at the
nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters
over the whole temperature range divided by TMIN – TMAX
.
Signal-to-Noise Ratio (SNR)SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding
the power at dc and the first five harmonics.
10
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
DEFINITION OF SPECIFICATIONS (continued)
P
P
S
N
SNR + 10log
10
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)SINAD is the ratio of the power of the fundamental (PS) to the power of all the
other spectral components including noise (PN) and distortion (PD), but excluding dc.
P
S
SINAD + 10log
10
P
) P
N
D
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Resolution BandwidthThe highest input frequency where the SNR (dB) is dropped by 3 dB for a full-scale input
amplitude.
Total Harmonic Distortion (THD)THD is the ratio of the power of the fundamental (PS) to the power of the first five
harmonics (PD).
P
S
THD + 10log
10
P
D
(3)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation DistortionIMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power
of the worst spectral component at either frequency 2f1– f2 or 2f2– f1). IMD3 is either given in units of dBc (dB
to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to full scale)
when the power of the fundamental is extrapolated to the converter’s full-scale range.
11
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS
Spectral Performance
(FFT For 10 MHz Input Signal)
Spectral Performance
(FFT For 100 MHz Input Signal)
0
−20
0
−20
SFDR = 86.8 dBc
SFDR = 76.1 dBc
SNR = 69 dBc
THD = 72.6 dBc
SINAD = 67.4 dBc
SNR = 68.7 dBc
THD = 82.3 dBc
SINAD = 68.5 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
G001
G002
Figure 3.
Figure 4.
Spectral Performance
(FFT For 170 MHz Input Signal)
Spectral Performance
(FFT For 230 MHz Input Signal)
0
−20
0
−20
SFDR = 77 dBc
SNR = 67.3 dBc
THD = 75.6 dBc
SINAD = 66.7 dBc
SFDR = 74.6 dBc
SNR = 68.4 dBc
THD = 72.5 dBc
SINAD = 67 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
G004
G003
Figure 5.
Figure 6.
12
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Spectral Performance
(FFT For 300 MHz Input Signal)
Spectral Performance
(FFT For 400 MHz Input Signal)
0
−20
0
−20
SFDR = 70.2 dBc
SFDR = 62.5 dBc
SNR = 67 dBc
THD = 69.5 dBc
SINAD = 65 dBc
SNR = 66.2 dBc
THD = 61.8 dBc
SINAD = 60.4 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
G005
G006
Figure 7.
Figure 8.
Two-Tone Intermodulation Distortion
(FFT For 51.5 MHz and 52.5 MHz Input Signals)
Two-Tone Intermodulation Distortion
(FFT For 51.5 MHz and 52.5 MHz Input Signals)
0
−20
0
−20
F
F
= 51.5 MHz, −7 dBFS
= 52.5 MHz, −7 dBFS
F
F
= 51.5 MHz, −16 dBFS
= 52.5 MHz, −16 dBFS
IN1
IN1
IN2
IN2
IMD3 = 100.6 dBFS
IMD3 = 99.6 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
G007
G008
Figure 9.
Figure 10.
13
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Two-Tone Intermodulation Distortion
(FFT For 151 MHz and 152 MHz Input Signals)
Two-Tone Intermodulation Distortion
(FFT For 151 MHz and 152 MHz Input Signals)
0
−20
0
−20
F
F
= 151 MHz, −7 dBFS
= 152 MHz, −7 dBFS
F
F
= 151 MHz, −16 dBFS
= 152 MHz, −16 dBFS
IN1
IN2
IN1
IN2
IMD3 = 89.4 dBFS
IMD3 = 92.5 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
G009
G010
Figure 11.
Figure 12.
Two-Tone Intermodulation Distortion
(FFT For 229 MHz and 230 MHz Input Signals)
Two-Tone Intermodulation Distortion
(FFT For 229 MHz and 230 MHz Input Signals)
0
−20
0
−20
F
F
= 229 MHz, −7 dBFS
= 230 MHz, −7 dBFS
F
F
= 229 MHz, −16 dBFS
= 230 MHz, −16 dBFS
IN1
IN2
IN1
IN2
IMD3 = 85.8 dBFS
IMD3 = 101.4 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
G011
G012
Figure 13.
Figure 14.
14
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Two-Tone Intermodulation Distortion
(FFT For 300 MHz and 301 MHz Input Signals)
Two-Tone Intermodulation Distortion
(FFT For 300 MHz and 301 MHz Input Signals)
0
−20
0
−20
F
F
= 300 MHz, −7 dBFS
= 301 MHz, −7 dBFS
F
F
= 300 MHz, −16 dBFS
= 301 MHz, −16 dBFS
IN1
IN2
IN1
IN2
IMD3 = 83.3 dBFS
IMD3 = 101.9 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency − MHz
G013
G014
Figure 15.
Figure 16.
Input Bandwidth
Differential Nonlinearity
1
0
0.4
0.2
f
f
= 250 MSPS
= 10 MHz
S
IN
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.0
−0.2
−0.4
f
A
= 250 MSPS
S
= −1 dBFS
IN
50 1050 2050 3050 4050 5050 6050 7050 8050
Code
1
10
100
1k
f
IN
− Input Frequency − MHz
G017
G018
Figure 17.
Figure 18.
15
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Integral Nonlinearity
Noise Histogram With Inputs Shorted
2.0
1.5
50
45
40
35
30
25
20
15
10
5
f
= 250 MSPS
S
1.0
0.5
0.0
−0.5
−1.0
−1.5
f
f
= 250 MSPS
= 10 MHz
S
IN
−2.0
0
0
1000 2000 3000 4000 5000 6000 7000 8000
Code
4109 4110 4111 4112 4113 4114 4115 4116
Code Number
G019
G020
Figure 19.
Figure 20.
AC Performance
vs
Input Amplitude
AC Performance
vs
Input Amplitude
120
100
80
120
100
80
SFDR (dBFS)
SFDR (dBFS)
SNR (dBFS)
SNR (dBFS)
60
60
SFDR (dBc)
SFDR (dBc)
40
40
20
20
SNR (dBc)
SNR (dBc)
0
0
−20
−40
−20
−40
f
f
= 250 MSPS
= 100 MHz
f
f
= 250 MSPS
= 230 MHz
S
S
IN
IN
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Input Amplitude − dBFS
Input Amplitude − dBFS
G021
G022
Figure 21.
Figure 22.
16
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Two-Tone Spurious Free Dynamic Range
Spurious Free Dynamic Range
vs
vs
Input Amplitude
Clock Duty Cycle
120
100
80
80.0
77.5
75.0
72.5
70.0
67.5
65.0
62.5
60.0
f
S
= 250 MSPS
SFDR (dBFS)
f
IN
= 230 MHz
60
SFDR (dBc)
40
f
IN
= 100 MHz
90 dBFS Line
20
0
f
f
= 250 MSPS
= 100 MHz
S
IN
−20
−110−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
0
20
40
60
80
100
Input Amplitude − dBFS
Duty Cycle − %
G023
G024
Figure 23.
Figure 24.
Spurious Free Dynamic Range
Signal-to-Noise Ratio
vs
vs
Clock Level
Clock Level
70
69
68
67
66
65
64
63
62
61
60
78
f
= 100 MHz
IN
76
74
72
70
68
66
64
62
60
f
= 230 MHz
IN
f
= 230 MHz
IN
f
= 100 MHz
IN
f
S
= 250 MSPS
f
= 250 MSPS
S
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Clock Amplitude − V
Clock Amplitude − V
P−P
P−P
G026
G025
Figure 25.
Figure 26.
17
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Performance
Spurious Free Dynamic Range
vs
AVDD Across Temperature
vs
Clock Common Mode Level
80
74
73
72
71
70
69
68
f
S
= 250 MSPS
T
A
= 65°C
75
70
65
60
55
50
SFDR
SNR
T = −40°C
A
T
A
= 25°C
T
A
= 0°C
T
A
= 85°C
f
f
= 250 MSPS
= 100 MHz
S
IN
0
1
2
3
4
5
4.65 4.75 4.85 4.95 5.05 5.15 5.25 5.35
Clock Common-Mode Voltage − V
AV − Supply Voltage − V
DD
G027
G028
Figure 27.
Figure 28.
Signal-to-Noise Ratio
vs
AVDD Across Temperature
Spurious Free Dynamic Range
vs
DRVDD Across Temperature
72.5
72.0
71.5
71.0
70.5
70.0
69.5
69.0
70.0
69.5
69.0
68.5
68.0
67.5
67.0
T = −40°C
f
= 250 MSPS
= 100 MHz
A
S
f
IN
T = 65°C
A
T = 25°C
A
T = −40°C
A
T = 0°C
A
T = 0°C
A
T = 25°C
A
T = 85°C
A
T = 65°C
A
f
f
= 250 MSPS
= 100 MHz
S
T = 85°C
A
IN
2.9
3.1
3.3
3.5
3.7
4.65 4.75 4.85 4.95 5.05 5.15 5.25 5.35
DRV − Supply Voltage − V
DD
AV − Supply Voltage − V
DD
G030
G029
Figure 29.
Figure 30.
18
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Signal-to-Noise Ratio
vs
DRVDD Across Temperature
69.0
f
f
= 250 MSPS
= 100 MHz
S
T
A
= 25°C
IN
T
A
= 65°C
68.9
68.8
68.7
68.6
68.5
68.4
T
A
= 85°C
T
= 0°C
A
T
A
= −40°C
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
DRV − Supply Voltage − V
DD
G031
Figure 31.
SNR
vs
Input Frequency and Sampling Frequency
300
250
200
69.5
69
150
100
50
68.5
68
67.5
67
66.5
66
65.5
50
100
150
200
250
300
350
400
fIN - Input Frequency - MHz
63
64
65
66
67
68
69
SNR - dBc
M0048-05
Figure 32.
19
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
SFDR
vs
Input Frequency and Sampling Frequency
300
68
65
71
68
68
74
71
74
250
200
150
100
50
80
86
83
77
77
80
68
77
80
83
71
74
89
83
86
83
77
89
86
80
68
89
71
74
300
50
100
150
200
250
350
400
fIN - Input Frequency - MHz
75
65
70
80
85
SFDR - dBc
M0048-06
Figure 33.
20
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
APPLICATION INFORMATION
Theory of Operation
The ADS5444 is a 13-bit, 250-MSPS, monolithic pipeline analog-to-digital converter (ADC). Its bipolar analog
core operates from a 5 V supply, while the output uses a 3.3-V supply to provide LVDS compatible outputs. The
conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series
of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process
results in a data latency of four clock cycles, after which the output data is available as a 13-bit parallel word,
coded in offset binary format.
Input Configuration
The analog input for the ADS5444 consists of an analog differential buffer followed by a bipolar T&H. The
analog buffer isolates the source driving the input of the ADC from any internal switching. The input common
mode is set internally through a 500-Ω resistor connected from 2.4 V to each of the inputs. This results in a
differential input impedance of 1 kΩ.
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings
symmetrically between 2.4 + 0.55 V and 2.4 – 0.55 V. This means that each input has a maximum signal swing
of 1.1 VPP for a total differential input signal swing of 2.2 VPP. The maximum swing is determined by the internal
reference voltage generator eliminating the need for any external circuitry for this purpose.
The ADS5444 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 34 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. If voltage gain is required, a step up transformer can be used. For voltage
gains that would require an impractical transformer turn ratio, a single-ended amplifier driving the transformer is
shown in Figure 35).
Z
50 W
R
50 W
0
0
AIN
1 : 1
R
50 W
ADS5444
AC Signal
Source
AIN
ADT1-1WT
Figure 34. Converting a Single-Ended Input to a Differential Signal Using RF Transformers
5 V
−5 V
R
100 Ω
S
0.1 µF
+
V
IN
R
R
1:1
IN
AIN
ADS5444
AIN
OPA695
−
R
100 Ω
T
C
IN
IN
1000 µF
R
1
400 Ω
A
V
= 8V/V
R
2
(18 dB)
57.5 Ω
Figure 35. Using the OPA695 With the ADS5444
21
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
Application Information (continued)
V
IN
From
50 Ω
Source
100 Ω
348 Ω
+5V
13-Bit
250 MSPS
78.9 Ω
49.9 Ω
49.9 Ω
0.22 µF
100 Ω
A
IN
18 pF
ADS5444
THS4509
CM
A
IN
V
REF
49.9 Ω
78.9 Ω
49.9 Ω
0.22 µF
0.22 µF
0.1 µF
0.1 µF
348 Ω
Figure 36. Using the THS4509 With the ADS5444
Besides the OPA695, TI offers a wide selection of single-ended operational amplifiers that can be selected
depending on the application. An RF gain block amplifier, such as the TI THS9001, can also be used with an RF
transformer for high input frequency applications. For applications requiring dc-coupling with the signal source, a
differential input/differential output amplifier like the THS4509 (see Figure 36) is a good solution, as it minimizes
board space and reduces the number of components.
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5444.
The 50-Ω resistors and 18-pF capacitor between the THS4509 outputs and ADS5444 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB).
Input termination is accomplished via the 78.9-Ω resistor and 0.22-µF capacitor to ground in conjunction with the
input impedance of the amplifier circuit. A 0.22-µF capacitor and 49.9-Ω resistor is inserted to ground across the
78.9-Ω resistor and 0.22-µF capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. See the THS4509 data
sheet for further component values to set proper 50-Ω termination for other common gains.
Since the ADS5444 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single
power supply input with VS+ = 5 V and VS– = 0 V (ground). This maintains maximum headroom on the internal
transistors of the THS4509.
Clock Inputs
The ADS5444 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low input frequency applications, where
jitter may not be a big concern, the use of single-ended clock (see Figure 37) could save some cost and board
space without any trade-off in performance. When driven on this configuration, it is best to connect CLK to
ground with a 0.01 µF capacitor, while CLK is ac-coupled with a 0.01-µF capacitor to the clock source, as shown
in Figure 37.
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
ADS5444
CLK
Figure 37. Single-Ended Clock
22
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
Application Information (continued)
0.1 µF
1:4
Clock
Source
CLK
ADS5444
CLK
MA3X71600LCT−ND
Figure 38. Differential Clock
For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) at
the system level. The first advantage is that it allows for common-mode noise rejection at the PCB level.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. See Clocking High Speed Data Converters (SLYT075) for more details.
Figure 38 shows this approach. The back-to-back Schottky diodes can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum ratings, even when using a differential clock.
100 nF
MC100EP16DT
Q
100 nF
100 nF
CLK
D
D
V
Q
ADS5444
CLK
BB
100 nF
499 W
499 W
50 Ω
50 Ω
100 nF
113 Ω
Figure 39. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, such as PECL. In this case, the slew rate of the edges will
most likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock.
This solution would minimize the effect of the slope dependent ADC jitter. Using logic gates to square a
sinusoidal clock may not produce the best results as logic gates may not have been optimized to act as
comparators, adding too much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5444 features good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty
cycle clock signal should be provided.
Digital Outputs
The ADC provides 13 data outputs (D12 to D0, with D12 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an over-range indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5444.
The ADS5444 digital outputs are LVDS compatible.
23
Submit Documentation Feedback
ADS5444-EP
www.ti.com
SGLS360–AUGUST 2006
Application Information (continued)
Power Supplies
The use of low noise power supplies with adequate decoupling is recommended. Linear supplies are the
preferred choice versus switched ones, which tend to generate more noise components that can be coupled to
the ADS5444.
The ADS5444 uses two power supplies. For the analog portion of the design, a 5-V AVDD is used, while for the
digital outputs supply (DRVDD) we recommend the use of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied together inside the package.
Layout Information
The evaluation board represents a good guideline of how to layout the board to obtain the maximum
performance out of the ADS5444. General design rules as the use of multilayer boards, single ground plane for
ADC ground connections and local decoupling ceramic chip capacitors should be applied. The input traces
should be isolated from any external source of interference or noise including the digital outputs, as well as the
clock traces. The clock signal traces should also be isolated from other signals, especially in applications where
low jitter is required as high IF sampling.
Besides performance oriented rules, care has to be taken when considering the heat dissipation out of the
device. The thermal heatsink should be soldered to the board as described in the PowerPad Package section.
PowerPAD Package
The PowerPAD package is a thermally-enhanced standard size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package.
The thermal pad on the bottom of the IC can then be soldered directly to the PCB using the PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads, as well as the thermal pad as illustrated
in the Mechanical Data section.
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter.
The small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25-mil diameter holes under the package, but outside the
thermal pad area to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as
a ground plane).
5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
SLMA004 application brief, PowerPAD Made Easy, or the technical brief, PowerPAD Thermally Enhanced
Package (SLMA002).
24
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
ADS5444MPFPEP
V62/06668-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PFP
80
96 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
HTQFP
PFP
80
96 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5444-EP :
Catalog: ADS5444
Space: ADS5444-SP
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
•
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Transportation and Automotive www.ti.com/automotive
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connctivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明