ADS5521IPAPRG4 [TI]
12-Bit, 105-MSPS Analog-to-Digital Converter (ADC) 64-HTQFP -40 to 85;
| 型号： | ADS5521IPAPRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit, 105-MSPS Analog-to-Digital Converter (ADC) 64-HTQFP -40 to 85 转换器 |
| 文件： | 总35页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5521
www.ti.com ...................................................................................................................................................... SBAS309D–MAY 2004–REVISED OCTOBER 2008
12-Bit, 105MSPS
Analog-To-Digital Converter
1
FEATURES
THS9001, OPA695, OPA847
2
•
12-Bit Resolution
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
105MSPS Sample Rate
•
Wireless Communication
High SNR: 70 dBFS at 100 MHz fIN
High SFDR: 86 dBc at 100 MHz fIN
2.3-VPP Differential Input Voltage
Internal Voltage Reference
3.3-V Single-Supply Voltage
Analog Power Dissipation: 571 mW
Serial Programming Interface
TQFP-64 PowerPAD™ Package
–
–
Communication Receivers
Base Station Infrastructure
•
•
•
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Communication Instrumentation
–
–
Radar
Infrared
•
•
Video and Imaging
Medical Equipment
Recommended Op Amps:
THS3201, THS3202, THS4503, THS4509,
DESCRIPTION
The ADS5521 is a high-performance, 12-bit, 105MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference.
Designed for applications demanding the highest speed and highest dynamic performance in little space, the
ADS5521 has excellent power consumption of 571 mW at 3.3-V single-supply voltage. This allows an even
higher system integration density. The provided internal reference simplifies system design requirements. Parallel
CMOS-compatible output ensures seamless interfacing with common logic.
The ADS5521 is available in a 64-pin TQFP PowerPAD package and in an industrial temperature grade device.
Table 1. ADS5500 Product Family
80MSPS
ADS5522
ADS5542
105MSPS
ADS5521
ADS5541
125MSPS
ADS5520
ADS5500
12 Bit
14 Bit
AV
DD
DRV
DD
CLK+
CLK−
Timing Circuitry
CLKOUT
12-Bit
Pipeline
ADC
D0
Digital
Error
Correction
V
IN+
.
.
.
Output
Control
S&H
V
D11
IN−
Core
OVR
DFS
Internal
Reference
Control Logic
CM
Serial Programming Register
ADS5521
A
GND
SEN
SDATA SCLK
DR
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated
ADS5521
SBAS309D–MAY 2004–REVISED OCTOBER 2008 ...................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT PACKAGE-LEAD
HTQFP-64(2)
ADS5521
ADS5521IPAP
Tray, 160
PAP
–40°C to 85°C
ADS5521I
PowerPAD
ADS5521IPAPR
Tape and Reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet.
(2) Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2 oz. copper
trace and pad soldered directly to a JEDEC standard, four-layer, 3 in x 3 in PCB.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
ADS5521
UNIT
V
AVDD to AGND, DRVDD to DRGND
AGND to DRGND
–0.3 to 3.7
Supply Voltage
±0.1
–0.3 to minimum (AVDD + 0.3, 3.6)
–0.3 to DRVDD
–0.3 to DRVDD
–40 to 85
V
(2)(3)
Analog input to AGND
Logic input to DRGND
V
V
Digital data output to DRGND
Operating temperature range
Junction temperature
V
°C
°C
°C
105
Storage temperature range
–65 to 150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 W should be added in series with each of the analog
input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle
of the overshoot should be limited to less than 5% for inputs up to 3.9 V.
(3) The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a
percentage. The total time of overshoot is the integrated time of all overshoot occurrences over the lifetime of the device.
2
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ADS5521
www.ti.com ...................................................................................................................................................... SBAS309D–MAY 2004–REVISED OCTOBER 2008
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Supplies
Analog supply voltage, AVDD
Output driver supply voltage, DRVDD
Analog input
3
3
3.3
3.3
3.6
3.6
V
V
Differential input range
2.3
VPP
V
(1)
Input common-mode voltage, VCM
1.45
1.55
1.65
Digital Output
Maximum output load
Clock Input
10
pF
DLL ON
60
2
105
80
ADCLK input sample rate (sine wave) 1/tC
MSPS
VPP
DLL OFF
Clock amplitude, sine wave, differential(2)
Clock duty cycle(3)
1
3
50%
Open free-air temperature range
–40
85
°C
(1) Input common-mode should be connected to CM.
(2) See Figure 49 for more information.
(3) See Figure 48 for more information.
ELECTRICAL CHARACTERISTICS
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
=
DRVDD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1dBFS differential
input, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12
Bits
Analog Inputs
Differential input range
2.3
6.6
4
VPP
kΩ
pF
Differential input impedance
Differential input capacitance
See Figure 39
See Figure 39
Analog input common-mode current
(per input)
250
750
4
µA
Analog input bandwidth
Source impedance = 50 Ω
MHz
Clock
cycles
Voltage overload recovery time
Internal Reference Voltages
Reference bottom voltage, VREFM
Reference top voltage, VREFP
Reference error
1
2.15
V
V
–4%
±0.9%
4%
1.55
±0.05
Common-mode voltage output, VCM
V
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
±0.25
±0.5
Differential nonlinearity error, DNL
Integral nonlinearity error, INL
Offset error
fIN = 55 MHz
fIN = 55 MHz
–0.5
–1.5
–11
+0.5
+1.5
11
LSB
LSB
±1.5
mV
Offset temperature coefficient
0.02
mV/°C
Δoffset error/ΔAVDD from AVDD = 3 V to
AVDD = 3.6 V
DC power-supply rejection ratio, DC PSRR
0.25
mV/V
(1)
Gain error
–2
±0.3
2
%FS
Gain temperature coefficient
–0.02
Δ%/°C
(1) Gain error is specified by design and characterization; it is not tested in production.
Copyright © 2004–2008, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
=
DRVDD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1dBFS differential
input, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic AC Characteristics
fIN = 10 MHz
fIN = 55 MHz
71
70.5
69
25°C to 85°C
Full temp range
68
66.8
Signal-to-noise ratio. SNR
fIN = 70 MHz
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
70.3
70
dBFS
LSB
dBc
69.3
67.8
0.32
83
RMS idle channel noise
Input tied to common-mode
fIN = 10 MHz
25°C
78
76
86
fIN = 55 MHz
Full temp range
85
Spurious-free dynamic range, SFDR
fIN = 70 MHz
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
fIN = 10 MHz
81
86
75
72
90
25°C
78
76
86
fIN = 55 MHz
Full temp range
85
Second-harmonic, HD2
fIN = 70 MHz
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
81
dBc
88
75
72
83
fIN = 10 MHz
fIN = 55 MHz
88
25°C
78
76
88
Full temp range
87
Third-harmonic, HD3
dBc
fIN = 70 MHz
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
87
86
80
78
Worst-harmonic/spur (other than HD2 and
HD3)
fIN = 55 MHz
fIN = 10 MHz
87
dBc
70.7
70
25°C
67
fIN = 55 MHz
Full temp range
65.8
68.5
69.6
69.3
68.2
65.8
Signal-to-noise + distortion, SINAD
fIN = 70 MHz
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
dBFS
4
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ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
=
DRVDD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1dBFS differential
input, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
79
MAX
UNIT
fIN = 10 MHz
fIN = 55 MHz
25°C
76
74
83
Full temp range
82
Total harmonic distortion, THD
fIN = 70 MHz
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
fIN = 55 MHz
78
dBc
84
74
70.3
11.3
94.6
96.6
84.7
35
Effective number of bits, ENOB
Bits
dBFS
dB
f = 10.1 MHz, 15.1 MHz (-7dBFS each tone)
f = 50.1 MHz, 55.1 MHz (-7dBFS each tone)
f = 150.1 MHz, 155.1 MHz (-7dBFS each tone)
Supply noise frequency ≤ 100 MHz
Two-tone intermodulation distortion, IMD
AC power supply rejection ratio, ACPSRR
Power Supply
Total supply current, ICC
fIN = 55 MHz
fIN = 55 MHz
fIN = 55 MHz
Analog only
223
173
50
250
185
65
mA
mA
mA
Analog supply current, IAVDD
Output buffer supply current, IDRVDD
571
611
Power dissipation
Standby power
mW
mW
Output buffer power with 10-pF load on digital
output to ground
165
180
215
250
With clocks running
DIGITAL CHARACTERISTICS
Valid over full recommended operating temperature range, AVDD = DRVDD = 3.3 V, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High-level input voltage, VIH
Low-level input voltage, VIL
High-level input current, IIH
Low-level input current, IIL
Input current for RESET
Input capacitance
2.4
V
0.8
10
V
µA
µA
µA
pF
-10
–20
4
Digital Outputs
Low-level output voltage, VOL
High-level output voltage, VOH
Output capacitance
CLOAD = 10 pF
0.3
3
0.4
V
V
CLOAD = 10 pF
2.4
3
pF
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TIMING CHARACTERISTICS(1)(2)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF, unless
otherwise noted(1)
=
PARAMETER
Switching Specification
Aperture delay, tA
DESCRIPTION
MIN
TYP
MAX
UNIT
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid(3) to 50% of CLKOUT rising edge
1
300
2.8
ns
fs
Aperture jitter (uncertainty)
Data setup time, tSETUP
Data hold time, tHOLD
2.2
2.2
ns
ns
50% of CLKOUT rising edge to data becoming
invalid(3)
2.5
Input clock to output data valid start,
tSTART
Input clock rising edge to data valid start delay
1.9
7.3
2.8
ns
ns
(4)(5)
Input clock to output data valid end,
Input clock rising edge to data valid end delay
5.8
(4)(5)
tEND
Output clock jitter, tJIT
Uncertainty in CLKOUT rising edge, peak-to-peak
Rise time of CLKOUT from 20% to 80% of DRVDD
Fall time of CLKOUT from 80% to 20% of DRVDD
175
2
250
2.2
1.8
5.5
psPP
ns
Output clock rise time, tr
Output clock fall time, tf
1.7
4.7
ns
Input clock to output clock delay, tPDI
Input clock rising edge, zero crossing, to output
clock rising edge 50%
4
ns
Data rise time, tr
Data rise time measured from 20% to 80% of
DRVDD
4.4
3.3
5.1
3.8
ns
ns
Data fall time, tf
Data fall time measured from 80% to 20% of
DRVDD
Output enable(OE) to data output delay
Time required for outputs to have stable timings
with regard to input clock(6) after OE is activated
1000
1000
1000
Clock
cycles
Time to valid data after coming out of software
power down
Clock
cycles
Wakeup time
Latency
Time to valid data after stopping and restarting the
clock
Time for a sample to propagate to the ADC outputs
17.5
Clock
cycles
(1) Timing parameters are ensured by design and characterization, and not tested in production.
(2) See Table 6 through Table 9 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.
(4) See the Output Information section for details on using the input clock for data capture.
(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
6
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ADS5521
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N + 3
N + 4
N + 2
Sample
N
Analog
Input
N + 1
N + 17
N + 16
N + 14
N + 15
Signal
t
A
Input Clock
t
START
t
PDI
Output Clock
t
su
Data Out
(D0−D11)
N − 17
N − 16
N − 15
N − 14
N − 13
N − 3
N − 2
N − 1
N
Data Invalid
t
t
END
h
17.5 Clock Cycles
A. It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
RESET TIMING CHARACTERISTICS
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted
=
PARAMETER
Switching Specification
DESCRIPTION
MIN
TYP
MAX
UNIT
Power-on delay, t1
Delay from power-on of AVDD and
DRVDD to RESET pulse active
10
ms
Reset pulse width, t2
Register write delay, t3
Pulse width of active RESET signal
2
2
µs
µs
Delay from RESET disable to SEN
active
Power-up time
Delay from power-up of AVDD and
DRVDD to output stable
40
ms
Power Supply
(AV , DRV
)
DD
DD
t . 10 ms
1
t . 2 ms
2
t . 2 ms
3
SEN Active
RESET (Pin 35)
Figure 2. Reset Timing Diagram
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SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The ADS5521 has a three-wire serial interface. The ADS5521 latches serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
•
•
•
•
•
•
Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.
Minimum width of data stream for a valid loading is 16 clocks.
Data is loaded at every 16th SCLK falling edge while SEN is low.
In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
Data can be loaded in multiples of 16-bit words within a single active SEN pulse.
The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
t
SLOADS
t
SEN
SLOADH
t
t
t
SCLK
WSCLK WSCLK
SCLK
t
t
h(D)
su(D)
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 2. Serial Programming Interface Timing Characteristics
SYMBOL
tSCLK
PARAMETER
SCLK period
MIN(1)
TYP(1)
MAX(1)
UNIT
50
ns
tWSCLK
tSLOADS
tSLOADH
tDS
SCLK duty cycle
SEN to SCLK setup time
SCLK to SEN hold time
Data setup time
25%
50%
75%
8
6
8
6
ns
ns
ns
ns
tDH
Data hold time
(1) Typ, min, and max values are characterized, but not production tested.
8
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Table 3. Serial Register Table(1)
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
DESCRIPTION
DLL
CTRL
Clock DLL
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Internal DLL is on; recommended for 60MSPS to 105MSPS
clock speeds.
Internal DLL is off; recommended for 2MSPS to 80MSPS
clock speeds.
TP<1>
TP<0>
Test Mode
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
Normal mode of operation
All outputs forced to 0
All outputs forced to 1
0
(2)(3)
0
Each output bit toggles between 0 and 1.
PDN
0
Power Down
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
0
Normal mode of operation
1
Device is put in power-down (low-current) mode.
(1) The register contents default to the appropriate setting for normal operation up on RESET.
(2) The patterns given are applicable to the straight offset binary output format. If 2's complement output format is selected, the test mode
outputs will be the binary 2's complement equivalent of these patterns as described in the Output Information section.
(3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D13. For
example, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
Table 4. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (VDFS
)
DATA FORMAT
CLOCK OUTPUT POLARITY
2
12
Straight Binary
Data valid on rising edge
V
t
AV
DD
DFS
5
12
4
12
2's complement
Straight Binary
2's complement
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
AV
AV
t V
t
AV
AV
DD
DD
DFS
8
12
7
12
t V
t
DD
DD
DFS
10
12
V
u
AV
DD
DFS
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PIN CONFIGURATION
PAP PACKAGE
HTQFP-64
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
DRGND
SCLK
SDATA
SEN
DRGND
D1
3
D0 (LSB)
4
45 NC
AVDD
AGND
5
44 NC
6
43 CLKOUT
7
42
41
AVDD
AGND
DRGND
OE
ADS5521
PowerPAD
8
AVDD
CLKP
CLKM
AGND
9
40 DFS
(Connected to Analog Ground)
10
11
12
39
38
37
AVDD
AGND
AVDD
AGND 13
AGND 14
AVDD 15
36 AGND
35 RESET
34 AVDD
16
33
AVDD
AGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10
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PIN ASSIGNMENTS(1)
TERMINAL
NO. OF
NAME
NO.
PINS
I/O DESCRIPTION
5, 7, 9, 15, 22,
24, 26, 28, 33,
34, 37, 39
AVDD
12
I
Analog power supply
6, 8, 12, 13,
14, 16, 18, 21,
23, 25, 27, 32,
36, 38
AGND
14
I
Analog ground
DRVDD
DRGND
49, 58
2
6
I
I
Output driver power supply
Output driver ground
1, 42, 48, 50,
57, 59
NC
44, 45
19
20
29
30
31
17
35
41
40
10
11
4
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
I
Not connected
INP
Differential analog input (positive)
INM
I
Differential analog input (negative)
REFP
REFM
IREF
CM
O
O
I
Reference voltage (positive); 1-µF capacitor in series with a 1-Ω resistor to GND
Reference voltage (negative); 1-µF capacitor in series with a 1-Ω resistor to GND
Current set; 56-kΩ resistor to GND; do not connect capacitors
Common-mode output voltage
O
I
(2)
RESET
OE
Reset (active high), 200-kΩ resistor to AVDD
Output enable (active high)(3)
Data format and clock out polarity select(4)(3)
Data converter differential input clock (positive)
Data converter differential input clock (negative)
Serial interface chip select(3)
I
DFS
I
CLKP
CLKM
SEN
I
I
I
SDATA
SCLK
3
I
Serial interface data(3)
Serial interface clock(3)
2
I
D0 (LSB) to
D11 (MSB)
46, 47, 51-56,
60-63
14
O
Parallel data output
OVR
64
43
1
1
O
O
Over-range indicator bit
CLKOUT
CMOS clock out in sync with data
(1) PowerPAD is connected to analog ground.
(2) If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details.
(3) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
(4) Table 4 defines the voltage levels for each mode selectable via the DFS pin.
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DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The offset error is the difference, given in number of
The analog input frequency at which the power of the
LSBs, between the ADC's actual average idle
fundamental is reduced by 3 dB with respect to the
channel output code and the ideal average idle
low frequency value.
channel output code. This quantity is often mapped
into mV.
Aperture Delay
Temperature Drift
The delay in time between the falling edge of the
input sampling clock and the actual time at which the
sampling occurs.
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree Celsius of the parameter from TMIN to TMAX. It
is calculated by dividing the maximum deviation of
the parameter across the TMIN to TMAX range by the
difference (TMAX – TMIN).
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Signal-to-Noise Ratio (SNR)
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty
cycle.
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
DC and the first eight harmonics.
PS
SNR + 10Log
10 PN
Maximum Conversion Rate
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to Full-Scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
DC.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1LSB apart. The DNL is the
deviation of any single step from this ideal value,
measured in units of LSBs.
PS
SINAD + 10Log
10 PN ) PD
Integral Nonlinearity (INL)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to Full-Scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
The INL is the deviation of the ADC's transfer
function from a best fit line determined by a least
squares curve fit of that transfer function, measured
in units of LSBs.
Effective Number of Bits (ENOB)
Gain Error
The ENOB is a measure of a converter's performance
as compared to the theoretical limit based on
quantization noise.
The gain error is the deviation of the ADC's actual
input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input
full-scale range. Gain error does not account for
variations in the internal reference voltages (see the
Electrical Specifications section for limits on the
variation of VREFP and VREFM).
SINAD * 1.76
ENOB +
6.02
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Total Harmonic Distortion (THD)
Two-Tone Intermodulation Distortion (IMD3)
THD is the ratio of the power of the fundamental (PS)
to the power of the first eight harmonics (PD).
IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst
spectral component at either frequency 2f1 – f2 or
2f2 –f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to Full-Scale)
when the power of the fundamental is extrapolated to
the converter's full-scale range.
PS
THD + 10Log
10 PD
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier).
DC Power Supply Rejection Ration (DC PSRR)
The DC PSSR is the ratio of the change in offset
error to a change in analog supply voltage. The DC
PSRR is typically given in units of mV/V.
Reference Error
The reference error is the variation of the actual
reference voltage (VREFP - VREFM) from its ideal
value. The reference error is typically given as a
percentage.
Voltage Overload Recovery Time
The voltage overload recovery time is defined as the
time required for the ADC to recover to within 1% of
the full-scale range in response to an input voltage
overload of 10% beyond the full-scale range.
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TYPICAL CHARACTERISTICS
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 4 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 16 MHz Input Signal)
0
20
40
60
80
0
20
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
100
120
100
120
0
0
0
10
20
30
40
50
0
0
0
10
20
30
40
50
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 5.
Figure 6.
SPECTRAL PERFORMANCE
(FFT for 55 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70 MHz Input Signal)
0
0
−
−
−
−
20
40
60
80
−
−
−
−
20
40
60
80
−
−
100
120
−
−
100
120
10
20
30
40
50
10
20
30
40
50
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 7.
Figure 8.
SPECTRAL PERFORMANCE
(FFT for 80 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 100 MHz Input Signal)
0
0
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
100
120
100
120
10
20
30
40
50
10
20
30
40
50
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 150 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 220 MHz Input Signal)
0
20
40
60
80
0
20
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
100
120
100
120
0
0
0
10
20
30
40
50
0
0
0
10
20
30
40
50
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 11.
Figure 12.
SPECTRAL PERFORMANCE
(FFT for 300 MHz Input Signal)
TWO-TONE
INTERMODULATION
0
0
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
100
120
−
−
100
120
10
20
30
40
50
10
20
30
40
50
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 13.
Figure 14.
TWO-TONE
INTERMODULATION
TWO-TONE
INTERMODULATION
0
0
−
−
f1 = 150.1MHz ( 7dBFS)
f2 = 155.1MHz ( 7dBFS)
2−Tone IMD = 85.1dBFS
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
100
120
−
−
100
120
10
20
30
40
50
10
20
30
40
50
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
DIFFERENTIAL
NONLINEARITY
INTEGRAL
NONLINEARITY
0.25
0.20
0.15
0.10
0.05
0
1.0
0.8
0.6
0.4
0.2
0
−
−
−
−
−
−
−
−
−
−
0.05
0.10
0.15
0.20
0.25
0.2
0.4
0.6
0.8
1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
Code
Code
Figure 17.
Figure 18.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
95
90
85
80
75
70
65
60
76
74
72
70
68
66
64
62
60
0
50
100
150
200
250
300
0
50
100
150
200
250
300
−
−
Frequency MHz
Frequency MHz
Figure 19.
Figure 20.
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
76
75
74
73
72
71
70
69
68
95
90
85
80
75
70
65
60
fIN = 150MHz
fIN = 70MHz
SFDR
SFDR
SNR
SNR
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−
−
−
−
AVDD Analog Supply Voltage
V
AVDD Analog Supply Voltage V
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
78
76
74
72
70
68
66
88
84
80
76
72
68
64
fIN = 150MHz
fIN = 70MHz
SFDR
SNR
SFDR
SNR
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−
−
−
−
DVDD Digital Supply Voltage
V
DVDD Digital Supply Voltage
V
Figure 23.
Figure 24.
POWER DISSIPATION
vs SAMPLE RATE
POWER DISSIPATION
vs SAMPLE RATE
800
750
700
650
600
550
500
450
800
750
700
650
600
550
500
450
fIN = 150MHz
DLL On
fIN = 70MHz
DLL On
DLL Off
DLL Off
10
20
30
40
50
60
70
80
90 100
10
20
30
40
50
60
70
80
90 100
−
Sample Rate MSPS
−
Sample Rate MSPS
Figure 25.
Figure 26.
AC PERFORMANCE
vs TEMPERATURE
AC PERFORMANCE
vs INPUT AMPLITUDE
90
85
80
75
70
65
60
90
80
70
60
50
40
30
20
10
0
fIN = 70MHz
SNR (dBFS)
SFDR
SNR
SFDR (dBc)
SNR (dBc)
−
10
20
30
−
−
fIN = 70MHz
−
−
−
−
−
−
−
−
−
−
−
−
10
40
15
+10
+35
− _
+60
+85
100 90
80
70
60
50
40
30 20
0
Temperature
C
−
Input Amplitude dBFS
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
AC PERFORMANCE
vs INPUT AMPLITUDE
AC PERFORMANCE
vs INPUT AMPLITUDE
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
SNR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBc)
SNR (dBc)
SNR (dBc)
−
−
−
10
20
30
−
−
−
10
20
30
fIN = 220MHz
fIN = 150MHz
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
100 90
80
70
60
50
40
30 20
10
0
100 90
80
70
60
50
40
30 20
0
3.0
65
−
−
Input Amplitude dBFS
Input Amplitude dBFS
Figure 29.
Figure 30.
OUTPUT
AC PERFORMANCE
vs CLOCK AMPLITUDE
NOISE HISTOGRAM
100
90
80
70
60
50
40
30
20
10
0
95
90
85
80
75
70
65
60
fIN = 70MHz
SFDR
SNR
0
0.5
1.0
1.5
2.0
2.5
−
Differential Clock Amplitude
V
Code
Figure 31.
Figure 32.
WCDMA
CARRIER
AC PERFORMANCE
vs CLOCK DUTY CYCLE
0
100
95
90
85
80
75
70
65
60
fIN = 20MHz
−
−
−
−
20
40
60
80
SFDR
SNR
−
−
−
100
120
140
0
5
10
15
20
25 30
35
40
45
50
35
40
45
50
55
%
60
−
−
f
Frequency MHz
−
Clock Duty Cycle
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,
unless otherwise noted
SIGNAL-TO-NOISE RATIO (SNR)
(DLL On)
125
69
71
120
71
69.5
70.5
70
115
110
105
100
95
70.5
70.5
70.5
70
68.5
69
71
70.5
70.5
69.5
69
69.5
90
85
71.5
71
70
68.5
68
80
68.5
68
69
75
71
70
67.5
69.5
70.5
70
65
20
40
60
80
100
120
140
160
180
200
220
−
Input Frequency MHz
Figure 35.
SIGNAL-TO-NOISE RATIO (SNR)
(DLL Off)
100
90
80
70
60
50
40
30
20
10
71
70
69
69
71
70
68
67
66
65
69
71
71
68
66
70
69
64
63
68
67
70
71
69
62
61
63
67
68
65
66
64
63
67
66
62
61
70
64
140
65
120
69
68
63
160
60
20
40
60
80
100
180
200
220
−
Input Frequency MHz
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,
unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
(DLL On)
125
81
79
81
83
77
120
115
110
105
100
95
87
90
85
80
75
70
85
79
89
85
83
75
79
81
77
77
85
75
79
81
83
81
91
83
87
87
87
89
85
89
90
85
83
81
93
89
75
79
85
77
73
80
87
81
81
91
89
87
75
83
79
70
85
85
79
75
65
77
81
80
20
40
60
100
120
140
160
180
200
220
−
Input Frequency MHz
Figure 37.
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
(DLL Off)
76
74
72
80
100
90
80
70
60
50
40
30
20
10
90
88
86
84
82
80
78
76
74
72
70
68
66
64
82
78
86
84
84
70
68
84
66
90
86
80
82
88
86
88
88
86
84
86
86
86
78
84
88
90
74
76
86
88
86
72 70
80
78
66
68
82
84
88
88
86
84
84
86
82
88
84
74
72
76
80
68
86
70
82
80
86
84
66
220
64
78
100
Input Frequency MHz
Figure 38.
20
40
60
80
120
140
160
180
200
−
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5521 is a low-power, 12-Bit, 105MSPS, CMOS, switched capacitor, pipeline ADC that operates from a
single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the
signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline every half clock cycle. This process results in a data
latency of 17.5 clock cycles, after which the output data is available as a 12-Bit parallel word, coded in either
straight offset binary or binary 2's complement format.
INPUT CONFIGURATION
The analog input for the ADS5521 consists of a differential sample-and-hold architecture implemented using the
switched capacitor technique shown in Figure 39.
S
3a
L1
R1a
C1a
INP
INM
S
S
1a
CP1
CP3
S
2
R3
CA
L2
R1b
C1b
VINCM
1V
1b
CP2
CP4
S
3b
L , L : 6 nH − 10 nH effective
1
2
R
1a
, R : 5W − 8W
1b
C , C : 2.2 pF − 2.6 pF
1a 1b
CP , CP : 2.5 pF − 3.5 pF
1
2
CP , CP : 1.2 pF − 1.8 pF
3
4
C : 0.8 pF − 1.2 pF
A
R : 80 W − 120 W
3
Swithches: S , S
On Resistance: 35 W − 50 W
1a 1b:
S : On Resistance: 7.5 W − 15 W
2
S
, S : On Resistance: 40 W − 60 W
3a 3b
All switches OFF Resistance: 10 GW
A. All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 39. Analog Input Stage
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This differential input topology produces a high level of ac-performance for high sampling rates. It also results in
a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling
applications. The ADS5521 requires each of the analog inputs (INP, INM) to be externally biased around the
common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential
lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575 V and CM – 0.575 V. This
means that each input is driven with a signal of up to CM + 0.575 V, so that each input has a maximum
differential signal of 1.15 VPP for a total differential input signal swing of 2.3 VPP. The maximum swing is
determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM,
pin 30).
The ADS5521 obtains optimum performance when the analog inputs are driven differentially. The circuit shown
in Figure 40 illustrates one possible configuration using an RF transformer.
R0
Z0
W
25
W
W
50
50
INP
1:1
R
AC Signal
S ource
ADS5521
W
50
W
25
INM
C M
ADT1−1W T
W
m
10
1nF
0.1
F
Figure 40. Transformer Input to Convert Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of an RF transformer. Placing a 25-Ω resistor in series with
INP and INM is recommended to dampen ringing due to ADC kickback.
Since the input signal must be biased around the common-mode voltage of the internal circuitry, the
common-mode voltage (VCM) from the ADS5521 is connected to the center-tap of the secondary winding.
To ensure a steady low-noise VCM reference, best performance is attained when the CM output (pin 17) is filtered
to ground with a 10-Ω series resistor and parallel 0.1-µF and 0.001-µF low-inductance capacitors, as illustrated in
Figure 39.
Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware
that the input structure of the ADC sinks a common-mode current in the order of 500 µA (250 µA per input).
Equation 1 describes the dependency of the common-mode current and the sampling frequency:
500mA fS (in MSPS)
105 MSPS
(1)
Where:
fS > 2MSPS.
This equation helps to design the output capability and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a
transformer, to drive the input of the ADS5521. Texas Instruments offers a wide selection of single-ended
operational amplifiers (including the THS3201, THS3202, OPA695, and OPA847) that can be selected
depending on the application. An RF gain block amplifier, such as Texas Instruments THS9001, can also be
used with an RF transformer for high input frequency applications. The THS4503 is a recommended differential
input/output amplifier. Table 5 lists the recommended amplifiers.
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Table 5. Recommended Amplifiers to Drive the Input of the ADS5521
INPUT SIGNAL FREQUENCY
DC to 20 MHz
RECOMMENDED AMPLIFIER
THS4503
TYPE OF AMPLIFIER
Differential In/Out Amp
Operational Amp
USE WITH TRANSFORMER?
No
Yes
No
DC to 50 MHz
OPA847
DC to 100 MHz
THS4509
Differential In/Out Amp
Operational Amp
OPA695
Yes
Yes
Yes
Yes
10 MHz to 120 MHz
THS3201
Operational Amp
THS3202
Operational Amp
Over 100 MHz
THS9001
RF Gain Block
When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA695, or OPA847) to
provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformer
and one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5521. These
three amplifier circuits minimize even-order harmonics. For high frequency inputs, an RF gain block amplifier can
be used to drive a transformer primary; in this case, the transformer secondary connections can drive the input of
the ADS5521 directly, as shown in Figure 40, or with the addition of the filter circuit shown in Figure 41.
Figure 41 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the
ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these
components be included in the ADS5521 circuit layout when any of the amplifier circuits discussed previously are
used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential lines
of the ADS5521 input produces a degradation in performance at high input frequencies, mainly characterized by
an increase in the even-order harmonics. In this case, special care should be taken to keep as much electrical
symmetry as possible between both inputs.
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that
can simplify the driver circuit for applications requiring dc-coupling of the input. Flexible in their configurations
(see Figure 42), such amplifiers can be used for single-ended-to-differential conversion signal amplification.
-
+5V 5V
RS
RIN
RIN
W
100
0.1 mF
25 W
25 W
VIN
1:1
INP
INM
OPA695
R1
RT
100
ADS5521
CM
CIN
1000 pF
W
W
400
AV = 8V/V
(18dB)
R2
57.5
W
10
W
0.1 mF
Figure 41. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
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R
S
R
G
R
F
+5V
R
T
+3.3V
0.1 mF
10 mF
R
R
IN
INP
ADS5521
12-Bit / 105MSPS
V
COM
IN
INM
1 mF
CM
THS4503
10 mF
0.1 mF
10
W
5V
-
R
G
R
F
0.1 mF
Figure 42. Using the THS4503 with the ADS5521
POWER-SUPPLY SEQUENCE
The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of
AVDD and DRVDD. In the event that DRVDD ramps up first in the system, care must be taken to ensure that AVDD
ramps up within 10 ms. Optionally, it is recommended to put a 2-kΩ resistor from REFP (pin 29) to AVDD as
shown in Figure 43. This helps to make the device more robust to power supply ramp-up timings.
28
29
AVDD
REFP
2 kW
1 W
1 mF
Figure 43.
POWER-DOWN
The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit
through the serial programming interface. Using the reduced clock speed, power-down may be initiated for clock
frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device.
Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and
only the internal reference remains on to reduce the power-up time. The power-down mode reduces power
dissipation to approximately 180 mW.
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REFERENCE CIRCUIT
The ADS5521 has built-in internal reference generation, requiring no external circuitry on the printed circuit board
(PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1-µF decoupling
capacitor (the 1-Ω resistor shown in Figure 44 is optional). In addition, an external 56.2-kΩ resistor should be
connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in
Figure 44. No capacitor should be connected between pin 31 and ground; only the 56.2-kΩ resistor should be
used.
1 W
REFP
REFM
IREF
29
30
31
1 mF
1 mF
1 W
56.2 kW
Figure 44. REFP, REFM, and IREF Connections for Optimum Performance
CLOCK INPUT
The ADS5521 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. The common-mode voltage of the clock inputs
is set internally to CM (pin 17) using internal 5-kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM
(pin 17), as shown in Figure 45.
CM
CM
5 kW
5 kW
CLKM
CLKP
6 pF
3 pF
3 pF
Figure 45. Clock Inputs
When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01-µF
capacitor, while CLKP is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in Figure 46.
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Square Wave
or Sine Wave
CLKP
(3 V )
PP
0.01 mF
ADS5521
CLKM
0.01 mF
Figure 46. AC-Coupled, Single-Ended Clock Input
The ADS5521 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this
case, it is best to connect both clock inputs to the differential input clock signal with 0.01-µF capacitors, as shown
in Figure 47.
0.01 mF
CLKP
Differential Square Wave
or Sine Wave
(3 V )
PP
ADS5521
CLKM
0.01 mF
Figure 47. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, the
internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty
cycle should be provided. Figure 48 shows the performance variation of the ADC versus clock duty cycle.
100
fIN = 20MHz
95
90
85
80
75
70
65
60
SFDR
SNR
35
40
45
50
55
%
60
65
−
Clock Duty Cycle
Figure 48. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When
using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a
differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute
maximum ratings of the ADC clock input. Figure 49 shows the performance variation of the device versus input
clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the
ADS55xxEVM User's Guide (SLWU010), available for download from www.ti.com.
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95
fIN = 70MHz
90
85
SFDR
80
75
SNR
70
65
60
0
0.5
1.0
1.5
2.0
2.5
3.0
−
Differential Clock Amplitude
V
Figure 49. AC Performance vs Clock Amplitude
INTERNAL DLL
In order to obtain the fastest sampling rates achievable with the ADS5521, the device uses an internal digital
delay lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance
at clock frequencies below 60 MSPS. In order to operate the device below 60 MSPS, the internal DLL must be
shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical
Performance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLL
OFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. The
limit of the clock frequency where the device functions properly with default settings is ensured to be over 2 MHz.
OUTPUT INFORMATION
The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the
full-scale limits.
Two different output formats (straight offset binary or 2's complement) and two different output clock polarities
(latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one
of four different voltages. Table 4 details the four modes. In addition, output enable control (OE, pin 41, active
high) is provided to put the outputs into a high-impedance state.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 0xFFF in straight offset binary output format and 0x7FF in 2's complement output
format. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x800
in 2's complement output format. These outputs to an overdrive signal are ensured through design and
characterization.
The output circuitry of the ADS5521, by design, minimizes the noise produced by the data switching transients,
and, in particular, its coupling to the ADC analog circuitry. Output D2 (pin 51) senses the load capacitance and
adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in
the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have
nearly the same load as D2 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply
voltage or temperature. Placing external resistors in series with the outputs is not recommended.
The timing characteristics of the digital outputs change for sampling rates below the 105MSPS maximum
sampling frequency. Table 6 and Table 7 show the setup, hold, input clock to output data delays, and rise and
fall times for different sampling frequencies with the DLL on and off, respectively.
Table 8 and Table 9 show the rise and fall times at additional sampling frequencies with DLL on and off,
respectively.
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To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, td, that
results in the desired setup or hold time. Use either of the following equations to calculate the value of td.
Desired setup time = td – tSTART
Desired hold time = tEND – td
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
tSETUP (ns)
tHOLD (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80
65
2.8
3.8
3.7
4.6
2.8
3.6
3.3
4.1
0.5
1.7
0.8
5.3
5.3
7.9
8.5
5.8
6.7
6.6
7.2
4.4
5.5
5.3
6.4
–0.5
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
tSETUP (ns)
tHOLD (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80
65
40
20
10
2
3.2
4.3
8.5
17
4.2
5.7
11
1.8
2
3
3.8
2.8
5
4.5
1.5
2
8.4
8.3
11
5.8
6.6
7.5
7.5
6.6
7.2
8
4.4
5.5
7.3
7.6
5.3
6.4
7.8
8
3
11.8
14.5
21.6
31
2.6
2.5
4
3.5
4.7
6.5
19
–1
8.9
25.7
51
–9.8
-30
185
9.5
8
27
-3
11.5
515
284
370
8
320
576
50
82
75
150
Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
CLKOUT Jitter,
Peak-to-Peak
tJIT (ps)
Input-to-Output
Clock Delay
tPDI (ns)
CLKOUT, Rise Time
tr (ns)
CLKOUT, Fall Time
tf (ns)
fS
(MSPS)
MIN
TYP
2.5
MAX
MIN
TYP
2.1
MAX
MIN
TYP
210
260
MAX
315
MIN
3.7
TYP
4.3
MAX
80
65
2.8
3.5
2.3
2.9
5.1
4.8
3.1
2.6
380
3.5
4.1
Table 9. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
CLKOUT Jitter,
Peak-to-Peak
tJIT (ps)
CLKOUT, Rise Time
tr (ns)
CLKOUT, Fall Time
tf (ns)
Input-to-Output Clock Delay
tPDI (ns)
fS
(MSPS)
MIN
TYP
2.5
3.1
4.8
8.3
MAX
MIN
TYP
2.1
2.6
4
MAX
MIN
TYP
210
260
445
800
MAX
315
MIN
7.1
7.8
9.5
13
TYP
8
MAX
8.9
80
65
40
20
10
2
2.8
3.5
5.3
9.5
2.3
2.9
4.4
8.2
380
8.5
9.4
650
10.4
15.5
20.7
551
11.4
18
7.6
1200
16
25.5
567
31
52
36
65
2610
4400
537
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SERIAL PROGRAMMING INTERFACE
The ADS5521 has internal registers for the programming of some of the modes described in the previous
sections. The registers should be reset after power-up by applying a 2 µs (minimum) high pulse on RESET (pin
35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-kΩ internal pullup
resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register
setting in the Serial Programing Interface section describe the programming of this register.
Table 3 shows the different modes and the bit values to be written to the register to enable them.
Note that some of these modes may modify the standard operation of the device and possibly vary the
performance with respect to the typical data shown in this data sheet.
Applying a RESET signal is absolutely essential to set the internal registers to their default states for normal
operation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground and
it is necessary to write the default values to the internal registers through the serial programming interface. The
following registers must be written in this order.
Write 9000h (Address 9, Data 000)
Write A000h (Address A, Data 000)
Write B000h (Address B, Data 000)
Write C000h (Address C, Data 000)
Write D000h (Address D, Data 000)
Write E000h (Address E, Data 804)
Write 0000h (Address 0, Data 000)
Write 1000h (Address 1, Data 000)
Write F000h (Address F, Data 000)
NOTE:
This procedure is only required if a RESET pulse is not provided to the device.
PowerPAD PACKAGE
The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom of
the IC. This provides a low thermal resistance path between the die and the exterior of the package. The thermal
pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a
heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section. The recommended thermal pad dimension is 8 mm x 8 mm.
2. Place a 5-by-5 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The
small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25 mil diameter holes under the package, but outside the
thermal pad area to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
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For more detailed information regarding the PowerPAD package and its thermal properties, see either the
application brief SLMA004B (PowerPAD Made Easy) or technical brief SLMA002 (PowerPAD Thermally
Enhanced Package).
Table 10. Revision History
Added notes regarding the input voltage overstress requirements in the absolute maximum ratings table.
Changed offset temperature coefficient to units of mV/°C.
Clarified output capture test modes in Table 3.
Updated the definitions section.
Updated the Power Down section to reflect the newly specified 2 MSPS minimum sampling rate.
Added footnotes in the Pin Assignements table or pins RESET,OE, SEN, SDATA and SCLK pins.
Removed the input voltage stress section in the Application Information section.
Tpdi parameter was added to the timing Table 8 and Table 9.
Added note in the Serial Programming section about mandatory RESET.
Added latency specification in the Timing Characteristics table.
Rev C
Added min/max specs for Offset and Gain errors.
Rev D
Output Information Section, p. 27.
Changed - From: binary output format and 0x4FFF To: binary output format and 0x7FF.
Changed From: binary output format and 0x2000 To: binary output format and 0x800.
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
PACKAGING INFORMATION
Orderable Device
ADS5521IPAP
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
HTQFP
HTQFP
PAP
64
64
160
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
-40 to 85 ADS5521I
ADS5521IPAPG4
ACTIVE
PAP
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
-40 to 85
ADS5521I
ADS5521I
ADS5521IPAPR
OBSOLETE
OBSOLETE
HTQFP
HTQFP
PAP
PAP
64
64
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
ADS5521IPAPRG4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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