ADS8353QPWQ1 [TI]
具有单端输入的汽车类 16 位 600kSPS 2 通道同步采样 SAR ADC | PW | 16 | -40 to 125;
| 型号： | ADS8353QPWQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有单端输入的汽车类 16 位 600kSPS 2 通道同步采样 SAR ADC | PW | 16 | -40 to 125 |
| 文件： | 总48页 (文件大小：2886K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8353-Q1
ZHCSJ89B –JANUARY 2019 –REVISED JULY 2022
ADS8353-Q1 汽车类16 位双通道
同步采样600kSPS 模数转换器
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100 标准：
• 电池管理系统(BMS)
• 直流/直流转换器
• 能量存储电源转换系统(PCS)
• 太阳能电弧保护
– 温度等级1：–40°C 至+125°C，TA
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 功能安全型
3 说明
– 可提供用于功能安全系统设计的文档
• 16 位分辨率
• 两个通道同步采样
ADS8353-Q1 是一款 16 位双通道高速同步采样模数转
换器(ADC)，可支持单端和伪差分模拟输入。
• 支持单端和伪差分输入
• 两个软件可选的单极输入范围：
– （0V 至VREF）或（0V 至2x VREF
• 高达600kSPS 的采样速度
• 出色的直流性能：
– ±0.6LSB DNL
– ±1LSB INL
– ±0.05% 增益误差
• 出色的交流性能：
ADS8353-Q1 包含两个可用于系统级增益校准的独立
可编程基准源。并且配有一个可在宽电源供电范围内运
行的灵活串行接口，从而轻松实现与多种主机控制器的
通信。该系列器件支持两种低功耗模式，可针对给定输
出优化功耗。ADS8353-Q1 的额定工作温度范围为 –
40°C 至+125°C，采用16 引脚TSSOP 封装。
）
封装信息(1)
封装尺寸（标称值）
器件型号
封装
ADS8353-Q1
TSSOP (16)
5.00mm × 4.40mm
– 89dB SNR
– -100dB THD
• 双路、低漂移(10ppm/°C)、可编程
2.5V 内部基准电压
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS931
ADS8353-Q1
ZHCSJ89B –JANUARY 2019 –REVISED JULY 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................21
7.5 Programming............................................................ 21
7.6 Register Maps...........................................................29
8 Application and Implementation..................................33
8.1 Application Information............................................. 33
8.2 Typical Application.................................................... 35
8.3 Power Supply Recommendations.............................36
8.4 Layout....................................................................... 37
9 Device and Documentation Support............................39
9.1 Device Support......................................................... 39
9.2 Documentation Support............................................ 39
9.3 接收文档更新通知..................................................... 39
9.4 支持资源....................................................................39
9.5 Trademarks...............................................................39
9.6 Electrostatic Discharge Caution................................39
9.7 术语表....................................................................... 39
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Thermal Information....................................................4
6.4 Recommended Operating Conditions.........................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................8
6.7 Switching Characteristics............................................8
6.8 Timing Diagram...........................................................9
6.9 Typical Characteristics..............................................10
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (March 2019) to Revision B (July 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式........................................................................................1
• 更改了特定于汽车的特性要点............................................................................................................................1
• 向特性部分添加了功能安全型要点....................................................................................................................1
• 更改了出色的直流性能子要点：将±1LSB（DNL 典型值） 更改为±0.6LSB (DNL)，并将±1LSB（INL 典型
值） 更改为±1LSB (INL) ...................................................................................................................................1
• 更改了应用部分..................................................................................................................................................1
Changes from Revision * (January 2019) to Revision A (March 2019)
Page
• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Pin Configuration and Functions
AINP_A
AINM_A
1
16
15
14
13
12
11
10
9
AVDD
GND
2
3
4
5
6
7
8
REFIO_A
REFGND_A
REFGND_B
REFIO_B
AINM_B
SDO_B
SDO_A
SCLK
CS
SDI
AINP_B
DVDD
Not to scale
图5-1. PW Package, 16-Pin TSSOP (Top View)
表5-1. Pin Functions
PIN
NAME
AINM_A
TSSOP
TYPE
Analog input
Analog input
Analog input
Analog input
Supply
DESCRIPTION
2
7
Negative analog input, channel A
Negative analog input, channel B
Positive analog input, channel A
Positive analog input, channel B
Supply voltage for ADC operation
Chip-select signal; active low
AINM_B
AINP_A
AINP_B
AVDD
1
8
16
11
9
CS
Digital input
Digital I/O supply
Supply
DVDD
Digital I/O supply
GND
15
4
Digital ground
REFGND_A
REFGND_B
REFIO_A
REFIO_B
SCLK
Supply
Reference ground potential A
5
Supply
Reference ground potential B
3
Analog input/output
Analog input/output
Digital input
Digital input
Digital output
Digital output
Reference voltage input/output, channel A
Reference voltage input/output, channel B
Clock for serial communication
6
12
10
13
14
SDI
Data input for serial communication
Data output for serial communication, channel A and channel B
Data output for serial communication, channel B
SDO_A
SDO_B
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
UNIT
AVDD to REFGND_x(2) or GND
DVDD to GND
6
6
V
V
Analog (AINP_x and AINM_x)(3) and reference input
AVDD + 0.3
V
REFGND_x –0.3
(REFIO_x) voltage with respect to REFGND_x
Digital input voltage with respect to GND
REFGND_x
DVDD + 0.3
GND –0.3
-10
DVDD + 0.3
GND + 0.3
10
V
V
Input current to any pin except supply pins
Junction temperature, TJ
mA
°C
°C
125
–40
Storage temperature, Tstg
150
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) REFGND_x refers to REFGND_A and REFGND_B. REFIO_x refers to REFIO_A and REFIO_B.
(3) AINP_x refers AINP_A and AINP_B. AINM_x refers to AINM_A and AINM_B.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Corner pins (1,8,9
±2000
V(ESD)
Electrostatic discharge
±750
±500
V
Charged-device model (CDM),
and 16)
per AEC Q100-001, level C4B
All other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Thermal Information
ADS8353-Q1
THERMAL METRIC(1)
PW (TSSOP)
UNIT
16 PINS
99
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.6
45
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.4
ΨJT
YJB
44.5
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
VREF range, internal reference
4.5
4.5
5
5
5.5
5.5
VREF range, external reference VEXT_REF < 4.5 V
VREF range, external reference VEXT_REF > 4.5 V
2x VREF range, internal reference
Analog supply voltage
(AVDD to AGND)
AVDD
DVDD
VEXT_REF
5
5
5.5
5.5
5.5
5.5
V
V
5
2x VREF range, external reference
2 x VEXT_REF
1.65
5
Digital supply voltage
3.3
ANALOG INPUTS (Single-Ended Configuration)
VREF range, single-ended input, AINM_x = GND
0
0
VREF
Full-scale input range
(AINP_x to AINM_x)(1)
FSR
VINP
VINM
V
V
V
2x VREF range, single-ended input, AINM_x =
GND
2 x VREF
Absolute input voltage VREF range
(AINP_x to
0
0
VREF
2 x VREF
0.1
REFGND_x)(2)
2x VREF range, AVDD ≥2x VREF
VREF range, single-ended input
–0.1
Absolute input voltage
(AINM_x to
REFGND_x)
2x VREF range, single-ended input, AVDD ≥2 x
0.1
–0.1
VREF
ANALOG INPUTS (Pseudo-Differential Configuration)
VREF range, pseudo-differential input, AINM_x =
VREF/2
VREF / 2
VREF
–VREF / 2
–VREF
Full-scale input range
(AINP_x-AINM_x)
FSR
VINP
VINM
V
V
V
2x VREF range, pseudo-differential input, AINM_x
= VREF
,
AVDD ≥2x VREF
Absolute input voltage
(AINP_x to
REFGND_x)
VREF range
0
0
VREF
Absolute input voltage
(AINP_x to
2 x VREF
2x VREF range, AVDD ≥2x VREF
REFGND_x)(2)
Absolute input voltage
(AINM_x -REFGND_x)
VREF range, pseudo-differential input
VREF / 2+0.1
VREF+0.1
V
REF / 2 –0.1
Absolute input voltage
(AINM_x -REFGND_x)
2x VREF range, single-ended input, AVDD ≥2x
VREF
V
REF–0.1
EXTERNAL REFERENCE INPUT
REFIO_x(3) input
VREF range
2.4
2.4
2.5
2.5
AVDD
VREFIO
voltage
V
2x VREF range
AVDD / 2
TEMPERATURE RANGE
TA
Ambient temperature
25
125
°C
–40
(1) AINP_x refers to analog input pins AINP_A and AINP_B. AINM_x refers to analog input pins AINM_A and AINM_B.
(2) REFGND_x refers to reference ground pins REFGND_A and REFGND_B.
(3) REFIO_x refers to voltage reference inputs REFIO_A and REFIO_B.
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6.5 Electrical Characteristics
at AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted);
minimum and maximum values at TA = –40°C to 125°C; typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUTS
In sample mode
40
4
Ci
Input capacitance
pF
µA
In hold mode
Ilkg
Input leakage current
0.1
RESOLUTION
Resolution
16
Bits
Bits
DC ACCURACY
NMC
INL
No missing codes
Integral nonlinearity
Differential nonlinearity
Input offset error
EIO match
16
±1
4
LSB
LSB
mV
–4
DNL
EIO
±0.6
±0.5
±0.5
1
1
1
–1
–1
ADC_A to ADC_B
mV
dEIO/dT
EG
Input offset thermal drift
Gain error
µV/°C
Referenced to the voltage at REFIO_x
ADC_A to ADC_B
±0.05
±0.05
1
0.1 %FS
0.1 %FS
ppm/°C
–0.1
–0.1
EG match
dEG/dT
Gain error thermal drift
Referenced to the voltage at REFIO_x
AC ACCURACY
VREF = 2.5 V, VREF input range
VREF = 2.5 V, 2x VREF input range
VREF = 5 V, VREF input range
VREF = 2.5 V, VREF input range
VREF = 2.5 V, 2x VREF input range
VREF = 5 V, VREF input range
VREF = 2.5 V, VREF input range
VREF = 2.5 V, 2x VREF input range
VREF = 5 V, VREF input range
VREF = 2.5 V, VREF input range
VREF = 2.5 V, 2 x VREF input range
VREF = 5 V, VREF input range
80.2
80.5
83
83.9
88.7
83
SINAD
SNR
Signal-to-noise + distortion
Signal-to-noise ratio
dB
dB
84
89
–100
–100
–100
105
THD
Total harmonic distortion
dB
dB
SFDR
Spurious-free dynamic range
105
105
INTERNAL VOLTAGE REFERENCE
VREFOUT
Reference output voltage
REFDAC_x = 1FFh (default) at 25°C
REFDAC_x = 1FFh (default) at 25°C
2.495
2.5 2.505
V
VREF-match
VREF_A to VREF_B matching
±1
mV
mV
REFDAC_x resolution(1)
1.1
Reference voltage temperature
drift
dVREFOUT/dT
dVREFOUT/dt
RO
REFDAC_x = 1FFh (default) at 25°C
1000 hours
±10
150
1
ppm/°C
ppm
Ω
Long-term stability
Internal reference output
impedance
IREFOUT
CREFOUT
tREFON
Reference output dc current
Reference output capacitor
Reference output settling time
2
10
8
mA
µF
ms
VOLTAGE REFERENCE INPUT
IREF Average reference input current
Per ADC
300
µA
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6.5 Electrical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted);
minimum and maximum values at TA = –40°C to 125°C; typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX UNIT
External ceramic reference
capacitor
CREF
µF
µA
Ilkg(dc)
DC leakage current
±0.1
SAMPLING DYNAMICS
tA
Aperture delay
tA match
8
40
50
ns
ps
ps
ADC_A to ADC_B
tAJIT
Aperture jitter
DIGITAL INPUTS
0.7
DVDD
DVDD
+ 0.3
DVDD > 2.3 V
DVDD ≤2.3 V
DVDD > 2.3 V
DVDD ≤2.3 V
VIH
High-level input voltage
V
0.8
DVDD
DVDD
+ 0.3
0.3
–0.3
–0.3
DVDD
V
VIL
Low-level input voltage
Input current
0.2
DVDD
±10
nA
DIGITAL OUTPUTS
0.8
DVDD
VOH
High-level output voltage
Low-level output voltage
IOH = 500-µA source
IOL = 500-µA sink
DVDD
V
V
0.2
DVDD
VOL
0
POWER SUPPLY
AVDD = 5 V, fastest throughput internal
reference
8.5
7.5
5.5
4.5
2.5
10
3.6
7
AVDD = 5 V, fastest throughput external
reference(2)
AVDD = 5V, no conversion internal
reference
mA
AIDD
Analog supply current
AVDD = 5 V, no conversion external
reference(2)
AVDD = 5 V, STANDBY mode internal
reference
AVDD = 5 V, STANDBY mode external
reference(2)
1
10
Power-down mode
50
µA
DVDD = 3.3 V, Cload = 10 pF, fastest
throughput
0.5
DIDD
PD
Digital supply current
mA
DVDD = 5 V, Cload = 10 pF, fastest
throughput
1
Power dissipation (normal
operation)
AVDD = 5 V, fastest throughput, internal
reference
42.5
50 mW
(1) Refer to the Reference section for more details.
(2) With internal reference powered down, CFR.B6 = 0.
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6.6 Timing Requirements
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +125°C; typical values at TA = 25°C.
MIN
0.4
NOM
MAX UNIT
0.6 tCLK
0.6 tCLK
20 MHz
33 x
tPH_CK
tPL_CK
fCLK
CLOCK high time
CLOCK low time
CLOCK frequency
0.4
32-clock, dual SDO mode
32-clock, single SDO mode
tCLK -
tCONV
tACQ
Acquisition time
ns
49 x
tCLK
-
tCONV
tCONV
Conversion time
730
ns
ns
ns
ns
ns
ns
ns
µs
tPH_CS
CS high time
40
150
15
15
5
tPH_CS_SHRT
tSU_CSCK
tD_CKCS
tSU_CKDI
tHT_CKDI
tPU_STDBY
CS high time after frame abort
Setup time: CS falling edge to SCLK falling edge
Delay time: Last SCLK falling edge to CS rising edge
Setup time: DIN data valid to SCLK falling edge
Hold time: SCLK falling edge to (previous) data valid on DIN
Power-up time from STANDBY mode
5
1
With internal reference
Power-up time from SPD mode
3
tPU_SPD
ms
With external reference
1
6.7 Switching Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +125°C; typical values at TA = 25°C.
PARAMETER
Throughput time
Throughput
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tTHROUGHPUT
fTHROUGHPUT
1.666
µs
600 kSPS
Delay time: CS falling edge to data
enable
tDV_CSDO
tDZ_CSDO
tD_CKDO
12
12
20
ns
ns
ns
Delay time: CS rising edge to data going
to 3-state
Delay time: SCLK falling edge to next
data valid
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6.8 Timing Diagram
CS
CS
SCLK
SDO
tSU_CSCK
SCLK
1
2
12
13
14
15
16
1
2
tSU_CKDI
tHT_CKDI
tDV_CSDO
SDI
B4
B3
B2
B1
B15
B14
Sample
N+1
Sample
N
CS
SCLK
SDO
tPL_CK
tSCLK
tD_CKCS
tPH_CK
1
2
N-9 N-8 N-7 N-6 N-5
N-4
N-3 N-2 N-1
N
tD_CKDO
tDZ_CSDO
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
V
V
图6-1. Serial Interface Timing Diagram
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6.9 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted)
0
-20
85.2
85
84.8
84.6
84.4
84.2
84
-40
-60
-80
-100
-120
-140
-160
-180
83.8
83.6
83.4
83.2
83
82.8
0
30
60
90 120 150 180 210 240 270 300
fIN, Input Frequency (kHz)
-60 -40 -20
0
20
40
60
80 100 120 140
Free-Air Temperature (èC)
D012
D014
fIN = 2 kHz
fIN = 2 kHz, SNR = 84.6 dB, THD = –107.6 dB
图6-2. Typical FFT
图6-3. SNR vs Temperature
85.2
85
89.5
89
84.8
84.6
84.4
84.2
84
88.5
88
87.5
87
83.8
83.6
83.4
83.2
83
86.5
86
85.5
85
82.8
84.5
-60 -40 -20
0
20
40
60
80 100 120 140
2.4
2.7
3
3.3
3.6
Reference voltage (V)
3.9
4.2
4.5
4.8
5.1
Free-Air Temperature (èC)
D011
D013
fIN = 2 kHz
fIN = 2 kHz
图6-4. SINAD vs Temperature
图6-5. SNR vs Reference Voltage
89.5
89
-72
-80
88.5
88
-88
87.5
87
-96
86.5
86
-104
-112
-120
85.5
85
84.5
2.4
2.7
3
3.3
3.6
Reference voltage (V)
3.9
4.2
4.5
4.8
5.1
-40
0
40
80
120
160
Free-Air Temperature (èC)
D010
D016
fIN = 2 kHz
fIN = 2 kHz
图6-6. SINAD vs Reference Voltage
图6-7. THD vs Temperature
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted)
-80
-88
12
10
8
-96
-104
-112
-120
6
4
2
2
2.5
3
3.5
Reference voltage (V)
4
4.5
5
5.5
-60
-30
0
30
60
90
120
150
Free-Air Temperature (èC)
D015
D018
fIN = 2 kHz
图6-8. THD vs Reference Voltage
图6-9. Analog Supply Current vs Temperature
12
10
8
18000
15000
12000
9000
6000
3000
0
6
4
2
0
3
6
9
12
SCLK Frequency (MHz)
15
18
21
D017
D005
65536 data points, VIN-DIFF = 0 V
图6-10. Analog Supply Current vs SCLK Frequency
图6-11. DC Histogram
600
1.5
1
450
300
150
0
0.5
0
-0.5
-150
-1
-60
-30
0
30
60
90
120
150
-60
-30
0
30
60
90
120
150
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D009
D004
图6-12. Offset Error vs Temperature
图6-13. Gain Error vs Temperature
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted)
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
13705
27410
Code
41115
54820
65535
0
13705
27410
Code
41115
54820
65535
D003
D008
图6-14. Typical DNL
图6-15. Typical INL
2
1.6
1.2
0.8
0.4
0
3
2
DNL_MIN
DNL_MAX
INL_MIN
INL_MAX
1
-0.4
-0.8
-1.2
-1.6
-2
0
-1
-2
-40
-10
20
50
80
110
140
-60
-30
0
30
60
90
120
150
Free-Air Temperature (èC)
Free-Air Temperature (C)è
D001
D006
图6-16. DNL vs Temperature
图6-17. INL vs Temperature
3
2
2
DNL_MIN
DNL_MAX
INL_MIN
INL_MAX
1
0
1
0
-1
-2
-3
-1
-2
2.4
2.8
3.2
3.6
Reference Voltage (V)
4
4.4
4.8
5.2
2.4
2.8
3.2
3.6
Reference Voltage (V)
4
4.4
4.8
5.2
D002
D007
图6-18. DNL vs Reference Voltage
图6-19. INL vs Reference Voltage
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7 Detailed Description
7.1 Overview
The ADS8353-Q1 is a 16-bit, dual-channel, high-speed, simultaneous-sampling, analog-to-digital converter
(ADC). The ADS8353-Q1 supports single-ended and pseudo-differential input signals. The device provides a
simple, serial interface to the host controller and operates over a wide range of analog and digital power
supplies.
The device has two independently programmable internal references to achieve system-level gain error
correction. The Functional Block Diagram section provides a functional block diagram of the device.
7.2 Functional Block Diagram
REF_A
Comparator
S/H
CDAC
SAR
SAR
ADC_A
ADC_B
Serial
Interface
CDAC
S/H
Comparator
REF_B
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7.3 Feature Description
7.3.1 Reference
The device has two simultaneous sampling ADCs (ADC_A and ADC_B). ADC_A and ADC_B operate with
reference voltages present on the REFIO_A and REFIO_B pins, respectively. Decouple the REFIO_A and
REFIO_B pins with the REFGND_A and REFGND_B pins, respectively, with 10-µF decoupling capacitors.
图 7-1 shows that the device supports operation either with an internal or external reference source. The
reference voltage source is determined by setting bit 6 of the configuration register (CFR.B6). This bit is common
to ADC_A and ADC_B.
AINP_A
ADC_A
AINM_A
REFGND_A
REFDAC_A
DAC_A
REFIO_A
10 mF
Enable
CFR.B6
INTREF
DAC_B
REFIO_B
REFDAC_B
10 mF
REFGND_B
AINP_B
AINM_B
ADC_B
图7-1. Reference Configurations and Connections
When CFR.B6 is 0, the device shuts down the internal reference source (INTREF) and ADC_A and ADC_B
operate on external reference voltages provided by the user on the REFIO_A and REFIO_B pins, respectively.
When CFR.B6 is 1, the device operates with the internal reference source (INTREF) connected to REFIO_A and
REFIO_B via DAC_A and DAC_B, respectively. In this configuration, VREF_A and VREF_B can be changed
independently by writing to the respective user-programmable registers, REFDAC_A and REFDAC_B,
respectively. See the Register Maps section for more details.
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7.3.2 Analog Inputs
The ADS8353-Q1 supports single-ended or pseudo-differential analog inputs on both ADC channels. These
inputs are sampled and converted simultaneously by the two ADCs, ADC_A and ADC_B. ADC_A samples and
converts (VAINP_A –VAINM_A), and ADC_B samples and converts (VAINP_B –VAINM_B).
图 7-2a and 图 7-2b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively. Series
resistance, RS, represents the on-state sampling switch resistance (typically 50 Ω) and CSAMPLE is the device
sampling capacitor (typically 40 pF).
AVDD
AVDD
RS CSAMPLE
RS CSAMPLE
AINP_A
AINP_B
GND
GND
AVDD
AVDD
RS CSAMPLE
RS CSAMPLE
AINM_A
AINM_B
GND
GND
a) ADC_A
b) ADC_B
图7-2. Equivalent Circuit for the Analog Input Pins
7.3.2.1 Analog Input: Full-Scale Range Selection
The full-scale range (FSR) supported at the analog inputs of the device is programmable with bit B9 of the
configuration register (CFR.B9). This bit is common for both ADCs (ADC_A and ADC_B). 方程式 1 and 方程式 2
give the FSR:
For CFR.B9 = 0, FSR_ADC_A = 0 to VREF_A and FSR_ADC_B = 0 to VREF_B
For CFR.B9 = 1, FSR_ADC_A = 0 to 2 × VREF_A and FSR_ADC_B = 0 to 2 × VREF_B
(1)
(2)
where:
• VREF_A and VREF_B are the reference voltages going to ADC_A and ADC_B, respectively (as described in the
Reference section).
Therefore, with appropriate settings of the REFDAC_A and REFDAC_B registers, CFR.B7, and CFR.B9, the
maximum dynamic range of the ADC can be used.
Make sure that the ADC analog supply (AVDD) is as in 方程式3 and 方程式4 when CFR.B9 is set to 1:
2 × VREF_A ≤AVDD ≤AVDD(max)
(3)
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2 × VREF_B ≤AVDD ≤AVDD(max)
(4)
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7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
The ADS8353-Q1 can support single-ended or pseudo-differential input configurations.
For supporting single-ended inputs, B7 in the configuration register (CFR.B7) must be set to 0 (CFR.B7 = 0) and
AINM_A and AINM_B must be externally connected to GND.
For supporting pseudo-differential inputs, CFR.B7 must be set to 1 (CFR.B7 = 1) and AINM_A and AINM_B
must be externally connected to FSR_ADC_A / 2 and FSR_ADC_B / 2, respectively. CFR.B7 is common to both
ADCs.
The CFR.B9 and CFR.B7 settings can be combined as shown in 表7-1 to select the desired input configuration.
表7-1. Input Configurations
INPUT RANGE SELECTION
AINM SELECTION
CONNECTION DIAGRAM
VREF_x
VREF_x
REFIO_x
AINP_x
CFR.B9 = 0
CFR.B7 = 0
(FSR_ADC_A = 0 to VREF_A
(FSR_ADC_B = 0 to VREF_B
)
)
(AINM_A = GND)
(AINM_B = GND)
0 V
Device
AINM_x
2 ì VREF_x
VREF_x
REFIO_x
AINP_x
CFR.B9 = 1
CFR.B7 = 0
(FSR_ADC_A = 0 to 2 x VREF_A
(FSR_ADC_B = 0 to 2 x VREF_B
)
)
(AINM_A = GND)
(AINM_B = GND)
0 V
Device
AINM_x
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表7-1. Input Configurations (continued)
INPUT RANGE SELECTION
AINM SELECTION
CONNECTION DIAGRAM
VREF_x
VREF_x
REFIO_x
AINP_x
0 V
VREF_x / 2
2 ì VREF_x
CFR.B9 = 0
(FSR_ADC_A = VREF_A
(FSR_ADC_B = VREF_B
CFR.B7 = 1
(AINM_A = VREF_A/2)
(AINM_B = VREF_B/2)
Device
)
)
AINM_x
VREF_x
REFIO_x
AINP_x
0 V
CFR.B9 = 1
CFR.B7 = 1
Device
(FSR_ADC_A = 2 x VREF_A
(FSR_ADC_B = 2 x VREF_B
)
)
(AINM_A = VREF_A
(AINM_B = VREF_B
)
)
AINM_x
VREF_x
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7.3.3 Transfer Function
The device supports two input configurations:
1. Single-ended inputs, CFR.B7 = 0 (default), or
2. Pseudo-differential inputs, CFR.B7 = 1
The device also supports two output data formats:
1. Straight binary output, CFR.B4 = 0 (default), or
2. Two's compliment output, CFR.B4 = 1
方程式5 calculates the device resolution:
1 LSB = (FSR_ADC_x) / (2N)
(5)
where:
• N = 16
• FSR_ADC_x = the full-scale input range of the ADC (see the Analog Inputs section for more details)
表7-2 and 表7-3 show the different input voltages and the corresponding output codes from the device.
表7-2. Transfer Characteristics for Straight Binary Output (CFR.B4 = 0, Default)
OUTPUT CODE (Hex)
INPUT VOLTAGE
INPUT
CONFIGURATION
STRAIGHT BINARY (CFR.B4 = 0, Default)
AINP_x
≤1 LSB
AINM_x
AINP_x - AINM_x
≤1 LSB
CODE
ADS8353-Q1
0000
ZC
Single-ended
(CFR.B7 = 0, default)
FSR_ADC_x / 2
FSR_ADC_x / 2
MC
7FFF
0
≥FSR_ADC_x –1
FSC
FFFF
≥FSR_ADC_x –1 LSB
LSB
ZC
0000
7FFF
≤1 LSB
≤–FSR_ADC_x / 2 + 1 LSB
Pseudo-differential
(CFR.B7 = 1)
FSR_ADC_x / 2
0
MC
FSR_ADC_x / 2
≥FSR_ADC_x –1
FSC
FFFF
≥FSR_ADC_x / 2 –1 LSB
LSB
表7-3. Transfer Characteristics for Two's Compliment Output (CFR.B4 = 1)
OUTPUT CODE (Hex)
INPUT VOLTAGE
INPUT
CONFIGURATION
TWO'S COMPLIMENT (CFR.B4 = 1,
Default)
AINP_x
≤1 LSB
AINM_x
AINP_x - AINM_x
≤1 LSB
CODE
ADS8353-Q1
8000
NFSC
MC
Single-ended
FSR_ADC_x / 2
FSR_ADC_x / 2
0000
0
(CFR.B7 = 0, default)
≥FSR_ADC_x –1
PFSC
7FFF
≥FSR_ADC_x –1 LSB
LSB
NFSC
MC
8000
0000
≤1 LSB
≤–FSR_ADC_x / 2 + 1 LSB
Pseudo-differential
(CFR.B7 = 1)
FSR_ADC_x / 2
0
FSR_ADC_x / 2
≥FSR_ADC_x –1
PFSC
7FFF
≥FSR_ADC_x / 2 –1 LSB
LSB
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图7-3 shows the ideal device transfer characteristics for the single-ended analog input.
FSC
PFSC
MC
MC
NFSC
ZC
1 LSB
FSR_ADC_x / 2
FSR_ADC_x œ 1 LSB
Single-Ended Analog Input
(AINP_x œ AINM_x)
VIN
图7-3. Ideal Transfer Characteristics for a Single-Ended Analog Input
图7-4 shows the ideal device transfer characteristics for the pseudo-differential analog input.
FSC
PFSC
-FSR_ADC_x/2
+ 1 LSB
0
MC
FSR_ADC_x/2
œ 1 LSB
MC
ZC
NFSC
Pseudo-Differential Analog Input
(AINP_x œ AINM_x)
图7-4. Ideal Transfer Characteristics for a Pseudo-Differential Analog Input
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7.4 Device Functional Modes
The device provides three user-programmable registers: the configuration register (CFR), the REFDAC_A
register, and the REFDAC_B register. These registers support write (see the Write to User-Programmable
Registers section) and readback (see the Reading User-Programmable Registers section) operations and allow
the ADC behavior to be customized for specific application requirements.
The device supports two interface modes (see the Conversion Data Read section), two low-power modes (see
the Low-Power Modes section), and a short-cycling or reconversion feature (see the Frame Abort,
Reconversion, or Short-Cycling section).
7.5 Programming
7.5.1 Serial Interface
The device uses the serial clock (SCLK) for synchronizing data transfers in and out of the device.
The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends
with a CS rising edge. Between the start and end of the frame, a minimum of N SCLK falling edges must be
provided to validate the read or write operation. As shown in 表7-4, N depends upon the interface mode used to
read the conversion result. When N SCLK falling edges are provided, the write operation attempted in the frame
is validated and the internal user-programmable registers are updated on the subsequent CS rising edge. This
CS rising edge also ends the frame.
表7-4. SCLK Falling Edges for a Valid Write Operation
MINIMUM SCLK FALLING EDGES REQUIRED TO
INTERFACE MODE
VALIDATE WRITE OPERATION N
32-CLK, dual-SDO mode (default); see the 32-CLK, Dual-SDO Mode (CFR.B11 = 0,
CFR.B10 = 0, Default) section
32
32-CLK, single-SDO mode; see the 32-CLK, Single-SDO Mode (CFR.B11 = 0,
CFR.B10 = 1) section
48
If CS is brought high before providing N SCLK falling edges, the write operation attempted in the frame is not
valid. See the Frame Abort, Reconversion, or Short-Cycling section for more details.
7.5.2 Write to User-Programmable Registers
The device features three user-programmable registers: the configuration register (CFR), the REFDAC_A
register, and the REFDAC_B register. These registers can be written with the device SDI pin. The first 16 bits of
data on SDI are latched into the device on the first 16 SCLK falling edges. However, the new configuration takes
effect only when the read or write operation is validated. If these registers are not required to update, SDI must
remain low during the respective frames.
The first four SDI data bits (B[15:12]) determine what operation is performed (that is, either a read or write
operation or no operation), which register address the operation uses, and the function of the next 12 SDI data
bits (B[11:0]). 表7-5 lists the various combinations supported for B[15:12].
表7-5. Data Write Operation
B15
0
B14
0
B13
0
B12
0
OPERATION
No operation is performed
REFDAC_A read
REFDAC_B read
CFR read
FUNCTION OF BITS B[11:0]
These bits are ignored
0
0
0
1
000h; see the Reading User-Programmable Registers section
000h; see the Reading User-Programmable Registers section
000h; see the Reading User-Programmable Registers section
See the CFR register
0
0
1
0
0
0
1
1
1
0
0
0
CFR write
1
0
0
1
REFDAC_A write
REFDAC_B write
No operation is performed
See the REFDAC register
1
0
1
0
See the REFDAC register
1
0
1
1
These bits are ignored
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表7-5. Data Write Operation (continued)
B15
B14
B13
B12
OPERATION
FUNCTION OF BITS B[11:0]
X
1
X
X
No operation is performed
These bits are ignored
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7.5.3 Data Read Operation
The device supports two types of read operations: reading user-programmable registers and reading conversion
results.
7.5.3.1 Reading User-Programmable Registers
The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B.
图7-5 shows a detailed timing diagram for this operation.
Frame (F)
Frame (F+1)
Frame (F+2)
Frame (F+3)
CS
1
2
N
1
2
3
4
5
16
48
1
2
15
16
47
48
1
2
N
SCLK
R15
R14
R1 R0
Valid Data
Valid Data
Valid Data
Valid Data
Valid data as per device configuration.
Valid data as per device configuration.
SDO-A
SDO-B
SDI
No change in device
configuration
No change in device
configuration
B15
B14 B13 B12
X
X
X
X
Device configuration for frame (F+3)
N is a function of the device configuration, as described in 表7-4.
图7-5. Register Readback Timing
To readback the user-programmable register settings, transmit the appropriate control word, as shown in 表 7-6,
to the device during frame (F+1). Frame (F+1) must have at least 48 SCLK falling edges.
表7-6. Control Word to Readback User-Programmable Registers
CONTROL WORD TO BE PROGRAMMED IN FRAME (F+1)
USER-PROGRAMMABLE REGISTER
B[15:12] (Binary)
B[11:0] (Hex)
CFR
0011b
000h
REFDAC_A
REFDAC_B
0001b
000h
0010b
000h
Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the
selected user-programmable register on the first 16 SCLK falling edges (as shown in 表 7-7) and then outputs
0's for any subsequent SCLK falling edges. The SDO_B pin outputs 0's for all SCLK falling edges.
表7-7. Register Data Read Back
USER-
DATA READ ON SDO-A IN FRAME (F+2)
PROGRAMMABLE
REGISTER
R15 R14
R13
R12
R11
R3
R2
CFG.B2
R1
CFG.B1
R0
CFG.B0
—
CFR
0
0
0
0
0
0
1
0
1
1
1
0
CFG.B11
CFG.B3
—
—
—
REFDAC_A
REFDAC_B
REFDAC_A.D8
REFDAC_B.D8
REFDAC_A.D0
REFDAC_B.D0
0
0
0
0
0
0
Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).
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7.5.3.2 Conversion Data Read
The device provides two different interface modes for reading the conversion result. These modes offer flexible
hardware connections and firmware programming. 表7-8 shows how to select one of the two interface modes.
表7-8. Interface Mode Selection
MINIMUM SCLK FALLING EDGES
CFR.B11
CFR.B10
INTERFACE MODE
REQUIRED TO VALIDATE WRITE
OPERATION N
0
0
0
1
32-CLK, dual-SDO mode (default)
32-CLK, single-SDO mode
32
48
In the 32-CLK interface modes, the device uses an internal clock to convert the sampled analog signal. The
conversion is completed during the first 16 periods of SCLK and the conversion result can be read on the
subsequent SCLK falling edges.
The following sections detail the various interface modes supported by the device.
7.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
The 32-CLK, dual-SDO mode is the default mode supported by the device. This mode can also be selected by
writing CFR.B11 = 0 and CFR.B10 = 0.
In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B
conversion result. 图7-6 shows a detailed timing diagram for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tACQ
tCONV
CS
SCLK
1
2
14
15 16
17
18
25 26
27
28
29
30 31
32
SDO_A and SDO_B
D7 D6
D5
D4 D3
D1 D0
D15 D14
D2
Data from sample N
SDI
X
B15 B14
B2
B1
B0
X
X
X
X
X
X
X
X
图7-6. 32-CLK, Dual-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins.
The device converts the sampled analog input during the conversion time (tCONV). SDO_A and SDO_B read 0
during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode.
The device outputs the MSBs of ADC_A and ADC_B on the SDO_A and SDO_B pins, respectively, on the 16th
SCLK falling edge. As shown in 表 7-9, the subsequent SCLK falling edges are used to shift out the rest of the
bits of the conversion result.
表7-9. Data Launch Edge
LAUNCH EDGE
CS
SCLK
CS
DEVICE
PINS
↓1
0
↓15
↓16
↓27
D4_A
D4_B
↓28
D3_A
D3_B
↓29
D2_A
D2_B
↓30
D1_A
D1_B
↓31
D0_A
D0_B
↓32 ...
0 ...
↓
0
—
—
—
—
—
—
↑
SDO-A
SDO-B
0
0
D15_A
D15_B
Hi-Z
Hi-Z
ADS8353-Q1
0
0
0 ...
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In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
See the Timing Requirements table for timing specifications specific to this serial interface mode.
7.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
The 32-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) to read conversion
results from both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect
(NC) pin.
This mode can be selected by writing CFR.B11 = 0 and CFR.B10 = 1. 图7-7 shows a detailed timing diagram for
this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tACQ
tCONV
CS
SCLK
1
2
14
15
16
17
18
28
29
30
31
32
33
34
44
45
46
47
25
48
D15 D14
D4
D3 D2 D1 D0 D15 D14
D4
D3 D2 D1 D0
SDO_A
ADC A Data
X
ADC B Data
X
SDI
B15 B14
B2
B1
B0
X
X
X
X
X
X
X
图7-7. 32-CLK, Single-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The device
converts the sampled analog input during the conversion time (tCONV). SDO_A reads 0 during this period. After
competing the conversion process, the sample-and-hold circuit goes back into sample mode. The device outputs
the MSB of ADC_A on the SDO_A pin on the 16th SCLK falling edge. As shown in 表 7-10, the subsequent
SCLK falling edges are used to shift out the conversion result of ADC_A followed by the conversion result of
ADC_B on the SDO_A pin.
表7-10. Data Launch Edge
LAUNCH EDGE
CS SCLK
CS
DEVICE
PIN
↓
48 ...
↓1
↓15
↓16
↓27
↓28
↓29
↓30
↓31
↓32
↓43
↓44 ↓45
↓46
↓47
↓
—
—
—
—
—
—
↑
ADS8353- SDO-
Q1
0
0
0
D15_A
D4_A D3_A D2_A D1_A D0_A
D15_B
D4_B D3_B D2_B D1_B D0_B
0 ...
Hi-Z
A
In this mode, at least 48 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
See the Timing Requirements table for timing specifications specific to this serial interface mode.
7.5.4 Low-Power Modes
In normal mode of operation, all internal circuits of the device are always powered up and the device is always
ready to commence a new conversion. This mode enables the device to support the rated throughput. The
device also supports two low-power modes to optimize the power consumption at lower throughputs: STANDBY
mode and software power-down (SPD) mode.
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7.5.4.1 STANDBY Mode
The device supports a STANDBY mode of operation where some of the internal circuits of the device are
powered down. However, if bit 6 in configuration register is set to 1 (CFR.B6 = 1), then the internal reference is
not powered down and the contents of the REFDAC_A and REFDAC_B registers are retained to enable faster
power-up to a normal mode of operation.
As shown in 图 7-8, a valid write operation in frame (F) programs the configuration register with B5 set to 1
(CFR.B5 = 1) and places the device into a STANDBY mode of operation on the following CS rising edge. While
in STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high.
To remain in STANDBY mode, SDI must remain low in the subsequent frames.
Device enters
STANDBY mode
Frame (F)
Frame (F+1)
Device in
STANDBY mode
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
N
SCLK
16
SDO-A and
SDO-B
Valid Data as per device configuration
CFG.B[5] = 1
SDI
CFG.B[4:0] = 00000b
CFG.B[15:12] = 1000b
CFG.B[11:6]
N is a function of the device configuration, as described in 表7-4.
图7-8. Enter STANDBY Mode
As shown in 图 7-9, a valid write operation in frame (F+3) writes the configuration register with B5 set to 0
(CFR.B5 = 0) and brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must
have at least 48 SCLK falling edges.
After exiting the STANDBY mode, a delay of tPU_STDBY must elapse for the internal circuits to fully power-up and
resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the
CFR.B[11:6] bits programmed during frame (F+3).
Frame (F+2)
Frame (F+3)
Device exits
STANDBY mode
Frame (F+4)
Device in
STANDBY
mode
tPU_STDBY
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
15
16
N
SCLK
16
48
SDO-A
and
SDO-B
Valid Data as per device configuration
CFG settings for Frame (F+5)
These bits set device
configuration for Frame (F+4)
CFG.B[5] = 0
SDI
CFG.B[15:12] = 1000b
CFG.B[11:6]
CFG.B[4:0] = 00000b
N is a function of the device configuration, as described in 表7-4.
图7-9. Exit STANDBY Mode
See the Timing Requirements table for timing specifications for this operating mode.
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7.5.4.2 Software Power-Down (SPD) Mode
In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down.
However, the contents of the REFDAC_A and REFDAC_B registers are retained.
As shown in 图 7-10, to enter SPD mode, the device must be selected (by bringing CS low) and SDI must be
kept high for a minimum of 48 SCLK cycles during frame (F). The device goes to SPD on the CS rising edge
following frame (F). While in SPD mode, SDO_A and SDO_B go to 3-state irrespective of the status of the CS
signal.
To remain in SPD mode, SDI must remain high in all subsequent frames.
Device enters SPD
mode
Frame (F)
Frame (F+1)
Device in SPD
mode
CS
1
2
3
47
1
2
SCLK
48
SDO-A and
SDO-B
Valid Data as per device configuration
SDI
图7-10. Enter SPD Mode
As shown in 图 7-11, to exit SPD mode, the device must be selected (by bringing CS low) and SDI must be kept
low for a minimum of 48 SCLK cycles during frame (F+3). The device starts powering-up on a CS rising edge
following frame (F+3). After frame (F+3), a delay of tPU_SPD must elapse before programming the configuration
register.
A valid write operation in frame (F+4) sets the device configuration for frame (F+5). Frame (F+4) must have at
least 48 SCLK falling edges. Discard the output data in frame (F+4).
Frame (F+2)
Frame (F+3)
Frame (F+4)
Frame (F+5)
Device exits
SPD
tPU_SPD
Device in
SPD
CS
SCLK
1
2
47
48
1
2
15
16
48
1
2
15
16
N
SDO-A
and
SDO-B
Invalid Data
Valid Data as per device configuration
CFG settings for Frame (F+6)
SDI
CFG settings for Frame (F+5)
N is a function of the device configuration, as described in 表7-4.
图7-11. Exit SPD Mode
See the Timing Requirements table for timing specifications for this operating mode.
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7.5.5 Frame Abort, Reconversion, or Short-Cycling
As shown in 图 7-12, the minimum number of SCLK falling edges (N) that must be provided between the
beginning and end of the frame depends on the serial interface mode. The SCLK falling edges (N) program the
device and retrieve the conversion result. If CS is brought high before the expected number of SCLK falling
edges are provided, the current frame is aborted and the device starts sampling the new analog input signal.
If frame (F) is aborted, then the register write operation attempted in frame (F) is considered invalid and the
internal registers are not updated. The device continues to have the same configuration in frame (F+1) from
frame (F).
The output data bits latched before the CS rising edge are still valid data that correspond to sample N.
tPL_CS
tPH_CS_SHRT
CS
1
2
SCLK
SDO
Sample
N
Sample
N + 1
tCONV
tACQ
tPH_CS_SHRT
CS
22
V
23
V
1
2
13
14
15
16
V
17
V
24
V
SCLK
SDO
Data From Sample N
图7-12. Frame Abort, Reconversion, or Short-Cycling Feature
See the Timing Requirements table for timing specifications for this operating mode.
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7.6 Register Maps
7.6.1 ADS8353-Q1 Registers
表 7-11 lists the memory-mapped registers for the ADS8353-Q1 registers. Consider any register offset
addresses not listed in 表7-11 as reserved locations and, therefore, do not modify the register contents.
表7-11. ADS8353-Q1 Registers
Offset
0h
Acronym
CFR
Register Name
Section
节7.6.1.2
节7.6.1.3
CFR register
2h
REFDAC
REFDAC register
Complex bit access types are encoded to fit into small table cells. 表 7-12 shows the codes that are used for
access types in this section.
表7-12. ADS8353-Q1 Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
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7.6.1.1 CFR Register (Offset = 0h) [reset = 0h]
CFR is shown in 图7-9 and described in 表7-13.
Return to 表7-11.
图7-13. CFR Register
15
14
13
12
11
10
9
8
RD_CLK_
MODE
RD_DATA_
LINES
WRITE_READ_CFR[3:0]
R/W-0000b
INPUT_RANGE RESERVED
R/W-0b
3
R/W-0b
2
R/W-0b
1
R/W-0b
0
7
6
5
4
RD_DATA_
FORMAT
INM_SEL
R/W-0b
REF_SEL
R/W-0b
STANDBY
W-0b
0[3:0]
R/W-0000b
R/W-0b
表7-13. CFR Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
WRITE_READ_CFR[3:0] R/W
0000b
These bits select the user-programmable register.
0011b = Select this combination to read the CFR register
1000b = Select this combination to write to CFR register and enable
bits 11:0
11
10
RD_CLK_MODE
RD_DATA_LINES
R/W
R/W
0b
0b
This bit must be set to 0 (default).
This bit provides data line selection for the serial interface.
0b = Use SDO_A to output ADC_A data and SDO_B to output of
ADC_B data (default)
1b = Use only SDO_A to output of ADC_A data followed by ADC_B
data
9
INPUT_RANGE
R/W
0b
This bit selects the maximum input range for the ADC as a function
of the reference voltage provided to the ADC. See the Analog Inputs
section for more details.
0b = FSR equals VREF
1b = FSR equals 2 × VREF
8
7
RESERVED
INM_SEL
R/W
R/W
0b
0b
This bit must be set to 0 (default).
This bit selects the voltage to be externally connected to the INM pin.
0b = INM must be externally connected to the GND potential
(default)
1b = INM must be externally connected to the FSR_ADC_x / 2
6
5
REF_SEL
STANDBY
R/W
0b
0b
This bit selects the ADC reference voltage source. See the
Reference section for more details.
0b = Use external reference (default)
1b = Use internal reference
W
This bit is used by the device to enter or exit STANDBY mode. See
the STANDBY Mode section for more details.
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表7-13. CFR Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
RD_DATA_FORMAT
R/W
0b
This bit selects the output data format.
0b = Output is in straight binary format (default)
1b = Output is in two's complement format
3-0
0[3:0]
R/W
0000b
These bits must be set to 0 (default).
7.6.1.2 REFDAC Register (Offset = 2h) [reset = 0h]
REFDAC is shown in 图7-10 and described in 表7-14.
Return to 表7-11.
图7-14. REFDAC Register
15
14
13
12
11
10
9
8
0
WRITE_READ_REFDAC[3:0]
R/W-0000b
D[8:0]
R/W-000000000b
7
6
5
4
3
2
1
D[8:0]
RESERVED
R/W-000b
R/W-000000000b
表7-14. REFDAC Register Field Descriptions
Bit
Field
WRITE_READ_REFDAC[3:0]
Type
Reset
Description
15-12
R/W
0000b
These bits select the configurable register address.
1001 = Select this combination to write to the REFDAC_A register
1010 = Select this combination to write to the REFDAC_B register
11-3
D[8:0]
R/W
R/W
000000000b
Data to program the individual DAC output voltage.
These bits are valid only for bits 15:12 = 1001 or bits 15:12 = 1010.
表7-15 shows the relationship between the REFDAC_x programmed value
and the DAC_x output voltage.
2-0
RESERVED
000b
This bit must be set to 0 (default).
表7-15. REFDAC Settings
REFDAC_x VALUE (Bits 11:3 in Hex)
B[2:0]
Typical DAC_x OUPTUT VOLTAGE (V)(1)
1FF (default)
1FE
000
000
000
2.5000
2.4989
2.4978
1FD
—
—
—
1D7
000
2.45
—
—
—
1AE
000
2.40
—
—
—
186
000
2.35
—
—
—
15D
000
2.30
—
—
—
134
000
2.25
—
—
—
10C
000
2.20
—
—
—
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表7-15. REFDAC Settings (continued)
REFDAC_x VALUE (Bits 11:3 in Hex)
B[2:0]
Typical DAC_x OUPTUT VOLTAGE (V)(1)
0E3
000
2.15
—
—
—
0BA
000
2.10
—
—
—
091
000
2.05
—
—
—
069
000
2.00
—
—
—
064 to 000
000
Do not use
(1) Actual output voltage may vary by a few millivolts from the specified value. To obtain the desired output voltage, TI recommends
starting with the specified register setting and then experimenting with five codes on either side of the specified register setting.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, and some application circuits designed using
these devices.
The device supports operation either with an internal or external reference source. See the Reference section for
details about the decoupling requirements.
The reference source to the ADC must provide low-drift and very accurate dc voltage and support the dynamic
charge requirements without affecting the noise and linearity performance of the device. The output broadband
noise (typically in the order of a few 100 μVRMS) of the reference source must be appropriately filtered by using
a low-pass filter with a cutoff frequency of a few hundred hertz. After band-limiting the noise from the reference
source, the next important step is to design a reference buffer that can drive the dynamic load posed by the
reference input of the ADC. At the start of each conversion, the reference buffer must regulate the voltage of the
reference pin within 1 LSB of the intended value. This condition necessitates the use of a large filter capacitor at
the reference pin of the ADC. The amplifier selected to drive the reference input pin must be stable while driving
this large capacitor and must have low output impedance, low offset, and temperature drift specifications. To
reduce the dynamic current requirements and crosstalk between the channels, a separate reference buffer is
recommended for driving the reference input of each ADC channel.
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an charge
kickback filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-
end circuit is critical to meet the linearity and noise performance of a high-precision ADC.
8.1.1 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC
inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. Select the
amplifier bandwidth as described in 方程式6 to maintain the overall stability of the input driver circuit:
≈
’
1
∆
∆
÷
÷
Unity - Gain Bandwidth í 4ì
2p
ì(RFLT + RFLT )ìCFLT
«
◊
(6)
• Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in
SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, keep the total noise contribution from the front-end
circuit below 20% of the input-referred noise of the ADC. 方程式7 calculates noise from the input driver
circuit. This noise is band-limited by designing a low cutoff frequency RC filter:
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2
SNR dB
(
20
)
≈
∆
’
÷
V
≈
∆
’
÷
-
1
f
_ AMP_PP
p
2
1
5
VREF
2
NG ì 2 ì
+ en2_RMS
ì
ì f-3dB
Ç
ì
ì10
«
◊
∆
∆
÷
÷
6.6
«
◊
(7)
where:
– V1/f_AMP_PP = the peak-to-peak flicker noise in µV
– en_RMS = the amplifier broadband noise density in nV/√Hz
– f–3dB = the 3-dB bandwidth of the RC filter
– NG = the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration
• Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC, as shown
in 方程式8, to ensure that the distortion performance of the data acquisition system is not limited by the front-
end circuit.
THDAMP Ç THDADC - 10
dB
(8)
• Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input
signal must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, always verify the settling behavior of the input driver with TINA™-SPICE
simulations before selecting the amplifier.
8.1.2 Charge Kickback Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, charge kickback filter must be used to remove
the harmonic content from the input signal before being sampled by the ADC. A charge kickback filter is
designed as a low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application
requirements. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is
designed to allow accurately settling the signal at the ADC inputs during the small acquisition time window. For
ac signals, keep the filter bandwidth low to band-limit the noise fed into the ADC input, thereby increasing the
signal-to-noise ratio (SNR) of the system.
A filter capacitor, CFLT, connected across the ADC inputs (see 图 8-1), filters the noise from the front-end drive
circuitry, reduces the sampling charge injection, and provides a charge bucket to quickly charge the internal
sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor must
be at least 10 times the specified value of the ADC sampling capacitance. For these devices, the input sampling
capacitance is equal to 40 pF. Thus, the value of CFLT must be greater than 400 pF. The capacitor must be a
COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable
electrical characteristics under varying voltages, frequency, and time.
RFLT
1
CFLT
AINP
ADS8353-Q1
AINM
f-3dB
=
2Πx RFLT x CFLT
GND
RFLT
CFLT
GND
图8-1. Charge Kickback Filter
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Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source
impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires
balancing the stability and distortion of the design. For more information on ADC input R-C filter component
selection, see the TI Precision Labs on ti.com.
8.2 Typical Application
Input Driver
AVDD
AVDD
OPA320-Q1
œ
49 ꢀ
AINP
AINM
+
3.3nF
3.3nF
Device
+
VIN
œ
GND
49 ꢀ
VDC
Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels.
图8-2. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at Full Throughput, 32-CLK Interface
AVDD
10 µF
REFGND_A
AVDD
0.1 ꢀ
ADC_A
REFIN_A
œ
1 kꢀ
+
REF34-Q1
VOUT
1µF
ADS8353-Q1
AVDD
10 µF
œ
1 kꢀ
REFIN_B
ADC_B
+
0.1 ꢀ
1µF
REFGND_B
OPA2320-Q1
10 µF
图8-3. Reference Drive Circuit
8.2.1 Design Requirements
表8-1 lists the target specifications for this application.
表8-1. Target Specifications
TARGET SPECIFICATIONS
TEST CONDITIONS
INPUT SIGNAL
FREQUENCY
SNR
THD
DEVICE
THROUGHPUT
INTERFACE MODE
> 83 dB
ADS8353-Q1
10 kHz
Maximum supported
32-CLK, dual-SDO
< –100 dB
8.2.2 Detailed Design Procedure
Best practice is for the distortion from the input driver to be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of rail-to-rail swing at the amplifier input. The low-power OPA320-Q1, used as an input driver,
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provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal.
The application circuit illustrated in 图8-2 is optimized to achieve the lowest distortion and lowest noise for a
10-kHz input signal fed to the ADS8353-Q1 operating at full throughput with the default 32-CLK, dual-SDO
interface mode. The input signal is processed through a high-bandwidth, low-distortion amplifier in an inverting
gain configuration and a low-pass RC filter before being fed into the device.
图 8-3 illustrates the reference driver circuit when operation with an external reference is desired. The reference
voltage is generated by the high-precision, low-noise REF34-Q1 circuit. The output broadband noise of the
reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The decoupling capacitor
on each reference pin is selected to be 10 µF. The low output impedance, low noise, and fast settling time make
the OPA2320-Q1 a good choice for driving this high capacitive load.
8.2.3 Application Curve
To minimize external components and to maximize the dynamic range of the ADC, the device is configured to
operate with internal reference (CFR.B6 = 1) and 2x VREF_x input full-scale range (CFR.B9 = 1).
图 8-4 shows the FFT plot and test result obtained with the ADS8353-Q1 operating at full throughput with a 32-
CLK interface and the circuit configuration of 图8-2.
0
œ20
œ40
œ60
œ80
œ100
œ120
œ140
œ160
œ180
œ200
0
60
120
180
240
300
C301
Input Frequency (kHz)
SNR = 83.5 dB, THD = –101.2 dB, fIN = 10.1 kHz
图8-4. ADS8353-Q1 in 32-CLK Interface Mode
8.3 Power Supply Recommendations
The device has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is used
for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible ranges.
When using the device with the 2× VREF input range (CFR.B9 = 1), the AVDD supply voltage value defines the
permissible voltage swing on the analog input pins. AVDD must be set as shown in 方程式 9, 方程式 10, and 方
程式11 to avoid saturation of output codes and to use the full dynamic range on the analog input pins:
AVDD ≥2 × VREF_A
AVDD ≥2 × VREF_B
4.75 V ≤AVDD ≤5.25 V
(9)
(10)
(11)
Decouple the AVDD and DVDD pins, as shown in 图 8-5, with the GND pin using individual 10-µF decoupling
capacitors.
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Device
AVDD
AVDD (Pin 16)
10 …F
GND (Pin 15)
DVDD (Pin 9)
10 …F
DVDD
图8-5. Power-Supply Decoupling
8.4 Layout
8.4.1 Layout Guidelines
图 8-6 shows a board layout example for the ADS8353-Q1 TSSOP package. Partition the printed circuit board
(PCB) into analog and digital sections. Avoid crossing digital lines with the analog signal path and keep the
analog input signals and the reference input signals away from noise sources. As shown in 图 8-6, the analog
input and reference signals are routed on the left side of the board and the digital connections are routed on the
right side of the device.
The power sources to the device must be clean and well-bypassed. Use 10-μF, ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the
AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low
impedance paths.
The REFIO-A and REFIO-B reference inputs and outputs are bypassed with 10-μF, X7R-grade, 0805-size, 16-V
rated ceramic capacitors (CREF-x). Place the reference bypass capacitors as close as possible to the reference
REFIO-x pins and connect the bypass capacitors using short, low-inductance connections. Avoid placing vias
between the REFIO-x pins and the bypass capacitors. Small 0.1-Ωto 0.2-Ωresistors (RREF-x) are used in series
with the reference bypass capacitors to improve stability.
The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,
COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG
(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and
temperature changes. 图 8-6 shows CIN-A and CIN-B filter capacitors placed across the analog input pins of the
device.
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8.4.2 Layout Example
GND
RFLT-A
1
CIN-A
16
AVDD
AINP_A
AINM_A
REFIO_A
CIN-A
CAVDD
GND 15
2
3
GND
RFLT-A
CREF-A
GND
RREF-A
SDO_B
14
SDO_A
SCLK
13
12
REFGND_A
REFGND_B
4
5
CREF-B
RREF-B
CS
11
10
REFIO_B
AINM_B
6
7
RFLT-B
SDI
CIN-B
CIN-B
9
AINP_B
8
DVDD
CDVDD
RFLT-B
GND
GND
图8-6. Recommended Layout
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
Texas Instruments, TI Precision Labs TI training and videos site
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx320-Q1 Precision, 20-MHz, 0.9-pA, low-noise, RRIO, CMOS operational amplifier
data sheet
• Texas Instruments, REF34-Q1 Low-drift, low-power, small-footprint series voltage references data sheet
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TINA™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8353QPWQ1
ADS8353QPWRQ1
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
A8353Q
A8353Q
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2021
OTHER QUALIFIED VERSIONS OF ADS8353-Q1 :
Catalog : ADS8353
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8353QPWRQ1
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
ADS8353QPWRQ1
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS8353QPWQ1
16
90
530
10.2
3600
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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