AMC1300BQDWVRQ1 [TI]
汽车类 ±250mV 输入、精密电流检测增强型隔离式放大器 | DWV | 8 | -40 to 125;型号: | AMC1300BQDWVRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 汽车类 ±250mV 输入、精密电流检测增强型隔离式放大器 | DWV | 8 | -40 to 125 放大器 |
文件: | 总33页 (文件大小:1870K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AMC1300B-Q1
ZHCSL27B –APRIL 2020 –REVISED JUNE 2022
AMC1300B-Q1 汽车类±250mV 输入、精密增强型隔离放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准:
– 温度等级1: –40 ° C 至125 ° C 、T A
• 提供功能安全
AMC1300B-Q1 是一款隔离式精密放大器,此放大器
的输出与输入电路由抗电磁干扰性能极强的隔离栅隔
开。该隔离栅经认证可提供高达5kVRMS 的增强型电隔
离,符合 DIN EN IEC 60747-17 (VDE 0884-17) 和
UL1577 标准,并且可支持高达 1.5kVRMS 的工作电
压。
– 有助于进行功能安全系统设计的文档
• ±250mV 输入电压范围,针对使用分流电阻器测量
电流进行了优化
• 固定增益:8.2 V/V
• 低直流误差:
该隔离栅可将系统中以不同共模电压电平运行的各器件
隔开,并保护电压较低的器件免受高电压冲击。
– 失调电压误差:±0.2mV(最大值)
– 温漂±0.9µV/°C(最大值)
– 增益误差:±0.3%(最大值)
– 增益漂移:±30ppm/°C(最大值)
– 非线性度:0.03%(最大值)
• 高侧和低侧以3.3V 或5V 电压运行
• 失效防护输出
AMC1300B-Q1 的输入针对直接连接低阻抗分流电阻
器或其他具有低信号电平的低阻抗电压源的情况进行了
优化。出色的直流精度和低温漂支持在 –40°C 至
+125°C 的整个汽车温度范围内,在 PFC 级、直流/直
流转换器、牵引逆变器和 OBC 中进行精确的电流控
制。
集成的无分流器和无高侧电源检测功能可简化系统级设
计和诊断。
• 高CMTI:100kV/µs(最小值)
• 低EMI,符合CISPR-11 和CISPR-25 标准
• 安全相关认证:
器件信息(1)
– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标
准的7071VPK 增强型隔离
封装尺寸(标称值)
器件型号
封装
SOIC (8)
AMC1300B-Q1
5.85mm × 7.50mm
– 符合UL1577 标准且长达1 分钟的5000VRMS
隔离
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
2 应用
• 基于分流电阻器的电流感应,可用于:
– HEV/EV 充电桩
– HEV/EV 车载充电器(OBC)
– HEV/EV 直流/直流转换器
– HEV/EV 牵引逆变器
High-side supply
(3.3 V or 5 V)
Low-side supply
(3.3 V or 5 V)
AMC1300B-Q1
VDD1
INP
VDD2
OUTP
I
+250 mV
0 V
VCMout
2.05 V
ADC
œ 250 mV
INN
OUTN
GND2
GND1
典型应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBASA40
AMC1300B-Q1
ZHCSL27B –APRIL 2020 –REVISED JUNE 2022
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Table of Contents
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
8.3 What to Do and What Not to Do............................... 24
9 Power Supply Recommendations................................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 25
11 Device and Documentation Support..........................26
11.1 Documentation Support.......................................... 26
11.2 接收文档更新通知................................................... 26
11.3 支持资源..................................................................26
11.4 Trademarks............................................................. 26
11.5 Electrostatic Discharge Caution..............................26
11.6 术语表..................................................................... 26
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values.................................................7
6.9 Electrical Characteristics.............................................8
6.10 Switching Characteristics..........................................9
6.11 Timing Diagram.........................................................9
6.12 Insulation Characteristics Curves........................... 10
6.13 Typical Characteristics............................................ 11
7 Detailed Description......................................................18
7.1 Overview...................................................................18
Information.................................................................... 26
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2021) to Revision B (June 2022)
Page
• 将隔离标准从DIN VDE V 0884-11 (VDE V 0884-11) 更改为DIN EN IEC 60747-17 (VDE 0884-17),并相应更
新了绝缘规格和安全相关认证表....................................................................................................................... 1
• 向特性列表添加了提供功能安全型要点.............................................................................................................1
• Changed external clearance (CLR) from ≥9 mm to ≥8.5 mm..........................................................................6
• Changed CIO from ~1 pF to ~1.5 pF...................................................................................................................6
Changes from Revision * (April 2020) to Revision A (January 2021)
Page
• Changed external clearance (CLR) from ≥8.5 mm to ≥9 mm..........................................................................6
• Changed TCVOS from ±3 µV/°C to ±0.9 µV/°C...................................................................................................8
• Changed TCEG from ±50 ppm/°C to ±30 ppm/°C...............................................................................................8
• Changed VDD1UV from 1.75 V (min) / 2.53 V (typ) / 2.7 V (max) to 2.4 V (min) / 2.6 V (typ) / 2.8 V (max)....... 8
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5 Pin Configuration and Functions
VDD1
INP
1
2
3
4
8
7
6
5
VDD2
OUTP
OUTN
GND2
INN
GND1
Not to scale
图5-1. DWV Package, 8-Pin SOIC (Top View)
表5-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
2
VDD1
INP
High-side power
Analog input
High-side power supply.(1)
Noninverting analog input. Either INP or INN must have a DC current path to GND1
to define the common-mode input voltage.(2)
Inverting analog input. Either INP or INN must have a DC current path to GND1 to
define the common-mode input voltage.(2)
3
INN
Analog input
4
5
6
7
8
GND1
GND2
OUTN
OUTP
VDD2
High-side ground
Low-side ground
Analog output
High-side analog ground.
Low-side analog ground.
Inverting analog output.
Noninverting analog output.
Low-side power supply.(1)
Analog output
Low-side power
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
(2) See the Layout section for details.
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
MIN
–0.3
MAX
UNIT
High-side VDD1 to GND1
6.5
6.5
Power-supply voltage
V
Low-side VDD2 to GND2
–0.3
Analog input voltage
Output voltage
Input current
INP, INN
VDD1 + 0.5
VDD2 + 0.5
10
V
V
GND1 –6
GND2 –0.5
–10
OUTP, OUTN
Continuous, any pin except power-supply pins
mA
Junction, TJ
Storage, Tstg
150
Temperature
°C
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification Level 2
,
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011,
CDM ESD classification Level C6
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
High-side power supply
Low-side power supply
ANALOG INPUT
VClipping Differential input voltage before clipping output
VDD1 to GND1
VDD2 to GND2
3
3
5
5.5
5.5
V
V
3.3
±320
mV
mV
VIN = VINP –VINN
VIN = VINP –VINN
VFSR
VCM
Specified linear differential full-scale voltage
Operating common-mode input voltage
250
–250
VDD1 –
2.1
(VINP + VINN) / 2 to GND1
V
–0.16
TEMPERATURE RANGE
TA Specified ambient temperature
125
°C
–40
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6.4 Thermal Information
AMC1300B-Q1
THERMAL METRIC(1)
DWV (SOIC)
8 PINS
85.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
26.8
RθJB
ψJT
Junction-to-board thermal resistance
43.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.8
41.2
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
VALUE
99
UNIT
PD
Maximum power dissipation (both sides) VDD1 = VDD2 = 5.5 V
mW
VDD1 = 3.6 V
Maximum power dissipation (high-side)
VDD1 = 5.5 V
31
PD1
mW
mW
54
VDD2 = 3.6 V
Maximum power dissipation (low-side)
VDD2 = 5.5 V
26
PD2
45
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UNIT
6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance(1)
External creepage(1)
Shortest pin-to-pin distance through air
mm
mm
≥8.5
≥8.5
CPG
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance) of the double
insulation
DTI
CTI
Distance through insulation
mm
V
≥0.021
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
≥600
I
I-IV
I-III
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
Overvoltage category
per IEC 60664-1
DIN EN IEC 60747-17 (VDE 0884-17)(2)
Maximum repetitive peak
VIORM
At AC voltage
2120
VPK
isolation voltage
At AC voltage (sine wave)
1500
2120
7000
8400
9800
VRMS
VDC
Maximum-rated isolation
VIOWM
working voltage
At DC voltage
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Tested in air, 1.2/50-µs waveform per IEC 62368-1
Maximum transient
VIOTM
VPK
isolation voltage
VIMP
Maximum impulse voltage(3)
VPK
VPK
Maximum surge
Tested in oil (qualification test),
1.2/50-µs waveform per IEC 62368-1
VIOSM
12800
≤5
isolation voltage(4)
Method a, after input/output safety test subgroups 2 and 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
qpd
Apparent charge(5)
pC
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875
× VIORM, tm = 1 s
≤5
Barrier capacitance,
input to output(6)
CIO
RIO
VIO = 0.5 VPP at 1 MHz
~1.5
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(6)
VIO = 500 V at 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
55/125/21
UL1577
VTEST = VISO = 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
VISO
Withstand isolation voltage
5000
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
DIN EN IEC 60747-17 (VDE 0884-17),
EN IEC 60747-17,
DIN EN IEC 62368-1 (VDE 0868-1),
EN IEC 62368-1,
Recognized under 1577 component recognition
IEC 62368-1 Clause : 5.4.3 ; 5.4.4.4 ; 5.4.9
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-
heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 85.4°C/W, VDDx = 5.5 V,
IS
IS
Safety input, output, or supply current
266
mA
TJ = 150°C, TA = 25°C
θJA = 85.4°C/W, VDDx = 3.6 V,
TJ = 150°C, TA = 25°C
θJA = 85.4°C/W, TJ = 150°C, TA = 25°C
R
Safety input, output, or supply current
407
mA
PS
TS
Safety input, output, or total power
Maximum safety temperature
R
1464
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP
= –250 mV to +250 mV, and INN = GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUT
Common-mode overvoltage
detection level
VCMov
(VINP + VINN) / 2 to GND1
V
VDD1 –2
Hysteresis of common-mode
overvoltage detection level
60
mV
VOS
Input offset voltage(1)
Input offset drift(1) (4)
Initial, at TA = 25°C, INP = INN = GND1
±0.01
±0.1
–100
–98
19
0.2
mV
–0.2
–0.9
TCVOS
0.9 µV/°C
fIN = 0 Hz, VCM min ≤VCM ≤VCM max
fIN = 10 kHz, VCM min ≤VCM ≤VCM max
INN = GND1
CMRR
Common-mode rejection ratio
dB
RIN
RIND
IIB
Single-ended input resistance
Differential input resistance
Input bias current
kΩ
kΩ
22
INP = INN = GND1; IIB = (IIBP + IIBN) / 2
µA
nA
pF
pF
–41
–30
±5
2
–24
IIO
Input offset current
IIO = IIBP –IIBN; INP = INN = GND1
INN = GND1, fIN = 275 kHz
fIN = 275 kHz
CIN
CIND
Single-ended input capacitance
Differential input capacitance
1
ANALOG OUTPUT
Nominal gain
8.2
±0.04%
±5
V/V
EG
Gain error(1)
at TA = 25°C
0.3%
–0.3%
–30
TCEG
Gain drift(1) (5)
30 ppm/°C
0.03%
Nonlinearity(1)
±0.01%
–85
–0.03%
THD
SNR
Total harmonic distortion(3)
fIN = 10 kHz
dB
INP = INN = GND1, fIN = 0 Hz,
BW = 100 kHz brickwall filter
Output noise
230
µVRMS
fIN = 1 kHz, BW = 10 kHz
fIN = 10 kHz, BW = 100 kHz
PSRR vs VDD1, at DC
81.5
85
72
Signal-to-noise ratio
dB
dB
–103
PSRR vs VDD1,
100-mV and 10-kHz ripple
–96
–106
–86
PSRR
Power-supply rejection ratio(2)
PSRR vs VDD2, at DC
PSRR vs VDD2,
100-mV and 10-kHz ripple
VCMout
Common-mode output voltage
1.39
1.44
1.49
2.52
V
V
VOUT = (VOUTP –VOUTN);
|VIN| = |VINP –VINN| > |VClipping
VCLIPout
Clipping differential output voltage
±2.49
–2.52
|
VFailsafe
BW
Failsafe differential output voltage
Output bandwidth
V
kHz
Ω
V
CM ≥VCMov, or VDD1 missing
–2.63
–2.57
310
–2.53
250
ROUT
Output resistance
On OUTP or OUTN
< 0.2
On OUTP or OUTN, sourcing or sinking,
INN = INP = GND1, outputs shorted to
either GND2 or VDD2
Output short-circuit current
14
mA
CMTI
Common-mode transient immunity
100
150
kV/µs
|GND1 –GND2| = 1 kV
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP
= –250 mV to +250 mV, and INN = GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
VDD1 undervoltage detection
threshold voltage
VDD1UV
IDD1
VDD1 falling
2.4
2.6
2.8
V
6.3
7.2
5.3
5.9
8.5
9.8
7.2
8.1
3.0 V ≤VDD1 ≤3.6 V
4.5 V ≤VDD1 ≤5.5 V
3.0 V ≤VDD2 ≤3.6 V
4.5 V ≤VDD2 ≤5.5 V
High-side supply current
Low-side supply current
mA
IDD2
mA
(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.
(2) This parameter is input referred.
(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (VOS,MAX - VOS,MIN) / TempRange where VOS,MAX and VOS,MIN refer to the maximum and minimum VOS values measured
within the temperature range (–40 to 125℃).
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %)
measured within the temperature range (–40 to 125℃).
6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.3
1.3
1
MAX
UNIT
µs
tr
tf
Output signal rise time
Output signal fall time
µs
VINx to VOUTx signal delay (50% - 10%)
VINx to VOUTx signal delay (50% - 50%)
VINx to VOUTx signal delay (50% - 90%)
Unfiltered output
1.5
2.1
3
µs
Unfiltered output
Unfiltered output
1.6
2.5
µs
µs
VDD1 step to 3.0 V with VDD2 ≥3.0 V,
to VOUTP, VOUTN valid, 0.1% settling
tAS
Analog settling time
500
µs
6.11 Timing Diagram
250 mV
INP - INN
0
œ 250 mV
tf
tr
OUTN
OUTP
VCMout
50% - 10%
50% - 50%
50% - 90%
图6-1. Rise, Fall, and Delay Time Definition
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6.12 Insulation Characteristics Curves
500
1600
1400
1200
1000
800
600
400
200
0
VDD1 = VDD2 = 3.6 V
VDD1 = VDD2 = 5.5 V
400
300
200
100
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
75
TA (°C)
100
125
150
D070
D069
图6-3. Thermal Derating Curve for Safety-Limiting
图6-2. Thermal Derating Curve for Safety-Limiting
Power per VDE
Current per VDE
1.E+11
87.5 %
254 Yrs
1.E+10
135 Yrs
1.E+09
1.E+08
1.E+07
TDDB Line (< 1 ppm Fail Rate)
VDE Safety Margin Zone
1.E+06
Operating Zone
1.E+05
1.E+04
1.E+03
20 %
1.E+02
1.E+01
500
1500
2500
3500
4500
5500
6500
7500
Applied Voltage (VRMS
)
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 year
图6-4. Reinforced Isolation Capacitor Lifetime Projection
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6.13 Typical Characteristics
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
3.8
3.4
3
3.3
3.25
3.2
3.15
3.1
2.6
2.2
1.8
1.4
1
3.05
3
2.95
2.9
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
3
3.5
4
4.5
VDD1 (V)
5
5.5
D002
D001
图6-6. Common-Mode Overvoltage Detection Level vs
图6-5. Common-Mode Overvoltage Detection Level vs High-
Temperature
Side Supply Voltage
50
40
30
20
10
0
200
VDD1
VDD2
150
100
50
0
-50
-100
-150
-200
3
3.5
4
4.5
VDDx (V)
5
5.5
D023
D027
VOS (mV)
图6-8. Input Offset Voltage vs Supply Voltage
图6-7. Input Offset Voltage Histogram
200
50
40
30
20
10
0
Device 1
Device 2
Device 3
150
100
50
0
-50
-100
-150
-200
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D024
D026
TCVOS (mV/èC)
图6-9. Input Offset Voltage vs Temperature
图6-10. Input Offset Drift Histogram
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
0
-70
-75
-20
-80
-40
-85
-60
-90
-95
-80
-100
-105
-110
-100
-120
0.001
0.01
0.1
1
fIN (kHz)
10
100
1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D038
D039
图6-11. Common-Mode Rejection Ratio vs Input Frequency
图6-12. Common-Mode Rejection Ratio vs Temperature
25
-23
-25
-27
-29
-31
-33
-35
-37
-39
-41
15
5
-5
-15
-25
-35
-45
-0.5
0
0.5
1
1.5
2
2.5
3
3
3.5
4
4.5
VDD1 (V)
5
5.5
VCM (V)
D003
D004
图6-13. Input Bias Current vs Common-Mode Input Voltage
图6-14. Input Bias Current vs High-Side Supply Voltage
-23
-25
-27
-29
-31
-33
-35
-37
-39
-41
50
40
30
20
10
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D018
EG (%)
D005
图6-16. Gain Error Histogram
图6-15. Input Bias Current vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
0.3
0.2
0.1
0
0.3
0.2
0.1
0
Device 1
Device 2
Device 3
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
VDD1
VDD1
3
3.5
4
4.5
VDDx (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D020
D021
图6-17. Gain Error vs Supply Voltage
图6-18. Gain Error vs Temperature
50
40
30
20
10
0
5
0
-5
-10
-15
-20
-25
-30
-35
-40
1
10
100
1000
D019
fIN (kHz)
TCEG (ppm/èC)
D007
图6-19. Gain Error Drift Histogram
图6-20. Normalized Gain vs Input Frequency
0°
-45°
5
4.5
4
OUTN
OUTP
-90°
3.5
3
-135°
-180°
-225°
-270°
-315°
-360°
2.5
2
1.5
1
0.5
0
1
10
100
1000
-350
-250
-150
-50
50
150
Differential Input Voltage (mV)
250
350
fIN (kHz)
D008
D006
图6-21. Output Phase vs Input Frequency
图6-22. Output Voltage vs Input Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
0.03
0.025
0.02
0.03
0.02
0.01
0
VDD1
VDD2
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.025
-0.03
-0.01
-0.02
-0.03
-250 -200 -150 -100 -50
0
Differential Input Voltage (mV)
50 100 150 200 250
3
3.5
4
4.5
VDDx (V)
5
5.5
D028
D029
图6-23. Nonlinearity vs Input Voltage
图6-24. Nonlinearity vs Supply Voltage
0.03
0.02
0.01
0
-70
-75
Device 1
Device 2
Device 3
VDD1
VDD2
-80
-85
-0.01
-0.02
-0.03
-90
-95
-100
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
VDDx (V)
5
5.5
D030
D056
图6-25. Nonlinearity vs Temperature
图6-26. Total Harmonic Distortion vs Supply Voltage
-70
-75
10000
1000
100
10
-80
-85
-90
Device 1
Device 2
Device 3
-95
-100
0.1
1
10
Frequency (kHz)
100
1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D017
D059
图6-28. Input-Referred Noise Density vs Frequency
图6-27. Total Harmonic Distortion vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
80
75
70
65
60
55
50
45
40
80
77.5
75
VDD1
VDD2
72.5
70
67.5
65
62.5
60
3
3.5
4
4.5
VDDx (V)
5
5.5
0
50
100
150
|VINP - VINN| (mV)
200
250
300
D034
D032
图6-30. Signal-to-Noise Ratio vs Supply Voltage
图6-29. Signal-to-Noise Ratio vs Input Voltage
80
0
77.5
75
-20
-40
-60
72.5
70
67.5
65
-80
Device 1
Device 2
Device 3
-100
62.5
60
VDD2
VDD1
-120
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0.001
0.01
0.1
1
10
Ripple Frequency (kHz)
100
1000
D035
D041
图6-31. Signal-to-Noise Ratio vs Temperature
图6-32. Power-Supply Rejection Ratio vs Ripple Frequency
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
1.39
1.39
3
3.5
4
4.5
VDD2 (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D009
D010
图6-33. Output Common-Mode Voltage vs Low-Side Supply
图6-34. Output Common-Mode Voltage vs Temperature
Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
360
340
320
300
280
260
240
360
340
320
300
280
260
240
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
VDD2 (V)
5
5.5
D012
D011
图6-36. Output Bandwidth vs Temperature
图6-35. Output Bandwidth vs Low-Side Supply Voltage
8.5
8
8.5
8
7.5
7
7.5
7
6.5
6
6.5
6
5.5
5
5.5
5
4.5
4.5
4
IDD1 vs VDD1
IDD2 vs VDD2
IDD1
IDD2
4
3.5
3.5
3
3.5
4
4.5
VDDx (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D043
D044
图6-37. Supply Current vs Supply Voltage
图6-38. Supply Current vs Temperature
4
3.5
3
4
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
3
3.5
4
4.5
VDD2 (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D065
D066
图6-39. Output Rise and Fall Time vs Low-Side Supply
图6-40. Output Rise and Fall Time vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, INP = –250 mV to 250 mV, INN = 0 V, and fIN = 10 kHz (unless otherwise noted)
3.8
3.4
3
3.8
3.4
3
50% - 90%
50% - 50%
50% - 10%
50% - 90%
50% - 50%
50% - 10%
2.6
2.2
1.8
1.4
1
2.6
2.2
1.8
1.4
1
0.6
0.2
0.6
0.2
3
3.5
4
4.5
VDD2 (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D067
D068
图6-41. VIN to VOUT Signal Delay vs Low-Side Supply Voltage
图6-42. VIN to VOUT Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC1300B-Q1 is a fully differential, precision, isolated amplifier. The input stage of the device consists of a
fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the
analog input signal into a digital bitstream that is transferred across the isolation barrier that separates the high-
side from the low-side. On the low-side, the received bitstream is processed by a fourth-order analog filter that
outputs a differential signal at the OUTP and OUTN pins that is proportional to the input signal.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the
ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the
AMC1300B-Q1 to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result
in high reliability and common-mode transient immunity.
7.2 Functional Block Diagram
VDD1
INP
VDD2
OUTP
OUTN
GND2
AMC1300B-Q1
Diagnostics
Analog Filter
ûꢀ Modulator
INN
GND1
7.3 Feature Description
7.3.1 Analog Input
The differential amplifier input stage of the AMC1300B-Q1 feeds a second-order, switched-capacitor, feed-
forward ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a
differential input impedance of RIND. The modulator converts the analog input signal into a bitstream that is
transferred across the isolation barrier, as described in the Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signals INP and INN. First, if the input voltages VINP or VINN
exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the
absolute maximum value, because the electrostatic discharge (ESD) protection turns on. In addition, the linearity
and parametric performance of the device are ensured only when the analog input voltage remains within the
linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the
Recommended Operating Conditions table.
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7.3.2 Isolation Channel Signal Transmission
The AMC1300B-Q1 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-1, to transmit the
modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the
Functional Block Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier to
represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC1300B-Q1 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides the
input to the 4th-order analog filter. The AMC1300B-Q1 transmission channel is optimized to achieve the highest
level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the high-
frequency carrier and RX/TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图7-1. OOK-Based Modulation Scheme
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7.3.3 Analog Output
The AMC1300B-Q1 offers a differential analog output comprised of the OUTP and OUTN pins. For differential
input voltages (VINP – VINN) in the range from –250 mV to 250 mV, the device provides a linear response with
a nominal gain of 8.2. For example, for a differential input voltage of 250 mV, the differential output voltage
(VOUTP – VOUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output
voltage VCMout, as specified in the Electrical Characteristics table. For absolute differential input voltages greater
than 250 mV but less than 320 mV, the differential output voltage continues to increase in magnitude but with
reduced linearity performance. The outputs saturate at a differential output voltage of VCLIPout, as shown in 图
7-2, if the differential input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping
)
Linear input range (VFSR
)
VOUTN
VCLIPout
VOUTP
VFAILSAFE
VCMout
œ 320 mV
œ 250 mV
320 mV
0
250 mV
Differential Input Voltage (VINP œ VINN
)
图7-2. Output Behavior of the AMC1300B-Q1
The AMC1300B-Q1 offers a failsafe feature that simplifies diagnostics on system level. 图 7-2 shows the failsafe
mode, in which the AMC1300B-Q1 outputs a negative differential output voltage that does not occur under
normal operating conditions. The failsafe output is active in two cases:
• When the high-side supply is missing or below the VDD1UV threshold
• When the common-mode input voltage, that is VCM = (VINP + VINN) / 2, exceeds the common-mode
overvoltage detection level VCMov
Use the maximum VFAILSAFE voltage specified in the Electrical Characteristics table as a reference value for
failsafe detection on system level.
7.4 Device Functional Modes
The AMC1300B-Q1 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The low analog input voltage range, excellent accuracy, and low temperature drift make the AMC1300B-Q1 a
high-performance solution for automotive applications where shunt-based current sensing in the presence of
high common-mode voltage levels is required.
8.2 Typical Application
The AMC1300B-Q1 is ideally suited for shunt-based current sensing applications where accurate current
monitoring is required in the presence of high common-mode voltages.
图 8-1 shows the AMC1300B-Q1 in a typical application. The load current flowing through an external shunt
resistor RSHUNT produces a voltage drop that is sensed by the AMC1300B-Q1. The AMC1300B-Q1 digitizes
the analog input signal on the high-side, transfers the data across the isolation barrier to the low-side,
reconstructs the analog signal, and presents that signal as a differential voltage on the output pins.
The differential input, differential output, and the high common-mode transient immunity (CMTI) of the
AMC1300B-Q1 ensure reliable and accurate operation even in high-noise environments.
Floating Gate
Driver Supply
+ DC Link
Low-side supply
(3.3 V or 5 V)
1 uF 100 nF
1 uF 100 nF
AMC1300B-Q1
VDD1
INP
VDD2
OUTP
OUTN
GND2
10 Ω
10 Ω
10 Ω
10 Ω
10 nF
10 nF
RSHUNT
ADC
INN
Load
GND1
œ DC Link
图8-1. Using the AMC1300B-Q1 for Current Sensing in a Typical Application
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8.2.1 Design Requirements
表8-1 lists the parameters for this typical application.
表8-1. Design Requirements
PARAMETER
High-side supply voltage
VALUE
3.3 V or 5 V
Low-side supply voltage
3.3 V or 5 V
Voltage drop across RSHUNT for a linear response
Signal delay (50% VIN to 90% OUTP, OUTN)
±250 mV (maximum)
3 µs (maximum)
8.2.2 Detailed Design Procedure
In 图 8-1, the high-side power supply (VDD1) for the AMC1300B-Q1 is derived from the floating power supply of
the upper gate driver.
The floating ground reference (GND1) is derived from the end of the shunt resistor that is connected to the
negative input of the AMC1300B-Q1 (INN). If a four-pin shunt is used, the inputs of the AMC1300B-Q1 are
connected to the inner leads and GND1 is connected to the outer lead on the INN-side of the shunt. To minimize
offset and improve accuracy, route the ground connection as a separate trace that connects directly to the shunt
resistor rather than shorting GND1 to INN directly at the input to the device. See the Layout section for more
details.
8.2.2.1 Shunt Resistor Sizing
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT.
Consider the following two restrictions when selecting the value of the shunt resistor, RSHUNT:
• The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range for a linear response: |VSHUNT| ≤|VFSR
|
• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: |VSHUNT| ≤|VClipping
|
8.2.2.2 Input Filter Design
TI recommends placing an RC-filter in front of the isolated amplifier to improve signal-to-noise performance of
the signal path. Design the input filter such that:
• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (20
MHz) of the ΔΣmodulator
• The input bias current does not generate significant voltage drop across the DC impedance of the input filter
• The impedances measured from the analog inputs are equal
For most applications, the structure shown in 图8-2 achieves excellent performance.
AMC1300B-Q1
VDD1
INP
VDD2
OUTP
OUTN
GND2
10 Ω
10 Ω
10 nF
INN
GND1
图8-2. Differential Input Filter
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8.2.2.3 Differential to Single-Ended Output Conversion
图 8-3 shows an example of a TLVx313-Q1-based signal conversion and filter circuit for systems using single-
ended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage
equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩand C1 = C2 = 330 pF yields good performance.
C1
AMC1300B-Q1
R2
VDD1
INP
VDD2
OUTP
OUTN
GND2
R1
R3
œ
ADC
To MCU
+
INN
TLV313-Q1
GND1
C2
R4
VREF
图8-3. Connecting the AMC1300B-Q1 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the
18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
8.2.3 Application Curve
One important aspect of power-stage design is the effective detection of an overcurrent condition to protect the
switching devices and passive components from damage. To power off the system quickly in the event of an
overcurrent condition, a low delay caused by the isolated amplifier is required. 图 8-4 shows the typical full-scale
step response of the AMC1300B-Q1.
VOUTP
VOUTN
VIN
图8-4. Step Response of the AMC1300B-Q1
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8.3 What to Do and What Not to Do
Do not leave the inputs of the AMC1300B-Q1 unconnected (floating) when the device is powered up. If the
device inputs are left floating, the input bias current may drive the inputs to a positive value that exceeds the
operating common-mode input voltage and the device outputs the fail-safe voltage as described in the Analog
Output section.
Connect the high-side ground (GND1) to INN, either by a hard short or through a resistive path. A DC current
path between INN and GND1 is required to define the input common-mode voltage. Take care not to exceed the
input common-mode range as specified in the Recommended Operating Conditions table. For best accuracy,
route the ground connection as a separate trace that connects directly to the shunt resistor rather than shorting
GND1 to INN directly at the input to the device. See the Layout section for more details.
9 Power Supply Recommendations
The AMC1300B-Q1 does not require any specific power up sequencing. The high-side power-supply (VDD1) is
decoupled with a low-ESR 100-nF capacitor (C1) parallel to a low-ESR 1-µF capacitor (C2). The low-side power
supply (VDD2) is equally decoupled with a low-ESR 100-nF capacitor (C3) parallel to a low-ESR 1-µF capacitor
(C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible.
The ground reference for the high-side (GND1) is derived from the end of the shunt resistor, which is connected
to the negative input (INN) of the device. For best DC accuracy, use a separate trace (as shown in 图 9-1) to
make this connection instead of shorting GND1 to INN directly at the device input. If a four-terminal shunt is
used, the device inputs are connected to the inner leads and GND1 is connected to the outer lead on the INN-
side of the shunt.
INP
VDD1
VDD2
C2 1 µF
C1 100 nF
R2 10 Ω
R1 10 Ω
C4 1 µF
AMC1300B-Q1
I
C3 100 nF
VDD1
INP
VDD2
OUTP
OUTN
GND2
to RC filter / ADC
to RC filter / ADC
C5
10 nF
INN
GND1
图9-1. Decoupling of the AMC1300B-Q1
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCCs) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
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10 Layout
10.1 Layout Guidelines
图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1300B-Q1 supply pins) and placement of the other components required by the device. For
best performance, place the shunt resistor close to the INP and INN inputs of the AMC1300B-Q1 and keep the
layout of both connections symmetrical.
10.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
C2
C1
C4
C3
INP
R2
to RC filter / ADC
to RC filter / ADC
OUTP
OUTN
AMC1300B-Q1
R1
INN
GND2
GND1
Top Metal
Inner or Bottom Layer Metal
Via
图10-1. Recommended Layout of the AMC1300B-Q1
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Isolation Glossary application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, TLVx313-Q1 Low-Power, Rail-to-Rail In/Out, 750-µV Typical Offset, 1-MHz Operational
Amplifier for Cost-Sensitive Systems data sheet
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
• Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1300BQDWVRQ1
ACTIVE
SOIC
DWV
8
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
MC1300BQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1300BQDWVRQ1
SOIC
DWV
8
1000
330.0
16.4
12.15
6.2
3.05
16.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DWV
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
AMC1300BQDWVRQ1
8
1000
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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